2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
116 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
117 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
121 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
123 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
124 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
126 switch (max_link_bw
) {
127 case DP_LINK_BW_1_62
:
130 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
131 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
132 INTEL_INFO(dev
)->gen
>= 8) &&
133 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
134 max_link_bw
= DP_LINK_BW_5_4
;
136 max_link_bw
= DP_LINK_BW_2_7
;
139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
141 max_link_bw
= DP_LINK_BW_1_62
;
147 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
149 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
150 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
151 u8 source_max
, sink_max
;
154 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
155 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
158 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
160 return min(source_max
, sink_max
);
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 * 270000 * 1 * 8 / 10 == 216000
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
181 intel_dp_link_required(int pixel_clock
, int bpp
)
183 return (pixel_clock
* bpp
+ 9) / 10;
187 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
189 return (max_link_clock
* max_lanes
* 8) / 10;
192 static enum drm_mode_status
193 intel_dp_mode_valid(struct drm_connector
*connector
,
194 struct drm_display_mode
*mode
)
196 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
197 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
198 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
199 int target_clock
= mode
->clock
;
200 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
202 if (is_edp(intel_dp
) && fixed_mode
) {
203 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
206 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
209 target_clock
= fixed_mode
->clock
;
212 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
213 max_lanes
= intel_dp_max_lane_count(intel_dp
);
215 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
216 mode_rate
= intel_dp_link_required(target_clock
, 18);
218 if (mode_rate
> max_rate
)
219 return MODE_CLOCK_HIGH
;
221 if (mode
->clock
< 10000)
222 return MODE_CLOCK_LOW
;
224 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
225 return MODE_H_ILLEGAL
;
231 pack_aux(const uint8_t *src
, int src_bytes
)
238 for (i
= 0; i
< src_bytes
; i
++)
239 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
244 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
249 for (i
= 0; i
< dst_bytes
; i
++)
250 dst
[i
] = src
>> ((3-i
) * 8);
253 /* hrawclock is 1/4 the FSB frequency */
255 intel_hrawclk(struct drm_device
*dev
)
257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
260 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
261 if (IS_VALLEYVIEW(dev
))
264 clkcfg
= I915_READ(CLKCFG
);
265 switch (clkcfg
& CLKCFG_FSB_MASK
) {
274 case CLKCFG_FSB_1067
:
276 case CLKCFG_FSB_1333
:
278 /* these two are just a guess; one of them might be right */
279 case CLKCFG_FSB_1600
:
280 case CLKCFG_FSB_1600_ALT
:
288 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
289 struct intel_dp
*intel_dp
);
291 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
292 struct intel_dp
*intel_dp
);
294 static void pps_lock(struct intel_dp
*intel_dp
)
296 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
297 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
298 struct drm_device
*dev
= encoder
->base
.dev
;
299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
300 enum intel_display_power_domain power_domain
;
303 * See vlv_power_sequencer_reset() why we need
304 * a power domain reference here.
306 power_domain
= intel_display_port_power_domain(encoder
);
307 intel_display_power_get(dev_priv
, power_domain
);
309 mutex_lock(&dev_priv
->pps_mutex
);
312 static void pps_unlock(struct intel_dp
*intel_dp
)
314 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
315 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
316 struct drm_device
*dev
= encoder
->base
.dev
;
317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
318 enum intel_display_power_domain power_domain
;
320 mutex_unlock(&dev_priv
->pps_mutex
);
322 power_domain
= intel_display_port_power_domain(encoder
);
323 intel_display_power_put(dev_priv
, power_domain
);
327 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
329 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
330 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
332 enum pipe pipe
= intel_dp
->pps_pipe
;
335 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
336 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
337 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
340 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
341 pipe_name(pipe
), port_name(intel_dig_port
->port
));
343 /* Preserve the BIOS-computed detected bit. This is
344 * supposed to be read-only.
346 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
347 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
348 DP
|= DP_PORT_WIDTH(1);
349 DP
|= DP_LINK_TRAIN_PAT_1
;
351 if (IS_CHERRYVIEW(dev
))
352 DP
|= DP_PIPE_SELECT_CHV(pipe
);
353 else if (pipe
== PIPE_B
)
354 DP
|= DP_PIPEB_SELECT
;
357 * Similar magic as in intel_dp_enable_port().
358 * We _must_ do this port enable + disable trick
359 * to make this power seqeuencer lock onto the port.
360 * Otherwise even VDD force bit won't work.
362 I915_WRITE(intel_dp
->output_reg
, DP
);
363 POSTING_READ(intel_dp
->output_reg
);
365 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
366 POSTING_READ(intel_dp
->output_reg
);
368 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
369 POSTING_READ(intel_dp
->output_reg
);
373 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
375 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
376 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
378 struct intel_encoder
*encoder
;
379 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
382 lockdep_assert_held(&dev_priv
->pps_mutex
);
384 /* We should never land here with regular DP ports */
385 WARN_ON(!is_edp(intel_dp
));
387 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
388 return intel_dp
->pps_pipe
;
391 * We don't have power sequencer currently.
392 * Pick one that's not used by other ports.
394 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
396 struct intel_dp
*tmp
;
398 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
401 tmp
= enc_to_intel_dp(&encoder
->base
);
403 if (tmp
->pps_pipe
!= INVALID_PIPE
)
404 pipes
&= ~(1 << tmp
->pps_pipe
);
408 * Didn't find one. This should not happen since there
409 * are two power sequencers and up to two eDP ports.
411 if (WARN_ON(pipes
== 0))
414 pipe
= ffs(pipes
) - 1;
416 vlv_steal_power_sequencer(dev
, pipe
);
417 intel_dp
->pps_pipe
= pipe
;
419 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
420 pipe_name(intel_dp
->pps_pipe
),
421 port_name(intel_dig_port
->port
));
423 /* init power sequencer on this pipe and port */
424 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
425 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
428 * Even vdd force doesn't work until we've made
429 * the power sequencer lock in on the port.
431 vlv_power_sequencer_kick(intel_dp
);
433 return intel_dp
->pps_pipe
;
436 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
439 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
442 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
445 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
448 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
451 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
458 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
460 vlv_pipe_check pipe_check
)
464 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
465 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
466 PANEL_PORT_SELECT_MASK
;
468 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
471 if (!pipe_check(dev_priv
, pipe
))
481 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
483 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
484 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
486 enum port port
= intel_dig_port
->port
;
488 lockdep_assert_held(&dev_priv
->pps_mutex
);
490 /* try to find a pipe with this port selected */
491 /* first pick one where the panel is on */
492 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
494 /* didn't find one? pick one where vdd is on */
495 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
496 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
497 vlv_pipe_has_vdd_on
);
498 /* didn't find one? pick one with just the correct port */
499 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
500 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
503 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
504 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
505 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
510 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
511 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
513 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
514 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
517 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
519 struct drm_device
*dev
= dev_priv
->dev
;
520 struct intel_encoder
*encoder
;
522 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
526 * We can't grab pps_mutex here due to deadlock with power_domain
527 * mutex when power_domain functions are called while holding pps_mutex.
528 * That also means that in order to use pps_pipe the code needs to
529 * hold both a power domain reference and pps_mutex, and the power domain
530 * reference get/put must be done while _not_ holding pps_mutex.
531 * pps_{lock,unlock}() do these steps in the correct order, so one
532 * should use them always.
535 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
536 struct intel_dp
*intel_dp
;
538 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
541 intel_dp
= enc_to_intel_dp(&encoder
->base
);
542 intel_dp
->pps_pipe
= INVALID_PIPE
;
546 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
548 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
550 if (HAS_PCH_SPLIT(dev
))
551 return PCH_PP_CONTROL
;
553 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
556 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
558 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
560 if (HAS_PCH_SPLIT(dev
))
561 return PCH_PP_STATUS
;
563 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
566 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
567 This function only applicable when panel PM state is not to be tracked */
568 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
571 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
573 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
576 u32 pp_ctrl_reg
, pp_div_reg
;
578 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
583 if (IS_VALLEYVIEW(dev
)) {
584 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
586 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
587 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
588 pp_div
= I915_READ(pp_div_reg
);
589 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
591 /* 0x1F write to PP_DIV_REG sets max cycle delay */
592 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
593 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
594 msleep(intel_dp
->panel_power_cycle_delay
);
597 pps_unlock(intel_dp
);
602 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
604 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
607 lockdep_assert_held(&dev_priv
->pps_mutex
);
609 if (IS_VALLEYVIEW(dev
) &&
610 intel_dp
->pps_pipe
== INVALID_PIPE
)
613 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
616 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
618 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
621 lockdep_assert_held(&dev_priv
->pps_mutex
);
623 if (IS_VALLEYVIEW(dev
) &&
624 intel_dp
->pps_pipe
== INVALID_PIPE
)
627 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
631 intel_dp_check_edp(struct intel_dp
*intel_dp
)
633 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
636 if (!is_edp(intel_dp
))
639 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
640 WARN(1, "eDP powered off while attempting aux channel communication.\n");
641 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
642 I915_READ(_pp_stat_reg(intel_dp
)),
643 I915_READ(_pp_ctrl_reg(intel_dp
)));
648 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
650 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
651 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
653 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
657 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
659 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
660 msecs_to_jiffies_timeout(10));
662 done
= wait_for_atomic(C
, 10) == 0;
664 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
671 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
673 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
674 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
677 * The clock divider is based off the hrawclk, and would like to run at
678 * 2MHz. So, take the hrawclk value and divide by 2 and use that
680 return index
? 0 : intel_hrawclk(dev
) / 2;
683 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
685 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
686 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
691 if (intel_dig_port
->port
== PORT_A
) {
692 if (IS_GEN6(dev
) || IS_GEN7(dev
))
693 return 200; /* SNB & IVB eDP input clock at 400Mhz */
695 return 225; /* eDP input clock at 450Mhz */
697 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
701 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
703 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
704 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
707 if (intel_dig_port
->port
== PORT_A
) {
710 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
711 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
712 /* Workaround for non-ULT HSW */
719 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
723 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
725 return index
? 0 : 100;
728 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
731 * SKL doesn't need us to program the AUX clock divider (Hardware will
732 * derive the clock from CDCLK automatically). We still implement the
733 * get_aux_clock_divider vfunc to plug-in into the existing code.
735 return index
? 0 : 1;
738 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
741 uint32_t aux_clock_divider
)
743 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
744 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
745 uint32_t precharge
, timeout
;
752 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
753 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
755 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
757 return DP_AUX_CH_CTL_SEND_BUSY
|
759 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
760 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
762 DP_AUX_CH_CTL_RECEIVE_ERROR
|
763 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
764 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
765 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
768 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
773 return DP_AUX_CH_CTL_SEND_BUSY
|
775 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
776 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
777 DP_AUX_CH_CTL_TIME_OUT_1600us
|
778 DP_AUX_CH_CTL_RECEIVE_ERROR
|
779 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
780 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
784 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
785 const uint8_t *send
, int send_bytes
,
786 uint8_t *recv
, int recv_size
)
788 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
789 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
791 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
792 uint32_t ch_data
= ch_ctl
+ 4;
793 uint32_t aux_clock_divider
;
794 int i
, ret
, recv_bytes
;
797 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
803 * We will be called with VDD already enabled for dpcd/edid/oui reads.
804 * In such cases we want to leave VDD enabled and it's up to upper layers
805 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
808 vdd
= edp_panel_vdd_on(intel_dp
);
810 /* dp aux is extremely sensitive to irq latency, hence request the
811 * lowest possible wakeup latency and so prevent the cpu from going into
814 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
816 intel_dp_check_edp(intel_dp
);
818 intel_aux_display_runtime_get(dev_priv
);
820 /* Try to wait for any previous AUX channel activity */
821 for (try = 0; try < 3; try++) {
822 status
= I915_READ_NOTRACE(ch_ctl
);
823 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
829 WARN(1, "dp_aux_ch not started status 0x%08x\n",
835 /* Only 5 data registers! */
836 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
841 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
842 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
847 /* Must try at least 3 times according to DP spec */
848 for (try = 0; try < 5; try++) {
849 /* Load the send data into the aux channel data registers */
850 for (i
= 0; i
< send_bytes
; i
+= 4)
851 I915_WRITE(ch_data
+ i
,
852 pack_aux(send
+ i
, send_bytes
- i
));
854 /* Send the command and wait for it to complete */
855 I915_WRITE(ch_ctl
, send_ctl
);
857 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
859 /* Clear done status and any errors */
863 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
864 DP_AUX_CH_CTL_RECEIVE_ERROR
);
866 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
867 DP_AUX_CH_CTL_RECEIVE_ERROR
))
869 if (status
& DP_AUX_CH_CTL_DONE
)
872 if (status
& DP_AUX_CH_CTL_DONE
)
876 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
877 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
882 /* Check for timeout or receive error.
883 * Timeouts occur when the sink is not connected
885 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
886 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
891 /* Timeouts occur when the device isn't connected, so they're
892 * "normal" -- don't fill the kernel log with these */
893 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
894 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
899 /* Unload any bytes sent back from the other side */
900 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
901 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
902 if (recv_bytes
> recv_size
)
903 recv_bytes
= recv_size
;
905 for (i
= 0; i
< recv_bytes
; i
+= 4)
906 unpack_aux(I915_READ(ch_data
+ i
),
907 recv
+ i
, recv_bytes
- i
);
911 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
912 intel_aux_display_runtime_put(dev_priv
);
915 edp_panel_vdd_off(intel_dp
, false);
917 pps_unlock(intel_dp
);
922 #define BARE_ADDRESS_SIZE 3
923 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
925 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
927 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
928 uint8_t txbuf
[20], rxbuf
[20];
929 size_t txsize
, rxsize
;
932 txbuf
[0] = msg
->request
<< 4;
933 txbuf
[1] = msg
->address
>> 8;
934 txbuf
[2] = msg
->address
& 0xff;
935 txbuf
[3] = msg
->size
- 1;
937 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
938 case DP_AUX_NATIVE_WRITE
:
939 case DP_AUX_I2C_WRITE
:
940 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
943 if (WARN_ON(txsize
> 20))
946 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
948 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
950 msg
->reply
= rxbuf
[0] >> 4;
952 /* Return payload size. */
957 case DP_AUX_NATIVE_READ
:
958 case DP_AUX_I2C_READ
:
959 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
960 rxsize
= msg
->size
+ 1;
962 if (WARN_ON(rxsize
> 20))
965 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
967 msg
->reply
= rxbuf
[0] >> 4;
969 * Assume happy day, and copy the data. The caller is
970 * expected to check msg->reply before touching it.
972 * Return payload size.
975 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
988 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
990 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
991 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
992 enum port port
= intel_dig_port
->port
;
993 const char *name
= NULL
;
998 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1002 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1006 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1010 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1018 * The AUX_CTL register is usually DP_CTL + 0x10.
1020 * On Haswell and Broadwell though:
1021 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1022 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1024 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1026 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
1027 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1029 intel_dp
->aux
.name
= name
;
1030 intel_dp
->aux
.dev
= dev
->dev
;
1031 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1033 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1034 connector
->base
.kdev
->kobj
.name
);
1036 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1038 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1043 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1044 &intel_dp
->aux
.ddc
.dev
.kobj
,
1045 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1047 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1048 drm_dp_aux_unregister(&intel_dp
->aux
);
1053 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1055 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1057 if (!intel_connector
->mst_port
)
1058 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1059 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1060 intel_connector_unregister(intel_connector
);
1064 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
1067 case DP_LINK_BW_1_62
:
1068 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1070 case DP_LINK_BW_2_7
:
1071 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1073 case DP_LINK_BW_5_4
:
1074 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1080 intel_dp_set_clock(struct intel_encoder
*encoder
,
1081 struct intel_crtc_config
*pipe_config
, int link_bw
)
1083 struct drm_device
*dev
= encoder
->base
.dev
;
1084 const struct dp_link_dpll
*divisor
= NULL
;
1088 divisor
= gen4_dpll
;
1089 count
= ARRAY_SIZE(gen4_dpll
);
1090 } else if (HAS_PCH_SPLIT(dev
)) {
1092 count
= ARRAY_SIZE(pch_dpll
);
1093 } else if (IS_CHERRYVIEW(dev
)) {
1095 count
= ARRAY_SIZE(chv_dpll
);
1096 } else if (IS_VALLEYVIEW(dev
)) {
1098 count
= ARRAY_SIZE(vlv_dpll
);
1101 if (divisor
&& count
) {
1102 for (i
= 0; i
< count
; i
++) {
1103 if (link_bw
== divisor
[i
].link_bw
) {
1104 pipe_config
->dpll
= divisor
[i
].dpll
;
1105 pipe_config
->clock_set
= true;
1113 intel_dp_compute_config(struct intel_encoder
*encoder
,
1114 struct intel_crtc_config
*pipe_config
)
1116 struct drm_device
*dev
= encoder
->base
.dev
;
1117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1118 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
1119 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1120 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1121 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
1122 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1123 int lane_count
, clock
;
1124 int min_lane_count
= 1;
1125 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1126 /* Conveniently, the link BW constants become indices with a shift...*/
1128 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
1130 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
1131 int link_avail
, link_clock
;
1133 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1134 pipe_config
->has_pch_encoder
= true;
1136 pipe_config
->has_dp_encoder
= true;
1137 pipe_config
->has_drrs
= false;
1138 pipe_config
->has_audio
= intel_dp
->has_audio
;
1140 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1141 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1143 if (!HAS_PCH_SPLIT(dev
))
1144 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1145 intel_connector
->panel
.fitting_mode
);
1147 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1148 intel_connector
->panel
.fitting_mode
);
1151 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1154 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1155 "max bw %02x pixel clock %iKHz\n",
1156 max_lane_count
, bws
[max_clock
],
1157 adjusted_mode
->crtc_clock
);
1159 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1160 * bpc in between. */
1161 bpp
= pipe_config
->pipe_bpp
;
1162 if (is_edp(intel_dp
)) {
1163 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1164 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1165 dev_priv
->vbt
.edp_bpp
);
1166 bpp
= dev_priv
->vbt
.edp_bpp
;
1170 * Use the maximum clock and number of lanes the eDP panel
1171 * advertizes being capable of. The panels are generally
1172 * designed to support only a single clock and lane
1173 * configuration, and typically these values correspond to the
1174 * native resolution of the panel.
1176 min_lane_count
= max_lane_count
;
1177 min_clock
= max_clock
;
1180 for (; bpp
>= 6*3; bpp
-= 2*3) {
1181 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1184 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1185 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
1186 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
1187 link_avail
= intel_dp_max_data_rate(link_clock
,
1190 if (mode_rate
<= link_avail
) {
1200 if (intel_dp
->color_range_auto
) {
1203 * CEA-861-E - 5.1 Default Encoding Parameters
1204 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1206 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1207 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1209 intel_dp
->color_range
= 0;
1212 if (intel_dp
->color_range
)
1213 pipe_config
->limited_color_range
= true;
1215 intel_dp
->link_bw
= bws
[clock
];
1216 intel_dp
->lane_count
= lane_count
;
1217 pipe_config
->pipe_bpp
= bpp
;
1218 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
1220 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1221 intel_dp
->link_bw
, intel_dp
->lane_count
,
1222 pipe_config
->port_clock
, bpp
);
1223 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1224 mode_rate
, link_avail
);
1226 intel_link_compute_m_n(bpp
, lane_count
,
1227 adjusted_mode
->crtc_clock
,
1228 pipe_config
->port_clock
,
1229 &pipe_config
->dp_m_n
);
1231 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1232 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
1233 pipe_config
->has_drrs
= true;
1234 intel_link_compute_m_n(bpp
, lane_count
,
1235 intel_connector
->panel
.downclock_mode
->clock
,
1236 pipe_config
->port_clock
,
1237 &pipe_config
->dp_m2_n2
);
1240 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1241 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1243 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1248 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1250 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1251 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1252 struct drm_device
*dev
= crtc
->base
.dev
;
1253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1256 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
1257 dpa_ctl
= I915_READ(DP_A
);
1258 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1260 if (crtc
->config
.port_clock
== 162000) {
1261 /* For a long time we've carried around a ILK-DevA w/a for the
1262 * 160MHz clock. If we're really unlucky, it's still required.
1264 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1265 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1266 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1268 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1269 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1272 I915_WRITE(DP_A
, dpa_ctl
);
1278 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1280 struct drm_device
*dev
= encoder
->base
.dev
;
1281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1282 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1283 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1284 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1285 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1288 * There are four kinds of DP registers:
1295 * IBX PCH and CPU are the same for almost everything,
1296 * except that the CPU DP PLL is configured in this
1299 * CPT PCH is quite different, having many bits moved
1300 * to the TRANS_DP_CTL register instead. That
1301 * configuration happens (oddly) in ironlake_pch_enable
1304 /* Preserve the BIOS-computed detected bit. This is
1305 * supposed to be read-only.
1307 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1309 /* Handle DP bits in common between all three register formats */
1310 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1311 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1313 if (crtc
->config
.has_audio
) {
1314 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1315 pipe_name(crtc
->pipe
));
1316 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1317 intel_write_eld(encoder
);
1320 /* Split out the IBX/CPU vs CPT settings */
1322 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1323 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1324 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1325 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1326 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1327 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1329 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1330 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1332 intel_dp
->DP
|= crtc
->pipe
<< 29;
1333 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1334 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1335 intel_dp
->DP
|= intel_dp
->color_range
;
1337 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1338 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1339 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1340 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1341 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1343 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1344 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1346 if (!IS_CHERRYVIEW(dev
)) {
1347 if (crtc
->pipe
== 1)
1348 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1350 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1353 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1357 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1358 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1360 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1361 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1363 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1364 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1366 static void wait_panel_status(struct intel_dp
*intel_dp
,
1370 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1372 u32 pp_stat_reg
, pp_ctrl_reg
;
1374 lockdep_assert_held(&dev_priv
->pps_mutex
);
1376 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1377 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1379 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1381 I915_READ(pp_stat_reg
),
1382 I915_READ(pp_ctrl_reg
));
1384 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1385 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1386 I915_READ(pp_stat_reg
),
1387 I915_READ(pp_ctrl_reg
));
1390 DRM_DEBUG_KMS("Wait complete\n");
1393 static void wait_panel_on(struct intel_dp
*intel_dp
)
1395 DRM_DEBUG_KMS("Wait for panel power on\n");
1396 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1399 static void wait_panel_off(struct intel_dp
*intel_dp
)
1401 DRM_DEBUG_KMS("Wait for panel power off time\n");
1402 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1405 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1407 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1409 /* When we disable the VDD override bit last we have to do the manual
1411 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1412 intel_dp
->panel_power_cycle_delay
);
1414 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1417 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1419 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1420 intel_dp
->backlight_on_delay
);
1423 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1425 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1426 intel_dp
->backlight_off_delay
);
1429 /* Read the current pp_control value, unlocking the register if it
1433 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1435 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1439 lockdep_assert_held(&dev_priv
->pps_mutex
);
1441 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1442 control
&= ~PANEL_UNLOCK_MASK
;
1443 control
|= PANEL_UNLOCK_REGS
;
1448 * Must be paired with edp_panel_vdd_off().
1449 * Must hold pps_mutex around the whole on/off sequence.
1450 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1452 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1454 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1455 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1456 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1458 enum intel_display_power_domain power_domain
;
1460 u32 pp_stat_reg
, pp_ctrl_reg
;
1461 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1463 lockdep_assert_held(&dev_priv
->pps_mutex
);
1465 if (!is_edp(intel_dp
))
1468 intel_dp
->want_panel_vdd
= true;
1470 if (edp_have_panel_vdd(intel_dp
))
1471 return need_to_disable
;
1473 power_domain
= intel_display_port_power_domain(intel_encoder
);
1474 intel_display_power_get(dev_priv
, power_domain
);
1476 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1478 if (!edp_have_panel_power(intel_dp
))
1479 wait_panel_power_cycle(intel_dp
);
1481 pp
= ironlake_get_pp_control(intel_dp
);
1482 pp
|= EDP_FORCE_VDD
;
1484 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1485 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1487 I915_WRITE(pp_ctrl_reg
, pp
);
1488 POSTING_READ(pp_ctrl_reg
);
1489 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1490 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1492 * If the panel wasn't on, delay before accessing aux channel
1494 if (!edp_have_panel_power(intel_dp
)) {
1495 DRM_DEBUG_KMS("eDP was not running\n");
1496 msleep(intel_dp
->panel_power_up_delay
);
1499 return need_to_disable
;
1503 * Must be paired with intel_edp_panel_vdd_off() or
1504 * intel_edp_panel_off().
1505 * Nested calls to these functions are not allowed since
1506 * we drop the lock. Caller must use some higher level
1507 * locking to prevent nested calls from other threads.
1509 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1513 if (!is_edp(intel_dp
))
1517 vdd
= edp_panel_vdd_on(intel_dp
);
1518 pps_unlock(intel_dp
);
1520 WARN(!vdd
, "eDP VDD already requested on\n");
1523 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1525 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1527 struct intel_digital_port
*intel_dig_port
=
1528 dp_to_dig_port(intel_dp
);
1529 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1530 enum intel_display_power_domain power_domain
;
1532 u32 pp_stat_reg
, pp_ctrl_reg
;
1534 lockdep_assert_held(&dev_priv
->pps_mutex
);
1536 WARN_ON(intel_dp
->want_panel_vdd
);
1538 if (!edp_have_panel_vdd(intel_dp
))
1541 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1543 pp
= ironlake_get_pp_control(intel_dp
);
1544 pp
&= ~EDP_FORCE_VDD
;
1546 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1547 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1549 I915_WRITE(pp_ctrl_reg
, pp
);
1550 POSTING_READ(pp_ctrl_reg
);
1552 /* Make sure sequencer is idle before allowing subsequent activity */
1553 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1554 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1556 if ((pp
& POWER_TARGET_ON
) == 0)
1557 intel_dp
->last_power_cycle
= jiffies
;
1559 power_domain
= intel_display_port_power_domain(intel_encoder
);
1560 intel_display_power_put(dev_priv
, power_domain
);
1563 static void edp_panel_vdd_work(struct work_struct
*__work
)
1565 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1566 struct intel_dp
, panel_vdd_work
);
1569 if (!intel_dp
->want_panel_vdd
)
1570 edp_panel_vdd_off_sync(intel_dp
);
1571 pps_unlock(intel_dp
);
1574 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1576 unsigned long delay
;
1579 * Queue the timer to fire a long time from now (relative to the power
1580 * down delay) to keep the panel power up across a sequence of
1583 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1584 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1588 * Must be paired with edp_panel_vdd_on().
1589 * Must hold pps_mutex around the whole on/off sequence.
1590 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1592 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1594 struct drm_i915_private
*dev_priv
=
1595 intel_dp_to_dev(intel_dp
)->dev_private
;
1597 lockdep_assert_held(&dev_priv
->pps_mutex
);
1599 if (!is_edp(intel_dp
))
1602 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1604 intel_dp
->want_panel_vdd
= false;
1607 edp_panel_vdd_off_sync(intel_dp
);
1609 edp_panel_vdd_schedule_off(intel_dp
);
1612 static void edp_panel_on(struct intel_dp
*intel_dp
)
1614 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1619 lockdep_assert_held(&dev_priv
->pps_mutex
);
1621 if (!is_edp(intel_dp
))
1624 DRM_DEBUG_KMS("Turn eDP power on\n");
1626 if (edp_have_panel_power(intel_dp
)) {
1627 DRM_DEBUG_KMS("eDP power already on\n");
1631 wait_panel_power_cycle(intel_dp
);
1633 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1634 pp
= ironlake_get_pp_control(intel_dp
);
1636 /* ILK workaround: disable reset around power sequence */
1637 pp
&= ~PANEL_POWER_RESET
;
1638 I915_WRITE(pp_ctrl_reg
, pp
);
1639 POSTING_READ(pp_ctrl_reg
);
1642 pp
|= POWER_TARGET_ON
;
1644 pp
|= PANEL_POWER_RESET
;
1646 I915_WRITE(pp_ctrl_reg
, pp
);
1647 POSTING_READ(pp_ctrl_reg
);
1649 wait_panel_on(intel_dp
);
1650 intel_dp
->last_power_on
= jiffies
;
1653 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1654 I915_WRITE(pp_ctrl_reg
, pp
);
1655 POSTING_READ(pp_ctrl_reg
);
1659 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1661 if (!is_edp(intel_dp
))
1665 edp_panel_on(intel_dp
);
1666 pps_unlock(intel_dp
);
1670 static void edp_panel_off(struct intel_dp
*intel_dp
)
1672 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1673 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1674 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1676 enum intel_display_power_domain power_domain
;
1680 lockdep_assert_held(&dev_priv
->pps_mutex
);
1682 if (!is_edp(intel_dp
))
1685 DRM_DEBUG_KMS("Turn eDP power off\n");
1687 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1689 pp
= ironlake_get_pp_control(intel_dp
);
1690 /* We need to switch off panel power _and_ force vdd, for otherwise some
1691 * panels get very unhappy and cease to work. */
1692 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1695 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1697 intel_dp
->want_panel_vdd
= false;
1699 I915_WRITE(pp_ctrl_reg
, pp
);
1700 POSTING_READ(pp_ctrl_reg
);
1702 intel_dp
->last_power_cycle
= jiffies
;
1703 wait_panel_off(intel_dp
);
1705 /* We got a reference when we enabled the VDD. */
1706 power_domain
= intel_display_port_power_domain(intel_encoder
);
1707 intel_display_power_put(dev_priv
, power_domain
);
1710 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1712 if (!is_edp(intel_dp
))
1716 edp_panel_off(intel_dp
);
1717 pps_unlock(intel_dp
);
1720 /* Enable backlight in the panel power control. */
1721 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1723 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1724 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1730 * If we enable the backlight right away following a panel power
1731 * on, we may see slight flicker as the panel syncs with the eDP
1732 * link. So delay a bit to make sure the image is solid before
1733 * allowing it to appear.
1735 wait_backlight_on(intel_dp
);
1739 pp
= ironlake_get_pp_control(intel_dp
);
1740 pp
|= EDP_BLC_ENABLE
;
1742 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1744 I915_WRITE(pp_ctrl_reg
, pp
);
1745 POSTING_READ(pp_ctrl_reg
);
1747 pps_unlock(intel_dp
);
1750 /* Enable backlight PWM and backlight PP control. */
1751 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1753 if (!is_edp(intel_dp
))
1756 DRM_DEBUG_KMS("\n");
1758 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1759 _intel_edp_backlight_on(intel_dp
);
1762 /* Disable backlight in the panel power control. */
1763 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1765 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1770 if (!is_edp(intel_dp
))
1775 pp
= ironlake_get_pp_control(intel_dp
);
1776 pp
&= ~EDP_BLC_ENABLE
;
1778 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1780 I915_WRITE(pp_ctrl_reg
, pp
);
1781 POSTING_READ(pp_ctrl_reg
);
1783 pps_unlock(intel_dp
);
1785 intel_dp
->last_backlight_off
= jiffies
;
1786 edp_wait_backlight_off(intel_dp
);
1789 /* Disable backlight PP control and backlight PWM. */
1790 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1792 if (!is_edp(intel_dp
))
1795 DRM_DEBUG_KMS("\n");
1797 _intel_edp_backlight_off(intel_dp
);
1798 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1802 * Hook for controlling the panel power control backlight through the bl_power
1803 * sysfs attribute. Take care to handle multiple calls.
1805 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1808 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1812 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1813 pps_unlock(intel_dp
);
1815 if (is_enabled
== enable
)
1818 DRM_DEBUG_KMS("panel power control backlight %s\n",
1819 enable
? "enable" : "disable");
1822 _intel_edp_backlight_on(intel_dp
);
1824 _intel_edp_backlight_off(intel_dp
);
1827 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1829 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1830 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1831 struct drm_device
*dev
= crtc
->dev
;
1832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1835 assert_pipe_disabled(dev_priv
,
1836 to_intel_crtc(crtc
)->pipe
);
1838 DRM_DEBUG_KMS("\n");
1839 dpa_ctl
= I915_READ(DP_A
);
1840 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1841 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1843 /* We don't adjust intel_dp->DP while tearing down the link, to
1844 * facilitate link retraining (e.g. after hotplug). Hence clear all
1845 * enable bits here to ensure that we don't enable too much. */
1846 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1847 intel_dp
->DP
|= DP_PLL_ENABLE
;
1848 I915_WRITE(DP_A
, intel_dp
->DP
);
1853 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1855 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1856 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1857 struct drm_device
*dev
= crtc
->dev
;
1858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1861 assert_pipe_disabled(dev_priv
,
1862 to_intel_crtc(crtc
)->pipe
);
1864 dpa_ctl
= I915_READ(DP_A
);
1865 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1866 "dp pll off, should be on\n");
1867 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1869 /* We can't rely on the value tracked for the DP register in
1870 * intel_dp->DP because link_down must not change that (otherwise link
1871 * re-training will fail. */
1872 dpa_ctl
&= ~DP_PLL_ENABLE
;
1873 I915_WRITE(DP_A
, dpa_ctl
);
1878 /* If the sink supports it, try to set the power state appropriately */
1879 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1883 /* Should have a valid DPCD by this point */
1884 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1887 if (mode
!= DRM_MODE_DPMS_ON
) {
1888 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1892 * When turning on, we need to retry for 1ms to give the sink
1895 for (i
= 0; i
< 3; i
++) {
1896 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1905 DRM_DEBUG_KMS("failed to %s sink power state\n",
1906 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
1909 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1912 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1913 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1914 struct drm_device
*dev
= encoder
->base
.dev
;
1915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1916 enum intel_display_power_domain power_domain
;
1919 power_domain
= intel_display_port_power_domain(encoder
);
1920 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1923 tmp
= I915_READ(intel_dp
->output_reg
);
1925 if (!(tmp
& DP_PORT_EN
))
1928 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1929 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1930 } else if (IS_CHERRYVIEW(dev
)) {
1931 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1932 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1933 *pipe
= PORT_TO_PIPE(tmp
);
1939 switch (intel_dp
->output_reg
) {
1941 trans_sel
= TRANS_DP_PORT_SEL_B
;
1944 trans_sel
= TRANS_DP_PORT_SEL_C
;
1947 trans_sel
= TRANS_DP_PORT_SEL_D
;
1953 for_each_pipe(dev_priv
, i
) {
1954 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1955 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1961 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1962 intel_dp
->output_reg
);
1968 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1969 struct intel_crtc_config
*pipe_config
)
1971 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1973 struct drm_device
*dev
= encoder
->base
.dev
;
1974 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1975 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1976 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1979 tmp
= I915_READ(intel_dp
->output_reg
);
1980 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1981 pipe_config
->has_audio
= true;
1983 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1984 if (tmp
& DP_SYNC_HS_HIGH
)
1985 flags
|= DRM_MODE_FLAG_PHSYNC
;
1987 flags
|= DRM_MODE_FLAG_NHSYNC
;
1989 if (tmp
& DP_SYNC_VS_HIGH
)
1990 flags
|= DRM_MODE_FLAG_PVSYNC
;
1992 flags
|= DRM_MODE_FLAG_NVSYNC
;
1994 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1995 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1996 flags
|= DRM_MODE_FLAG_PHSYNC
;
1998 flags
|= DRM_MODE_FLAG_NHSYNC
;
2000 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2001 flags
|= DRM_MODE_FLAG_PVSYNC
;
2003 flags
|= DRM_MODE_FLAG_NVSYNC
;
2006 pipe_config
->adjusted_mode
.flags
|= flags
;
2008 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2009 tmp
& DP_COLOR_RANGE_16_235
)
2010 pipe_config
->limited_color_range
= true;
2012 pipe_config
->has_dp_encoder
= true;
2014 intel_dp_get_m_n(crtc
, pipe_config
);
2016 if (port
== PORT_A
) {
2017 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2018 pipe_config
->port_clock
= 162000;
2020 pipe_config
->port_clock
= 270000;
2023 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2024 &pipe_config
->dp_m_n
);
2026 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2027 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2029 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
2031 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2032 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2034 * This is a big fat ugly hack.
2036 * Some machines in UEFI boot mode provide us a VBT that has 18
2037 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2038 * unknown we fail to light up. Yet the same BIOS boots up with
2039 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2040 * max, not what it tells us to use.
2042 * Note: This will still be broken if the eDP panel is not lit
2043 * up by the BIOS, and thus we can't get the mode at module
2046 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2047 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2048 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2052 static bool is_edp_psr(struct intel_dp
*intel_dp
)
2054 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
2057 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
2059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2064 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2067 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
2068 struct edp_vsc_psr
*vsc_psr
)
2070 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2071 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2073 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
2074 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
2075 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
2076 uint32_t *data
= (uint32_t *) vsc_psr
;
2079 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2080 the video DIP being updated before program video DIP data buffer
2081 registers for DIP being updated. */
2082 I915_WRITE(ctl_reg
, 0);
2083 POSTING_READ(ctl_reg
);
2085 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
2086 if (i
< sizeof(struct edp_vsc_psr
))
2087 I915_WRITE(data_reg
+ i
, *data
++);
2089 I915_WRITE(data_reg
+ i
, 0);
2092 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
2093 POSTING_READ(ctl_reg
);
2096 static void intel_edp_psr_setup_vsc(struct intel_dp
*intel_dp
)
2098 struct edp_vsc_psr psr_vsc
;
2100 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2101 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
2102 psr_vsc
.sdp_header
.HB0
= 0;
2103 psr_vsc
.sdp_header
.HB1
= 0x7;
2104 psr_vsc
.sdp_header
.HB2
= 0x2;
2105 psr_vsc
.sdp_header
.HB3
= 0x8;
2106 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
2109 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
2111 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2112 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2114 uint32_t aux_clock_divider
;
2115 int precharge
= 0x3;
2116 bool only_standby
= false;
2117 static const uint8_t aux_msg
[] = {
2118 [0] = DP_AUX_NATIVE_WRITE
<< 4,
2119 [1] = DP_SET_POWER
>> 8,
2120 [2] = DP_SET_POWER
& 0xff,
2122 [4] = DP_SET_POWER_D0
,
2126 BUILD_BUG_ON(sizeof(aux_msg
) > 20);
2128 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
2130 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2131 only_standby
= true;
2133 /* Enable PSR in sink */
2134 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
2135 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2136 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
2138 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2139 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
2141 /* Setup AUX registers */
2142 for (i
= 0; i
< sizeof(aux_msg
); i
+= 4)
2143 I915_WRITE(EDP_PSR_AUX_DATA1(dev
) + i
,
2144 pack_aux(&aux_msg
[i
], sizeof(aux_msg
) - i
));
2146 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
2147 DP_AUX_CH_CTL_TIME_OUT_400us
|
2148 (sizeof(aux_msg
) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
2149 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
2150 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
2153 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
2155 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2156 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2158 uint32_t max_sleep_time
= 0x1f;
2159 uint32_t idle_frames
= 1;
2161 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
2162 bool only_standby
= false;
2164 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2165 only_standby
= true;
2167 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
2168 val
|= EDP_PSR_LINK_STANDBY
;
2169 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
2170 val
|= EDP_PSR_TP1_TIME_0us
;
2171 val
|= EDP_PSR_SKIP_AUX_EXIT
;
2172 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
2174 val
|= EDP_PSR_LINK_DISABLE
;
2176 I915_WRITE(EDP_PSR_CTL(dev
), val
|
2177 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
2178 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
2179 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
2183 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
2185 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2186 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2188 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
2189 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2191 lockdep_assert_held(&dev_priv
->psr
.lock
);
2192 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
2193 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
2195 dev_priv
->psr
.source_ok
= false;
2197 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
2198 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2202 if (!i915
.enable_psr
) {
2203 DRM_DEBUG_KMS("PSR disable by flag\n");
2207 /* Below limitations aren't valid for Broadwell */
2208 if (IS_BROADWELL(dev
))
2211 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
2213 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2217 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
2218 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2223 dev_priv
->psr
.source_ok
= true;
2227 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
2229 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2230 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2233 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2234 WARN_ON(dev_priv
->psr
.active
);
2235 lockdep_assert_held(&dev_priv
->psr
.lock
);
2237 /* Enable/Re-enable PSR on the host */
2238 intel_edp_psr_enable_source(intel_dp
);
2240 dev_priv
->psr
.active
= true;
2243 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
2245 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2248 if (!HAS_PSR(dev
)) {
2249 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2253 if (!is_edp_psr(intel_dp
)) {
2254 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2258 mutex_lock(&dev_priv
->psr
.lock
);
2259 if (dev_priv
->psr
.enabled
) {
2260 DRM_DEBUG_KMS("PSR already in use\n");
2264 if (!intel_edp_psr_match_conditions(intel_dp
))
2267 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
2269 intel_edp_psr_setup_vsc(intel_dp
);
2271 /* Avoid continuous PSR exit by masking memup and hpd */
2272 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
2273 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
2275 /* Enable PSR on the panel */
2276 intel_edp_psr_enable_sink(intel_dp
);
2278 dev_priv
->psr
.enabled
= intel_dp
;
2280 mutex_unlock(&dev_priv
->psr
.lock
);
2283 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
2285 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2288 mutex_lock(&dev_priv
->psr
.lock
);
2289 if (!dev_priv
->psr
.enabled
) {
2290 mutex_unlock(&dev_priv
->psr
.lock
);
2294 if (dev_priv
->psr
.active
) {
2295 I915_WRITE(EDP_PSR_CTL(dev
),
2296 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
2298 /* Wait till PSR is idle */
2299 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
2300 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
2301 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2303 dev_priv
->psr
.active
= false;
2305 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2308 dev_priv
->psr
.enabled
= NULL
;
2309 mutex_unlock(&dev_priv
->psr
.lock
);
2311 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
2314 static void intel_edp_psr_work(struct work_struct
*work
)
2316 struct drm_i915_private
*dev_priv
=
2317 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
2318 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
2320 /* We have to make sure PSR is ready for re-enable
2321 * otherwise it keeps disabled until next full enable/disable cycle.
2322 * PSR might take some time to get fully disabled
2323 * and be ready for re-enable.
2325 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv
->dev
)) &
2326 EDP_PSR_STATUS_STATE_MASK
) == 0, 50)) {
2327 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2331 mutex_lock(&dev_priv
->psr
.lock
);
2332 intel_dp
= dev_priv
->psr
.enabled
;
2338 * The delayed work can race with an invalidate hence we need to
2339 * recheck. Since psr_flush first clears this and then reschedules we
2340 * won't ever miss a flush when bailing out here.
2342 if (dev_priv
->psr
.busy_frontbuffer_bits
)
2345 intel_edp_psr_do_enable(intel_dp
);
2347 mutex_unlock(&dev_priv
->psr
.lock
);
2350 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
2352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2354 if (dev_priv
->psr
.active
) {
2355 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
2357 WARN_ON(!(val
& EDP_PSR_ENABLE
));
2359 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
2361 dev_priv
->psr
.active
= false;
2366 void intel_edp_psr_invalidate(struct drm_device
*dev
,
2367 unsigned frontbuffer_bits
)
2369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2370 struct drm_crtc
*crtc
;
2373 mutex_lock(&dev_priv
->psr
.lock
);
2374 if (!dev_priv
->psr
.enabled
) {
2375 mutex_unlock(&dev_priv
->psr
.lock
);
2379 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2380 pipe
= to_intel_crtc(crtc
)->pipe
;
2382 intel_edp_psr_do_exit(dev
);
2384 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
2386 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
2387 mutex_unlock(&dev_priv
->psr
.lock
);
2390 void intel_edp_psr_flush(struct drm_device
*dev
,
2391 unsigned frontbuffer_bits
)
2393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2394 struct drm_crtc
*crtc
;
2397 mutex_lock(&dev_priv
->psr
.lock
);
2398 if (!dev_priv
->psr
.enabled
) {
2399 mutex_unlock(&dev_priv
->psr
.lock
);
2403 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2404 pipe
= to_intel_crtc(crtc
)->pipe
;
2405 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2408 * On Haswell sprite plane updates don't result in a psr invalidating
2409 * signal in the hardware. Which means we need to manually fake this in
2410 * software for all flushes, not just when we've seen a preceding
2411 * invalidation through frontbuffer rendering.
2413 if (IS_HASWELL(dev
) &&
2414 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2415 intel_edp_psr_do_exit(dev
);
2417 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2418 schedule_delayed_work(&dev_priv
->psr
.work
,
2419 msecs_to_jiffies(100));
2420 mutex_unlock(&dev_priv
->psr
.lock
);
2423 void intel_edp_psr_init(struct drm_device
*dev
)
2425 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2427 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2428 mutex_init(&dev_priv
->psr
.lock
);
2431 static void intel_disable_dp(struct intel_encoder
*encoder
)
2433 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2434 struct drm_device
*dev
= encoder
->base
.dev
;
2436 /* Make sure the panel is off before trying to change the mode. But also
2437 * ensure that we have vdd while we switch off the panel. */
2438 intel_edp_panel_vdd_on(intel_dp
);
2439 intel_edp_backlight_off(intel_dp
);
2440 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2441 intel_edp_panel_off(intel_dp
);
2443 /* disable the port before the pipe on g4x */
2444 if (INTEL_INFO(dev
)->gen
< 5)
2445 intel_dp_link_down(intel_dp
);
2448 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2450 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2451 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2453 intel_dp_link_down(intel_dp
);
2455 ironlake_edp_pll_off(intel_dp
);
2458 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2460 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2462 intel_dp_link_down(intel_dp
);
2465 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2467 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2468 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2469 struct drm_device
*dev
= encoder
->base
.dev
;
2470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2471 struct intel_crtc
*intel_crtc
=
2472 to_intel_crtc(encoder
->base
.crtc
);
2473 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2474 enum pipe pipe
= intel_crtc
->pipe
;
2477 intel_dp_link_down(intel_dp
);
2479 mutex_lock(&dev_priv
->dpio_lock
);
2481 /* Propagate soft reset to data lane reset */
2482 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2483 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2484 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2486 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2487 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2488 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2490 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2491 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2492 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2494 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2495 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2496 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2498 mutex_unlock(&dev_priv
->dpio_lock
);
2502 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2504 uint8_t dp_train_pat
)
2506 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2507 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2509 enum port port
= intel_dig_port
->port
;
2512 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2514 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2515 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2517 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2519 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2520 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2521 case DP_TRAINING_PATTERN_DISABLE
:
2522 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2525 case DP_TRAINING_PATTERN_1
:
2526 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2528 case DP_TRAINING_PATTERN_2
:
2529 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2531 case DP_TRAINING_PATTERN_3
:
2532 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2535 I915_WRITE(DP_TP_CTL(port
), temp
);
2537 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2538 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2540 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2541 case DP_TRAINING_PATTERN_DISABLE
:
2542 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2544 case DP_TRAINING_PATTERN_1
:
2545 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2547 case DP_TRAINING_PATTERN_2
:
2548 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2550 case DP_TRAINING_PATTERN_3
:
2551 DRM_ERROR("DP training pattern 3 not supported\n");
2552 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2557 if (IS_CHERRYVIEW(dev
))
2558 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2560 *DP
&= ~DP_LINK_TRAIN_MASK
;
2562 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2563 case DP_TRAINING_PATTERN_DISABLE
:
2564 *DP
|= DP_LINK_TRAIN_OFF
;
2566 case DP_TRAINING_PATTERN_1
:
2567 *DP
|= DP_LINK_TRAIN_PAT_1
;
2569 case DP_TRAINING_PATTERN_2
:
2570 *DP
|= DP_LINK_TRAIN_PAT_2
;
2572 case DP_TRAINING_PATTERN_3
:
2573 if (IS_CHERRYVIEW(dev
)) {
2574 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2576 DRM_ERROR("DP training pattern 3 not supported\n");
2577 *DP
|= DP_LINK_TRAIN_PAT_2
;
2584 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2586 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2589 /* enable with pattern 1 (as per spec) */
2590 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2591 DP_TRAINING_PATTERN_1
);
2593 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2594 POSTING_READ(intel_dp
->output_reg
);
2597 * Magic for VLV/CHV. We _must_ first set up the register
2598 * without actually enabling the port, and then do another
2599 * write to enable the port. Otherwise link training will
2600 * fail when the power sequencer is freshly used for this port.
2602 intel_dp
->DP
|= DP_PORT_EN
;
2604 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2605 POSTING_READ(intel_dp
->output_reg
);
2608 static void intel_enable_dp(struct intel_encoder
*encoder
)
2610 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2611 struct drm_device
*dev
= encoder
->base
.dev
;
2612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2613 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2615 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2620 if (IS_VALLEYVIEW(dev
))
2621 vlv_init_panel_power_sequencer(intel_dp
);
2623 intel_dp_enable_port(intel_dp
);
2625 edp_panel_vdd_on(intel_dp
);
2626 edp_panel_on(intel_dp
);
2627 edp_panel_vdd_off(intel_dp
, true);
2629 pps_unlock(intel_dp
);
2631 if (IS_VALLEYVIEW(dev
))
2632 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
));
2634 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2635 intel_dp_start_link_train(intel_dp
);
2636 intel_dp_complete_link_train(intel_dp
);
2637 intel_dp_stop_link_train(intel_dp
);
2640 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2642 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2644 intel_enable_dp(encoder
);
2645 intel_edp_backlight_on(intel_dp
);
2648 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2650 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2652 intel_edp_backlight_on(intel_dp
);
2655 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2657 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2658 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2660 intel_dp_prepare(encoder
);
2662 /* Only ilk+ has port A */
2663 if (dport
->port
== PORT_A
) {
2664 ironlake_set_pll_cpu_edp(intel_dp
);
2665 ironlake_edp_pll_on(intel_dp
);
2669 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2671 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2672 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2673 enum pipe pipe
= intel_dp
->pps_pipe
;
2674 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2676 edp_panel_vdd_off_sync(intel_dp
);
2679 * VLV seems to get confused when multiple power seqeuencers
2680 * have the same port selected (even if only one has power/vdd
2681 * enabled). The failure manifests as vlv_wait_port_ready() failing
2682 * CHV on the other hand doesn't seem to mind having the same port
2683 * selected in multiple power seqeuencers, but let's clear the
2684 * port select always when logically disconnecting a power sequencer
2687 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2688 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2689 I915_WRITE(pp_on_reg
, 0);
2690 POSTING_READ(pp_on_reg
);
2692 intel_dp
->pps_pipe
= INVALID_PIPE
;
2695 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2699 struct intel_encoder
*encoder
;
2701 lockdep_assert_held(&dev_priv
->pps_mutex
);
2703 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2706 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2708 struct intel_dp
*intel_dp
;
2711 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2714 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2715 port
= dp_to_dig_port(intel_dp
)->port
;
2717 if (intel_dp
->pps_pipe
!= pipe
)
2720 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2721 pipe_name(pipe
), port_name(port
));
2723 /* make sure vdd is off before we steal it */
2724 vlv_detach_power_sequencer(intel_dp
);
2728 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2730 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2731 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2732 struct drm_device
*dev
= encoder
->base
.dev
;
2733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2734 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2736 lockdep_assert_held(&dev_priv
->pps_mutex
);
2738 if (!is_edp(intel_dp
))
2741 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2745 * If another power sequencer was being used on this
2746 * port previously make sure to turn off vdd there while
2747 * we still have control of it.
2749 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2750 vlv_detach_power_sequencer(intel_dp
);
2753 * We may be stealing the power
2754 * sequencer from another port.
2756 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2758 /* now it's all ours */
2759 intel_dp
->pps_pipe
= crtc
->pipe
;
2761 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2762 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2764 /* init power sequencer on this pipe and port */
2765 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2766 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2769 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2771 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2772 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2773 struct drm_device
*dev
= encoder
->base
.dev
;
2774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2775 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2776 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2777 int pipe
= intel_crtc
->pipe
;
2780 mutex_lock(&dev_priv
->dpio_lock
);
2782 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2789 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2790 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2791 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2793 mutex_unlock(&dev_priv
->dpio_lock
);
2795 intel_enable_dp(encoder
);
2798 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2800 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2801 struct drm_device
*dev
= encoder
->base
.dev
;
2802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2803 struct intel_crtc
*intel_crtc
=
2804 to_intel_crtc(encoder
->base
.crtc
);
2805 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2806 int pipe
= intel_crtc
->pipe
;
2808 intel_dp_prepare(encoder
);
2810 /* Program Tx lane resets to default */
2811 mutex_lock(&dev_priv
->dpio_lock
);
2812 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2813 DPIO_PCS_TX_LANE2_RESET
|
2814 DPIO_PCS_TX_LANE1_RESET
);
2815 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2816 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2817 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2818 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2819 DPIO_PCS_CLK_SOFT_RESET
);
2821 /* Fix up inter-pair skew failure */
2822 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2823 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2824 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2825 mutex_unlock(&dev_priv
->dpio_lock
);
2828 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2830 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2831 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2832 struct drm_device
*dev
= encoder
->base
.dev
;
2833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2834 struct intel_crtc
*intel_crtc
=
2835 to_intel_crtc(encoder
->base
.crtc
);
2836 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2837 int pipe
= intel_crtc
->pipe
;
2841 mutex_lock(&dev_priv
->dpio_lock
);
2843 /* allow hardware to manage TX FIFO reset source */
2844 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2845 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2846 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2848 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2849 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2850 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2852 /* Deassert soft data lane reset*/
2853 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2854 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2855 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2857 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2858 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2859 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2861 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2862 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2863 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2865 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2866 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2867 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2869 /* Program Tx lane latency optimal setting*/
2870 for (i
= 0; i
< 4; i
++) {
2871 /* Set the latency optimal bit */
2872 data
= (i
== 1) ? 0x0 : 0x6;
2873 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2874 data
<< DPIO_FRC_LATENCY_SHFIT
);
2876 /* Set the upar bit */
2877 data
= (i
== 1) ? 0x0 : 0x1;
2878 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2879 data
<< DPIO_UPAR_SHIFT
);
2882 /* Data lane stagger programming */
2883 /* FIXME: Fix up value only after power analysis */
2885 mutex_unlock(&dev_priv
->dpio_lock
);
2887 intel_enable_dp(encoder
);
2890 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2892 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2893 struct drm_device
*dev
= encoder
->base
.dev
;
2894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2895 struct intel_crtc
*intel_crtc
=
2896 to_intel_crtc(encoder
->base
.crtc
);
2897 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2898 enum pipe pipe
= intel_crtc
->pipe
;
2901 intel_dp_prepare(encoder
);
2903 mutex_lock(&dev_priv
->dpio_lock
);
2905 /* program left/right clock distribution */
2906 if (pipe
!= PIPE_B
) {
2907 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2908 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2910 val
|= CHV_BUFLEFTENA1_FORCE
;
2912 val
|= CHV_BUFRIGHTENA1_FORCE
;
2913 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2915 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2916 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2918 val
|= CHV_BUFLEFTENA2_FORCE
;
2920 val
|= CHV_BUFRIGHTENA2_FORCE
;
2921 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2924 /* program clock channel usage */
2925 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2926 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2928 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2930 val
|= CHV_PCS_USEDCLKCHANNEL
;
2931 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2933 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2934 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2936 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2938 val
|= CHV_PCS_USEDCLKCHANNEL
;
2939 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2942 * This a a bit weird since generally CL
2943 * matches the pipe, but here we need to
2944 * pick the CL based on the port.
2946 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2948 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2950 val
|= CHV_CMN_USEDCLKCHANNEL
;
2951 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2953 mutex_unlock(&dev_priv
->dpio_lock
);
2957 * Native read with retry for link status and receiver capability reads for
2958 * cases where the sink may still be asleep.
2960 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2961 * supposed to retry 3 times per the spec.
2964 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2965 void *buffer
, size_t size
)
2970 for (i
= 0; i
< 3; i
++) {
2971 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2981 * Fetch AUX CH registers 0x202 - 0x207 which contain
2982 * link status information
2985 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2987 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2990 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2993 /* These are source-specific values. */
2995 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2997 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2998 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3000 if (INTEL_INFO(dev
)->gen
>= 9)
3001 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3002 else if (IS_VALLEYVIEW(dev
))
3003 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3004 else if (IS_GEN7(dev
) && port
== PORT_A
)
3005 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3006 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
3007 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3009 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3013 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3015 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3016 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3018 if (INTEL_INFO(dev
)->gen
>= 9) {
3019 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3021 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3023 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3024 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3025 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3027 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3029 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3030 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3034 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3036 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3039 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3041 } else if (IS_VALLEYVIEW(dev
)) {
3042 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3044 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3046 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3048 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3051 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3053 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3054 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3056 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3059 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3061 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3064 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3065 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3066 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3068 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3070 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3073 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3078 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
3080 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3082 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3083 struct intel_crtc
*intel_crtc
=
3084 to_intel_crtc(dport
->base
.base
.crtc
);
3085 unsigned long demph_reg_value
, preemph_reg_value
,
3086 uniqtranscale_reg_value
;
3087 uint8_t train_set
= intel_dp
->train_set
[0];
3088 enum dpio_channel port
= vlv_dport_to_channel(dport
);
3089 int pipe
= intel_crtc
->pipe
;
3091 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3092 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3093 preemph_reg_value
= 0x0004000;
3094 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3096 demph_reg_value
= 0x2B405555;
3097 uniqtranscale_reg_value
= 0x552AB83A;
3099 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3100 demph_reg_value
= 0x2B404040;
3101 uniqtranscale_reg_value
= 0x5548B83A;
3103 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3104 demph_reg_value
= 0x2B245555;
3105 uniqtranscale_reg_value
= 0x5560B83A;
3107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3108 demph_reg_value
= 0x2B405555;
3109 uniqtranscale_reg_value
= 0x5598DA3A;
3115 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3116 preemph_reg_value
= 0x0002000;
3117 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3118 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3119 demph_reg_value
= 0x2B404040;
3120 uniqtranscale_reg_value
= 0x5552B83A;
3122 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3123 demph_reg_value
= 0x2B404848;
3124 uniqtranscale_reg_value
= 0x5580B83A;
3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3127 demph_reg_value
= 0x2B404040;
3128 uniqtranscale_reg_value
= 0x55ADDA3A;
3134 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3135 preemph_reg_value
= 0x0000000;
3136 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3137 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3138 demph_reg_value
= 0x2B305555;
3139 uniqtranscale_reg_value
= 0x5570B83A;
3141 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3142 demph_reg_value
= 0x2B2B4040;
3143 uniqtranscale_reg_value
= 0x55ADDA3A;
3149 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3150 preemph_reg_value
= 0x0006000;
3151 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3152 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3153 demph_reg_value
= 0x1B405555;
3154 uniqtranscale_reg_value
= 0x55ADDA3A;
3164 mutex_lock(&dev_priv
->dpio_lock
);
3165 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3166 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3167 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3168 uniqtranscale_reg_value
);
3169 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3170 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3171 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3172 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3173 mutex_unlock(&dev_priv
->dpio_lock
);
3178 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
3180 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3182 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3183 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3184 u32 deemph_reg_value
, margin_reg_value
, val
;
3185 uint8_t train_set
= intel_dp
->train_set
[0];
3186 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3187 enum pipe pipe
= intel_crtc
->pipe
;
3190 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3191 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3192 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3194 deemph_reg_value
= 128;
3195 margin_reg_value
= 52;
3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3198 deemph_reg_value
= 128;
3199 margin_reg_value
= 77;
3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3202 deemph_reg_value
= 128;
3203 margin_reg_value
= 102;
3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3206 deemph_reg_value
= 128;
3207 margin_reg_value
= 154;
3208 /* FIXME extra to set for 1200 */
3214 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3215 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3217 deemph_reg_value
= 85;
3218 margin_reg_value
= 78;
3220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3221 deemph_reg_value
= 85;
3222 margin_reg_value
= 116;
3224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3225 deemph_reg_value
= 85;
3226 margin_reg_value
= 154;
3232 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3233 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3234 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3235 deemph_reg_value
= 64;
3236 margin_reg_value
= 104;
3238 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3239 deemph_reg_value
= 64;
3240 margin_reg_value
= 154;
3246 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3247 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3249 deemph_reg_value
= 43;
3250 margin_reg_value
= 154;
3260 mutex_lock(&dev_priv
->dpio_lock
);
3262 /* Clear calc init */
3263 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3264 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3265 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3266 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3267 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3269 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3270 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3271 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3272 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3273 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3275 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3276 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3277 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3278 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3280 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3281 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3282 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3283 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3285 /* Program swing deemph */
3286 for (i
= 0; i
< 4; i
++) {
3287 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3288 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3289 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3290 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3293 /* Program swing margin */
3294 for (i
= 0; i
< 4; i
++) {
3295 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3296 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3297 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3298 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3301 /* Disable unique transition scale */
3302 for (i
= 0; i
< 4; i
++) {
3303 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3304 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3305 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3308 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3309 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3310 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3311 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3314 * The document said it needs to set bit 27 for ch0 and bit 26
3315 * for ch1. Might be a typo in the doc.
3316 * For now, for this unique transition scale selection, set bit
3317 * 27 for ch0 and ch1.
3319 for (i
= 0; i
< 4; i
++) {
3320 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3321 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3322 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3325 for (i
= 0; i
< 4; i
++) {
3326 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3327 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3328 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3329 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3333 /* Start swing calculation */
3334 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3335 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3336 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3338 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3339 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3340 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3343 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3344 val
|= DPIO_LRC_BYPASS
;
3345 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3347 mutex_unlock(&dev_priv
->dpio_lock
);
3353 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3354 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3359 uint8_t voltage_max
;
3360 uint8_t preemph_max
;
3362 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3363 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3364 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3372 voltage_max
= intel_dp_voltage_max(intel_dp
);
3373 if (v
>= voltage_max
)
3374 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3376 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3377 if (p
>= preemph_max
)
3378 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3380 for (lane
= 0; lane
< 4; lane
++)
3381 intel_dp
->train_set
[lane
] = v
| p
;
3385 intel_gen4_signal_levels(uint8_t train_set
)
3387 uint32_t signal_levels
= 0;
3389 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3392 signal_levels
|= DP_VOLTAGE_0_4
;
3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3395 signal_levels
|= DP_VOLTAGE_0_6
;
3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3398 signal_levels
|= DP_VOLTAGE_0_8
;
3400 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3401 signal_levels
|= DP_VOLTAGE_1_2
;
3404 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3405 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3407 signal_levels
|= DP_PRE_EMPHASIS_0
;
3409 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3410 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3412 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3413 signal_levels
|= DP_PRE_EMPHASIS_6
;
3415 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3416 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3419 return signal_levels
;
3422 /* Gen6's DP voltage swing and pre-emphasis control */
3424 intel_gen6_edp_signal_levels(uint8_t train_set
)
3426 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3427 DP_TRAIN_PRE_EMPHASIS_MASK
);
3428 switch (signal_levels
) {
3429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3431 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3432 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3433 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3434 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3435 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3436 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3437 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3438 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3439 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3440 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3441 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3442 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3444 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3445 "0x%x\n", signal_levels
);
3446 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3450 /* Gen7's DP voltage swing and pre-emphasis control */
3452 intel_gen7_edp_signal_levels(uint8_t train_set
)
3454 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3455 DP_TRAIN_PRE_EMPHASIS_MASK
);
3456 switch (signal_levels
) {
3457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3458 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3460 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3462 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3464 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3465 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3466 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3467 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3469 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3470 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3471 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3472 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3475 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3476 "0x%x\n", signal_levels
);
3477 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3481 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3483 intel_hsw_signal_levels(uint8_t train_set
)
3485 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3486 DP_TRAIN_PRE_EMPHASIS_MASK
);
3487 switch (signal_levels
) {
3488 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3489 return DDI_BUF_TRANS_SELECT(0);
3490 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3491 return DDI_BUF_TRANS_SELECT(1);
3492 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3493 return DDI_BUF_TRANS_SELECT(2);
3494 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3495 return DDI_BUF_TRANS_SELECT(3);
3497 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3498 return DDI_BUF_TRANS_SELECT(4);
3499 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3500 return DDI_BUF_TRANS_SELECT(5);
3501 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3502 return DDI_BUF_TRANS_SELECT(6);
3504 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3505 return DDI_BUF_TRANS_SELECT(7);
3506 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3507 return DDI_BUF_TRANS_SELECT(8);
3509 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3510 "0x%x\n", signal_levels
);
3511 return DDI_BUF_TRANS_SELECT(0);
3515 /* Properly updates "DP" with the correct signal levels. */
3517 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3519 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3520 enum port port
= intel_dig_port
->port
;
3521 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3522 uint32_t signal_levels
, mask
;
3523 uint8_t train_set
= intel_dp
->train_set
[0];
3525 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
3526 signal_levels
= intel_hsw_signal_levels(train_set
);
3527 mask
= DDI_BUF_EMP_MASK
;
3528 } else if (IS_CHERRYVIEW(dev
)) {
3529 signal_levels
= intel_chv_signal_levels(intel_dp
);
3531 } else if (IS_VALLEYVIEW(dev
)) {
3532 signal_levels
= intel_vlv_signal_levels(intel_dp
);
3534 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3535 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
3536 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3537 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3538 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
3539 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3541 signal_levels
= intel_gen4_signal_levels(train_set
);
3542 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3545 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3547 *DP
= (*DP
& ~mask
) | signal_levels
;
3551 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3553 uint8_t dp_train_pat
)
3555 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3556 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3558 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3561 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3563 I915_WRITE(intel_dp
->output_reg
, *DP
);
3564 POSTING_READ(intel_dp
->output_reg
);
3566 buf
[0] = dp_train_pat
;
3567 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3568 DP_TRAINING_PATTERN_DISABLE
) {
3569 /* don't write DP_TRAINING_LANEx_SET on disable */
3572 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3573 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3574 len
= intel_dp
->lane_count
+ 1;
3577 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3584 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3585 uint8_t dp_train_pat
)
3587 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3588 intel_dp_set_signal_levels(intel_dp
, DP
);
3589 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3593 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3594 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3596 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3597 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3601 intel_get_adjust_train(intel_dp
, link_status
);
3602 intel_dp_set_signal_levels(intel_dp
, DP
);
3604 I915_WRITE(intel_dp
->output_reg
, *DP
);
3605 POSTING_READ(intel_dp
->output_reg
);
3607 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3608 intel_dp
->train_set
, intel_dp
->lane_count
);
3610 return ret
== intel_dp
->lane_count
;
3613 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3615 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3616 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3618 enum port port
= intel_dig_port
->port
;
3624 val
= I915_READ(DP_TP_CTL(port
));
3625 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3626 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3627 I915_WRITE(DP_TP_CTL(port
), val
);
3630 * On PORT_A we can have only eDP in SST mode. There the only reason
3631 * we need to set idle transmission mode is to work around a HW issue
3632 * where we enable the pipe while not in idle link-training mode.
3633 * In this case there is requirement to wait for a minimum number of
3634 * idle patterns to be sent.
3639 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3641 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3644 /* Enable corresponding port and start training pattern 1 */
3646 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3648 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3649 struct drm_device
*dev
= encoder
->dev
;
3652 int voltage_tries
, loop_tries
;
3653 uint32_t DP
= intel_dp
->DP
;
3654 uint8_t link_config
[2];
3657 intel_ddi_prepare_link_retrain(encoder
);
3659 /* Write the link configuration data */
3660 link_config
[0] = intel_dp
->link_bw
;
3661 link_config
[1] = intel_dp
->lane_count
;
3662 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3663 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3664 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3667 link_config
[1] = DP_SET_ANSI_8B10B
;
3668 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3672 /* clock recovery */
3673 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3674 DP_TRAINING_PATTERN_1
|
3675 DP_LINK_SCRAMBLING_DISABLE
)) {
3676 DRM_ERROR("failed to enable link training\n");
3684 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3686 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3687 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3688 DRM_ERROR("failed to get link status\n");
3692 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3693 DRM_DEBUG_KMS("clock recovery OK\n");
3697 /* Check to see if we've tried the max voltage */
3698 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3699 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3701 if (i
== intel_dp
->lane_count
) {
3703 if (loop_tries
== 5) {
3704 DRM_ERROR("too many full retries, give up\n");
3707 intel_dp_reset_link_train(intel_dp
, &DP
,
3708 DP_TRAINING_PATTERN_1
|
3709 DP_LINK_SCRAMBLING_DISABLE
);
3714 /* Check to see if we've tried the same voltage 5 times */
3715 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3717 if (voltage_tries
== 5) {
3718 DRM_ERROR("too many voltage retries, give up\n");
3723 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3725 /* Update training set as requested by target */
3726 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3727 DRM_ERROR("failed to update link training\n");
3736 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3738 bool channel_eq
= false;
3739 int tries
, cr_tries
;
3740 uint32_t DP
= intel_dp
->DP
;
3741 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3743 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3744 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3745 training_pattern
= DP_TRAINING_PATTERN_3
;
3747 /* channel equalization */
3748 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3750 DP_LINK_SCRAMBLING_DISABLE
)) {
3751 DRM_ERROR("failed to start channel equalization\n");
3759 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3762 DRM_ERROR("failed to train DP, aborting\n");
3766 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3767 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3768 DRM_ERROR("failed to get link status\n");
3772 /* Make sure clock is still ok */
3773 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3774 intel_dp_start_link_train(intel_dp
);
3775 intel_dp_set_link_train(intel_dp
, &DP
,
3777 DP_LINK_SCRAMBLING_DISABLE
);
3782 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3787 /* Try 5 times, then try clock recovery if that fails */
3789 intel_dp_link_down(intel_dp
);
3790 intel_dp_start_link_train(intel_dp
);
3791 intel_dp_set_link_train(intel_dp
, &DP
,
3793 DP_LINK_SCRAMBLING_DISABLE
);
3799 /* Update training set as requested by target */
3800 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3801 DRM_ERROR("failed to update link training\n");
3807 intel_dp_set_idle_link_train(intel_dp
);
3812 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3816 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3818 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3819 DP_TRAINING_PATTERN_DISABLE
);
3823 intel_dp_link_down(struct intel_dp
*intel_dp
)
3825 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3826 enum port port
= intel_dig_port
->port
;
3827 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3829 struct intel_crtc
*intel_crtc
=
3830 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3831 uint32_t DP
= intel_dp
->DP
;
3833 if (WARN_ON(HAS_DDI(dev
)))
3836 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3839 DRM_DEBUG_KMS("\n");
3841 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3842 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3843 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3845 if (IS_CHERRYVIEW(dev
))
3846 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3848 DP
&= ~DP_LINK_TRAIN_MASK
;
3849 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3851 POSTING_READ(intel_dp
->output_reg
);
3853 if (HAS_PCH_IBX(dev
) &&
3854 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3855 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3857 /* Hardware workaround: leaving our transcoder select
3858 * set to transcoder B while it's off will prevent the
3859 * corresponding HDMI output on transcoder A.
3861 * Combine this with another hardware workaround:
3862 * transcoder select bit can only be cleared while the
3865 DP
&= ~DP_PIPEB_SELECT
;
3866 I915_WRITE(intel_dp
->output_reg
, DP
);
3868 /* Changes to enable or select take place the vblank
3869 * after being written.
3871 if (WARN_ON(crtc
== NULL
)) {
3872 /* We should never try to disable a port without a crtc
3873 * attached. For paranoia keep the code around for a
3875 POSTING_READ(intel_dp
->output_reg
);
3878 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3881 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3882 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3883 POSTING_READ(intel_dp
->output_reg
);
3884 msleep(intel_dp
->panel_power_down_delay
);
3888 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3890 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3891 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3894 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3895 sizeof(intel_dp
->dpcd
)) < 0)
3896 return false; /* aux transfer failed */
3898 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3900 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3901 return false; /* DPCD not present */
3903 /* Check if the panel supports PSR */
3904 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3905 if (is_edp(intel_dp
)) {
3906 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3908 sizeof(intel_dp
->psr_dpcd
));
3909 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3910 dev_priv
->psr
.sink_support
= true;
3911 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3915 /* Training Pattern 3 support */
3916 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3917 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3918 intel_dp
->use_tps3
= true;
3919 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3921 intel_dp
->use_tps3
= false;
3923 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3924 DP_DWN_STRM_PORT_PRESENT
))
3925 return true; /* native DP sink */
3927 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3928 return true; /* no per-port downstream info */
3930 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3931 intel_dp
->downstream_ports
,
3932 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3933 return false; /* downstream port status fetch failed */
3939 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3943 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3946 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3947 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3948 buf
[0], buf
[1], buf
[2]);
3950 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3951 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3952 buf
[0], buf
[1], buf
[2]);
3956 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3960 if (!intel_dp
->can_mst
)
3963 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3966 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3967 if (buf
[0] & DP_MST_CAP
) {
3968 DRM_DEBUG_KMS("Sink is MST capable\n");
3969 intel_dp
->is_mst
= true;
3971 DRM_DEBUG_KMS("Sink is not MST capable\n");
3972 intel_dp
->is_mst
= false;
3976 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3977 return intel_dp
->is_mst
;
3980 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3982 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3983 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3984 struct intel_crtc
*intel_crtc
=
3985 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3990 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3993 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3996 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3999 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4000 buf
| DP_TEST_SINK_START
) < 0)
4003 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
4005 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
4008 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4009 DP_TEST_SINK_MISC
, &buf
) < 0)
4011 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4012 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
4014 if (attempts
== 0) {
4015 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
4019 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
4022 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
4024 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4025 buf
& ~DP_TEST_SINK_START
) < 0)
4032 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4034 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4035 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4036 sink_irq_vector
, 1) == 1;
4040 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4044 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4046 sink_irq_vector
, 14);
4054 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4056 /* NAK by default */
4057 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
4061 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4065 if (intel_dp
->is_mst
) {
4070 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4074 /* check link status - esi[10] = 0x200c */
4075 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4076 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4077 intel_dp_start_link_train(intel_dp
);
4078 intel_dp_complete_link_train(intel_dp
);
4079 intel_dp_stop_link_train(intel_dp
);
4082 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
4083 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4086 for (retry
= 0; retry
< 3; retry
++) {
4088 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4089 DP_SINK_COUNT_ESI
+1,
4096 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4098 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
4106 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4107 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4108 intel_dp
->is_mst
= false;
4109 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4110 /* send a hotplug event */
4111 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4118 * According to DP spec
4121 * 2. Configure link according to Receiver Capabilities
4122 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4123 * 4. Check link status on receipt of hot-plug interrupt
4126 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4128 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4129 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4131 u8 link_status
[DP_LINK_STATUS_SIZE
];
4133 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4135 if (!intel_encoder
->connectors_active
)
4138 if (WARN_ON(!intel_encoder
->base
.crtc
))
4141 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4144 /* Try to read receiver status if the link appears to be up */
4145 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4149 /* Now read the DPCD to see if it's actually running */
4150 if (!intel_dp_get_dpcd(intel_dp
)) {
4154 /* Try to read the source of the interrupt */
4155 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4156 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4157 /* Clear interrupt source */
4158 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4159 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4162 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4163 intel_dp_handle_test_request(intel_dp
);
4164 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4165 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4168 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4169 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4170 intel_encoder
->base
.name
);
4171 intel_dp_start_link_train(intel_dp
);
4172 intel_dp_complete_link_train(intel_dp
);
4173 intel_dp_stop_link_train(intel_dp
);
4177 /* XXX this is probably wrong for multiple downstream ports */
4178 static enum drm_connector_status
4179 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4181 uint8_t *dpcd
= intel_dp
->dpcd
;
4184 if (!intel_dp_get_dpcd(intel_dp
))
4185 return connector_status_disconnected
;
4187 /* if there's no downstream port, we're done */
4188 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4189 return connector_status_connected
;
4191 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4192 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4193 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4196 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4198 return connector_status_unknown
;
4200 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4201 : connector_status_disconnected
;
4204 /* If no HPD, poke DDC gently */
4205 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4206 return connector_status_connected
;
4208 /* Well we tried, say unknown for unreliable port types */
4209 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4210 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4211 if (type
== DP_DS_PORT_TYPE_VGA
||
4212 type
== DP_DS_PORT_TYPE_NON_EDID
)
4213 return connector_status_unknown
;
4215 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4216 DP_DWN_STRM_PORT_TYPE_MASK
;
4217 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4218 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4219 return connector_status_unknown
;
4222 /* Anything else is out of spec, warn and ignore */
4223 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4224 return connector_status_disconnected
;
4227 static enum drm_connector_status
4228 edp_detect(struct intel_dp
*intel_dp
)
4230 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4231 enum drm_connector_status status
;
4233 status
= intel_panel_detect(dev
);
4234 if (status
== connector_status_unknown
)
4235 status
= connector_status_connected
;
4240 static enum drm_connector_status
4241 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4243 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4245 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4247 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4248 return connector_status_disconnected
;
4250 return intel_dp_detect_dpcd(intel_dp
);
4253 static int g4x_digital_port_connected(struct drm_device
*dev
,
4254 struct intel_digital_port
*intel_dig_port
)
4256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4259 if (IS_VALLEYVIEW(dev
)) {
4260 switch (intel_dig_port
->port
) {
4262 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4265 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4268 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4274 switch (intel_dig_port
->port
) {
4276 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4279 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4282 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4289 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4294 static enum drm_connector_status
4295 g4x_dp_detect(struct intel_dp
*intel_dp
)
4297 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4298 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4301 /* Can't disconnect eDP, but you can close the lid... */
4302 if (is_edp(intel_dp
)) {
4303 enum drm_connector_status status
;
4305 status
= intel_panel_detect(dev
);
4306 if (status
== connector_status_unknown
)
4307 status
= connector_status_connected
;
4311 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4313 return connector_status_unknown
;
4315 return connector_status_disconnected
;
4317 return intel_dp_detect_dpcd(intel_dp
);
4320 static struct edid
*
4321 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4323 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4325 /* use cached edid if we have one */
4326 if (intel_connector
->edid
) {
4328 if (IS_ERR(intel_connector
->edid
))
4331 return drm_edid_duplicate(intel_connector
->edid
);
4333 return drm_get_edid(&intel_connector
->base
,
4334 &intel_dp
->aux
.ddc
);
4338 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4340 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4343 edid
= intel_dp_get_edid(intel_dp
);
4344 intel_connector
->detect_edid
= edid
;
4346 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4347 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4349 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4353 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4355 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4357 kfree(intel_connector
->detect_edid
);
4358 intel_connector
->detect_edid
= NULL
;
4360 intel_dp
->has_audio
= false;
4363 static enum intel_display_power_domain
4364 intel_dp_power_get(struct intel_dp
*dp
)
4366 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4367 enum intel_display_power_domain power_domain
;
4369 power_domain
= intel_display_port_power_domain(encoder
);
4370 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4372 return power_domain
;
4376 intel_dp_power_put(struct intel_dp
*dp
,
4377 enum intel_display_power_domain power_domain
)
4379 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4380 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4383 static enum drm_connector_status
4384 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4386 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4387 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4388 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4389 struct drm_device
*dev
= connector
->dev
;
4390 enum drm_connector_status status
;
4391 enum intel_display_power_domain power_domain
;
4394 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4395 connector
->base
.id
, connector
->name
);
4396 intel_dp_unset_edid(intel_dp
);
4398 if (intel_dp
->is_mst
) {
4399 /* MST devices are disconnected from a monitor POV */
4400 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4401 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4402 return connector_status_disconnected
;
4405 power_domain
= intel_dp_power_get(intel_dp
);
4407 /* Can't disconnect eDP, but you can close the lid... */
4408 if (is_edp(intel_dp
))
4409 status
= edp_detect(intel_dp
);
4410 else if (HAS_PCH_SPLIT(dev
))
4411 status
= ironlake_dp_detect(intel_dp
);
4413 status
= g4x_dp_detect(intel_dp
);
4414 if (status
!= connector_status_connected
)
4417 intel_dp_probe_oui(intel_dp
);
4419 ret
= intel_dp_probe_mst(intel_dp
);
4421 /* if we are in MST mode then this connector
4422 won't appear connected or have anything with EDID on it */
4423 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4424 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4425 status
= connector_status_disconnected
;
4429 intel_dp_set_edid(intel_dp
);
4431 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4432 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4433 status
= connector_status_connected
;
4436 intel_dp_power_put(intel_dp
, power_domain
);
4441 intel_dp_force(struct drm_connector
*connector
)
4443 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4444 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4445 enum intel_display_power_domain power_domain
;
4447 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4448 connector
->base
.id
, connector
->name
);
4449 intel_dp_unset_edid(intel_dp
);
4451 if (connector
->status
!= connector_status_connected
)
4454 power_domain
= intel_dp_power_get(intel_dp
);
4456 intel_dp_set_edid(intel_dp
);
4458 intel_dp_power_put(intel_dp
, power_domain
);
4460 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4461 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4464 static int intel_dp_get_modes(struct drm_connector
*connector
)
4466 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4469 edid
= intel_connector
->detect_edid
;
4471 int ret
= intel_connector_update_modes(connector
, edid
);
4476 /* if eDP has no EDID, fall back to fixed mode */
4477 if (is_edp(intel_attached_dp(connector
)) &&
4478 intel_connector
->panel
.fixed_mode
) {
4479 struct drm_display_mode
*mode
;
4481 mode
= drm_mode_duplicate(connector
->dev
,
4482 intel_connector
->panel
.fixed_mode
);
4484 drm_mode_probed_add(connector
, mode
);
4493 intel_dp_detect_audio(struct drm_connector
*connector
)
4495 bool has_audio
= false;
4498 edid
= to_intel_connector(connector
)->detect_edid
;
4500 has_audio
= drm_detect_monitor_audio(edid
);
4506 intel_dp_set_property(struct drm_connector
*connector
,
4507 struct drm_property
*property
,
4510 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4511 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4512 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4513 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4516 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4520 if (property
== dev_priv
->force_audio_property
) {
4524 if (i
== intel_dp
->force_audio
)
4527 intel_dp
->force_audio
= i
;
4529 if (i
== HDMI_AUDIO_AUTO
)
4530 has_audio
= intel_dp_detect_audio(connector
);
4532 has_audio
= (i
== HDMI_AUDIO_ON
);
4534 if (has_audio
== intel_dp
->has_audio
)
4537 intel_dp
->has_audio
= has_audio
;
4541 if (property
== dev_priv
->broadcast_rgb_property
) {
4542 bool old_auto
= intel_dp
->color_range_auto
;
4543 uint32_t old_range
= intel_dp
->color_range
;
4546 case INTEL_BROADCAST_RGB_AUTO
:
4547 intel_dp
->color_range_auto
= true;
4549 case INTEL_BROADCAST_RGB_FULL
:
4550 intel_dp
->color_range_auto
= false;
4551 intel_dp
->color_range
= 0;
4553 case INTEL_BROADCAST_RGB_LIMITED
:
4554 intel_dp
->color_range_auto
= false;
4555 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4561 if (old_auto
== intel_dp
->color_range_auto
&&
4562 old_range
== intel_dp
->color_range
)
4568 if (is_edp(intel_dp
) &&
4569 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4570 if (val
== DRM_MODE_SCALE_NONE
) {
4571 DRM_DEBUG_KMS("no scaling not supported\n");
4575 if (intel_connector
->panel
.fitting_mode
== val
) {
4576 /* the eDP scaling property is not changed */
4579 intel_connector
->panel
.fitting_mode
= val
;
4587 if (intel_encoder
->base
.crtc
)
4588 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4594 intel_dp_connector_destroy(struct drm_connector
*connector
)
4596 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4598 kfree(intel_connector
->detect_edid
);
4600 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4601 kfree(intel_connector
->edid
);
4603 /* Can't call is_edp() since the encoder may have been destroyed
4605 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4606 intel_panel_fini(&intel_connector
->panel
);
4608 drm_connector_cleanup(connector
);
4612 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4614 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4615 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4617 drm_dp_aux_unregister(&intel_dp
->aux
);
4618 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4619 drm_encoder_cleanup(encoder
);
4620 if (is_edp(intel_dp
)) {
4621 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4623 * vdd might still be enabled do to the delayed vdd off.
4624 * Make sure vdd is actually turned off here.
4627 edp_panel_vdd_off_sync(intel_dp
);
4628 pps_unlock(intel_dp
);
4630 if (intel_dp
->edp_notifier
.notifier_call
) {
4631 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4632 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4635 kfree(intel_dig_port
);
4638 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4640 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4642 if (!is_edp(intel_dp
))
4646 * vdd might still be enabled do to the delayed vdd off.
4647 * Make sure vdd is actually turned off here.
4650 edp_panel_vdd_off_sync(intel_dp
);
4651 pps_unlock(intel_dp
);
4654 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4656 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder
));
4659 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4660 .dpms
= intel_connector_dpms
,
4661 .detect
= intel_dp_detect
,
4662 .force
= intel_dp_force
,
4663 .fill_modes
= drm_helper_probe_single_connector_modes
,
4664 .set_property
= intel_dp_set_property
,
4665 .destroy
= intel_dp_connector_destroy
,
4668 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4669 .get_modes
= intel_dp_get_modes
,
4670 .mode_valid
= intel_dp_mode_valid
,
4671 .best_encoder
= intel_best_encoder
,
4674 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4675 .reset
= intel_dp_encoder_reset
,
4676 .destroy
= intel_dp_encoder_destroy
,
4680 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4686 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4688 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4689 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4690 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4692 enum intel_display_power_domain power_domain
;
4695 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4696 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4698 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4699 port_name(intel_dig_port
->port
),
4700 long_hpd
? "long" : "short");
4702 power_domain
= intel_display_port_power_domain(intel_encoder
);
4703 intel_display_power_get(dev_priv
, power_domain
);
4707 if (HAS_PCH_SPLIT(dev
)) {
4708 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4711 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4715 if (!intel_dp_get_dpcd(intel_dp
)) {
4719 intel_dp_probe_oui(intel_dp
);
4721 if (!intel_dp_probe_mst(intel_dp
))
4725 if (intel_dp
->is_mst
) {
4726 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4730 if (!intel_dp
->is_mst
) {
4732 * we'll check the link status via the normal hot plug path later -
4733 * but for short hpds we should check it now
4735 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4736 intel_dp_check_link_status(intel_dp
);
4737 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4743 /* if we were in MST mode, and device is not there get out of MST mode */
4744 if (intel_dp
->is_mst
) {
4745 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4746 intel_dp
->is_mst
= false;
4747 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4750 intel_display_power_put(dev_priv
, power_domain
);
4755 /* Return which DP Port should be selected for Transcoder DP control */
4757 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4759 struct drm_device
*dev
= crtc
->dev
;
4760 struct intel_encoder
*intel_encoder
;
4761 struct intel_dp
*intel_dp
;
4763 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4764 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4766 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4767 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4768 return intel_dp
->output_reg
;
4774 /* check the VBT to see whether the eDP is on DP-D port */
4775 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4778 union child_device_config
*p_child
;
4780 static const short port_mapping
[] = {
4781 [PORT_B
] = PORT_IDPB
,
4782 [PORT_C
] = PORT_IDPC
,
4783 [PORT_D
] = PORT_IDPD
,
4789 if (!dev_priv
->vbt
.child_dev_num
)
4792 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4793 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4795 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4796 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4797 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4804 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4806 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4808 intel_attach_force_audio_property(connector
);
4809 intel_attach_broadcast_rgb_property(connector
);
4810 intel_dp
->color_range_auto
= true;
4812 if (is_edp(intel_dp
)) {
4813 drm_mode_create_scaling_mode_property(connector
->dev
);
4814 drm_object_attach_property(
4816 connector
->dev
->mode_config
.scaling_mode_property
,
4817 DRM_MODE_SCALE_ASPECT
);
4818 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4822 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4824 intel_dp
->last_power_cycle
= jiffies
;
4825 intel_dp
->last_power_on
= jiffies
;
4826 intel_dp
->last_backlight_off
= jiffies
;
4830 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4831 struct intel_dp
*intel_dp
)
4833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4834 struct edp_power_seq cur
, vbt
, spec
,
4835 *final
= &intel_dp
->pps_delays
;
4836 u32 pp_on
, pp_off
, pp_div
, pp
;
4837 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4839 lockdep_assert_held(&dev_priv
->pps_mutex
);
4841 /* already initialized? */
4842 if (final
->t11_t12
!= 0)
4845 if (HAS_PCH_SPLIT(dev
)) {
4846 pp_ctrl_reg
= PCH_PP_CONTROL
;
4847 pp_on_reg
= PCH_PP_ON_DELAYS
;
4848 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4849 pp_div_reg
= PCH_PP_DIVISOR
;
4851 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4853 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4854 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4855 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4856 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4859 /* Workaround: Need to write PP_CONTROL with the unlock key as
4860 * the very first thing. */
4861 pp
= ironlake_get_pp_control(intel_dp
);
4862 I915_WRITE(pp_ctrl_reg
, pp
);
4864 pp_on
= I915_READ(pp_on_reg
);
4865 pp_off
= I915_READ(pp_off_reg
);
4866 pp_div
= I915_READ(pp_div_reg
);
4868 /* Pull timing values out of registers */
4869 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4870 PANEL_POWER_UP_DELAY_SHIFT
;
4872 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4873 PANEL_LIGHT_ON_DELAY_SHIFT
;
4875 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4876 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4878 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4879 PANEL_POWER_DOWN_DELAY_SHIFT
;
4881 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4882 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4884 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4885 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4887 vbt
= dev_priv
->vbt
.edp_pps
;
4889 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4890 * our hw here, which are all in 100usec. */
4891 spec
.t1_t3
= 210 * 10;
4892 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4893 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4894 spec
.t10
= 500 * 10;
4895 /* This one is special and actually in units of 100ms, but zero
4896 * based in the hw (so we need to add 100 ms). But the sw vbt
4897 * table multiplies it with 1000 to make it in units of 100usec,
4899 spec
.t11_t12
= (510 + 100) * 10;
4901 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4902 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4904 /* Use the max of the register settings and vbt. If both are
4905 * unset, fall back to the spec limits. */
4906 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4908 max(cur.field, vbt.field))
4909 assign_final(t1_t3
);
4913 assign_final(t11_t12
);
4916 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4917 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4918 intel_dp
->backlight_on_delay
= get_delay(t8
);
4919 intel_dp
->backlight_off_delay
= get_delay(t9
);
4920 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4921 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4924 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4925 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4926 intel_dp
->panel_power_cycle_delay
);
4928 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4929 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4933 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4934 struct intel_dp
*intel_dp
)
4936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4937 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4938 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4939 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4940 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4941 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
4943 lockdep_assert_held(&dev_priv
->pps_mutex
);
4945 if (HAS_PCH_SPLIT(dev
)) {
4946 pp_on_reg
= PCH_PP_ON_DELAYS
;
4947 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4948 pp_div_reg
= PCH_PP_DIVISOR
;
4950 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4952 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4953 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4954 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4958 * And finally store the new values in the power sequencer. The
4959 * backlight delays are set to 1 because we do manual waits on them. For
4960 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4961 * we'll end up waiting for the backlight off delay twice: once when we
4962 * do the manual sleep, and once when we disable the panel and wait for
4963 * the PP_STATUS bit to become zero.
4965 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4966 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4967 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4968 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4969 /* Compute the divisor for the pp clock, simply match the Bspec
4971 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4972 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4973 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4975 /* Haswell doesn't have any port selection bits for the panel
4976 * power sequencer any more. */
4977 if (IS_VALLEYVIEW(dev
)) {
4978 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4979 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4981 port_sel
= PANEL_PORT_SELECT_DPA
;
4983 port_sel
= PANEL_PORT_SELECT_DPD
;
4988 I915_WRITE(pp_on_reg
, pp_on
);
4989 I915_WRITE(pp_off_reg
, pp_off
);
4990 I915_WRITE(pp_div_reg
, pp_div
);
4992 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4993 I915_READ(pp_on_reg
),
4994 I915_READ(pp_off_reg
),
4995 I915_READ(pp_div_reg
));
4998 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5001 struct intel_encoder
*encoder
;
5002 struct intel_dp
*intel_dp
= NULL
;
5003 struct intel_crtc_config
*config
= NULL
;
5004 struct intel_crtc
*intel_crtc
= NULL
;
5005 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
5007 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5009 if (refresh_rate
<= 0) {
5010 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5014 if (intel_connector
== NULL
) {
5015 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
5020 * FIXME: This needs proper synchronization with psr state. But really
5021 * hard to tell without seeing the user of this function of this code.
5022 * Check locking and ordering once that lands.
5024 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
5025 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
5029 encoder
= intel_attached_encoder(&intel_connector
->base
);
5030 intel_dp
= enc_to_intel_dp(&encoder
->base
);
5031 intel_crtc
= encoder
->new_crtc
;
5034 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5038 config
= &intel_crtc
->config
;
5040 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
5041 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5045 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
5046 index
= DRRS_LOW_RR
;
5048 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
5050 "DRRS requested for previously set RR...ignoring\n");
5054 if (!intel_crtc
->active
) {
5055 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5059 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
5060 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
5061 val
= I915_READ(reg
);
5062 if (index
> DRRS_HIGH_RR
) {
5063 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5064 intel_dp_set_m_n(intel_crtc
);
5066 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5068 I915_WRITE(reg
, val
);
5072 * mutex taken to ensure that there is no race between differnt
5073 * drrs calls trying to update refresh rate. This scenario may occur
5074 * in future when idleness detection based DRRS in kernel and
5075 * possible calls from user space to set differnt RR are made.
5078 mutex_lock(&intel_dp
->drrs_state
.mutex
);
5080 intel_dp
->drrs_state
.refresh_rate_type
= index
;
5082 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
5084 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5087 static struct drm_display_mode
*
5088 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
5089 struct intel_connector
*intel_connector
,
5090 struct drm_display_mode
*fixed_mode
)
5092 struct drm_connector
*connector
= &intel_connector
->base
;
5093 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5094 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
5095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5096 struct drm_display_mode
*downclock_mode
= NULL
;
5098 if (INTEL_INFO(dev
)->gen
<= 6) {
5099 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5103 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5104 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5108 downclock_mode
= intel_find_panel_downclock
5109 (dev
, fixed_mode
, connector
);
5111 if (!downclock_mode
) {
5112 DRM_DEBUG_KMS("DRRS not supported\n");
5116 dev_priv
->drrs
.connector
= intel_connector
;
5118 mutex_init(&intel_dp
->drrs_state
.mutex
);
5120 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
5122 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
5123 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5124 return downclock_mode
;
5127 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
)
5129 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5131 struct intel_dp
*intel_dp
;
5132 enum intel_display_power_domain power_domain
;
5134 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
5137 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5141 if (!edp_have_panel_vdd(intel_dp
))
5144 * The VDD bit needs a power domain reference, so if the bit is
5145 * already enabled when we boot or resume, grab this reference and
5146 * schedule a vdd off, so we don't hold on to the reference
5149 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5150 power_domain
= intel_display_port_power_domain(intel_encoder
);
5151 intel_display_power_get(dev_priv
, power_domain
);
5153 edp_panel_vdd_schedule_off(intel_dp
);
5155 pps_unlock(intel_dp
);
5158 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5159 struct intel_connector
*intel_connector
)
5161 struct drm_connector
*connector
= &intel_connector
->base
;
5162 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5163 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5164 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5166 struct drm_display_mode
*fixed_mode
= NULL
;
5167 struct drm_display_mode
*downclock_mode
= NULL
;
5169 struct drm_display_mode
*scan
;
5172 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
5174 if (!is_edp(intel_dp
))
5177 intel_edp_panel_vdd_sanitize(intel_encoder
);
5179 /* Cache DPCD and EDID for edp. */
5180 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5183 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5184 dev_priv
->no_aux_handshake
=
5185 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5186 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5188 /* if this fails, presume the device is a ghost */
5189 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5193 /* We now know it's not a ghost, init power sequence regs. */
5195 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5196 pps_unlock(intel_dp
);
5198 mutex_lock(&dev
->mode_config
.mutex
);
5199 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5201 if (drm_add_edid_modes(connector
, edid
)) {
5202 drm_mode_connector_update_edid_property(connector
,
5204 drm_edid_to_eld(connector
, edid
);
5207 edid
= ERR_PTR(-EINVAL
);
5210 edid
= ERR_PTR(-ENOENT
);
5212 intel_connector
->edid
= edid
;
5214 /* prefer fixed mode from EDID if available */
5215 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5216 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5217 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5218 downclock_mode
= intel_dp_drrs_init(
5220 intel_connector
, fixed_mode
);
5225 /* fallback to VBT if available for eDP */
5226 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5227 fixed_mode
= drm_mode_duplicate(dev
,
5228 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5230 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5232 mutex_unlock(&dev
->mode_config
.mutex
);
5234 if (IS_VALLEYVIEW(dev
)) {
5235 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5236 register_reboot_notifier(&intel_dp
->edp_notifier
);
5239 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5240 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5241 intel_panel_setup_backlight(connector
);
5247 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5248 struct intel_connector
*intel_connector
)
5250 struct drm_connector
*connector
= &intel_connector
->base
;
5251 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5252 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5253 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5255 enum port port
= intel_dig_port
->port
;
5258 intel_dp
->pps_pipe
= INVALID_PIPE
;
5260 /* intel_dp vfuncs */
5261 if (INTEL_INFO(dev
)->gen
>= 9)
5262 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5263 else if (IS_VALLEYVIEW(dev
))
5264 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5265 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5266 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5267 else if (HAS_PCH_SPLIT(dev
))
5268 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5270 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5272 if (INTEL_INFO(dev
)->gen
>= 9)
5273 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5275 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5277 /* Preserve the current hw state. */
5278 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5279 intel_dp
->attached_connector
= intel_connector
;
5281 if (intel_dp_is_edp(dev
, port
))
5282 type
= DRM_MODE_CONNECTOR_eDP
;
5284 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5287 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5288 * for DP the encoder type can be set by the caller to
5289 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5291 if (type
== DRM_MODE_CONNECTOR_eDP
)
5292 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5294 /* eDP only on port B and/or C on vlv/chv */
5295 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5296 port
!= PORT_B
&& port
!= PORT_C
))
5299 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5300 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5303 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5304 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5306 connector
->interlace_allowed
= true;
5307 connector
->doublescan_allowed
= 0;
5309 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5310 edp_panel_vdd_work
);
5312 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5313 drm_connector_register(connector
);
5316 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5318 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5319 intel_connector
->unregister
= intel_dp_connector_unregister
;
5321 /* Set up the hotplug pin. */
5324 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5327 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5330 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5333 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5339 if (is_edp(intel_dp
)) {
5341 if (IS_VALLEYVIEW(dev
)) {
5342 vlv_initial_power_sequencer_setup(intel_dp
);
5344 intel_dp_init_panel_power_timestamps(intel_dp
);
5345 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5347 pps_unlock(intel_dp
);
5350 intel_dp_aux_init(intel_dp
, intel_connector
);
5352 /* init MST on ports that can support it */
5353 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5354 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5355 intel_dp_mst_encoder_init(intel_dig_port
,
5356 intel_connector
->base
.base
.id
);
5360 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5361 drm_dp_aux_unregister(&intel_dp
->aux
);
5362 if (is_edp(intel_dp
)) {
5363 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5365 * vdd might still be enabled do to the delayed vdd off.
5366 * Make sure vdd is actually turned off here.
5369 edp_panel_vdd_off_sync(intel_dp
);
5370 pps_unlock(intel_dp
);
5372 drm_connector_unregister(connector
);
5373 drm_connector_cleanup(connector
);
5377 intel_dp_add_properties(intel_dp
, connector
);
5379 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5380 * 0xd. Failure to do so will result in spurious interrupts being
5381 * generated on the port when a cable is not attached.
5383 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5384 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5385 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5392 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5395 struct intel_digital_port
*intel_dig_port
;
5396 struct intel_encoder
*intel_encoder
;
5397 struct drm_encoder
*encoder
;
5398 struct intel_connector
*intel_connector
;
5400 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5401 if (!intel_dig_port
)
5404 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
5405 if (!intel_connector
) {
5406 kfree(intel_dig_port
);
5410 intel_encoder
= &intel_dig_port
->base
;
5411 encoder
= &intel_encoder
->base
;
5413 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5414 DRM_MODE_ENCODER_TMDS
);
5416 intel_encoder
->compute_config
= intel_dp_compute_config
;
5417 intel_encoder
->disable
= intel_disable_dp
;
5418 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5419 intel_encoder
->get_config
= intel_dp_get_config
;
5420 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5421 if (IS_CHERRYVIEW(dev
)) {
5422 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5423 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5424 intel_encoder
->enable
= vlv_enable_dp
;
5425 intel_encoder
->post_disable
= chv_post_disable_dp
;
5426 } else if (IS_VALLEYVIEW(dev
)) {
5427 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5428 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5429 intel_encoder
->enable
= vlv_enable_dp
;
5430 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5432 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5433 intel_encoder
->enable
= g4x_enable_dp
;
5434 if (INTEL_INFO(dev
)->gen
>= 5)
5435 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5438 intel_dig_port
->port
= port
;
5439 intel_dig_port
->dp
.output_reg
= output_reg
;
5441 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5442 if (IS_CHERRYVIEW(dev
)) {
5444 intel_encoder
->crtc_mask
= 1 << 2;
5446 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5448 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5450 intel_encoder
->cloneable
= 0;
5451 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5453 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5454 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5456 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5457 drm_encoder_cleanup(encoder
);
5458 kfree(intel_dig_port
);
5459 kfree(intel_connector
);
5463 void intel_dp_mst_suspend(struct drm_device
*dev
)
5465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5469 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5470 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5471 if (!intel_dig_port
)
5474 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5475 if (!intel_dig_port
->dp
.can_mst
)
5477 if (intel_dig_port
->dp
.is_mst
)
5478 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5483 void intel_dp_mst_resume(struct drm_device
*dev
)
5485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5488 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5489 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5490 if (!intel_dig_port
)
5492 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5495 if (!intel_dig_port
->dp
.can_mst
)
5498 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5500 intel_dp_check_mst_status(&intel_dig_port
->dp
);