2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
118 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
120 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
121 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
123 switch (max_link_bw
) {
124 case DP_LINK_BW_1_62
:
127 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
129 INTEL_INFO(dev
)->gen
>= 8) &&
130 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
131 max_link_bw
= DP_LINK_BW_5_4
;
133 max_link_bw
= DP_LINK_BW_2_7
;
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw
= DP_LINK_BW_1_62
;
144 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
147 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
148 u8 source_max
, sink_max
;
151 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
152 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
155 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
157 return min(source_max
, sink_max
);
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock
, int bpp
)
180 return (pixel_clock
* bpp
+ 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
186 return (max_link_clock
* max_lanes
* 8) / 10;
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector
*connector
,
191 struct drm_display_mode
*mode
)
193 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
194 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
195 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
196 int target_clock
= mode
->clock
;
197 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
199 if (is_edp(intel_dp
) && fixed_mode
) {
200 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
203 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
206 target_clock
= fixed_mode
->clock
;
209 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
210 max_lanes
= intel_dp_max_lane_count(intel_dp
);
212 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 mode_rate
= intel_dp_link_required(target_clock
, 18);
215 if (mode_rate
> max_rate
)
216 return MODE_CLOCK_HIGH
;
218 if (mode
->clock
< 10000)
219 return MODE_CLOCK_LOW
;
221 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
222 return MODE_H_ILLEGAL
;
228 pack_aux(uint8_t *src
, int src_bytes
)
235 for (i
= 0; i
< src_bytes
; i
++)
236 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
241 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
246 for (i
= 0; i
< dst_bytes
; i
++)
247 dst
[i
] = src
>> ((3-i
) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device
*dev
)
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev
))
261 clkcfg
= I915_READ(CLKCFG
);
262 switch (clkcfg
& CLKCFG_FSB_MASK
) {
271 case CLKCFG_FSB_1067
:
273 case CLKCFG_FSB_1333
:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600
:
277 case CLKCFG_FSB_1600_ALT
:
285 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
286 struct intel_dp
*intel_dp
,
287 struct edp_power_seq
*out
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
,
291 struct edp_power_seq
*out
);
294 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
296 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
297 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
298 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
300 enum port port
= intel_dig_port
->port
;
303 /* modeset should have pipe */
305 return to_intel_crtc(crtc
)->pipe
;
307 /* init time, try to find a pipe with this port selected */
308 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
309 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
310 PANEL_PORT_SELECT_MASK
;
311 if (port_sel
== PANEL_PORT_SELECT_VLV(port
))
319 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
321 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
323 if (HAS_PCH_SPLIT(dev
))
324 return PCH_PP_CONTROL
;
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
329 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
331 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
333 if (HAS_PCH_SPLIT(dev
))
334 return PCH_PP_STATUS
;
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
339 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
340 This function only applicable when panel PM state is not to be tracked */
341 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
344 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
346 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
349 u32 pp_ctrl_reg
, pp_div_reg
;
350 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
352 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
355 if (IS_VALLEYVIEW(dev
)) {
356 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
357 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
358 pp_div
= I915_READ(pp_div_reg
);
359 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
361 /* 0x1F write to PP_DIV_REG sets max cycle delay */
362 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
363 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
364 msleep(intel_dp
->panel_power_cycle_delay
);
370 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
372 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
375 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
378 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
380 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
382 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
383 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
384 enum intel_display_power_domain power_domain
;
386 power_domain
= intel_display_port_power_domain(intel_encoder
);
387 return intel_display_power_enabled(dev_priv
, power_domain
) &&
388 (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
392 intel_dp_check_edp(struct intel_dp
*intel_dp
)
394 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
397 if (!is_edp(intel_dp
))
400 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
401 WARN(1, "eDP powered off while attempting aux channel communication.\n");
402 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
403 I915_READ(_pp_stat_reg(intel_dp
)),
404 I915_READ(_pp_ctrl_reg(intel_dp
)));
409 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
411 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
412 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
414 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
418 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
420 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
421 msecs_to_jiffies_timeout(10));
423 done
= wait_for_atomic(C
, 10) == 0;
425 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
432 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
434 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
435 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
438 * The clock divider is based off the hrawclk, and would like to run at
439 * 2MHz. So, take the hrawclk value and divide by 2 and use that
441 return index
? 0 : intel_hrawclk(dev
) / 2;
444 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
446 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
447 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
452 if (intel_dig_port
->port
== PORT_A
) {
453 if (IS_GEN6(dev
) || IS_GEN7(dev
))
454 return 200; /* SNB & IVB eDP input clock at 400Mhz */
456 return 225; /* eDP input clock at 450Mhz */
458 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
462 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
464 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
465 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
468 if (intel_dig_port
->port
== PORT_A
) {
471 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
472 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
473 /* Workaround for non-ULT HSW */
480 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
484 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
486 return index
? 0 : 100;
489 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
492 uint32_t aux_clock_divider
)
494 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
495 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
496 uint32_t precharge
, timeout
;
503 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
504 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
506 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
508 return DP_AUX_CH_CTL_SEND_BUSY
|
510 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
511 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
513 DP_AUX_CH_CTL_RECEIVE_ERROR
|
514 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
515 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
516 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
520 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
521 uint8_t *send
, int send_bytes
,
522 uint8_t *recv
, int recv_size
)
524 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
525 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
527 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
528 uint32_t ch_data
= ch_ctl
+ 4;
529 uint32_t aux_clock_divider
;
530 int i
, ret
, recv_bytes
;
533 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
536 vdd
= _edp_panel_vdd_on(intel_dp
);
538 /* dp aux is extremely sensitive to irq latency, hence request the
539 * lowest possible wakeup latency and so prevent the cpu from going into
542 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
544 intel_dp_check_edp(intel_dp
);
546 intel_aux_display_runtime_get(dev_priv
);
548 /* Try to wait for any previous AUX channel activity */
549 for (try = 0; try < 3; try++) {
550 status
= I915_READ_NOTRACE(ch_ctl
);
551 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
557 WARN(1, "dp_aux_ch not started status 0x%08x\n",
563 /* Only 5 data registers! */
564 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
569 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
570 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
575 /* Must try at least 3 times according to DP spec */
576 for (try = 0; try < 5; try++) {
577 /* Load the send data into the aux channel data registers */
578 for (i
= 0; i
< send_bytes
; i
+= 4)
579 I915_WRITE(ch_data
+ i
,
580 pack_aux(send
+ i
, send_bytes
- i
));
582 /* Send the command and wait for it to complete */
583 I915_WRITE(ch_ctl
, send_ctl
);
585 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
587 /* Clear done status and any errors */
591 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
592 DP_AUX_CH_CTL_RECEIVE_ERROR
);
594 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
595 DP_AUX_CH_CTL_RECEIVE_ERROR
))
597 if (status
& DP_AUX_CH_CTL_DONE
)
600 if (status
& DP_AUX_CH_CTL_DONE
)
604 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
605 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
610 /* Check for timeout or receive error.
611 * Timeouts occur when the sink is not connected
613 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
614 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
619 /* Timeouts occur when the device isn't connected, so they're
620 * "normal" -- don't fill the kernel log with these */
621 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
622 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
627 /* Unload any bytes sent back from the other side */
628 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
629 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
630 if (recv_bytes
> recv_size
)
631 recv_bytes
= recv_size
;
633 for (i
= 0; i
< recv_bytes
; i
+= 4)
634 unpack_aux(I915_READ(ch_data
+ i
),
635 recv
+ i
, recv_bytes
- i
);
639 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
640 intel_aux_display_runtime_put(dev_priv
);
643 edp_panel_vdd_off(intel_dp
, false);
648 #define BARE_ADDRESS_SIZE 3
649 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
651 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
653 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
654 uint8_t txbuf
[20], rxbuf
[20];
655 size_t txsize
, rxsize
;
658 txbuf
[0] = msg
->request
<< 4;
659 txbuf
[1] = msg
->address
>> 8;
660 txbuf
[2] = msg
->address
& 0xff;
661 txbuf
[3] = msg
->size
- 1;
663 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
664 case DP_AUX_NATIVE_WRITE
:
665 case DP_AUX_I2C_WRITE
:
666 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
669 if (WARN_ON(txsize
> 20))
672 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
674 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
676 msg
->reply
= rxbuf
[0] >> 4;
678 /* Return payload size. */
683 case DP_AUX_NATIVE_READ
:
684 case DP_AUX_I2C_READ
:
685 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
686 rxsize
= msg
->size
+ 1;
688 if (WARN_ON(rxsize
> 20))
691 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
693 msg
->reply
= rxbuf
[0] >> 4;
695 * Assume happy day, and copy the data. The caller is
696 * expected to check msg->reply before touching it.
698 * Return payload size.
701 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
714 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
716 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
717 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
718 enum port port
= intel_dig_port
->port
;
719 const char *name
= NULL
;
724 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
728 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
732 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
736 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
744 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
746 intel_dp
->aux
.name
= name
;
747 intel_dp
->aux
.dev
= dev
->dev
;
748 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
750 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
751 connector
->base
.kdev
->kobj
.name
);
753 ret
= drm_dp_aux_register(&intel_dp
->aux
);
755 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
760 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
761 &intel_dp
->aux
.ddc
.dev
.kobj
,
762 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
764 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
765 drm_dp_aux_unregister(&intel_dp
->aux
);
770 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
772 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
774 if (!intel_connector
->mst_port
)
775 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
776 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
777 intel_connector_unregister(intel_connector
);
781 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
784 case DP_LINK_BW_1_62
:
785 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
788 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
791 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
797 intel_dp_set_clock(struct intel_encoder
*encoder
,
798 struct intel_crtc_config
*pipe_config
, int link_bw
)
800 struct drm_device
*dev
= encoder
->base
.dev
;
801 const struct dp_link_dpll
*divisor
= NULL
;
806 count
= ARRAY_SIZE(gen4_dpll
);
807 } else if (HAS_PCH_SPLIT(dev
)) {
809 count
= ARRAY_SIZE(pch_dpll
);
810 } else if (IS_CHERRYVIEW(dev
)) {
812 count
= ARRAY_SIZE(chv_dpll
);
813 } else if (IS_VALLEYVIEW(dev
)) {
815 count
= ARRAY_SIZE(vlv_dpll
);
818 if (divisor
&& count
) {
819 for (i
= 0; i
< count
; i
++) {
820 if (link_bw
== divisor
[i
].link_bw
) {
821 pipe_config
->dpll
= divisor
[i
].dpll
;
822 pipe_config
->clock_set
= true;
830 intel_dp_compute_config(struct intel_encoder
*encoder
,
831 struct intel_crtc_config
*pipe_config
)
833 struct drm_device
*dev
= encoder
->base
.dev
;
834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
835 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
836 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
837 enum port port
= dp_to_dig_port(intel_dp
)->port
;
838 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
839 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
840 int lane_count
, clock
;
841 int min_lane_count
= 1;
842 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
843 /* Conveniently, the link BW constants become indices with a shift...*/
845 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
847 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
848 int link_avail
, link_clock
;
850 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
851 pipe_config
->has_pch_encoder
= true;
853 pipe_config
->has_dp_encoder
= true;
854 pipe_config
->has_drrs
= false;
855 pipe_config
->has_audio
= intel_dp
->has_audio
;
857 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
858 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
860 if (!HAS_PCH_SPLIT(dev
))
861 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
862 intel_connector
->panel
.fitting_mode
);
864 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
865 intel_connector
->panel
.fitting_mode
);
868 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
871 DRM_DEBUG_KMS("DP link computation with max lane count %i "
872 "max bw %02x pixel clock %iKHz\n",
873 max_lane_count
, bws
[max_clock
],
874 adjusted_mode
->crtc_clock
);
876 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
878 bpp
= pipe_config
->pipe_bpp
;
879 if (is_edp(intel_dp
)) {
880 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
881 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
882 dev_priv
->vbt
.edp_bpp
);
883 bpp
= dev_priv
->vbt
.edp_bpp
;
886 if (IS_BROADWELL(dev
)) {
887 /* Yes, it's an ugly hack. */
888 min_lane_count
= max_lane_count
;
889 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
891 } else if (dev_priv
->vbt
.edp_lanes
) {
892 min_lane_count
= min(dev_priv
->vbt
.edp_lanes
,
894 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
898 if (dev_priv
->vbt
.edp_rate
) {
899 min_clock
= min(dev_priv
->vbt
.edp_rate
>> 3, max_clock
);
900 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
905 for (; bpp
>= 6*3; bpp
-= 2*3) {
906 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
909 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
910 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
911 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
912 link_avail
= intel_dp_max_data_rate(link_clock
,
915 if (mode_rate
<= link_avail
) {
925 if (intel_dp
->color_range_auto
) {
928 * CEA-861-E - 5.1 Default Encoding Parameters
929 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
931 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
932 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
934 intel_dp
->color_range
= 0;
937 if (intel_dp
->color_range
)
938 pipe_config
->limited_color_range
= true;
940 intel_dp
->link_bw
= bws
[clock
];
941 intel_dp
->lane_count
= lane_count
;
942 pipe_config
->pipe_bpp
= bpp
;
943 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
945 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
946 intel_dp
->link_bw
, intel_dp
->lane_count
,
947 pipe_config
->port_clock
, bpp
);
948 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
949 mode_rate
, link_avail
);
951 intel_link_compute_m_n(bpp
, lane_count
,
952 adjusted_mode
->crtc_clock
,
953 pipe_config
->port_clock
,
954 &pipe_config
->dp_m_n
);
956 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
957 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
958 pipe_config
->has_drrs
= true;
959 intel_link_compute_m_n(bpp
, lane_count
,
960 intel_connector
->panel
.downclock_mode
->clock
,
961 pipe_config
->port_clock
,
962 &pipe_config
->dp_m2_n2
);
965 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
966 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
968 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
973 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
975 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
976 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
977 struct drm_device
*dev
= crtc
->base
.dev
;
978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
981 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
982 dpa_ctl
= I915_READ(DP_A
);
983 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
985 if (crtc
->config
.port_clock
== 162000) {
986 /* For a long time we've carried around a ILK-DevA w/a for the
987 * 160MHz clock. If we're really unlucky, it's still required.
989 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
990 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
991 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
993 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
994 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
997 I915_WRITE(DP_A
, dpa_ctl
);
1003 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1005 struct drm_device
*dev
= encoder
->base
.dev
;
1006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1007 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1008 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1009 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1010 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1013 * There are four kinds of DP registers:
1020 * IBX PCH and CPU are the same for almost everything,
1021 * except that the CPU DP PLL is configured in this
1024 * CPT PCH is quite different, having many bits moved
1025 * to the TRANS_DP_CTL register instead. That
1026 * configuration happens (oddly) in ironlake_pch_enable
1029 /* Preserve the BIOS-computed detected bit. This is
1030 * supposed to be read-only.
1032 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1034 /* Handle DP bits in common between all three register formats */
1035 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1036 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1038 if (crtc
->config
.has_audio
) {
1039 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1040 pipe_name(crtc
->pipe
));
1041 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1042 intel_write_eld(&encoder
->base
, adjusted_mode
);
1045 /* Split out the IBX/CPU vs CPT settings */
1047 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1048 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1049 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1050 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1051 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1052 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1054 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1055 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1057 intel_dp
->DP
|= crtc
->pipe
<< 29;
1058 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1059 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1060 intel_dp
->DP
|= intel_dp
->color_range
;
1062 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1063 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1064 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1065 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1066 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1068 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1069 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1071 if (!IS_CHERRYVIEW(dev
)) {
1072 if (crtc
->pipe
== 1)
1073 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1075 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1078 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1082 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1083 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1085 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1086 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1088 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1089 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1091 static void wait_panel_status(struct intel_dp
*intel_dp
,
1095 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1097 u32 pp_stat_reg
, pp_ctrl_reg
;
1099 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1100 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1102 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1104 I915_READ(pp_stat_reg
),
1105 I915_READ(pp_ctrl_reg
));
1107 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1108 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1109 I915_READ(pp_stat_reg
),
1110 I915_READ(pp_ctrl_reg
));
1113 DRM_DEBUG_KMS("Wait complete\n");
1116 static void wait_panel_on(struct intel_dp
*intel_dp
)
1118 DRM_DEBUG_KMS("Wait for panel power on\n");
1119 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1122 static void wait_panel_off(struct intel_dp
*intel_dp
)
1124 DRM_DEBUG_KMS("Wait for panel power off time\n");
1125 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1128 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1130 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1132 /* When we disable the VDD override bit last we have to do the manual
1134 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1135 intel_dp
->panel_power_cycle_delay
);
1137 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1140 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1142 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1143 intel_dp
->backlight_on_delay
);
1146 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1148 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1149 intel_dp
->backlight_off_delay
);
1152 /* Read the current pp_control value, unlocking the register if it
1156 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1158 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1162 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1163 control
&= ~PANEL_UNLOCK_MASK
;
1164 control
|= PANEL_UNLOCK_REGS
;
1168 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1170 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1171 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1172 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1174 enum intel_display_power_domain power_domain
;
1176 u32 pp_stat_reg
, pp_ctrl_reg
;
1177 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1179 if (!is_edp(intel_dp
))
1182 intel_dp
->want_panel_vdd
= true;
1184 if (edp_have_panel_vdd(intel_dp
))
1185 return need_to_disable
;
1187 power_domain
= intel_display_port_power_domain(intel_encoder
);
1188 intel_display_power_get(dev_priv
, power_domain
);
1190 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1192 if (!edp_have_panel_power(intel_dp
))
1193 wait_panel_power_cycle(intel_dp
);
1195 pp
= ironlake_get_pp_control(intel_dp
);
1196 pp
|= EDP_FORCE_VDD
;
1198 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1199 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1201 I915_WRITE(pp_ctrl_reg
, pp
);
1202 POSTING_READ(pp_ctrl_reg
);
1203 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1204 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1206 * If the panel wasn't on, delay before accessing aux channel
1208 if (!edp_have_panel_power(intel_dp
)) {
1209 DRM_DEBUG_KMS("eDP was not running\n");
1210 msleep(intel_dp
->panel_power_up_delay
);
1213 return need_to_disable
;
1216 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1218 if (is_edp(intel_dp
)) {
1219 bool vdd
= _edp_panel_vdd_on(intel_dp
);
1221 WARN(!vdd
, "eDP VDD already requested on\n");
1225 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1227 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1230 u32 pp_stat_reg
, pp_ctrl_reg
;
1232 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
1234 if (!intel_dp
->want_panel_vdd
&& edp_have_panel_vdd(intel_dp
)) {
1235 struct intel_digital_port
*intel_dig_port
=
1236 dp_to_dig_port(intel_dp
);
1237 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1238 enum intel_display_power_domain power_domain
;
1240 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1242 pp
= ironlake_get_pp_control(intel_dp
);
1243 pp
&= ~EDP_FORCE_VDD
;
1245 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1246 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1248 I915_WRITE(pp_ctrl_reg
, pp
);
1249 POSTING_READ(pp_ctrl_reg
);
1251 /* Make sure sequencer is idle before allowing subsequent activity */
1252 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1253 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1255 if ((pp
& POWER_TARGET_ON
) == 0)
1256 intel_dp
->last_power_cycle
= jiffies
;
1258 power_domain
= intel_display_port_power_domain(intel_encoder
);
1259 intel_display_power_put(dev_priv
, power_domain
);
1263 static void edp_panel_vdd_work(struct work_struct
*__work
)
1265 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1266 struct intel_dp
, panel_vdd_work
);
1267 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1269 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
1270 edp_panel_vdd_off_sync(intel_dp
);
1271 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
1274 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1276 unsigned long delay
;
1279 * Queue the timer to fire a long time from now (relative to the power
1280 * down delay) to keep the panel power up across a sequence of
1283 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1284 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1287 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1289 if (!is_edp(intel_dp
))
1292 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1294 intel_dp
->want_panel_vdd
= false;
1297 edp_panel_vdd_off_sync(intel_dp
);
1299 edp_panel_vdd_schedule_off(intel_dp
);
1302 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1304 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1309 if (!is_edp(intel_dp
))
1312 DRM_DEBUG_KMS("Turn eDP power on\n");
1314 if (edp_have_panel_power(intel_dp
)) {
1315 DRM_DEBUG_KMS("eDP power already on\n");
1319 wait_panel_power_cycle(intel_dp
);
1321 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1322 pp
= ironlake_get_pp_control(intel_dp
);
1324 /* ILK workaround: disable reset around power sequence */
1325 pp
&= ~PANEL_POWER_RESET
;
1326 I915_WRITE(pp_ctrl_reg
, pp
);
1327 POSTING_READ(pp_ctrl_reg
);
1330 pp
|= POWER_TARGET_ON
;
1332 pp
|= PANEL_POWER_RESET
;
1334 I915_WRITE(pp_ctrl_reg
, pp
);
1335 POSTING_READ(pp_ctrl_reg
);
1337 wait_panel_on(intel_dp
);
1338 intel_dp
->last_power_on
= jiffies
;
1341 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1342 I915_WRITE(pp_ctrl_reg
, pp
);
1343 POSTING_READ(pp_ctrl_reg
);
1347 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1349 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1350 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1351 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1353 enum intel_display_power_domain power_domain
;
1357 if (!is_edp(intel_dp
))
1360 DRM_DEBUG_KMS("Turn eDP power off\n");
1362 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1364 pp
= ironlake_get_pp_control(intel_dp
);
1365 /* We need to switch off panel power _and_ force vdd, for otherwise some
1366 * panels get very unhappy and cease to work. */
1367 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1370 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1372 intel_dp
->want_panel_vdd
= false;
1374 I915_WRITE(pp_ctrl_reg
, pp
);
1375 POSTING_READ(pp_ctrl_reg
);
1377 intel_dp
->last_power_cycle
= jiffies
;
1378 wait_panel_off(intel_dp
);
1380 /* We got a reference when we enabled the VDD. */
1381 power_domain
= intel_display_port_power_domain(intel_encoder
);
1382 intel_display_power_put(dev_priv
, power_domain
);
1385 /* Enable backlight in the panel power control. */
1386 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1388 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1389 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1395 * If we enable the backlight right away following a panel power
1396 * on, we may see slight flicker as the panel syncs with the eDP
1397 * link. So delay a bit to make sure the image is solid before
1398 * allowing it to appear.
1400 wait_backlight_on(intel_dp
);
1401 pp
= ironlake_get_pp_control(intel_dp
);
1402 pp
|= EDP_BLC_ENABLE
;
1404 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1406 I915_WRITE(pp_ctrl_reg
, pp
);
1407 POSTING_READ(pp_ctrl_reg
);
1410 /* Enable backlight PWM and backlight PP control. */
1411 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1413 if (!is_edp(intel_dp
))
1416 DRM_DEBUG_KMS("\n");
1418 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1419 _intel_edp_backlight_on(intel_dp
);
1422 /* Disable backlight in the panel power control. */
1423 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1425 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1430 pp
= ironlake_get_pp_control(intel_dp
);
1431 pp
&= ~EDP_BLC_ENABLE
;
1433 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1435 I915_WRITE(pp_ctrl_reg
, pp
);
1436 POSTING_READ(pp_ctrl_reg
);
1437 intel_dp
->last_backlight_off
= jiffies
;
1439 edp_wait_backlight_off(intel_dp
);
1442 /* Disable backlight PP control and backlight PWM. */
1443 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1445 if (!is_edp(intel_dp
))
1448 DRM_DEBUG_KMS("\n");
1450 _intel_edp_backlight_off(intel_dp
);
1451 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1455 * Hook for controlling the panel power control backlight through the bl_power
1456 * sysfs attribute. Take care to handle multiple calls.
1458 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1461 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1462 bool is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1464 if (is_enabled
== enable
)
1467 DRM_DEBUG_KMS("\n");
1470 _intel_edp_backlight_on(intel_dp
);
1472 _intel_edp_backlight_off(intel_dp
);
1475 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1477 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1478 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1479 struct drm_device
*dev
= crtc
->dev
;
1480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1483 assert_pipe_disabled(dev_priv
,
1484 to_intel_crtc(crtc
)->pipe
);
1486 DRM_DEBUG_KMS("\n");
1487 dpa_ctl
= I915_READ(DP_A
);
1488 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1489 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1491 /* We don't adjust intel_dp->DP while tearing down the link, to
1492 * facilitate link retraining (e.g. after hotplug). Hence clear all
1493 * enable bits here to ensure that we don't enable too much. */
1494 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1495 intel_dp
->DP
|= DP_PLL_ENABLE
;
1496 I915_WRITE(DP_A
, intel_dp
->DP
);
1501 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1503 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1504 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1505 struct drm_device
*dev
= crtc
->dev
;
1506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1509 assert_pipe_disabled(dev_priv
,
1510 to_intel_crtc(crtc
)->pipe
);
1512 dpa_ctl
= I915_READ(DP_A
);
1513 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1514 "dp pll off, should be on\n");
1515 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1517 /* We can't rely on the value tracked for the DP register in
1518 * intel_dp->DP because link_down must not change that (otherwise link
1519 * re-training will fail. */
1520 dpa_ctl
&= ~DP_PLL_ENABLE
;
1521 I915_WRITE(DP_A
, dpa_ctl
);
1526 /* If the sink supports it, try to set the power state appropriately */
1527 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1531 /* Should have a valid DPCD by this point */
1532 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1535 if (mode
!= DRM_MODE_DPMS_ON
) {
1536 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1539 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1542 * When turning on, we need to retry for 1ms to give the sink
1545 for (i
= 0; i
< 3; i
++) {
1546 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1555 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1558 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1559 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1560 struct drm_device
*dev
= encoder
->base
.dev
;
1561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1562 enum intel_display_power_domain power_domain
;
1565 power_domain
= intel_display_port_power_domain(encoder
);
1566 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1569 tmp
= I915_READ(intel_dp
->output_reg
);
1571 if (!(tmp
& DP_PORT_EN
))
1574 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1575 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1576 } else if (IS_CHERRYVIEW(dev
)) {
1577 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1578 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1579 *pipe
= PORT_TO_PIPE(tmp
);
1585 switch (intel_dp
->output_reg
) {
1587 trans_sel
= TRANS_DP_PORT_SEL_B
;
1590 trans_sel
= TRANS_DP_PORT_SEL_C
;
1593 trans_sel
= TRANS_DP_PORT_SEL_D
;
1599 for_each_pipe(dev_priv
, i
) {
1600 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1601 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1607 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1608 intel_dp
->output_reg
);
1614 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1615 struct intel_crtc_config
*pipe_config
)
1617 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1619 struct drm_device
*dev
= encoder
->base
.dev
;
1620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1621 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1622 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1625 tmp
= I915_READ(intel_dp
->output_reg
);
1626 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1627 pipe_config
->has_audio
= true;
1629 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1630 if (tmp
& DP_SYNC_HS_HIGH
)
1631 flags
|= DRM_MODE_FLAG_PHSYNC
;
1633 flags
|= DRM_MODE_FLAG_NHSYNC
;
1635 if (tmp
& DP_SYNC_VS_HIGH
)
1636 flags
|= DRM_MODE_FLAG_PVSYNC
;
1638 flags
|= DRM_MODE_FLAG_NVSYNC
;
1640 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1641 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1642 flags
|= DRM_MODE_FLAG_PHSYNC
;
1644 flags
|= DRM_MODE_FLAG_NHSYNC
;
1646 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1647 flags
|= DRM_MODE_FLAG_PVSYNC
;
1649 flags
|= DRM_MODE_FLAG_NVSYNC
;
1652 pipe_config
->adjusted_mode
.flags
|= flags
;
1654 pipe_config
->has_dp_encoder
= true;
1656 intel_dp_get_m_n(crtc
, pipe_config
);
1658 if (port
== PORT_A
) {
1659 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1660 pipe_config
->port_clock
= 162000;
1662 pipe_config
->port_clock
= 270000;
1665 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1666 &pipe_config
->dp_m_n
);
1668 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1669 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1671 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1673 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1674 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1676 * This is a big fat ugly hack.
1678 * Some machines in UEFI boot mode provide us a VBT that has 18
1679 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1680 * unknown we fail to light up. Yet the same BIOS boots up with
1681 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1682 * max, not what it tells us to use.
1684 * Note: This will still be broken if the eDP panel is not lit
1685 * up by the BIOS, and thus we can't get the mode at module
1688 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1689 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1690 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1694 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1696 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1699 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1706 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1709 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1710 struct edp_vsc_psr
*vsc_psr
)
1712 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1713 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1715 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1716 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1717 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1718 uint32_t *data
= (uint32_t *) vsc_psr
;
1721 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1722 the video DIP being updated before program video DIP data buffer
1723 registers for DIP being updated. */
1724 I915_WRITE(ctl_reg
, 0);
1725 POSTING_READ(ctl_reg
);
1727 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1728 if (i
< sizeof(struct edp_vsc_psr
))
1729 I915_WRITE(data_reg
+ i
, *data
++);
1731 I915_WRITE(data_reg
+ i
, 0);
1734 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1735 POSTING_READ(ctl_reg
);
1738 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1740 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1742 struct edp_vsc_psr psr_vsc
;
1744 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1745 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1746 psr_vsc
.sdp_header
.HB0
= 0;
1747 psr_vsc
.sdp_header
.HB1
= 0x7;
1748 psr_vsc
.sdp_header
.HB2
= 0x2;
1749 psr_vsc
.sdp_header
.HB3
= 0x8;
1750 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1752 /* Avoid continuous PSR exit by masking memup and hpd */
1753 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1754 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1757 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1759 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1760 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1762 uint32_t aux_clock_divider
;
1763 int precharge
= 0x3;
1764 int msg_size
= 5; /* Header(4) + Message(1) */
1765 bool only_standby
= false;
1767 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
1769 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
1770 only_standby
= true;
1772 /* Enable PSR in sink */
1773 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
1774 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1775 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
1777 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1778 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
1780 /* Setup AUX registers */
1781 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
1782 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
1783 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
1784 DP_AUX_CH_CTL_TIME_OUT_400us
|
1785 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1786 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1787 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1790 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1792 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1793 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1795 uint32_t max_sleep_time
= 0x1f;
1796 uint32_t idle_frames
= 1;
1798 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
1799 bool only_standby
= false;
1801 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
1802 only_standby
= true;
1804 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
1805 val
|= EDP_PSR_LINK_STANDBY
;
1806 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1807 val
|= EDP_PSR_TP1_TIME_0us
;
1808 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1809 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
1811 val
|= EDP_PSR_LINK_DISABLE
;
1813 I915_WRITE(EDP_PSR_CTL(dev
), val
|
1814 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
1815 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1816 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1820 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1822 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1823 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1825 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1826 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1828 lockdep_assert_held(&dev_priv
->psr
.lock
);
1829 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
1830 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
1832 dev_priv
->psr
.source_ok
= false;
1834 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
1835 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1839 if (!i915
.enable_psr
) {
1840 DRM_DEBUG_KMS("PSR disable by flag\n");
1844 /* Below limitations aren't valid for Broadwell */
1845 if (IS_BROADWELL(dev
))
1848 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1850 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1854 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1855 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1860 dev_priv
->psr
.source_ok
= true;
1864 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1866 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1867 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1870 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
1871 WARN_ON(dev_priv
->psr
.active
);
1872 lockdep_assert_held(&dev_priv
->psr
.lock
);
1874 /* Enable PSR on the panel */
1875 intel_edp_psr_enable_sink(intel_dp
);
1877 /* Enable PSR on the host */
1878 intel_edp_psr_enable_source(intel_dp
);
1880 dev_priv
->psr
.active
= true;
1883 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1885 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1888 if (!HAS_PSR(dev
)) {
1889 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1893 if (!is_edp_psr(intel_dp
)) {
1894 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1898 mutex_lock(&dev_priv
->psr
.lock
);
1899 if (dev_priv
->psr
.enabled
) {
1900 DRM_DEBUG_KMS("PSR already in use\n");
1901 mutex_unlock(&dev_priv
->psr
.lock
);
1905 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
1907 /* Setup PSR once */
1908 intel_edp_psr_setup(intel_dp
);
1910 if (intel_edp_psr_match_conditions(intel_dp
))
1911 dev_priv
->psr
.enabled
= intel_dp
;
1912 mutex_unlock(&dev_priv
->psr
.lock
);
1915 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1917 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1920 mutex_lock(&dev_priv
->psr
.lock
);
1921 if (!dev_priv
->psr
.enabled
) {
1922 mutex_unlock(&dev_priv
->psr
.lock
);
1926 if (dev_priv
->psr
.active
) {
1927 I915_WRITE(EDP_PSR_CTL(dev
),
1928 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
1930 /* Wait till PSR is idle */
1931 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
1932 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1933 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1935 dev_priv
->psr
.active
= false;
1937 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
1940 dev_priv
->psr
.enabled
= NULL
;
1941 mutex_unlock(&dev_priv
->psr
.lock
);
1943 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
1946 static void intel_edp_psr_work(struct work_struct
*work
)
1948 struct drm_i915_private
*dev_priv
=
1949 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
1950 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
1952 mutex_lock(&dev_priv
->psr
.lock
);
1953 intel_dp
= dev_priv
->psr
.enabled
;
1959 * The delayed work can race with an invalidate hence we need to
1960 * recheck. Since psr_flush first clears this and then reschedules we
1961 * won't ever miss a flush when bailing out here.
1963 if (dev_priv
->psr
.busy_frontbuffer_bits
)
1966 intel_edp_psr_do_enable(intel_dp
);
1968 mutex_unlock(&dev_priv
->psr
.lock
);
1971 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
1973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1975 if (dev_priv
->psr
.active
) {
1976 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
1978 WARN_ON(!(val
& EDP_PSR_ENABLE
));
1980 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
1982 dev_priv
->psr
.active
= false;
1987 void intel_edp_psr_invalidate(struct drm_device
*dev
,
1988 unsigned frontbuffer_bits
)
1990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1991 struct drm_crtc
*crtc
;
1994 mutex_lock(&dev_priv
->psr
.lock
);
1995 if (!dev_priv
->psr
.enabled
) {
1996 mutex_unlock(&dev_priv
->psr
.lock
);
2000 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2001 pipe
= to_intel_crtc(crtc
)->pipe
;
2003 intel_edp_psr_do_exit(dev
);
2005 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
2007 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
2008 mutex_unlock(&dev_priv
->psr
.lock
);
2011 void intel_edp_psr_flush(struct drm_device
*dev
,
2012 unsigned frontbuffer_bits
)
2014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2015 struct drm_crtc
*crtc
;
2018 mutex_lock(&dev_priv
->psr
.lock
);
2019 if (!dev_priv
->psr
.enabled
) {
2020 mutex_unlock(&dev_priv
->psr
.lock
);
2024 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2025 pipe
= to_intel_crtc(crtc
)->pipe
;
2026 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2029 * On Haswell sprite plane updates don't result in a psr invalidating
2030 * signal in the hardware. Which means we need to manually fake this in
2031 * software for all flushes, not just when we've seen a preceding
2032 * invalidation through frontbuffer rendering.
2034 if (IS_HASWELL(dev
) &&
2035 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2036 intel_edp_psr_do_exit(dev
);
2038 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2039 schedule_delayed_work(&dev_priv
->psr
.work
,
2040 msecs_to_jiffies(100));
2041 mutex_unlock(&dev_priv
->psr
.lock
);
2044 void intel_edp_psr_init(struct drm_device
*dev
)
2046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2048 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2049 mutex_init(&dev_priv
->psr
.lock
);
2052 static void intel_disable_dp(struct intel_encoder
*encoder
)
2054 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2055 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2056 struct drm_device
*dev
= encoder
->base
.dev
;
2058 /* Make sure the panel is off before trying to change the mode. But also
2059 * ensure that we have vdd while we switch off the panel. */
2060 intel_edp_panel_vdd_on(intel_dp
);
2061 intel_edp_backlight_off(intel_dp
);
2062 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2063 intel_edp_panel_off(intel_dp
);
2065 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2066 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
2067 intel_dp_link_down(intel_dp
);
2070 static void g4x_post_disable_dp(struct intel_encoder
*encoder
)
2072 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2073 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2078 intel_dp_link_down(intel_dp
);
2079 ironlake_edp_pll_off(intel_dp
);
2082 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2084 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2086 intel_dp_link_down(intel_dp
);
2089 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2091 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2092 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2093 struct drm_device
*dev
= encoder
->base
.dev
;
2094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2095 struct intel_crtc
*intel_crtc
=
2096 to_intel_crtc(encoder
->base
.crtc
);
2097 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2098 enum pipe pipe
= intel_crtc
->pipe
;
2101 intel_dp_link_down(intel_dp
);
2103 mutex_lock(&dev_priv
->dpio_lock
);
2105 /* Propagate soft reset to data lane reset */
2106 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2107 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2108 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2110 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2111 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2112 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2114 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2115 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2116 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2118 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2119 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2120 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2122 mutex_unlock(&dev_priv
->dpio_lock
);
2125 static void intel_enable_dp(struct intel_encoder
*encoder
)
2127 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2128 struct drm_device
*dev
= encoder
->base
.dev
;
2129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2130 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2132 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2135 intel_edp_panel_vdd_on(intel_dp
);
2136 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2137 intel_dp_start_link_train(intel_dp
);
2138 intel_edp_panel_on(intel_dp
);
2139 edp_panel_vdd_off(intel_dp
, true);
2140 intel_dp_complete_link_train(intel_dp
);
2141 intel_dp_stop_link_train(intel_dp
);
2144 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2146 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2148 intel_enable_dp(encoder
);
2149 intel_edp_backlight_on(intel_dp
);
2152 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2154 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2156 intel_edp_backlight_on(intel_dp
);
2159 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2161 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2162 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2164 intel_dp_prepare(encoder
);
2166 /* Only ilk+ has port A */
2167 if (dport
->port
== PORT_A
) {
2168 ironlake_set_pll_cpu_edp(intel_dp
);
2169 ironlake_edp_pll_on(intel_dp
);
2173 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2175 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2176 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2177 struct drm_device
*dev
= encoder
->base
.dev
;
2178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2179 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2180 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2181 int pipe
= intel_crtc
->pipe
;
2182 struct edp_power_seq power_seq
;
2185 mutex_lock(&dev_priv
->dpio_lock
);
2187 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2194 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2195 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2196 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2198 mutex_unlock(&dev_priv
->dpio_lock
);
2200 if (is_edp(intel_dp
)) {
2201 /* init power sequencer on this pipe and port */
2202 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2203 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2207 intel_enable_dp(encoder
);
2209 vlv_wait_port_ready(dev_priv
, dport
);
2212 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2214 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2215 struct drm_device
*dev
= encoder
->base
.dev
;
2216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2217 struct intel_crtc
*intel_crtc
=
2218 to_intel_crtc(encoder
->base
.crtc
);
2219 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2220 int pipe
= intel_crtc
->pipe
;
2222 intel_dp_prepare(encoder
);
2224 /* Program Tx lane resets to default */
2225 mutex_lock(&dev_priv
->dpio_lock
);
2226 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2227 DPIO_PCS_TX_LANE2_RESET
|
2228 DPIO_PCS_TX_LANE1_RESET
);
2229 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2230 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2231 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2232 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2233 DPIO_PCS_CLK_SOFT_RESET
);
2235 /* Fix up inter-pair skew failure */
2236 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2237 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2238 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2239 mutex_unlock(&dev_priv
->dpio_lock
);
2242 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2244 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2245 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2246 struct drm_device
*dev
= encoder
->base
.dev
;
2247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2248 struct edp_power_seq power_seq
;
2249 struct intel_crtc
*intel_crtc
=
2250 to_intel_crtc(encoder
->base
.crtc
);
2251 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2252 int pipe
= intel_crtc
->pipe
;
2256 mutex_lock(&dev_priv
->dpio_lock
);
2258 /* Deassert soft data lane reset*/
2259 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2260 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2261 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2263 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2264 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2265 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2267 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2268 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2269 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2271 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2272 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2273 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2275 /* Program Tx lane latency optimal setting*/
2276 for (i
= 0; i
< 4; i
++) {
2277 /* Set the latency optimal bit */
2278 data
= (i
== 1) ? 0x0 : 0x6;
2279 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2280 data
<< DPIO_FRC_LATENCY_SHFIT
);
2282 /* Set the upar bit */
2283 data
= (i
== 1) ? 0x0 : 0x1;
2284 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2285 data
<< DPIO_UPAR_SHIFT
);
2288 /* Data lane stagger programming */
2289 /* FIXME: Fix up value only after power analysis */
2291 mutex_unlock(&dev_priv
->dpio_lock
);
2293 if (is_edp(intel_dp
)) {
2294 /* init power sequencer on this pipe and port */
2295 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2296 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2300 intel_enable_dp(encoder
);
2302 vlv_wait_port_ready(dev_priv
, dport
);
2305 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2307 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2308 struct drm_device
*dev
= encoder
->base
.dev
;
2309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2310 struct intel_crtc
*intel_crtc
=
2311 to_intel_crtc(encoder
->base
.crtc
);
2312 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2313 enum pipe pipe
= intel_crtc
->pipe
;
2316 intel_dp_prepare(encoder
);
2318 mutex_lock(&dev_priv
->dpio_lock
);
2320 /* program left/right clock distribution */
2321 if (pipe
!= PIPE_B
) {
2322 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2323 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2325 val
|= CHV_BUFLEFTENA1_FORCE
;
2327 val
|= CHV_BUFRIGHTENA1_FORCE
;
2328 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2330 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2331 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2333 val
|= CHV_BUFLEFTENA2_FORCE
;
2335 val
|= CHV_BUFRIGHTENA2_FORCE
;
2336 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2339 /* program clock channel usage */
2340 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2341 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2343 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2345 val
|= CHV_PCS_USEDCLKCHANNEL
;
2346 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2348 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2349 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2351 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2353 val
|= CHV_PCS_USEDCLKCHANNEL
;
2354 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2357 * This a a bit weird since generally CL
2358 * matches the pipe, but here we need to
2359 * pick the CL based on the port.
2361 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2363 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2365 val
|= CHV_CMN_USEDCLKCHANNEL
;
2366 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2368 mutex_unlock(&dev_priv
->dpio_lock
);
2372 * Native read with retry for link status and receiver capability reads for
2373 * cases where the sink may still be asleep.
2375 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2376 * supposed to retry 3 times per the spec.
2379 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2380 void *buffer
, size_t size
)
2385 for (i
= 0; i
< 3; i
++) {
2386 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2396 * Fetch AUX CH registers 0x202 - 0x207 which contain
2397 * link status information
2400 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2402 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2405 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2408 /* These are source-specific values. */
2410 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2412 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2413 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2415 if (IS_VALLEYVIEW(dev
))
2416 return DP_TRAIN_VOLTAGE_SWING_1200
;
2417 else if (IS_GEN7(dev
) && port
== PORT_A
)
2418 return DP_TRAIN_VOLTAGE_SWING_800
;
2419 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2420 return DP_TRAIN_VOLTAGE_SWING_1200
;
2422 return DP_TRAIN_VOLTAGE_SWING_800
;
2426 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2428 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2429 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2431 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2432 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2433 case DP_TRAIN_VOLTAGE_SWING_400
:
2434 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2435 case DP_TRAIN_VOLTAGE_SWING_600
:
2436 return DP_TRAIN_PRE_EMPHASIS_6
;
2437 case DP_TRAIN_VOLTAGE_SWING_800
:
2438 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2439 case DP_TRAIN_VOLTAGE_SWING_1200
:
2441 return DP_TRAIN_PRE_EMPHASIS_0
;
2443 } else if (IS_VALLEYVIEW(dev
)) {
2444 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2445 case DP_TRAIN_VOLTAGE_SWING_400
:
2446 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2447 case DP_TRAIN_VOLTAGE_SWING_600
:
2448 return DP_TRAIN_PRE_EMPHASIS_6
;
2449 case DP_TRAIN_VOLTAGE_SWING_800
:
2450 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2451 case DP_TRAIN_VOLTAGE_SWING_1200
:
2453 return DP_TRAIN_PRE_EMPHASIS_0
;
2455 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2456 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2457 case DP_TRAIN_VOLTAGE_SWING_400
:
2458 return DP_TRAIN_PRE_EMPHASIS_6
;
2459 case DP_TRAIN_VOLTAGE_SWING_600
:
2460 case DP_TRAIN_VOLTAGE_SWING_800
:
2461 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2463 return DP_TRAIN_PRE_EMPHASIS_0
;
2466 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2467 case DP_TRAIN_VOLTAGE_SWING_400
:
2468 return DP_TRAIN_PRE_EMPHASIS_6
;
2469 case DP_TRAIN_VOLTAGE_SWING_600
:
2470 return DP_TRAIN_PRE_EMPHASIS_6
;
2471 case DP_TRAIN_VOLTAGE_SWING_800
:
2472 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2473 case DP_TRAIN_VOLTAGE_SWING_1200
:
2475 return DP_TRAIN_PRE_EMPHASIS_0
;
2480 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2482 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2484 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2485 struct intel_crtc
*intel_crtc
=
2486 to_intel_crtc(dport
->base
.base
.crtc
);
2487 unsigned long demph_reg_value
, preemph_reg_value
,
2488 uniqtranscale_reg_value
;
2489 uint8_t train_set
= intel_dp
->train_set
[0];
2490 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2491 int pipe
= intel_crtc
->pipe
;
2493 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2494 case DP_TRAIN_PRE_EMPHASIS_0
:
2495 preemph_reg_value
= 0x0004000;
2496 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2497 case DP_TRAIN_VOLTAGE_SWING_400
:
2498 demph_reg_value
= 0x2B405555;
2499 uniqtranscale_reg_value
= 0x552AB83A;
2501 case DP_TRAIN_VOLTAGE_SWING_600
:
2502 demph_reg_value
= 0x2B404040;
2503 uniqtranscale_reg_value
= 0x5548B83A;
2505 case DP_TRAIN_VOLTAGE_SWING_800
:
2506 demph_reg_value
= 0x2B245555;
2507 uniqtranscale_reg_value
= 0x5560B83A;
2509 case DP_TRAIN_VOLTAGE_SWING_1200
:
2510 demph_reg_value
= 0x2B405555;
2511 uniqtranscale_reg_value
= 0x5598DA3A;
2517 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2518 preemph_reg_value
= 0x0002000;
2519 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2520 case DP_TRAIN_VOLTAGE_SWING_400
:
2521 demph_reg_value
= 0x2B404040;
2522 uniqtranscale_reg_value
= 0x5552B83A;
2524 case DP_TRAIN_VOLTAGE_SWING_600
:
2525 demph_reg_value
= 0x2B404848;
2526 uniqtranscale_reg_value
= 0x5580B83A;
2528 case DP_TRAIN_VOLTAGE_SWING_800
:
2529 demph_reg_value
= 0x2B404040;
2530 uniqtranscale_reg_value
= 0x55ADDA3A;
2536 case DP_TRAIN_PRE_EMPHASIS_6
:
2537 preemph_reg_value
= 0x0000000;
2538 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2539 case DP_TRAIN_VOLTAGE_SWING_400
:
2540 demph_reg_value
= 0x2B305555;
2541 uniqtranscale_reg_value
= 0x5570B83A;
2543 case DP_TRAIN_VOLTAGE_SWING_600
:
2544 demph_reg_value
= 0x2B2B4040;
2545 uniqtranscale_reg_value
= 0x55ADDA3A;
2551 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2552 preemph_reg_value
= 0x0006000;
2553 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2554 case DP_TRAIN_VOLTAGE_SWING_400
:
2555 demph_reg_value
= 0x1B405555;
2556 uniqtranscale_reg_value
= 0x55ADDA3A;
2566 mutex_lock(&dev_priv
->dpio_lock
);
2567 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2568 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2569 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2570 uniqtranscale_reg_value
);
2571 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2572 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2573 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2574 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2575 mutex_unlock(&dev_priv
->dpio_lock
);
2580 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
2582 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2584 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2585 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
2586 u32 deemph_reg_value
, margin_reg_value
, val
;
2587 uint8_t train_set
= intel_dp
->train_set
[0];
2588 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2589 enum pipe pipe
= intel_crtc
->pipe
;
2592 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2593 case DP_TRAIN_PRE_EMPHASIS_0
:
2594 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2595 case DP_TRAIN_VOLTAGE_SWING_400
:
2596 deemph_reg_value
= 128;
2597 margin_reg_value
= 52;
2599 case DP_TRAIN_VOLTAGE_SWING_600
:
2600 deemph_reg_value
= 128;
2601 margin_reg_value
= 77;
2603 case DP_TRAIN_VOLTAGE_SWING_800
:
2604 deemph_reg_value
= 128;
2605 margin_reg_value
= 102;
2607 case DP_TRAIN_VOLTAGE_SWING_1200
:
2608 deemph_reg_value
= 128;
2609 margin_reg_value
= 154;
2610 /* FIXME extra to set for 1200 */
2616 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2617 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2618 case DP_TRAIN_VOLTAGE_SWING_400
:
2619 deemph_reg_value
= 85;
2620 margin_reg_value
= 78;
2622 case DP_TRAIN_VOLTAGE_SWING_600
:
2623 deemph_reg_value
= 85;
2624 margin_reg_value
= 116;
2626 case DP_TRAIN_VOLTAGE_SWING_800
:
2627 deemph_reg_value
= 85;
2628 margin_reg_value
= 154;
2634 case DP_TRAIN_PRE_EMPHASIS_6
:
2635 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2636 case DP_TRAIN_VOLTAGE_SWING_400
:
2637 deemph_reg_value
= 64;
2638 margin_reg_value
= 104;
2640 case DP_TRAIN_VOLTAGE_SWING_600
:
2641 deemph_reg_value
= 64;
2642 margin_reg_value
= 154;
2648 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2649 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2650 case DP_TRAIN_VOLTAGE_SWING_400
:
2651 deemph_reg_value
= 43;
2652 margin_reg_value
= 154;
2662 mutex_lock(&dev_priv
->dpio_lock
);
2664 /* Clear calc init */
2665 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2666 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2667 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2669 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2670 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2671 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2673 /* Program swing deemph */
2674 for (i
= 0; i
< 4; i
++) {
2675 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
2676 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
2677 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
2678 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
2681 /* Program swing margin */
2682 for (i
= 0; i
< 4; i
++) {
2683 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2684 val
&= ~DPIO_SWING_MARGIN000_MASK
;
2685 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
2686 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2689 /* Disable unique transition scale */
2690 for (i
= 0; i
< 4; i
++) {
2691 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2692 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2693 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2696 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
2697 == DP_TRAIN_PRE_EMPHASIS_0
) &&
2698 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
2699 == DP_TRAIN_VOLTAGE_SWING_1200
)) {
2702 * The document said it needs to set bit 27 for ch0 and bit 26
2703 * for ch1. Might be a typo in the doc.
2704 * For now, for this unique transition scale selection, set bit
2705 * 27 for ch0 and ch1.
2707 for (i
= 0; i
< 4; i
++) {
2708 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2709 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2710 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2713 for (i
= 0; i
< 4; i
++) {
2714 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2715 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2716 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2717 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2721 /* Start swing calculation */
2722 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2723 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2724 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2726 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2727 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2728 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2731 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
2732 val
|= DPIO_LRC_BYPASS
;
2733 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
2735 mutex_unlock(&dev_priv
->dpio_lock
);
2741 intel_get_adjust_train(struct intel_dp
*intel_dp
,
2742 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2747 uint8_t voltage_max
;
2748 uint8_t preemph_max
;
2750 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2751 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2752 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2760 voltage_max
= intel_dp_voltage_max(intel_dp
);
2761 if (v
>= voltage_max
)
2762 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2764 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2765 if (p
>= preemph_max
)
2766 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2768 for (lane
= 0; lane
< 4; lane
++)
2769 intel_dp
->train_set
[lane
] = v
| p
;
2773 intel_gen4_signal_levels(uint8_t train_set
)
2775 uint32_t signal_levels
= 0;
2777 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2778 case DP_TRAIN_VOLTAGE_SWING_400
:
2780 signal_levels
|= DP_VOLTAGE_0_4
;
2782 case DP_TRAIN_VOLTAGE_SWING_600
:
2783 signal_levels
|= DP_VOLTAGE_0_6
;
2785 case DP_TRAIN_VOLTAGE_SWING_800
:
2786 signal_levels
|= DP_VOLTAGE_0_8
;
2788 case DP_TRAIN_VOLTAGE_SWING_1200
:
2789 signal_levels
|= DP_VOLTAGE_1_2
;
2792 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2793 case DP_TRAIN_PRE_EMPHASIS_0
:
2795 signal_levels
|= DP_PRE_EMPHASIS_0
;
2797 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2798 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2800 case DP_TRAIN_PRE_EMPHASIS_6
:
2801 signal_levels
|= DP_PRE_EMPHASIS_6
;
2803 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2804 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2807 return signal_levels
;
2810 /* Gen6's DP voltage swing and pre-emphasis control */
2812 intel_gen6_edp_signal_levels(uint8_t train_set
)
2814 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2815 DP_TRAIN_PRE_EMPHASIS_MASK
);
2816 switch (signal_levels
) {
2817 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2818 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2819 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2820 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2821 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2822 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2823 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2824 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2825 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2826 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2827 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2828 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2829 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2830 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2832 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2833 "0x%x\n", signal_levels
);
2834 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2838 /* Gen7's DP voltage swing and pre-emphasis control */
2840 intel_gen7_edp_signal_levels(uint8_t train_set
)
2842 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2843 DP_TRAIN_PRE_EMPHASIS_MASK
);
2844 switch (signal_levels
) {
2845 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2846 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2847 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2848 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2849 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2850 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2852 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2853 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2854 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2855 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2857 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2858 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2859 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2860 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2863 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2864 "0x%x\n", signal_levels
);
2865 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2869 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2871 intel_hsw_signal_levels(uint8_t train_set
)
2873 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2874 DP_TRAIN_PRE_EMPHASIS_MASK
);
2875 switch (signal_levels
) {
2876 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2877 return DDI_BUF_EMP_400MV_0DB_HSW
;
2878 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2879 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2880 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2881 return DDI_BUF_EMP_400MV_6DB_HSW
;
2882 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2883 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2885 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2886 return DDI_BUF_EMP_600MV_0DB_HSW
;
2887 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2888 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2889 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2890 return DDI_BUF_EMP_600MV_6DB_HSW
;
2892 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2893 return DDI_BUF_EMP_800MV_0DB_HSW
;
2894 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2895 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2897 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2898 "0x%x\n", signal_levels
);
2899 return DDI_BUF_EMP_400MV_0DB_HSW
;
2903 /* Properly updates "DP" with the correct signal levels. */
2905 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2907 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2908 enum port port
= intel_dig_port
->port
;
2909 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2910 uint32_t signal_levels
, mask
;
2911 uint8_t train_set
= intel_dp
->train_set
[0];
2913 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2914 signal_levels
= intel_hsw_signal_levels(train_set
);
2915 mask
= DDI_BUF_EMP_MASK
;
2916 } else if (IS_CHERRYVIEW(dev
)) {
2917 signal_levels
= intel_chv_signal_levels(intel_dp
);
2919 } else if (IS_VALLEYVIEW(dev
)) {
2920 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2922 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2923 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2924 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2925 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2926 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2927 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2929 signal_levels
= intel_gen4_signal_levels(train_set
);
2930 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2933 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2935 *DP
= (*DP
& ~mask
) | signal_levels
;
2939 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2941 uint8_t dp_train_pat
)
2943 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2944 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2946 enum port port
= intel_dig_port
->port
;
2947 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
2951 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2953 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2954 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2956 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2958 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2959 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2960 case DP_TRAINING_PATTERN_DISABLE
:
2961 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2964 case DP_TRAINING_PATTERN_1
:
2965 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2967 case DP_TRAINING_PATTERN_2
:
2968 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2970 case DP_TRAINING_PATTERN_3
:
2971 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2974 I915_WRITE(DP_TP_CTL(port
), temp
);
2976 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2977 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2979 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2980 case DP_TRAINING_PATTERN_DISABLE
:
2981 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2983 case DP_TRAINING_PATTERN_1
:
2984 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2986 case DP_TRAINING_PATTERN_2
:
2987 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2989 case DP_TRAINING_PATTERN_3
:
2990 DRM_ERROR("DP training pattern 3 not supported\n");
2991 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2996 if (IS_CHERRYVIEW(dev
))
2997 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2999 *DP
&= ~DP_LINK_TRAIN_MASK
;
3001 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
3002 case DP_TRAINING_PATTERN_DISABLE
:
3003 *DP
|= DP_LINK_TRAIN_OFF
;
3005 case DP_TRAINING_PATTERN_1
:
3006 *DP
|= DP_LINK_TRAIN_PAT_1
;
3008 case DP_TRAINING_PATTERN_2
:
3009 *DP
|= DP_LINK_TRAIN_PAT_2
;
3011 case DP_TRAINING_PATTERN_3
:
3012 if (IS_CHERRYVIEW(dev
)) {
3013 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
3015 DRM_ERROR("DP training pattern 3 not supported\n");
3016 *DP
|= DP_LINK_TRAIN_PAT_2
;
3022 I915_WRITE(intel_dp
->output_reg
, *DP
);
3023 POSTING_READ(intel_dp
->output_reg
);
3025 buf
[0] = dp_train_pat
;
3026 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3027 DP_TRAINING_PATTERN_DISABLE
) {
3028 /* don't write DP_TRAINING_LANEx_SET on disable */
3031 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3032 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3033 len
= intel_dp
->lane_count
+ 1;
3036 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3043 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3044 uint8_t dp_train_pat
)
3046 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3047 intel_dp_set_signal_levels(intel_dp
, DP
);
3048 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3052 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3053 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3055 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3056 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3060 intel_get_adjust_train(intel_dp
, link_status
);
3061 intel_dp_set_signal_levels(intel_dp
, DP
);
3063 I915_WRITE(intel_dp
->output_reg
, *DP
);
3064 POSTING_READ(intel_dp
->output_reg
);
3066 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3067 intel_dp
->train_set
, intel_dp
->lane_count
);
3069 return ret
== intel_dp
->lane_count
;
3072 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3074 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3075 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3077 enum port port
= intel_dig_port
->port
;
3083 val
= I915_READ(DP_TP_CTL(port
));
3084 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3085 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3086 I915_WRITE(DP_TP_CTL(port
), val
);
3089 * On PORT_A we can have only eDP in SST mode. There the only reason
3090 * we need to set idle transmission mode is to work around a HW issue
3091 * where we enable the pipe while not in idle link-training mode.
3092 * In this case there is requirement to wait for a minimum number of
3093 * idle patterns to be sent.
3098 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3100 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3103 /* Enable corresponding port and start training pattern 1 */
3105 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3107 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3108 struct drm_device
*dev
= encoder
->dev
;
3111 int voltage_tries
, loop_tries
;
3112 uint32_t DP
= intel_dp
->DP
;
3113 uint8_t link_config
[2];
3116 intel_ddi_prepare_link_retrain(encoder
);
3118 /* Write the link configuration data */
3119 link_config
[0] = intel_dp
->link_bw
;
3120 link_config
[1] = intel_dp
->lane_count
;
3121 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3122 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3123 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3126 link_config
[1] = DP_SET_ANSI_8B10B
;
3127 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3131 /* clock recovery */
3132 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3133 DP_TRAINING_PATTERN_1
|
3134 DP_LINK_SCRAMBLING_DISABLE
)) {
3135 DRM_ERROR("failed to enable link training\n");
3143 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3145 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3146 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3147 DRM_ERROR("failed to get link status\n");
3151 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3152 DRM_DEBUG_KMS("clock recovery OK\n");
3156 /* Check to see if we've tried the max voltage */
3157 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3158 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3160 if (i
== intel_dp
->lane_count
) {
3162 if (loop_tries
== 5) {
3163 DRM_ERROR("too many full retries, give up\n");
3166 intel_dp_reset_link_train(intel_dp
, &DP
,
3167 DP_TRAINING_PATTERN_1
|
3168 DP_LINK_SCRAMBLING_DISABLE
);
3173 /* Check to see if we've tried the same voltage 5 times */
3174 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3176 if (voltage_tries
== 5) {
3177 DRM_ERROR("too many voltage retries, give up\n");
3182 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3184 /* Update training set as requested by target */
3185 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3186 DRM_ERROR("failed to update link training\n");
3195 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3197 bool channel_eq
= false;
3198 int tries
, cr_tries
;
3199 uint32_t DP
= intel_dp
->DP
;
3200 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3202 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3203 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3204 training_pattern
= DP_TRAINING_PATTERN_3
;
3206 /* channel equalization */
3207 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3209 DP_LINK_SCRAMBLING_DISABLE
)) {
3210 DRM_ERROR("failed to start channel equalization\n");
3218 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3221 DRM_ERROR("failed to train DP, aborting\n");
3225 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3226 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3227 DRM_ERROR("failed to get link status\n");
3231 /* Make sure clock is still ok */
3232 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3233 intel_dp_start_link_train(intel_dp
);
3234 intel_dp_set_link_train(intel_dp
, &DP
,
3236 DP_LINK_SCRAMBLING_DISABLE
);
3241 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3246 /* Try 5 times, then try clock recovery if that fails */
3248 intel_dp_link_down(intel_dp
);
3249 intel_dp_start_link_train(intel_dp
);
3250 intel_dp_set_link_train(intel_dp
, &DP
,
3252 DP_LINK_SCRAMBLING_DISABLE
);
3258 /* Update training set as requested by target */
3259 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3260 DRM_ERROR("failed to update link training\n");
3266 intel_dp_set_idle_link_train(intel_dp
);
3271 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3275 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3277 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3278 DP_TRAINING_PATTERN_DISABLE
);
3282 intel_dp_link_down(struct intel_dp
*intel_dp
)
3284 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3285 enum port port
= intel_dig_port
->port
;
3286 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3288 struct intel_crtc
*intel_crtc
=
3289 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3290 uint32_t DP
= intel_dp
->DP
;
3292 if (WARN_ON(HAS_DDI(dev
)))
3295 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3298 DRM_DEBUG_KMS("\n");
3300 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3301 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3302 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3304 if (IS_CHERRYVIEW(dev
))
3305 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3307 DP
&= ~DP_LINK_TRAIN_MASK
;
3308 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3310 POSTING_READ(intel_dp
->output_reg
);
3312 if (HAS_PCH_IBX(dev
) &&
3313 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3314 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3316 /* Hardware workaround: leaving our transcoder select
3317 * set to transcoder B while it's off will prevent the
3318 * corresponding HDMI output on transcoder A.
3320 * Combine this with another hardware workaround:
3321 * transcoder select bit can only be cleared while the
3324 DP
&= ~DP_PIPEB_SELECT
;
3325 I915_WRITE(intel_dp
->output_reg
, DP
);
3327 /* Changes to enable or select take place the vblank
3328 * after being written.
3330 if (WARN_ON(crtc
== NULL
)) {
3331 /* We should never try to disable a port without a crtc
3332 * attached. For paranoia keep the code around for a
3334 POSTING_READ(intel_dp
->output_reg
);
3337 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3340 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3341 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3342 POSTING_READ(intel_dp
->output_reg
);
3343 msleep(intel_dp
->panel_power_down_delay
);
3347 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3349 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3350 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3353 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
3355 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3356 sizeof(intel_dp
->dpcd
)) < 0)
3357 return false; /* aux transfer failed */
3359 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
3360 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
3361 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
3363 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3364 return false; /* DPCD not present */
3366 /* Check if the panel supports PSR */
3367 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3368 if (is_edp(intel_dp
)) {
3369 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3371 sizeof(intel_dp
->psr_dpcd
));
3372 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3373 dev_priv
->psr
.sink_support
= true;
3374 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3378 /* Training Pattern 3 support */
3379 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3380 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3381 intel_dp
->use_tps3
= true;
3382 DRM_DEBUG_KMS("Displayport TPS3 supported");
3384 intel_dp
->use_tps3
= false;
3386 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3387 DP_DWN_STRM_PORT_PRESENT
))
3388 return true; /* native DP sink */
3390 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3391 return true; /* no per-port downstream info */
3393 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3394 intel_dp
->downstream_ports
,
3395 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3396 return false; /* downstream port status fetch failed */
3402 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3406 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3409 intel_edp_panel_vdd_on(intel_dp
);
3411 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3412 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3413 buf
[0], buf
[1], buf
[2]);
3415 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3416 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3417 buf
[0], buf
[1], buf
[2]);
3419 edp_panel_vdd_off(intel_dp
, false);
3423 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3427 if (!intel_dp
->can_mst
)
3430 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3433 _edp_panel_vdd_on(intel_dp
);
3434 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3435 if (buf
[0] & DP_MST_CAP
) {
3436 DRM_DEBUG_KMS("Sink is MST capable\n");
3437 intel_dp
->is_mst
= true;
3439 DRM_DEBUG_KMS("Sink is not MST capable\n");
3440 intel_dp
->is_mst
= false;
3443 edp_panel_vdd_off(intel_dp
, false);
3445 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3446 return intel_dp
->is_mst
;
3449 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3451 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3452 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3453 struct intel_crtc
*intel_crtc
=
3454 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3457 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
3460 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
3463 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3464 DP_TEST_SINK_START
) < 0)
3467 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3468 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3469 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3471 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3474 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
3479 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3481 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3482 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3483 sink_irq_vector
, 1) == 1;
3487 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3491 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3493 sink_irq_vector
, 14);
3501 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3503 /* NAK by default */
3504 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3508 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3512 if (intel_dp
->is_mst
) {
3517 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3521 /* check link status - esi[10] = 0x200c */
3522 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3523 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3524 intel_dp_start_link_train(intel_dp
);
3525 intel_dp_complete_link_train(intel_dp
);
3526 intel_dp_stop_link_train(intel_dp
);
3529 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3530 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3533 for (retry
= 0; retry
< 3; retry
++) {
3535 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3536 DP_SINK_COUNT_ESI
+1,
3543 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3545 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3553 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3554 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3555 intel_dp
->is_mst
= false;
3556 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3557 /* send a hotplug event */
3558 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3565 * According to DP spec
3568 * 2. Configure link according to Receiver Capabilities
3569 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3570 * 4. Check link status on receipt of hot-plug interrupt
3573 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3575 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3576 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3578 u8 link_status
[DP_LINK_STATUS_SIZE
];
3580 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3582 if (!intel_encoder
->connectors_active
)
3585 if (WARN_ON(!intel_encoder
->base
.crtc
))
3588 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3591 /* Try to read receiver status if the link appears to be up */
3592 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3596 /* Now read the DPCD to see if it's actually running */
3597 if (!intel_dp_get_dpcd(intel_dp
)) {
3601 /* Try to read the source of the interrupt */
3602 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3603 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3604 /* Clear interrupt source */
3605 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3606 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3609 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3610 intel_dp_handle_test_request(intel_dp
);
3611 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3612 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3615 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3616 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3617 intel_encoder
->base
.name
);
3618 intel_dp_start_link_train(intel_dp
);
3619 intel_dp_complete_link_train(intel_dp
);
3620 intel_dp_stop_link_train(intel_dp
);
3624 /* XXX this is probably wrong for multiple downstream ports */
3625 static enum drm_connector_status
3626 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3628 uint8_t *dpcd
= intel_dp
->dpcd
;
3631 if (!intel_dp_get_dpcd(intel_dp
))
3632 return connector_status_disconnected
;
3634 /* if there's no downstream port, we're done */
3635 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3636 return connector_status_connected
;
3638 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3639 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3640 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3643 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3645 return connector_status_unknown
;
3647 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3648 : connector_status_disconnected
;
3651 /* If no HPD, poke DDC gently */
3652 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3653 return connector_status_connected
;
3655 /* Well we tried, say unknown for unreliable port types */
3656 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3657 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3658 if (type
== DP_DS_PORT_TYPE_VGA
||
3659 type
== DP_DS_PORT_TYPE_NON_EDID
)
3660 return connector_status_unknown
;
3662 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3663 DP_DWN_STRM_PORT_TYPE_MASK
;
3664 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3665 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3666 return connector_status_unknown
;
3669 /* Anything else is out of spec, warn and ignore */
3670 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3671 return connector_status_disconnected
;
3674 static enum drm_connector_status
3675 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3677 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3679 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3680 enum drm_connector_status status
;
3682 /* Can't disconnect eDP, but you can close the lid... */
3683 if (is_edp(intel_dp
)) {
3684 status
= intel_panel_detect(dev
);
3685 if (status
== connector_status_unknown
)
3686 status
= connector_status_connected
;
3690 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3691 return connector_status_disconnected
;
3693 return intel_dp_detect_dpcd(intel_dp
);
3696 static enum drm_connector_status
3697 g4x_dp_detect(struct intel_dp
*intel_dp
)
3699 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3701 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3704 /* Can't disconnect eDP, but you can close the lid... */
3705 if (is_edp(intel_dp
)) {
3706 enum drm_connector_status status
;
3708 status
= intel_panel_detect(dev
);
3709 if (status
== connector_status_unknown
)
3710 status
= connector_status_connected
;
3714 if (IS_VALLEYVIEW(dev
)) {
3715 switch (intel_dig_port
->port
) {
3717 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3720 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3723 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3726 return connector_status_unknown
;
3729 switch (intel_dig_port
->port
) {
3731 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3734 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3737 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3740 return connector_status_unknown
;
3744 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3745 return connector_status_disconnected
;
3747 return intel_dp_detect_dpcd(intel_dp
);
3750 static struct edid
*
3751 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3753 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3755 /* use cached edid if we have one */
3756 if (intel_connector
->edid
) {
3758 if (IS_ERR(intel_connector
->edid
))
3761 return drm_edid_duplicate(intel_connector
->edid
);
3764 return drm_get_edid(connector
, adapter
);
3768 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3770 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3772 /* use cached edid if we have one */
3773 if (intel_connector
->edid
) {
3775 if (IS_ERR(intel_connector
->edid
))
3778 return intel_connector_update_modes(connector
,
3779 intel_connector
->edid
);
3782 return intel_ddc_get_modes(connector
, adapter
);
3785 static enum drm_connector_status
3786 intel_dp_detect(struct drm_connector
*connector
, bool force
)
3788 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3789 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3790 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3791 struct drm_device
*dev
= connector
->dev
;
3792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3793 enum drm_connector_status status
;
3794 enum intel_display_power_domain power_domain
;
3795 struct edid
*edid
= NULL
;
3798 power_domain
= intel_display_port_power_domain(intel_encoder
);
3799 intel_display_power_get(dev_priv
, power_domain
);
3801 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3802 connector
->base
.id
, connector
->name
);
3804 if (intel_dp
->is_mst
) {
3805 /* MST devices are disconnected from a monitor POV */
3806 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3807 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3808 status
= connector_status_disconnected
;
3812 intel_dp
->has_audio
= false;
3814 if (HAS_PCH_SPLIT(dev
))
3815 status
= ironlake_dp_detect(intel_dp
);
3817 status
= g4x_dp_detect(intel_dp
);
3819 if (status
!= connector_status_connected
)
3822 intel_dp_probe_oui(intel_dp
);
3824 ret
= intel_dp_probe_mst(intel_dp
);
3826 /* if we are in MST mode then this connector
3827 won't appear connected or have anything with EDID on it */
3828 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3829 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3830 status
= connector_status_disconnected
;
3834 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
3835 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
3837 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3839 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
3844 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3845 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3846 status
= connector_status_connected
;
3849 intel_display_power_put(dev_priv
, power_domain
);
3853 static int intel_dp_get_modes(struct drm_connector
*connector
)
3855 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3856 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3857 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3858 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3859 struct drm_device
*dev
= connector
->dev
;
3860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3861 enum intel_display_power_domain power_domain
;
3864 /* We should parse the EDID data and find out if it has an audio sink
3867 power_domain
= intel_display_port_power_domain(intel_encoder
);
3868 intel_display_power_get(dev_priv
, power_domain
);
3870 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->aux
.ddc
);
3871 intel_display_power_put(dev_priv
, power_domain
);
3875 /* if eDP has no EDID, fall back to fixed mode */
3876 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3877 struct drm_display_mode
*mode
;
3878 mode
= drm_mode_duplicate(dev
,
3879 intel_connector
->panel
.fixed_mode
);
3881 drm_mode_probed_add(connector
, mode
);
3889 intel_dp_detect_audio(struct drm_connector
*connector
)
3891 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3892 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3893 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3894 struct drm_device
*dev
= connector
->dev
;
3895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3896 enum intel_display_power_domain power_domain
;
3898 bool has_audio
= false;
3900 power_domain
= intel_display_port_power_domain(intel_encoder
);
3901 intel_display_power_get(dev_priv
, power_domain
);
3903 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3905 has_audio
= drm_detect_monitor_audio(edid
);
3909 intel_display_power_put(dev_priv
, power_domain
);
3915 intel_dp_set_property(struct drm_connector
*connector
,
3916 struct drm_property
*property
,
3919 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3920 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3921 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3922 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3925 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3929 if (property
== dev_priv
->force_audio_property
) {
3933 if (i
== intel_dp
->force_audio
)
3936 intel_dp
->force_audio
= i
;
3938 if (i
== HDMI_AUDIO_AUTO
)
3939 has_audio
= intel_dp_detect_audio(connector
);
3941 has_audio
= (i
== HDMI_AUDIO_ON
);
3943 if (has_audio
== intel_dp
->has_audio
)
3946 intel_dp
->has_audio
= has_audio
;
3950 if (property
== dev_priv
->broadcast_rgb_property
) {
3951 bool old_auto
= intel_dp
->color_range_auto
;
3952 uint32_t old_range
= intel_dp
->color_range
;
3955 case INTEL_BROADCAST_RGB_AUTO
:
3956 intel_dp
->color_range_auto
= true;
3958 case INTEL_BROADCAST_RGB_FULL
:
3959 intel_dp
->color_range_auto
= false;
3960 intel_dp
->color_range
= 0;
3962 case INTEL_BROADCAST_RGB_LIMITED
:
3963 intel_dp
->color_range_auto
= false;
3964 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3970 if (old_auto
== intel_dp
->color_range_auto
&&
3971 old_range
== intel_dp
->color_range
)
3977 if (is_edp(intel_dp
) &&
3978 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3979 if (val
== DRM_MODE_SCALE_NONE
) {
3980 DRM_DEBUG_KMS("no scaling not supported\n");
3984 if (intel_connector
->panel
.fitting_mode
== val
) {
3985 /* the eDP scaling property is not changed */
3988 intel_connector
->panel
.fitting_mode
= val
;
3996 if (intel_encoder
->base
.crtc
)
3997 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4003 intel_dp_connector_destroy(struct drm_connector
*connector
)
4005 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4007 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4008 kfree(intel_connector
->edid
);
4010 /* Can't call is_edp() since the encoder may have been destroyed
4012 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4013 intel_panel_fini(&intel_connector
->panel
);
4015 drm_connector_cleanup(connector
);
4019 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4021 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4022 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4023 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4025 drm_dp_aux_unregister(&intel_dp
->aux
);
4026 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4027 drm_encoder_cleanup(encoder
);
4028 if (is_edp(intel_dp
)) {
4029 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4030 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4031 edp_panel_vdd_off_sync(intel_dp
);
4032 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4033 if (intel_dp
->edp_notifier
.notifier_call
) {
4034 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4035 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4038 kfree(intel_dig_port
);
4041 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4043 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4045 if (!is_edp(intel_dp
))
4048 edp_panel_vdd_off_sync(intel_dp
);
4051 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4053 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder
));
4056 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4057 .dpms
= intel_connector_dpms
,
4058 .detect
= intel_dp_detect
,
4059 .fill_modes
= drm_helper_probe_single_connector_modes
,
4060 .set_property
= intel_dp_set_property
,
4061 .destroy
= intel_dp_connector_destroy
,
4064 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4065 .get_modes
= intel_dp_get_modes
,
4066 .mode_valid
= intel_dp_mode_valid
,
4067 .best_encoder
= intel_best_encoder
,
4070 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4071 .reset
= intel_dp_encoder_reset
,
4072 .destroy
= intel_dp_encoder_destroy
,
4076 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4082 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4084 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4085 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4086 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4088 enum intel_display_power_domain power_domain
;
4091 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4092 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4094 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4095 port_name(intel_dig_port
->port
),
4096 long_hpd
? "long" : "short");
4098 power_domain
= intel_display_port_power_domain(intel_encoder
);
4099 intel_display_power_get(dev_priv
, power_domain
);
4102 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4105 if (!intel_dp_get_dpcd(intel_dp
)) {
4109 intel_dp_probe_oui(intel_dp
);
4111 if (!intel_dp_probe_mst(intel_dp
))
4115 if (intel_dp
->is_mst
) {
4116 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4120 if (!intel_dp
->is_mst
) {
4122 * we'll check the link status via the normal hot plug path later -
4123 * but for short hpds we should check it now
4125 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4126 intel_dp_check_link_status(intel_dp
);
4127 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4133 /* if we were in MST mode, and device is not there get out of MST mode */
4134 if (intel_dp
->is_mst
) {
4135 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4136 intel_dp
->is_mst
= false;
4137 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4140 intel_display_power_put(dev_priv
, power_domain
);
4145 /* Return which DP Port should be selected for Transcoder DP control */
4147 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4149 struct drm_device
*dev
= crtc
->dev
;
4150 struct intel_encoder
*intel_encoder
;
4151 struct intel_dp
*intel_dp
;
4153 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4154 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4156 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4157 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4158 return intel_dp
->output_reg
;
4164 /* check the VBT to see whether the eDP is on DP-D port */
4165 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4168 union child_device_config
*p_child
;
4170 static const short port_mapping
[] = {
4171 [PORT_B
] = PORT_IDPB
,
4172 [PORT_C
] = PORT_IDPC
,
4173 [PORT_D
] = PORT_IDPD
,
4179 if (!dev_priv
->vbt
.child_dev_num
)
4182 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4183 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4185 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4186 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4187 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4194 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4196 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4198 intel_attach_force_audio_property(connector
);
4199 intel_attach_broadcast_rgb_property(connector
);
4200 intel_dp
->color_range_auto
= true;
4202 if (is_edp(intel_dp
)) {
4203 drm_mode_create_scaling_mode_property(connector
->dev
);
4204 drm_object_attach_property(
4206 connector
->dev
->mode_config
.scaling_mode_property
,
4207 DRM_MODE_SCALE_ASPECT
);
4208 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4212 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4214 intel_dp
->last_power_cycle
= jiffies
;
4215 intel_dp
->last_power_on
= jiffies
;
4216 intel_dp
->last_backlight_off
= jiffies
;
4220 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4221 struct intel_dp
*intel_dp
,
4222 struct edp_power_seq
*out
)
4224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4225 struct edp_power_seq cur
, vbt
, spec
, final
;
4226 u32 pp_on
, pp_off
, pp_div
, pp
;
4227 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4229 if (HAS_PCH_SPLIT(dev
)) {
4230 pp_ctrl_reg
= PCH_PP_CONTROL
;
4231 pp_on_reg
= PCH_PP_ON_DELAYS
;
4232 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4233 pp_div_reg
= PCH_PP_DIVISOR
;
4235 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4237 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4238 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4239 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4240 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4243 /* Workaround: Need to write PP_CONTROL with the unlock key as
4244 * the very first thing. */
4245 pp
= ironlake_get_pp_control(intel_dp
);
4246 I915_WRITE(pp_ctrl_reg
, pp
);
4248 pp_on
= I915_READ(pp_on_reg
);
4249 pp_off
= I915_READ(pp_off_reg
);
4250 pp_div
= I915_READ(pp_div_reg
);
4252 /* Pull timing values out of registers */
4253 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4254 PANEL_POWER_UP_DELAY_SHIFT
;
4256 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4257 PANEL_LIGHT_ON_DELAY_SHIFT
;
4259 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4260 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4262 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4263 PANEL_POWER_DOWN_DELAY_SHIFT
;
4265 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4266 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4268 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4269 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4271 vbt
= dev_priv
->vbt
.edp_pps
;
4273 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4274 * our hw here, which are all in 100usec. */
4275 spec
.t1_t3
= 210 * 10;
4276 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4277 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4278 spec
.t10
= 500 * 10;
4279 /* This one is special and actually in units of 100ms, but zero
4280 * based in the hw (so we need to add 100 ms). But the sw vbt
4281 * table multiplies it with 1000 to make it in units of 100usec,
4283 spec
.t11_t12
= (510 + 100) * 10;
4285 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4286 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4288 /* Use the max of the register settings and vbt. If both are
4289 * unset, fall back to the spec limits. */
4290 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4292 max(cur.field, vbt.field))
4293 assign_final(t1_t3
);
4297 assign_final(t11_t12
);
4300 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4301 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4302 intel_dp
->backlight_on_delay
= get_delay(t8
);
4303 intel_dp
->backlight_off_delay
= get_delay(t9
);
4304 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4305 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4308 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4309 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4310 intel_dp
->panel_power_cycle_delay
);
4312 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4313 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4320 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4321 struct intel_dp
*intel_dp
,
4322 struct edp_power_seq
*seq
)
4324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4325 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4326 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4327 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4328 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4330 if (HAS_PCH_SPLIT(dev
)) {
4331 pp_on_reg
= PCH_PP_ON_DELAYS
;
4332 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4333 pp_div_reg
= PCH_PP_DIVISOR
;
4335 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4337 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4338 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4339 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4343 * And finally store the new values in the power sequencer. The
4344 * backlight delays are set to 1 because we do manual waits on them. For
4345 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4346 * we'll end up waiting for the backlight off delay twice: once when we
4347 * do the manual sleep, and once when we disable the panel and wait for
4348 * the PP_STATUS bit to become zero.
4350 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4351 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4352 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4353 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4354 /* Compute the divisor for the pp clock, simply match the Bspec
4356 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4357 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4358 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4360 /* Haswell doesn't have any port selection bits for the panel
4361 * power sequencer any more. */
4362 if (IS_VALLEYVIEW(dev
)) {
4363 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4364 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4366 port_sel
= PANEL_PORT_SELECT_DPA
;
4368 port_sel
= PANEL_PORT_SELECT_DPD
;
4373 I915_WRITE(pp_on_reg
, pp_on
);
4374 I915_WRITE(pp_off_reg
, pp_off
);
4375 I915_WRITE(pp_div_reg
, pp_div
);
4377 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4378 I915_READ(pp_on_reg
),
4379 I915_READ(pp_off_reg
),
4380 I915_READ(pp_div_reg
));
4383 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4386 struct intel_encoder
*encoder
;
4387 struct intel_dp
*intel_dp
= NULL
;
4388 struct intel_crtc_config
*config
= NULL
;
4389 struct intel_crtc
*intel_crtc
= NULL
;
4390 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4392 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4394 if (refresh_rate
<= 0) {
4395 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4399 if (intel_connector
== NULL
) {
4400 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4405 * FIXME: This needs proper synchronization with psr state. But really
4406 * hard to tell without seeing the user of this function of this code.
4407 * Check locking and ordering once that lands.
4409 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4410 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4414 encoder
= intel_attached_encoder(&intel_connector
->base
);
4415 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4416 intel_crtc
= encoder
->new_crtc
;
4419 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4423 config
= &intel_crtc
->config
;
4425 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4426 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4430 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4431 index
= DRRS_LOW_RR
;
4433 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4435 "DRRS requested for previously set RR...ignoring\n");
4439 if (!intel_crtc
->active
) {
4440 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4444 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4445 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4446 val
= I915_READ(reg
);
4447 if (index
> DRRS_HIGH_RR
) {
4448 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4449 intel_dp_set_m_n(intel_crtc
);
4451 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4453 I915_WRITE(reg
, val
);
4457 * mutex taken to ensure that there is no race between differnt
4458 * drrs calls trying to update refresh rate. This scenario may occur
4459 * in future when idleness detection based DRRS in kernel and
4460 * possible calls from user space to set differnt RR are made.
4463 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4465 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4467 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4469 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4472 static struct drm_display_mode
*
4473 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4474 struct intel_connector
*intel_connector
,
4475 struct drm_display_mode
*fixed_mode
)
4477 struct drm_connector
*connector
= &intel_connector
->base
;
4478 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4479 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4481 struct drm_display_mode
*downclock_mode
= NULL
;
4483 if (INTEL_INFO(dev
)->gen
<= 6) {
4484 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4488 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4489 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4493 downclock_mode
= intel_find_panel_downclock
4494 (dev
, fixed_mode
, connector
);
4496 if (!downclock_mode
) {
4497 DRM_DEBUG_KMS("DRRS not supported\n");
4501 dev_priv
->drrs
.connector
= intel_connector
;
4503 mutex_init(&intel_dp
->drrs_state
.mutex
);
4505 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
4507 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
4508 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4509 return downclock_mode
;
4512 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
)
4514 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4516 struct intel_dp
*intel_dp
;
4517 enum intel_display_power_domain power_domain
;
4519 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4522 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4523 if (!edp_have_panel_vdd(intel_dp
))
4526 * The VDD bit needs a power domain reference, so if the bit is
4527 * already enabled when we boot or resume, grab this reference and
4528 * schedule a vdd off, so we don't hold on to the reference
4531 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4532 power_domain
= intel_display_port_power_domain(intel_encoder
);
4533 intel_display_power_get(dev_priv
, power_domain
);
4535 edp_panel_vdd_schedule_off(intel_dp
);
4538 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4539 struct intel_connector
*intel_connector
,
4540 struct edp_power_seq
*power_seq
)
4542 struct drm_connector
*connector
= &intel_connector
->base
;
4543 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4544 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4545 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4547 struct drm_display_mode
*fixed_mode
= NULL
;
4548 struct drm_display_mode
*downclock_mode
= NULL
;
4550 struct drm_display_mode
*scan
;
4553 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
4555 if (!is_edp(intel_dp
))
4558 intel_edp_panel_vdd_sanitize(intel_encoder
);
4560 /* Cache DPCD and EDID for edp. */
4561 intel_edp_panel_vdd_on(intel_dp
);
4562 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
4563 edp_panel_vdd_off(intel_dp
, false);
4566 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4567 dev_priv
->no_aux_handshake
=
4568 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4569 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4571 /* if this fails, presume the device is a ghost */
4572 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4576 /* We now know it's not a ghost, init power sequence regs. */
4577 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
4579 mutex_lock(&dev
->mode_config
.mutex
);
4580 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
4582 if (drm_add_edid_modes(connector
, edid
)) {
4583 drm_mode_connector_update_edid_property(connector
,
4585 drm_edid_to_eld(connector
, edid
);
4588 edid
= ERR_PTR(-EINVAL
);
4591 edid
= ERR_PTR(-ENOENT
);
4593 intel_connector
->edid
= edid
;
4595 /* prefer fixed mode from EDID if available */
4596 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
4597 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
4598 fixed_mode
= drm_mode_duplicate(dev
, scan
);
4599 downclock_mode
= intel_dp_drrs_init(
4601 intel_connector
, fixed_mode
);
4606 /* fallback to VBT if available for eDP */
4607 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
4608 fixed_mode
= drm_mode_duplicate(dev
,
4609 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
4611 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4613 mutex_unlock(&dev
->mode_config
.mutex
);
4615 if (IS_VALLEYVIEW(dev
)) {
4616 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
4617 register_reboot_notifier(&intel_dp
->edp_notifier
);
4620 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
4621 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
4622 intel_panel_setup_backlight(connector
);
4628 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
4629 struct intel_connector
*intel_connector
)
4631 struct drm_connector
*connector
= &intel_connector
->base
;
4632 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4633 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4634 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4636 enum port port
= intel_dig_port
->port
;
4637 struct edp_power_seq power_seq
= { 0 };
4640 /* intel_dp vfuncs */
4641 if (IS_VALLEYVIEW(dev
))
4642 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
4643 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4644 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
4645 else if (HAS_PCH_SPLIT(dev
))
4646 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
4648 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
4650 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
4652 /* Preserve the current hw state. */
4653 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4654 intel_dp
->attached_connector
= intel_connector
;
4656 if (intel_dp_is_edp(dev
, port
))
4657 type
= DRM_MODE_CONNECTOR_eDP
;
4659 type
= DRM_MODE_CONNECTOR_DisplayPort
;
4662 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4663 * for DP the encoder type can be set by the caller to
4664 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4666 if (type
== DRM_MODE_CONNECTOR_eDP
)
4667 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
4669 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4670 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
4673 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
4674 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
4676 connector
->interlace_allowed
= true;
4677 connector
->doublescan_allowed
= 0;
4679 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
4680 edp_panel_vdd_work
);
4682 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
4683 drm_connector_register(connector
);
4686 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
4688 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
4689 intel_connector
->unregister
= intel_dp_connector_unregister
;
4691 /* Set up the hotplug pin. */
4694 intel_encoder
->hpd_pin
= HPD_PORT_A
;
4697 intel_encoder
->hpd_pin
= HPD_PORT_B
;
4700 intel_encoder
->hpd_pin
= HPD_PORT_C
;
4703 intel_encoder
->hpd_pin
= HPD_PORT_D
;
4709 if (is_edp(intel_dp
)) {
4710 intel_dp_init_panel_power_timestamps(intel_dp
);
4711 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
4714 intel_dp_aux_init(intel_dp
, intel_connector
);
4716 /* init MST on ports that can support it */
4717 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
4718 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
4719 intel_dp_mst_encoder_init(intel_dig_port
, intel_connector
->base
.base
.id
);
4723 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
4724 drm_dp_aux_unregister(&intel_dp
->aux
);
4725 if (is_edp(intel_dp
)) {
4726 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4727 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4728 edp_panel_vdd_off_sync(intel_dp
);
4729 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4731 drm_connector_unregister(connector
);
4732 drm_connector_cleanup(connector
);
4736 intel_dp_add_properties(intel_dp
, connector
);
4738 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4739 * 0xd. Failure to do so will result in spurious interrupts being
4740 * generated on the port when a cable is not attached.
4742 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
4743 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
4744 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
4751 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
4753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4754 struct intel_digital_port
*intel_dig_port
;
4755 struct intel_encoder
*intel_encoder
;
4756 struct drm_encoder
*encoder
;
4757 struct intel_connector
*intel_connector
;
4759 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
4760 if (!intel_dig_port
)
4763 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
4764 if (!intel_connector
) {
4765 kfree(intel_dig_port
);
4769 intel_encoder
= &intel_dig_port
->base
;
4770 encoder
= &intel_encoder
->base
;
4772 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
4773 DRM_MODE_ENCODER_TMDS
);
4775 intel_encoder
->compute_config
= intel_dp_compute_config
;
4776 intel_encoder
->disable
= intel_disable_dp
;
4777 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
4778 intel_encoder
->get_config
= intel_dp_get_config
;
4779 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
4780 if (IS_CHERRYVIEW(dev
)) {
4781 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
4782 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
4783 intel_encoder
->enable
= vlv_enable_dp
;
4784 intel_encoder
->post_disable
= chv_post_disable_dp
;
4785 } else if (IS_VALLEYVIEW(dev
)) {
4786 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
4787 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
4788 intel_encoder
->enable
= vlv_enable_dp
;
4789 intel_encoder
->post_disable
= vlv_post_disable_dp
;
4791 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
4792 intel_encoder
->enable
= g4x_enable_dp
;
4793 intel_encoder
->post_disable
= g4x_post_disable_dp
;
4796 intel_dig_port
->port
= port
;
4797 intel_dig_port
->dp
.output_reg
= output_reg
;
4799 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4800 if (IS_CHERRYVIEW(dev
)) {
4802 intel_encoder
->crtc_mask
= 1 << 2;
4804 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
4806 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
4808 intel_encoder
->cloneable
= 0;
4809 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
4811 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
4812 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
4814 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
4815 drm_encoder_cleanup(encoder
);
4816 kfree(intel_dig_port
);
4817 kfree(intel_connector
);
4821 void intel_dp_mst_suspend(struct drm_device
*dev
)
4823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4827 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
4828 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
4829 if (!intel_dig_port
)
4832 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
4833 if (!intel_dig_port
->dp
.can_mst
)
4835 if (intel_dig_port
->dp
.is_mst
)
4836 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
4841 void intel_dp_mst_resume(struct drm_device
*dev
)
4843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4846 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
4847 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
4848 if (!intel_dig_port
)
4850 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
4853 if (!intel_dig_port
->dp
.can_mst
)
4856 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
4858 intel_dp_check_mst_status(&intel_dig_port
->dp
);