2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
34 #include "drm_crtc_helper.h"
35 #include "intel_drv.h"
38 #include "drm_dp_helper.h"
40 #define DP_RECEIVER_CAP_SIZE 0xf
41 #define DP_LINK_STATUS_SIZE 6
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 #define DP_LINK_CONFIGURATION_SIZE 9
47 struct intel_encoder base
;
50 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
57 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
58 struct i2c_adapter adapter
;
59 struct i2c_algo_dp_aux_data algo
;
62 int panel_power_up_delay
;
63 int panel_power_down_delay
;
64 int panel_power_cycle_delay
;
65 int backlight_on_delay
;
66 int backlight_off_delay
;
67 struct drm_display_mode
*panel_fixed_mode
; /* for eDP */
68 struct delayed_work panel_vdd_work
;
73 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
74 * @intel_dp: DP struct
76 * If a CPU or PCH DP output is attached to an eDP panel, this function
77 * will return true, and false otherwise.
79 static bool is_edp(struct intel_dp
*intel_dp
)
81 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
85 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
86 * @intel_dp: DP struct
88 * Returns true if the given DP struct corresponds to a PCH DP port attached
89 * to an eDP panel, false otherwise. Helpful for determining whether we
90 * may need FDI resources for a given DP output or not.
92 static bool is_pch_edp(struct intel_dp
*intel_dp
)
94 return intel_dp
->is_pch_edp
;
98 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
99 * @intel_dp: DP struct
101 * Returns true if the given DP struct corresponds to a CPU eDP port.
103 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
105 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
108 static struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
110 return container_of(encoder
, struct intel_dp
, base
.base
);
113 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
115 return container_of(intel_attached_encoder(connector
),
116 struct intel_dp
, base
);
120 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
121 * @encoder: DRM encoder
123 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
124 * by intel_display.c.
126 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
128 struct intel_dp
*intel_dp
;
133 intel_dp
= enc_to_intel_dp(encoder
);
135 return is_pch_edp(intel_dp
);
138 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
139 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
140 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
143 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
144 int *lane_num
, int *link_bw
)
146 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
148 *lane_num
= intel_dp
->lane_count
;
149 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
151 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
156 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
158 int max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
159 switch (max_lane_count
) {
160 case 1: case 2: case 4:
165 return max_lane_count
;
169 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
171 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
173 switch (max_link_bw
) {
174 case DP_LINK_BW_1_62
:
178 max_link_bw
= DP_LINK_BW_1_62
;
185 intel_dp_link_clock(uint8_t link_bw
)
187 if (link_bw
== DP_LINK_BW_2_7
)
194 * The units on the numbers in the next two are... bizarre. Examples will
195 * make it clearer; this one parallels an example in the eDP spec.
197 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
199 * 270000 * 1 * 8 / 10 == 216000
201 * The actual data capacity of that configuration is 2.16Gbit/s, so the
202 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
203 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
204 * 119000. At 18bpp that's 2142000 kilobits per second.
206 * Thus the strange-looking division by 10 in intel_dp_link_required, to
207 * get the result in decakilobits instead of kilobits.
211 intel_dp_link_required(struct intel_dp
*intel_dp
, int pixel_clock
)
213 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
214 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
218 bpp
= intel_crtc
->bpp
;
220 return (pixel_clock
* bpp
+ 9) / 10;
224 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
226 return (max_link_clock
* max_lanes
* 8) / 10;
230 intel_dp_mode_valid(struct drm_connector
*connector
,
231 struct drm_display_mode
*mode
)
233 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
234 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
235 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
237 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
238 if (mode
->hdisplay
> intel_dp
->panel_fixed_mode
->hdisplay
)
241 if (mode
->vdisplay
> intel_dp
->panel_fixed_mode
->vdisplay
)
245 if (intel_dp_link_required(intel_dp
, mode
->clock
)
246 > intel_dp_max_data_rate(max_link_clock
, max_lanes
))
247 return MODE_CLOCK_HIGH
;
249 if (mode
->clock
< 10000)
250 return MODE_CLOCK_LOW
;
256 pack_aux(uint8_t *src
, int src_bytes
)
263 for (i
= 0; i
< src_bytes
; i
++)
264 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
269 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
274 for (i
= 0; i
< dst_bytes
; i
++)
275 dst
[i
] = src
>> ((3-i
) * 8);
278 /* hrawclock is 1/4 the FSB frequency */
280 intel_hrawclk(struct drm_device
*dev
)
282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
285 clkcfg
= I915_READ(CLKCFG
);
286 switch (clkcfg
& CLKCFG_FSB_MASK
) {
295 case CLKCFG_FSB_1067
:
297 case CLKCFG_FSB_1333
:
299 /* these two are just a guess; one of them might be right */
300 case CLKCFG_FSB_1600
:
301 case CLKCFG_FSB_1600_ALT
:
308 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
310 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
313 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
316 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
318 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
321 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
325 intel_dp_check_edp(struct intel_dp
*intel_dp
)
327 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
330 if (!is_edp(intel_dp
))
332 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
333 WARN(1, "eDP powered off while attempting aux channel communication.\n");
334 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
335 I915_READ(PCH_PP_STATUS
),
336 I915_READ(PCH_PP_CONTROL
));
341 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
342 uint8_t *send
, int send_bytes
,
343 uint8_t *recv
, int recv_size
)
345 uint32_t output_reg
= intel_dp
->output_reg
;
346 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
348 uint32_t ch_ctl
= output_reg
+ 0x10;
349 uint32_t ch_data
= ch_ctl
+ 4;
353 uint32_t aux_clock_divider
;
356 intel_dp_check_edp(intel_dp
);
357 /* The clock divider is based off the hrawclk,
358 * and would like to run at 2MHz. So, take the
359 * hrawclk value and divide by 2 and use that
361 * Note that PCH attached eDP panels should use a 125MHz input
364 if (is_cpu_edp(intel_dp
)) {
366 aux_clock_divider
= 200; /* SNB eDP input clock at 400Mhz */
368 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
369 } else if (HAS_PCH_SPLIT(dev
))
370 aux_clock_divider
= 62; /* IRL input clock fixed at 125Mhz */
372 aux_clock_divider
= intel_hrawclk(dev
) / 2;
379 /* Try to wait for any previous AUX channel activity */
380 for (try = 0; try < 3; try++) {
381 status
= I915_READ(ch_ctl
);
382 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
388 WARN(1, "dp_aux_ch not started status 0x%08x\n",
393 /* Must try at least 3 times according to DP spec */
394 for (try = 0; try < 5; try++) {
395 /* Load the send data into the aux channel data registers */
396 for (i
= 0; i
< send_bytes
; i
+= 4)
397 I915_WRITE(ch_data
+ i
,
398 pack_aux(send
+ i
, send_bytes
- i
));
400 /* Send the command and wait for it to complete */
402 DP_AUX_CH_CTL_SEND_BUSY
|
403 DP_AUX_CH_CTL_TIME_OUT_400us
|
404 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
405 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
406 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
408 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
409 DP_AUX_CH_CTL_RECEIVE_ERROR
);
411 status
= I915_READ(ch_ctl
);
412 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
417 /* Clear done status and any errors */
421 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
422 DP_AUX_CH_CTL_RECEIVE_ERROR
);
423 if (status
& DP_AUX_CH_CTL_DONE
)
427 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
428 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
432 /* Check for timeout or receive error.
433 * Timeouts occur when the sink is not connected
435 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
436 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
440 /* Timeouts occur when the device isn't connected, so they're
441 * "normal" -- don't fill the kernel log with these */
442 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
443 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
447 /* Unload any bytes sent back from the other side */
448 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
449 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
450 if (recv_bytes
> recv_size
)
451 recv_bytes
= recv_size
;
453 for (i
= 0; i
< recv_bytes
; i
+= 4)
454 unpack_aux(I915_READ(ch_data
+ i
),
455 recv
+ i
, recv_bytes
- i
);
460 /* Write data to the aux channel in native mode */
462 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
463 uint16_t address
, uint8_t *send
, int send_bytes
)
470 intel_dp_check_edp(intel_dp
);
473 msg
[0] = AUX_NATIVE_WRITE
<< 4;
474 msg
[1] = address
>> 8;
475 msg
[2] = address
& 0xff;
476 msg
[3] = send_bytes
- 1;
477 memcpy(&msg
[4], send
, send_bytes
);
478 msg_bytes
= send_bytes
+ 4;
480 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
483 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
485 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
493 /* Write a single byte to the aux channel in native mode */
495 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
496 uint16_t address
, uint8_t byte
)
498 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
501 /* read bytes from a native aux channel */
503 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
504 uint16_t address
, uint8_t *recv
, int recv_bytes
)
513 intel_dp_check_edp(intel_dp
);
514 msg
[0] = AUX_NATIVE_READ
<< 4;
515 msg
[1] = address
>> 8;
516 msg
[2] = address
& 0xff;
517 msg
[3] = recv_bytes
- 1;
520 reply_bytes
= recv_bytes
+ 1;
523 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
530 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
531 memcpy(recv
, reply
+ 1, ret
- 1);
534 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
542 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
543 uint8_t write_byte
, uint8_t *read_byte
)
545 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
546 struct intel_dp
*intel_dp
= container_of(adapter
,
549 uint16_t address
= algo_data
->address
;
557 intel_dp_check_edp(intel_dp
);
558 /* Set up the command byte */
559 if (mode
& MODE_I2C_READ
)
560 msg
[0] = AUX_I2C_READ
<< 4;
562 msg
[0] = AUX_I2C_WRITE
<< 4;
564 if (!(mode
& MODE_I2C_STOP
))
565 msg
[0] |= AUX_I2C_MOT
<< 4;
567 msg
[1] = address
>> 8;
588 for (retry
= 0; retry
< 5; retry
++) {
589 ret
= intel_dp_aux_ch(intel_dp
,
593 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
597 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
598 case AUX_NATIVE_REPLY_ACK
:
599 /* I2C-over-AUX Reply field is only valid
600 * when paired with AUX ACK.
603 case AUX_NATIVE_REPLY_NACK
:
604 DRM_DEBUG_KMS("aux_ch native nack\n");
606 case AUX_NATIVE_REPLY_DEFER
:
610 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
615 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
616 case AUX_I2C_REPLY_ACK
:
617 if (mode
== MODE_I2C_READ
) {
618 *read_byte
= reply
[1];
620 return reply_bytes
- 1;
621 case AUX_I2C_REPLY_NACK
:
622 DRM_DEBUG_KMS("aux_i2c nack\n");
624 case AUX_I2C_REPLY_DEFER
:
625 DRM_DEBUG_KMS("aux_i2c defer\n");
629 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
634 DRM_ERROR("too many retries, giving up\n");
638 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
639 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
642 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
643 struct intel_connector
*intel_connector
, const char *name
)
647 DRM_DEBUG_KMS("i2c_init %s\n", name
);
648 intel_dp
->algo
.running
= false;
649 intel_dp
->algo
.address
= 0;
650 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
652 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
653 intel_dp
->adapter
.owner
= THIS_MODULE
;
654 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
655 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
656 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
657 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
658 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
660 ironlake_edp_panel_vdd_on(intel_dp
);
661 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
662 ironlake_edp_panel_vdd_off(intel_dp
, false);
667 intel_dp_mode_fixup(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
668 struct drm_display_mode
*adjusted_mode
)
670 struct drm_device
*dev
= encoder
->dev
;
671 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
672 int lane_count
, clock
;
673 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
674 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
675 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
677 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
678 intel_fixed_panel_mode(intel_dp
->panel_fixed_mode
, adjusted_mode
);
679 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
680 mode
, adjusted_mode
);
682 * the mode->clock is used to calculate the Data&Link M/N
683 * of the pipe. For the eDP the fixed clock should be used.
685 mode
->clock
= intel_dp
->panel_fixed_mode
->clock
;
688 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
689 for (clock
= 0; clock
<= max_clock
; clock
++) {
690 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
692 if (intel_dp_link_required(intel_dp
, mode
->clock
)
694 intel_dp
->link_bw
= bws
[clock
];
695 intel_dp
->lane_count
= lane_count
;
696 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
697 DRM_DEBUG_KMS("Display port link bw %02x lane "
698 "count %d clock %d\n",
699 intel_dp
->link_bw
, intel_dp
->lane_count
,
700 adjusted_mode
->clock
);
709 struct intel_dp_m_n
{
718 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
720 while (*num
> 0xffffff || *den
> 0xffffff) {
727 intel_dp_compute_m_n(int bpp
,
731 struct intel_dp_m_n
*m_n
)
734 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
735 m_n
->gmch_n
= link_clock
* nlanes
;
736 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
737 m_n
->link_m
= pixel_clock
;
738 m_n
->link_n
= link_clock
;
739 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
743 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
744 struct drm_display_mode
*adjusted_mode
)
746 struct drm_device
*dev
= crtc
->dev
;
747 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
748 struct drm_encoder
*encoder
;
749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
750 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
752 struct intel_dp_m_n m_n
;
753 int pipe
= intel_crtc
->pipe
;
756 * Find the lane count in the intel_encoder private
758 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
759 struct intel_dp
*intel_dp
;
761 if (encoder
->crtc
!= crtc
)
764 intel_dp
= enc_to_intel_dp(encoder
);
765 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
766 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
768 lane_count
= intel_dp
->lane_count
;
774 * Compute the GMCH and Link ratios. The '3' here is
775 * the number of bytes_per_pixel post-LUT, which we always
776 * set up for 8-bits of R/G/B, or 3 bytes total.
778 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
779 mode
->clock
, adjusted_mode
->clock
, &m_n
);
781 if (HAS_PCH_SPLIT(dev
)) {
782 I915_WRITE(TRANSDATA_M1(pipe
),
783 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
785 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
786 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
787 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
789 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
790 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
792 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
793 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
794 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
798 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
);
799 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
);
802 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
803 struct drm_display_mode
*adjusted_mode
)
805 struct drm_device
*dev
= encoder
->dev
;
806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
807 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
808 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
809 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
811 /* Turn on the eDP PLL if needed */
812 if (is_edp(intel_dp
)) {
813 if (!is_pch_edp(intel_dp
))
814 ironlake_edp_pll_on(encoder
);
816 ironlake_edp_pll_off(encoder
);
820 * There are three kinds of DP registers:
826 * IBX PCH and CPU are the same for almost everything,
827 * except that the CPU DP PLL is configured in this
830 * CPT PCH is quite different, having many bits moved
831 * to the TRANS_DP_CTL register instead. That
832 * configuration happens (oddly) in ironlake_pch_enable
835 /* Preserve the BIOS-computed detected bit. This is
836 * supposed to be read-only.
838 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
839 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
841 /* Handle DP bits in common between all three register formats */
843 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
845 switch (intel_dp
->lane_count
) {
847 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
850 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
853 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
856 if (intel_dp
->has_audio
) {
857 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
858 pipe_name(intel_crtc
->pipe
));
859 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
860 intel_write_eld(encoder
, adjusted_mode
);
862 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
863 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
864 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
865 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
867 * Check for DPCD version > 1.1 and enhanced framing support
869 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
870 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
871 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
874 /* Split out the IBX/CPU vs CPT settings */
876 if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
877 intel_dp
->DP
|= intel_dp
->color_range
;
879 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
880 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
881 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
882 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
883 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
885 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
886 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
888 if (intel_crtc
->pipe
== 1)
889 intel_dp
->DP
|= DP_PIPEB_SELECT
;
891 if (is_cpu_edp(intel_dp
)) {
892 /* don't miss out required setting for eDP */
893 intel_dp
->DP
|= DP_PLL_ENABLE
;
894 if (adjusted_mode
->clock
< 200000)
895 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
897 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
900 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
904 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
905 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
907 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
908 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
910 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
911 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
913 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
917 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
920 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
922 I915_READ(PCH_PP_STATUS
),
923 I915_READ(PCH_PP_CONTROL
));
925 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
926 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
927 I915_READ(PCH_PP_STATUS
),
928 I915_READ(PCH_PP_CONTROL
));
932 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
934 DRM_DEBUG_KMS("Wait for panel power on\n");
935 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
938 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
940 DRM_DEBUG_KMS("Wait for panel power off time\n");
941 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
944 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
946 DRM_DEBUG_KMS("Wait for panel power cycle\n");
947 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
951 /* Read the current pp_control value, unlocking the register if it
955 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
957 u32 control
= I915_READ(PCH_PP_CONTROL
);
959 control
&= ~PANEL_UNLOCK_MASK
;
960 control
|= PANEL_UNLOCK_REGS
;
964 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
966 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
970 if (!is_edp(intel_dp
))
972 DRM_DEBUG_KMS("Turn eDP VDD on\n");
974 WARN(intel_dp
->want_panel_vdd
,
975 "eDP VDD already requested on\n");
977 intel_dp
->want_panel_vdd
= true;
979 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
980 DRM_DEBUG_KMS("eDP VDD already on\n");
984 if (!ironlake_edp_have_panel_power(intel_dp
))
985 ironlake_wait_panel_power_cycle(intel_dp
);
987 pp
= ironlake_get_pp_control(dev_priv
);
989 I915_WRITE(PCH_PP_CONTROL
, pp
);
990 POSTING_READ(PCH_PP_CONTROL
);
991 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
992 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
995 * If the panel wasn't on, delay before accessing aux channel
997 if (!ironlake_edp_have_panel_power(intel_dp
)) {
998 DRM_DEBUG_KMS("eDP was not running\n");
999 msleep(intel_dp
->panel_power_up_delay
);
1003 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1005 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1009 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1010 pp
= ironlake_get_pp_control(dev_priv
);
1011 pp
&= ~EDP_FORCE_VDD
;
1012 I915_WRITE(PCH_PP_CONTROL
, pp
);
1013 POSTING_READ(PCH_PP_CONTROL
);
1015 /* Make sure sequencer is idle before allowing subsequent activity */
1016 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1017 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1019 msleep(intel_dp
->panel_power_down_delay
);
1023 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1025 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1026 struct intel_dp
, panel_vdd_work
);
1027 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1029 mutex_lock(&dev
->mode_config
.mutex
);
1030 ironlake_panel_vdd_off_sync(intel_dp
);
1031 mutex_unlock(&dev
->mode_config
.mutex
);
1034 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1036 if (!is_edp(intel_dp
))
1039 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1040 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1042 intel_dp
->want_panel_vdd
= false;
1045 ironlake_panel_vdd_off_sync(intel_dp
);
1048 * Queue the timer to fire a long
1049 * time from now (relative to the power down delay)
1050 * to keep the panel power up across a sequence of operations
1052 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1053 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1057 static void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1059 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1063 if (!is_edp(intel_dp
))
1066 DRM_DEBUG_KMS("Turn eDP power on\n");
1068 if (ironlake_edp_have_panel_power(intel_dp
)) {
1069 DRM_DEBUG_KMS("eDP power already on\n");
1073 ironlake_wait_panel_power_cycle(intel_dp
);
1075 pp
= ironlake_get_pp_control(dev_priv
);
1077 /* ILK workaround: disable reset around power sequence */
1078 pp
&= ~PANEL_POWER_RESET
;
1079 I915_WRITE(PCH_PP_CONTROL
, pp
);
1080 POSTING_READ(PCH_PP_CONTROL
);
1083 pp
|= POWER_TARGET_ON
;
1085 pp
|= PANEL_POWER_RESET
;
1087 I915_WRITE(PCH_PP_CONTROL
, pp
);
1088 POSTING_READ(PCH_PP_CONTROL
);
1090 ironlake_wait_panel_on(intel_dp
);
1093 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1094 I915_WRITE(PCH_PP_CONTROL
, pp
);
1095 POSTING_READ(PCH_PP_CONTROL
);
1099 static void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1101 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1105 if (!is_edp(intel_dp
))
1108 DRM_DEBUG_KMS("Turn eDP power off\n");
1110 WARN(intel_dp
->want_panel_vdd
, "Cannot turn power off while VDD is on\n");
1112 pp
= ironlake_get_pp_control(dev_priv
);
1113 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1114 I915_WRITE(PCH_PP_CONTROL
, pp
);
1115 POSTING_READ(PCH_PP_CONTROL
);
1117 ironlake_wait_panel_off(intel_dp
);
1120 static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1122 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1126 if (!is_edp(intel_dp
))
1129 DRM_DEBUG_KMS("\n");
1131 * If we enable the backlight right away following a panel power
1132 * on, we may see slight flicker as the panel syncs with the eDP
1133 * link. So delay a bit to make sure the image is solid before
1134 * allowing it to appear.
1136 msleep(intel_dp
->backlight_on_delay
);
1137 pp
= ironlake_get_pp_control(dev_priv
);
1138 pp
|= EDP_BLC_ENABLE
;
1139 I915_WRITE(PCH_PP_CONTROL
, pp
);
1140 POSTING_READ(PCH_PP_CONTROL
);
1143 static void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1145 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1149 if (!is_edp(intel_dp
))
1152 DRM_DEBUG_KMS("\n");
1153 pp
= ironlake_get_pp_control(dev_priv
);
1154 pp
&= ~EDP_BLC_ENABLE
;
1155 I915_WRITE(PCH_PP_CONTROL
, pp
);
1156 POSTING_READ(PCH_PP_CONTROL
);
1157 msleep(intel_dp
->backlight_off_delay
);
1160 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
)
1162 struct drm_device
*dev
= encoder
->dev
;
1163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1166 DRM_DEBUG_KMS("\n");
1167 dpa_ctl
= I915_READ(DP_A
);
1168 dpa_ctl
|= DP_PLL_ENABLE
;
1169 I915_WRITE(DP_A
, dpa_ctl
);
1174 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
)
1176 struct drm_device
*dev
= encoder
->dev
;
1177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1180 dpa_ctl
= I915_READ(DP_A
);
1181 dpa_ctl
&= ~DP_PLL_ENABLE
;
1182 I915_WRITE(DP_A
, dpa_ctl
);
1187 /* If the sink supports it, try to set the power state appropriately */
1188 static void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1192 /* Should have a valid DPCD by this point */
1193 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1196 if (mode
!= DRM_MODE_DPMS_ON
) {
1197 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1200 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1203 * When turning on, we need to retry for 1ms to give the sink
1206 for (i
= 0; i
< 3; i
++) {
1207 ret
= intel_dp_aux_native_write_1(intel_dp
,
1217 static void intel_dp_prepare(struct drm_encoder
*encoder
)
1219 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1221 ironlake_edp_backlight_off(intel_dp
);
1222 ironlake_edp_panel_off(intel_dp
);
1224 /* Wake up the sink first */
1225 ironlake_edp_panel_vdd_on(intel_dp
);
1226 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1227 intel_dp_link_down(intel_dp
);
1228 ironlake_edp_panel_vdd_off(intel_dp
, false);
1230 /* Make sure the panel is off before trying to
1235 static void intel_dp_commit(struct drm_encoder
*encoder
)
1237 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1238 struct drm_device
*dev
= encoder
->dev
;
1239 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1241 ironlake_edp_panel_vdd_on(intel_dp
);
1242 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1243 intel_dp_start_link_train(intel_dp
);
1244 ironlake_edp_panel_on(intel_dp
);
1245 ironlake_edp_panel_vdd_off(intel_dp
, true);
1246 intel_dp_complete_link_train(intel_dp
);
1247 ironlake_edp_backlight_on(intel_dp
);
1249 intel_dp
->dpms_mode
= DRM_MODE_DPMS_ON
;
1251 if (HAS_PCH_CPT(dev
))
1252 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
1256 intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
1258 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1259 struct drm_device
*dev
= encoder
->dev
;
1260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1261 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1263 if (mode
!= DRM_MODE_DPMS_ON
) {
1264 ironlake_edp_backlight_off(intel_dp
);
1265 ironlake_edp_panel_off(intel_dp
);
1267 ironlake_edp_panel_vdd_on(intel_dp
);
1268 intel_dp_sink_dpms(intel_dp
, mode
);
1269 intel_dp_link_down(intel_dp
);
1270 ironlake_edp_panel_vdd_off(intel_dp
, false);
1272 if (is_cpu_edp(intel_dp
))
1273 ironlake_edp_pll_off(encoder
);
1275 if (is_cpu_edp(intel_dp
))
1276 ironlake_edp_pll_on(encoder
);
1278 ironlake_edp_panel_vdd_on(intel_dp
);
1279 intel_dp_sink_dpms(intel_dp
, mode
);
1280 if (!(dp_reg
& DP_PORT_EN
)) {
1281 intel_dp_start_link_train(intel_dp
);
1282 ironlake_edp_panel_on(intel_dp
);
1283 ironlake_edp_panel_vdd_off(intel_dp
, true);
1284 intel_dp_complete_link_train(intel_dp
);
1286 ironlake_edp_panel_vdd_off(intel_dp
, false);
1287 ironlake_edp_backlight_on(intel_dp
);
1289 intel_dp
->dpms_mode
= mode
;
1293 * Native read with retry for link status and receiver capability reads for
1294 * cases where the sink may still be asleep.
1297 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1298 uint8_t *recv
, int recv_bytes
)
1303 * Sinks are *supposed* to come up within 1ms from an off state,
1304 * but we're also supposed to retry 3 times per the spec.
1306 for (i
= 0; i
< 3; i
++) {
1307 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1309 if (ret
== recv_bytes
)
1318 * Fetch AUX CH registers 0x202 - 0x207 which contain
1319 * link status information
1322 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1324 return intel_dp_aux_native_read_retry(intel_dp
,
1327 DP_LINK_STATUS_SIZE
);
1331 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1334 return link_status
[r
- DP_LANE0_1_STATUS
];
1338 intel_get_adjust_request_voltage(uint8_t adjust_request
[2],
1341 int s
= ((lane
& 1) ?
1342 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1343 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1344 uint8_t l
= adjust_request
[lane
>>1];
1346 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1350 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request
[2],
1353 int s
= ((lane
& 1) ?
1354 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1355 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1356 uint8_t l
= adjust_request
[lane
>>1];
1358 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1363 static char *voltage_names
[] = {
1364 "0.4V", "0.6V", "0.8V", "1.2V"
1366 static char *pre_emph_names
[] = {
1367 "0dB", "3.5dB", "6dB", "9.5dB"
1369 static char *link_train_names
[] = {
1370 "pattern 1", "pattern 2", "idle", "off"
1375 * These are source-specific values; current Intel hardware supports
1376 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1378 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1379 #define I830_DP_VOLTAGE_MAX_CPT DP_TRAIN_VOLTAGE_SWING_1200
1382 intel_dp_pre_emphasis_max(uint8_t voltage_swing
)
1384 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1385 case DP_TRAIN_VOLTAGE_SWING_400
:
1386 return DP_TRAIN_PRE_EMPHASIS_6
;
1387 case DP_TRAIN_VOLTAGE_SWING_600
:
1388 return DP_TRAIN_PRE_EMPHASIS_6
;
1389 case DP_TRAIN_VOLTAGE_SWING_800
:
1390 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1391 case DP_TRAIN_VOLTAGE_SWING_1200
:
1393 return DP_TRAIN_PRE_EMPHASIS_0
;
1398 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1400 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1404 uint8_t *adjust_request
= link_status
+ (DP_ADJUST_REQUEST_LANE0_1
- DP_LANE0_1_STATUS
);
1407 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1408 uint8_t this_v
= intel_get_adjust_request_voltage(adjust_request
, lane
);
1409 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(adjust_request
, lane
);
1417 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1418 voltage_max
= I830_DP_VOLTAGE_MAX_CPT
;
1420 voltage_max
= I830_DP_VOLTAGE_MAX
;
1421 if (v
>= voltage_max
)
1422 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1424 if (p
>= intel_dp_pre_emphasis_max(v
))
1425 p
= intel_dp_pre_emphasis_max(v
) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1427 for (lane
= 0; lane
< 4; lane
++)
1428 intel_dp
->train_set
[lane
] = v
| p
;
1432 intel_dp_signal_levels(uint8_t train_set
)
1434 uint32_t signal_levels
= 0;
1436 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1437 case DP_TRAIN_VOLTAGE_SWING_400
:
1439 signal_levels
|= DP_VOLTAGE_0_4
;
1441 case DP_TRAIN_VOLTAGE_SWING_600
:
1442 signal_levels
|= DP_VOLTAGE_0_6
;
1444 case DP_TRAIN_VOLTAGE_SWING_800
:
1445 signal_levels
|= DP_VOLTAGE_0_8
;
1447 case DP_TRAIN_VOLTAGE_SWING_1200
:
1448 signal_levels
|= DP_VOLTAGE_1_2
;
1451 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1452 case DP_TRAIN_PRE_EMPHASIS_0
:
1454 signal_levels
|= DP_PRE_EMPHASIS_0
;
1456 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1457 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1459 case DP_TRAIN_PRE_EMPHASIS_6
:
1460 signal_levels
|= DP_PRE_EMPHASIS_6
;
1462 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1463 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1466 return signal_levels
;
1469 /* Gen6's DP voltage swing and pre-emphasis control */
1471 intel_gen6_edp_signal_levels(uint8_t train_set
)
1473 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1474 DP_TRAIN_PRE_EMPHASIS_MASK
);
1475 switch (signal_levels
) {
1476 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1477 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1478 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1479 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1480 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1481 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1482 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1483 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1484 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1485 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1486 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1487 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1488 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1489 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1491 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1492 "0x%x\n", signal_levels
);
1493 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1498 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1501 int s
= (lane
& 1) * 4;
1502 uint8_t l
= link_status
[lane
>>1];
1504 return (l
>> s
) & 0xf;
1507 /* Check for clock recovery is done on all channels */
1509 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1512 uint8_t lane_status
;
1514 for (lane
= 0; lane
< lane_count
; lane
++) {
1515 lane_status
= intel_get_lane_status(link_status
, lane
);
1516 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1522 /* Check to see if channel eq is done on all channels */
1523 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1524 DP_LANE_CHANNEL_EQ_DONE|\
1525 DP_LANE_SYMBOL_LOCKED)
1527 intel_channel_eq_ok(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1530 uint8_t lane_status
;
1533 lane_align
= intel_dp_link_status(link_status
,
1534 DP_LANE_ALIGN_STATUS_UPDATED
);
1535 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1537 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1538 lane_status
= intel_get_lane_status(link_status
, lane
);
1539 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1546 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1547 uint32_t dp_reg_value
,
1548 uint8_t dp_train_pat
)
1550 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1554 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1555 POSTING_READ(intel_dp
->output_reg
);
1557 intel_dp_aux_native_write_1(intel_dp
,
1558 DP_TRAINING_PATTERN_SET
,
1561 ret
= intel_dp_aux_native_write(intel_dp
,
1562 DP_TRAINING_LANE0_SET
,
1563 intel_dp
->train_set
,
1564 intel_dp
->lane_count
);
1565 if (ret
!= intel_dp
->lane_count
)
1571 /* Enable corresponding port and start training pattern 1 */
1573 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1575 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1577 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1580 bool clock_recovery
= false;
1581 int voltage_tries
, loop_tries
;
1583 uint32_t DP
= intel_dp
->DP
;
1586 * On CPT we have to enable the port in training pattern 1, which
1587 * will happen below in intel_dp_set_link_train. Otherwise, enable
1588 * the port and wait for it to become active.
1590 if (!HAS_PCH_CPT(dev
)) {
1591 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
1592 POSTING_READ(intel_dp
->output_reg
);
1593 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1596 /* Write the link configuration data */
1597 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1598 intel_dp
->link_configuration
,
1599 DP_LINK_CONFIGURATION_SIZE
);
1602 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1603 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1605 DP
&= ~DP_LINK_TRAIN_MASK
;
1606 memset(intel_dp
->train_set
, 0, 4);
1610 clock_recovery
= false;
1612 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1613 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1614 uint32_t signal_levels
;
1616 if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1617 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1618 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1620 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1621 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels
);
1622 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1625 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1626 reg
= DP
| DP_LINK_TRAIN_PAT_1_CPT
;
1628 reg
= DP
| DP_LINK_TRAIN_PAT_1
;
1630 if (!intel_dp_set_link_train(intel_dp
, reg
,
1631 DP_TRAINING_PATTERN_1
|
1632 DP_LINK_SCRAMBLING_DISABLE
))
1634 /* Set training pattern 1 */
1637 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1638 DRM_ERROR("failed to get link status\n");
1642 if (intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1643 DRM_DEBUG_KMS("clock recovery OK\n");
1644 clock_recovery
= true;
1648 /* Check to see if we've tried the max voltage */
1649 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1650 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1652 if (i
== intel_dp
->lane_count
) {
1654 if (loop_tries
== 5) {
1655 DRM_DEBUG_KMS("too many full retries, give up\n");
1658 memset(intel_dp
->train_set
, 0, 4);
1663 /* Check to see if we've tried the same voltage 5 times */
1664 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1666 if (voltage_tries
== 5) {
1667 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1672 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1674 /* Compute new intel_dp->train_set as requested by target */
1675 intel_get_adjust_train(intel_dp
, link_status
);
1682 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1684 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1686 bool channel_eq
= false;
1687 int tries
, cr_tries
;
1689 uint32_t DP
= intel_dp
->DP
;
1691 /* channel equalization */
1696 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1697 uint32_t signal_levels
;
1698 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1701 DRM_ERROR("failed to train DP, aborting\n");
1702 intel_dp_link_down(intel_dp
);
1706 if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1707 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1708 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1710 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1711 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1714 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1715 reg
= DP
| DP_LINK_TRAIN_PAT_2_CPT
;
1717 reg
= DP
| DP_LINK_TRAIN_PAT_2
;
1719 /* channel eq pattern */
1720 if (!intel_dp_set_link_train(intel_dp
, reg
,
1721 DP_TRAINING_PATTERN_2
|
1722 DP_LINK_SCRAMBLING_DISABLE
))
1726 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1729 /* Make sure clock is still ok */
1730 if (!intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1731 intel_dp_start_link_train(intel_dp
);
1736 if (intel_channel_eq_ok(intel_dp
, link_status
)) {
1741 /* Try 5 times, then try clock recovery if that fails */
1743 intel_dp_link_down(intel_dp
);
1744 intel_dp_start_link_train(intel_dp
);
1750 /* Compute new intel_dp->train_set as requested by target */
1751 intel_get_adjust_train(intel_dp
, link_status
);
1755 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1756 reg
= DP
| DP_LINK_TRAIN_OFF_CPT
;
1758 reg
= DP
| DP_LINK_TRAIN_OFF
;
1760 I915_WRITE(intel_dp
->output_reg
, reg
);
1761 POSTING_READ(intel_dp
->output_reg
);
1762 intel_dp_aux_native_write_1(intel_dp
,
1763 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
1767 intel_dp_link_down(struct intel_dp
*intel_dp
)
1769 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1771 uint32_t DP
= intel_dp
->DP
;
1773 if ((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0)
1776 DRM_DEBUG_KMS("\n");
1778 if (is_edp(intel_dp
)) {
1779 DP
&= ~DP_PLL_ENABLE
;
1780 I915_WRITE(intel_dp
->output_reg
, DP
);
1781 POSTING_READ(intel_dp
->output_reg
);
1785 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
)) {
1786 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1787 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1789 DP
&= ~DP_LINK_TRAIN_MASK
;
1790 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1792 POSTING_READ(intel_dp
->output_reg
);
1796 if (is_edp(intel_dp
)) {
1797 if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1798 DP
|= DP_LINK_TRAIN_OFF_CPT
;
1800 DP
|= DP_LINK_TRAIN_OFF
;
1803 if (!HAS_PCH_CPT(dev
) &&
1804 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
1805 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1807 /* Hardware workaround: leaving our transcoder select
1808 * set to transcoder B while it's off will prevent the
1809 * corresponding HDMI output on transcoder A.
1811 * Combine this with another hardware workaround:
1812 * transcoder select bit can only be cleared while the
1815 DP
&= ~DP_PIPEB_SELECT
;
1816 I915_WRITE(intel_dp
->output_reg
, DP
);
1818 /* Changes to enable or select take place the vblank
1819 * after being written.
1822 /* We can arrive here never having been attached
1823 * to a CRTC, for instance, due to inheriting
1824 * random state from the BIOS.
1826 * If the pipe is not running, play safe and
1827 * wait for the clocks to stabilise before
1830 POSTING_READ(intel_dp
->output_reg
);
1833 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
1836 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1837 POSTING_READ(intel_dp
->output_reg
);
1838 msleep(intel_dp
->panel_power_down_delay
);
1842 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
1844 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
1845 sizeof(intel_dp
->dpcd
)) &&
1846 (intel_dp
->dpcd
[DP_DPCD_REV
] != 0)) {
1854 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
1858 ret
= intel_dp_aux_native_read_retry(intel_dp
,
1859 DP_DEVICE_SERVICE_IRQ_VECTOR
,
1860 sink_irq_vector
, 1);
1868 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
1870 /* NAK by default */
1871 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_ACK
);
1875 * According to DP spec
1878 * 2. Configure link according to Receiver Capabilities
1879 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1880 * 4. Check link status on receipt of hot-plug interrupt
1884 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
1887 u8 link_status
[DP_LINK_STATUS_SIZE
];
1889 if (intel_dp
->dpms_mode
!= DRM_MODE_DPMS_ON
)
1892 if (!intel_dp
->base
.base
.crtc
)
1895 /* Try to read receiver status if the link appears to be up */
1896 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1897 intel_dp_link_down(intel_dp
);
1901 /* Now read the DPCD to see if it's actually running */
1902 if (!intel_dp_get_dpcd(intel_dp
)) {
1903 intel_dp_link_down(intel_dp
);
1907 /* Try to read the source of the interrupt */
1908 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
1909 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
1910 /* Clear interrupt source */
1911 intel_dp_aux_native_write_1(intel_dp
,
1912 DP_DEVICE_SERVICE_IRQ_VECTOR
,
1915 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
1916 intel_dp_handle_test_request(intel_dp
);
1917 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
1918 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
1921 if (!intel_channel_eq_ok(intel_dp
, link_status
)) {
1922 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1923 drm_get_encoder_name(&intel_dp
->base
.base
));
1924 intel_dp_start_link_train(intel_dp
);
1925 intel_dp_complete_link_train(intel_dp
);
1929 static enum drm_connector_status
1930 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
1932 if (intel_dp_get_dpcd(intel_dp
))
1933 return connector_status_connected
;
1934 return connector_status_disconnected
;
1937 static enum drm_connector_status
1938 ironlake_dp_detect(struct intel_dp
*intel_dp
)
1940 enum drm_connector_status status
;
1942 /* Can't disconnect eDP, but you can close the lid... */
1943 if (is_edp(intel_dp
)) {
1944 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
1945 if (status
== connector_status_unknown
)
1946 status
= connector_status_connected
;
1950 return intel_dp_detect_dpcd(intel_dp
);
1953 static enum drm_connector_status
1954 g4x_dp_detect(struct intel_dp
*intel_dp
)
1956 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1960 switch (intel_dp
->output_reg
) {
1962 bit
= DPB_HOTPLUG_INT_STATUS
;
1965 bit
= DPC_HOTPLUG_INT_STATUS
;
1968 bit
= DPD_HOTPLUG_INT_STATUS
;
1971 return connector_status_unknown
;
1974 temp
= I915_READ(PORT_HOTPLUG_STAT
);
1976 if ((temp
& bit
) == 0)
1977 return connector_status_disconnected
;
1979 return intel_dp_detect_dpcd(intel_dp
);
1982 static struct edid
*
1983 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
1985 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
1988 ironlake_edp_panel_vdd_on(intel_dp
);
1989 edid
= drm_get_edid(connector
, adapter
);
1990 ironlake_edp_panel_vdd_off(intel_dp
, false);
1995 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
1997 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2000 ironlake_edp_panel_vdd_on(intel_dp
);
2001 ret
= intel_ddc_get_modes(connector
, adapter
);
2002 ironlake_edp_panel_vdd_off(intel_dp
, false);
2008 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2010 * \return true if DP port is connected.
2011 * \return false if DP port is disconnected.
2013 static enum drm_connector_status
2014 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2016 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2017 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2018 enum drm_connector_status status
;
2019 struct edid
*edid
= NULL
;
2021 intel_dp
->has_audio
= false;
2023 if (HAS_PCH_SPLIT(dev
))
2024 status
= ironlake_dp_detect(intel_dp
);
2026 status
= g4x_dp_detect(intel_dp
);
2028 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2029 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
2030 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
2031 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
2033 if (status
!= connector_status_connected
)
2036 if (intel_dp
->force_audio
) {
2037 intel_dp
->has_audio
= intel_dp
->force_audio
> 0;
2039 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2041 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2042 connector
->display_info
.raw_edid
= NULL
;
2047 return connector_status_connected
;
2050 static int intel_dp_get_modes(struct drm_connector
*connector
)
2052 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2053 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2057 /* We should parse the EDID data and find out if it has an audio sink
2060 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2062 if (is_edp(intel_dp
) && !intel_dp
->panel_fixed_mode
) {
2063 struct drm_display_mode
*newmode
;
2064 list_for_each_entry(newmode
, &connector
->probed_modes
,
2066 if ((newmode
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2067 intel_dp
->panel_fixed_mode
=
2068 drm_mode_duplicate(dev
, newmode
);
2076 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2077 if (is_edp(intel_dp
)) {
2078 /* initialize panel mode from VBT if available for eDP */
2079 if (intel_dp
->panel_fixed_mode
== NULL
&& dev_priv
->lfp_lvds_vbt_mode
!= NULL
) {
2080 intel_dp
->panel_fixed_mode
=
2081 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2082 if (intel_dp
->panel_fixed_mode
) {
2083 intel_dp
->panel_fixed_mode
->type
|=
2084 DRM_MODE_TYPE_PREFERRED
;
2087 if (intel_dp
->panel_fixed_mode
) {
2088 struct drm_display_mode
*mode
;
2089 mode
= drm_mode_duplicate(dev
, intel_dp
->panel_fixed_mode
);
2090 drm_mode_probed_add(connector
, mode
);
2098 intel_dp_detect_audio(struct drm_connector
*connector
)
2100 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2102 bool has_audio
= false;
2104 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2106 has_audio
= drm_detect_monitor_audio(edid
);
2108 connector
->display_info
.raw_edid
= NULL
;
2116 intel_dp_set_property(struct drm_connector
*connector
,
2117 struct drm_property
*property
,
2120 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2121 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2124 ret
= drm_connector_property_set_value(connector
, property
, val
);
2128 if (property
== dev_priv
->force_audio_property
) {
2132 if (i
== intel_dp
->force_audio
)
2135 intel_dp
->force_audio
= i
;
2138 has_audio
= intel_dp_detect_audio(connector
);
2142 if (has_audio
== intel_dp
->has_audio
)
2145 intel_dp
->has_audio
= has_audio
;
2149 if (property
== dev_priv
->broadcast_rgb_property
) {
2150 if (val
== !!intel_dp
->color_range
)
2153 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2160 if (intel_dp
->base
.base
.crtc
) {
2161 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2162 drm_crtc_helper_set_mode(crtc
, &crtc
->mode
,
2171 intel_dp_destroy(struct drm_connector
*connector
)
2173 struct drm_device
*dev
= connector
->dev
;
2175 if (intel_dpd_is_edp(dev
))
2176 intel_panel_destroy_backlight(dev
);
2178 drm_sysfs_connector_remove(connector
);
2179 drm_connector_cleanup(connector
);
2183 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2185 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2187 i2c_del_adapter(&intel_dp
->adapter
);
2188 drm_encoder_cleanup(encoder
);
2189 if (is_edp(intel_dp
)) {
2190 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2191 ironlake_panel_vdd_off_sync(intel_dp
);
2196 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2197 .dpms
= intel_dp_dpms
,
2198 .mode_fixup
= intel_dp_mode_fixup
,
2199 .prepare
= intel_dp_prepare
,
2200 .mode_set
= intel_dp_mode_set
,
2201 .commit
= intel_dp_commit
,
2204 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2205 .dpms
= drm_helper_connector_dpms
,
2206 .detect
= intel_dp_detect
,
2207 .fill_modes
= drm_helper_probe_single_connector_modes
,
2208 .set_property
= intel_dp_set_property
,
2209 .destroy
= intel_dp_destroy
,
2212 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2213 .get_modes
= intel_dp_get_modes
,
2214 .mode_valid
= intel_dp_mode_valid
,
2215 .best_encoder
= intel_best_encoder
,
2218 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2219 .destroy
= intel_dp_encoder_destroy
,
2223 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2225 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
2227 intel_dp_check_link_status(intel_dp
);
2230 /* Return which DP Port should be selected for Transcoder DP control */
2232 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2234 struct drm_device
*dev
= crtc
->dev
;
2235 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2236 struct drm_encoder
*encoder
;
2238 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
2239 struct intel_dp
*intel_dp
;
2241 if (encoder
->crtc
!= crtc
)
2244 intel_dp
= enc_to_intel_dp(encoder
);
2245 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
2246 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
2247 return intel_dp
->output_reg
;
2253 /* check the VBT to see whether the eDP is on DP-D port */
2254 bool intel_dpd_is_edp(struct drm_device
*dev
)
2256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2257 struct child_device_config
*p_child
;
2260 if (!dev_priv
->child_dev_num
)
2263 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2264 p_child
= dev_priv
->child_dev
+ i
;
2266 if (p_child
->dvo_port
== PORT_IDPD
&&
2267 p_child
->device_type
== DEVICE_TYPE_eDP
)
2274 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2276 intel_attach_force_audio_property(connector
);
2277 intel_attach_broadcast_rgb_property(connector
);
2281 intel_dp_init(struct drm_device
*dev
, int output_reg
)
2283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2284 struct drm_connector
*connector
;
2285 struct intel_dp
*intel_dp
;
2286 struct intel_encoder
*intel_encoder
;
2287 struct intel_connector
*intel_connector
;
2288 const char *name
= NULL
;
2291 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
2295 intel_dp
->output_reg
= output_reg
;
2296 intel_dp
->dpms_mode
= -1;
2298 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2299 if (!intel_connector
) {
2303 intel_encoder
= &intel_dp
->base
;
2305 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
2306 if (intel_dpd_is_edp(dev
))
2307 intel_dp
->is_pch_edp
= true;
2309 if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
2310 type
= DRM_MODE_CONNECTOR_eDP
;
2311 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2313 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2314 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2317 connector
= &intel_connector
->base
;
2318 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2319 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2321 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2323 if (output_reg
== DP_B
|| output_reg
== PCH_DP_B
)
2324 intel_encoder
->clone_mask
= (1 << INTEL_DP_B_CLONE_BIT
);
2325 else if (output_reg
== DP_C
|| output_reg
== PCH_DP_C
)
2326 intel_encoder
->clone_mask
= (1 << INTEL_DP_C_CLONE_BIT
);
2327 else if (output_reg
== DP_D
|| output_reg
== PCH_DP_D
)
2328 intel_encoder
->clone_mask
= (1 << INTEL_DP_D_CLONE_BIT
);
2330 if (is_edp(intel_dp
)) {
2331 intel_encoder
->clone_mask
= (1 << INTEL_EDP_CLONE_BIT
);
2332 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2333 ironlake_panel_vdd_work
);
2336 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2337 connector
->interlace_allowed
= true;
2338 connector
->doublescan_allowed
= 0;
2340 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2341 DRM_MODE_ENCODER_TMDS
);
2342 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2344 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2345 drm_sysfs_connector_add(connector
);
2347 /* Set up the DDC bus. */
2348 switch (output_reg
) {
2354 dev_priv
->hotplug_supported_mask
|=
2355 HDMIB_HOTPLUG_INT_STATUS
;
2360 dev_priv
->hotplug_supported_mask
|=
2361 HDMIC_HOTPLUG_INT_STATUS
;
2366 dev_priv
->hotplug_supported_mask
|=
2367 HDMID_HOTPLUG_INT_STATUS
;
2372 /* Cache some DPCD data in the eDP case */
2373 if (is_edp(intel_dp
)) {
2375 struct edp_power_seq cur
, vbt
;
2376 u32 pp_on
, pp_off
, pp_div
;
2378 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2379 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2380 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2382 /* Pull timing values out of registers */
2383 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2384 PANEL_POWER_UP_DELAY_SHIFT
;
2386 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2387 PANEL_LIGHT_ON_DELAY_SHIFT
;
2389 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2390 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2392 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2393 PANEL_POWER_DOWN_DELAY_SHIFT
;
2395 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2396 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2398 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2399 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2401 vbt
= dev_priv
->edp
.pps
;
2403 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2404 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2406 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2408 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2409 intel_dp
->backlight_on_delay
= get_delay(t8
);
2410 intel_dp
->backlight_off_delay
= get_delay(t9
);
2411 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2412 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2414 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2415 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2416 intel_dp
->panel_power_cycle_delay
);
2418 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2419 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2421 ironlake_edp_panel_vdd_on(intel_dp
);
2422 ret
= intel_dp_get_dpcd(intel_dp
);
2423 ironlake_edp_panel_vdd_off(intel_dp
, false);
2426 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2427 dev_priv
->no_aux_handshake
=
2428 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2429 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2431 /* if this fails, presume the device is a ghost */
2432 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2433 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2434 intel_dp_destroy(&intel_connector
->base
);
2439 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2441 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2443 if (is_edp(intel_dp
)) {
2444 dev_priv
->int_edp_connector
= connector
;
2445 intel_panel_setup_backlight(dev
);
2448 intel_dp_add_properties(intel_dp
, connector
);
2450 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2451 * 0xd. Failure to do so will result in spurious interrupts being
2452 * generated on the port when a cable is not attached.
2454 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2455 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2456 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);