2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int skl_rates
[] = { 162000, 216000, 270000,
95 324000, 432000, 540000 };
96 static const int chv_rates
[] = { 162000, 202500, 210000, 216000,
97 243000, 270000, 324000, 405000,
98 420000, 432000, 540000 };
99 static const int default_rates
[] = { 162000, 270000, 540000 };
102 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
103 * @intel_dp: DP struct
105 * If a CPU or PCH DP output is attached to an eDP panel, this function
106 * will return true, and false otherwise.
108 static bool is_edp(struct intel_dp
*intel_dp
)
110 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
112 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
115 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
117 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
119 return intel_dig_port
->base
.base
.dev
;
122 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
124 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
127 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
128 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
129 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
130 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
131 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
135 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
137 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
139 switch (max_link_bw
) {
140 case DP_LINK_BW_1_62
:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw
= DP_LINK_BW_1_62
;
153 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
155 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
156 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
157 u8 source_max
, sink_max
;
160 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
161 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
164 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
166 return min(source_max
, sink_max
);
170 * The units on the numbers in the next two are... bizarre. Examples will
171 * make it clearer; this one parallels an example in the eDP spec.
173 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
175 * 270000 * 1 * 8 / 10 == 216000
177 * The actual data capacity of that configuration is 2.16Gbit/s, so the
178 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
179 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
180 * 119000. At 18bpp that's 2142000 kilobits per second.
182 * Thus the strange-looking division by 10 in intel_dp_link_required, to
183 * get the result in decakilobits instead of kilobits.
187 intel_dp_link_required(int pixel_clock
, int bpp
)
189 return (pixel_clock
* bpp
+ 9) / 10;
193 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
195 return (max_link_clock
* max_lanes
* 8) / 10;
198 static enum drm_mode_status
199 intel_dp_mode_valid(struct drm_connector
*connector
,
200 struct drm_display_mode
*mode
)
202 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
203 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
204 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
205 int target_clock
= mode
->clock
;
206 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
208 if (is_edp(intel_dp
) && fixed_mode
) {
209 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
212 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
215 target_clock
= fixed_mode
->clock
;
218 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
219 max_lanes
= intel_dp_max_lane_count(intel_dp
);
221 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
222 mode_rate
= intel_dp_link_required(target_clock
, 18);
224 if (mode_rate
> max_rate
)
225 return MODE_CLOCK_HIGH
;
227 if (mode
->clock
< 10000)
228 return MODE_CLOCK_LOW
;
230 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
231 return MODE_H_ILLEGAL
;
236 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
243 for (i
= 0; i
< src_bytes
; i
++)
244 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
248 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
253 for (i
= 0; i
< dst_bytes
; i
++)
254 dst
[i
] = src
>> ((3-i
) * 8);
257 /* hrawclock is 1/4 the FSB frequency */
259 intel_hrawclk(struct drm_device
*dev
)
261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
264 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
265 if (IS_VALLEYVIEW(dev
))
268 clkcfg
= I915_READ(CLKCFG
);
269 switch (clkcfg
& CLKCFG_FSB_MASK
) {
278 case CLKCFG_FSB_1067
:
280 case CLKCFG_FSB_1333
:
282 /* these two are just a guess; one of them might be right */
283 case CLKCFG_FSB_1600
:
284 case CLKCFG_FSB_1600_ALT
:
292 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
293 struct intel_dp
*intel_dp
);
295 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
296 struct intel_dp
*intel_dp
);
298 static void pps_lock(struct intel_dp
*intel_dp
)
300 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
301 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
302 struct drm_device
*dev
= encoder
->base
.dev
;
303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
304 enum intel_display_power_domain power_domain
;
307 * See vlv_power_sequencer_reset() why we need
308 * a power domain reference here.
310 power_domain
= intel_display_port_power_domain(encoder
);
311 intel_display_power_get(dev_priv
, power_domain
);
313 mutex_lock(&dev_priv
->pps_mutex
);
316 static void pps_unlock(struct intel_dp
*intel_dp
)
318 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
319 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
320 struct drm_device
*dev
= encoder
->base
.dev
;
321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
322 enum intel_display_power_domain power_domain
;
324 mutex_unlock(&dev_priv
->pps_mutex
);
326 power_domain
= intel_display_port_power_domain(encoder
);
327 intel_display_power_put(dev_priv
, power_domain
);
331 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
333 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
334 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
336 enum pipe pipe
= intel_dp
->pps_pipe
;
340 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
341 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
342 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
345 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
346 pipe_name(pipe
), port_name(intel_dig_port
->port
));
348 /* Preserve the BIOS-computed detected bit. This is
349 * supposed to be read-only.
351 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
352 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
353 DP
|= DP_PORT_WIDTH(1);
354 DP
|= DP_LINK_TRAIN_PAT_1
;
356 if (IS_CHERRYVIEW(dev
))
357 DP
|= DP_PIPE_SELECT_CHV(pipe
);
358 else if (pipe
== PIPE_B
)
359 DP
|= DP_PIPEB_SELECT
;
361 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
364 * The DPLL for the pipe must be enabled for this to work.
365 * So enable temporarily it if it's not already enabled.
368 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
369 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
372 * Similar magic as in intel_dp_enable_port().
373 * We _must_ do this port enable + disable trick
374 * to make this power seqeuencer lock onto the port.
375 * Otherwise even VDD force bit won't work.
377 I915_WRITE(intel_dp
->output_reg
, DP
);
378 POSTING_READ(intel_dp
->output_reg
);
380 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
381 POSTING_READ(intel_dp
->output_reg
);
383 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
384 POSTING_READ(intel_dp
->output_reg
);
387 vlv_force_pll_off(dev
, pipe
);
391 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
393 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
394 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
396 struct intel_encoder
*encoder
;
397 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
400 lockdep_assert_held(&dev_priv
->pps_mutex
);
402 /* We should never land here with regular DP ports */
403 WARN_ON(!is_edp(intel_dp
));
405 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
406 return intel_dp
->pps_pipe
;
409 * We don't have power sequencer currently.
410 * Pick one that's not used by other ports.
412 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
414 struct intel_dp
*tmp
;
416 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
419 tmp
= enc_to_intel_dp(&encoder
->base
);
421 if (tmp
->pps_pipe
!= INVALID_PIPE
)
422 pipes
&= ~(1 << tmp
->pps_pipe
);
426 * Didn't find one. This should not happen since there
427 * are two power sequencers and up to two eDP ports.
429 if (WARN_ON(pipes
== 0))
432 pipe
= ffs(pipes
) - 1;
434 vlv_steal_power_sequencer(dev
, pipe
);
435 intel_dp
->pps_pipe
= pipe
;
437 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
438 pipe_name(intel_dp
->pps_pipe
),
439 port_name(intel_dig_port
->port
));
441 /* init power sequencer on this pipe and port */
442 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
443 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
446 * Even vdd force doesn't work until we've made
447 * the power sequencer lock in on the port.
449 vlv_power_sequencer_kick(intel_dp
);
451 return intel_dp
->pps_pipe
;
454 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
457 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
460 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
463 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
466 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
469 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
476 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
478 vlv_pipe_check pipe_check
)
482 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
483 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
484 PANEL_PORT_SELECT_MASK
;
486 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
489 if (!pipe_check(dev_priv
, pipe
))
499 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
501 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
502 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
504 enum port port
= intel_dig_port
->port
;
506 lockdep_assert_held(&dev_priv
->pps_mutex
);
508 /* try to find a pipe with this port selected */
509 /* first pick one where the panel is on */
510 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
512 /* didn't find one? pick one where vdd is on */
513 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
514 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
515 vlv_pipe_has_vdd_on
);
516 /* didn't find one? pick one with just the correct port */
517 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
518 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
521 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
522 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
523 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
528 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
529 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
531 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
532 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
535 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
537 struct drm_device
*dev
= dev_priv
->dev
;
538 struct intel_encoder
*encoder
;
540 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
544 * We can't grab pps_mutex here due to deadlock with power_domain
545 * mutex when power_domain functions are called while holding pps_mutex.
546 * That also means that in order to use pps_pipe the code needs to
547 * hold both a power domain reference and pps_mutex, and the power domain
548 * reference get/put must be done while _not_ holding pps_mutex.
549 * pps_{lock,unlock}() do these steps in the correct order, so one
550 * should use them always.
553 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
554 struct intel_dp
*intel_dp
;
556 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
559 intel_dp
= enc_to_intel_dp(&encoder
->base
);
560 intel_dp
->pps_pipe
= INVALID_PIPE
;
564 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
566 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
568 if (HAS_PCH_SPLIT(dev
))
569 return PCH_PP_CONTROL
;
571 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
574 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
576 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
578 if (HAS_PCH_SPLIT(dev
))
579 return PCH_PP_STATUS
;
581 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
584 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
585 This function only applicable when panel PM state is not to be tracked */
586 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
589 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
591 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
594 u32 pp_ctrl_reg
, pp_div_reg
;
596 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
601 if (IS_VALLEYVIEW(dev
)) {
602 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
604 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
605 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
606 pp_div
= I915_READ(pp_div_reg
);
607 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
609 /* 0x1F write to PP_DIV_REG sets max cycle delay */
610 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
611 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
612 msleep(intel_dp
->panel_power_cycle_delay
);
615 pps_unlock(intel_dp
);
620 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
622 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
625 lockdep_assert_held(&dev_priv
->pps_mutex
);
627 if (IS_VALLEYVIEW(dev
) &&
628 intel_dp
->pps_pipe
== INVALID_PIPE
)
631 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
634 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
636 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
639 lockdep_assert_held(&dev_priv
->pps_mutex
);
641 if (IS_VALLEYVIEW(dev
) &&
642 intel_dp
->pps_pipe
== INVALID_PIPE
)
645 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
649 intel_dp_check_edp(struct intel_dp
*intel_dp
)
651 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
654 if (!is_edp(intel_dp
))
657 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
658 WARN(1, "eDP powered off while attempting aux channel communication.\n");
659 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
660 I915_READ(_pp_stat_reg(intel_dp
)),
661 I915_READ(_pp_ctrl_reg(intel_dp
)));
666 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
668 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
669 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
671 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
675 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
677 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
678 msecs_to_jiffies_timeout(10));
680 done
= wait_for_atomic(C
, 10) == 0;
682 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
689 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
691 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
692 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
695 * The clock divider is based off the hrawclk, and would like to run at
696 * 2MHz. So, take the hrawclk value and divide by 2 and use that
698 return index
? 0 : intel_hrawclk(dev
) / 2;
701 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
703 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
704 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
710 if (intel_dig_port
->port
== PORT_A
) {
711 return DIV_ROUND_UP(dev_priv
->display
.get_display_clock_speed(dev
), 2000);
713 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
717 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
719 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
720 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
723 if (intel_dig_port
->port
== PORT_A
) {
726 return DIV_ROUND_CLOSEST(dev_priv
->display
.get_display_clock_speed(dev
), 2000);
727 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
728 /* Workaround for non-ULT HSW */
735 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
739 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
741 return index
? 0 : 100;
744 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
747 * SKL doesn't need us to program the AUX clock divider (Hardware will
748 * derive the clock from CDCLK automatically). We still implement the
749 * get_aux_clock_divider vfunc to plug-in into the existing code.
751 return index
? 0 : 1;
754 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
757 uint32_t aux_clock_divider
)
759 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
760 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
761 uint32_t precharge
, timeout
;
768 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
769 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
771 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
773 return DP_AUX_CH_CTL_SEND_BUSY
|
775 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
776 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
778 DP_AUX_CH_CTL_RECEIVE_ERROR
|
779 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
780 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
781 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
784 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
789 return DP_AUX_CH_CTL_SEND_BUSY
|
791 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
792 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
793 DP_AUX_CH_CTL_TIME_OUT_1600us
|
794 DP_AUX_CH_CTL_RECEIVE_ERROR
|
795 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
796 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
800 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
801 const uint8_t *send
, int send_bytes
,
802 uint8_t *recv
, int recv_size
)
804 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
805 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
807 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
808 uint32_t ch_data
= ch_ctl
+ 4;
809 uint32_t aux_clock_divider
;
810 int i
, ret
, recv_bytes
;
813 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
819 * We will be called with VDD already enabled for dpcd/edid/oui reads.
820 * In such cases we want to leave VDD enabled and it's up to upper layers
821 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
824 vdd
= edp_panel_vdd_on(intel_dp
);
826 /* dp aux is extremely sensitive to irq latency, hence request the
827 * lowest possible wakeup latency and so prevent the cpu from going into
830 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
832 intel_dp_check_edp(intel_dp
);
834 intel_aux_display_runtime_get(dev_priv
);
836 /* Try to wait for any previous AUX channel activity */
837 for (try = 0; try < 3; try++) {
838 status
= I915_READ_NOTRACE(ch_ctl
);
839 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
845 WARN(1, "dp_aux_ch not started status 0x%08x\n",
851 /* Only 5 data registers! */
852 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
857 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
858 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
863 /* Must try at least 3 times according to DP spec */
864 for (try = 0; try < 5; try++) {
865 /* Load the send data into the aux channel data registers */
866 for (i
= 0; i
< send_bytes
; i
+= 4)
867 I915_WRITE(ch_data
+ i
,
868 intel_dp_pack_aux(send
+ i
,
871 /* Send the command and wait for it to complete */
872 I915_WRITE(ch_ctl
, send_ctl
);
874 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
876 /* Clear done status and any errors */
880 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
881 DP_AUX_CH_CTL_RECEIVE_ERROR
);
883 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
886 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
887 * 400us delay required for errors and timeouts
888 * Timeout errors from the HW already meet this
889 * requirement so skip to next iteration
891 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
892 usleep_range(400, 500);
895 if (status
& DP_AUX_CH_CTL_DONE
)
898 if (status
& DP_AUX_CH_CTL_DONE
)
902 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
903 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
908 /* Check for timeout or receive error.
909 * Timeouts occur when the sink is not connected
911 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
912 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
917 /* Timeouts occur when the device isn't connected, so they're
918 * "normal" -- don't fill the kernel log with these */
919 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
920 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
925 /* Unload any bytes sent back from the other side */
926 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
927 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
928 if (recv_bytes
> recv_size
)
929 recv_bytes
= recv_size
;
931 for (i
= 0; i
< recv_bytes
; i
+= 4)
932 intel_dp_unpack_aux(I915_READ(ch_data
+ i
),
933 recv
+ i
, recv_bytes
- i
);
937 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
938 intel_aux_display_runtime_put(dev_priv
);
941 edp_panel_vdd_off(intel_dp
, false);
943 pps_unlock(intel_dp
);
948 #define BARE_ADDRESS_SIZE 3
949 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
951 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
953 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
954 uint8_t txbuf
[20], rxbuf
[20];
955 size_t txsize
, rxsize
;
958 txbuf
[0] = (msg
->request
<< 4) |
959 ((msg
->address
>> 16) & 0xf);
960 txbuf
[1] = (msg
->address
>> 8) & 0xff;
961 txbuf
[2] = msg
->address
& 0xff;
962 txbuf
[3] = msg
->size
- 1;
964 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
965 case DP_AUX_NATIVE_WRITE
:
966 case DP_AUX_I2C_WRITE
:
967 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
968 rxsize
= 2; /* 0 or 1 data bytes */
970 if (WARN_ON(txsize
> 20))
973 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
975 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
977 msg
->reply
= rxbuf
[0] >> 4;
980 /* Number of bytes written in a short write. */
981 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
983 /* Return payload size. */
989 case DP_AUX_NATIVE_READ
:
990 case DP_AUX_I2C_READ
:
991 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
992 rxsize
= msg
->size
+ 1;
994 if (WARN_ON(rxsize
> 20))
997 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
999 msg
->reply
= rxbuf
[0] >> 4;
1001 * Assume happy day, and copy the data. The caller is
1002 * expected to check msg->reply before touching it.
1004 * Return payload size.
1007 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1020 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1022 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1023 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1024 enum port port
= intel_dig_port
->port
;
1025 const char *name
= NULL
;
1030 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1034 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1038 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1042 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1050 * The AUX_CTL register is usually DP_CTL + 0x10.
1052 * On Haswell and Broadwell though:
1053 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1054 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1056 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1058 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
1059 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1061 intel_dp
->aux
.name
= name
;
1062 intel_dp
->aux
.dev
= dev
->dev
;
1063 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1065 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1066 connector
->base
.kdev
->kobj
.name
);
1068 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1070 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1075 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1076 &intel_dp
->aux
.ddc
.dev
.kobj
,
1077 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1079 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1080 drm_dp_aux_unregister(&intel_dp
->aux
);
1085 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1087 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1089 if (!intel_connector
->mst_port
)
1090 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1091 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1092 intel_connector_unregister(intel_connector
);
1096 skl_edp_set_pll_config(struct intel_crtc_state
*pipe_config
, int link_clock
)
1100 memset(&pipe_config
->dpll_hw_state
, 0,
1101 sizeof(pipe_config
->dpll_hw_state
));
1103 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
1104 pipe_config
->dpll_hw_state
.cfgcr1
= 0;
1105 pipe_config
->dpll_hw_state
.cfgcr2
= 0;
1107 ctrl1
= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
1108 switch (link_clock
/ 2) {
1110 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
1114 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
,
1118 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
,
1122 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
,
1125 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1126 results in CDCLK change. Need to handle the change of CDCLK by
1127 disabling pipes and re-enabling them */
1129 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
1133 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
,
1138 pipe_config
->dpll_hw_state
.ctrl1
= ctrl1
;
1142 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state
*pipe_config
, int link_bw
)
1145 case DP_LINK_BW_1_62
:
1146 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1148 case DP_LINK_BW_2_7
:
1149 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1151 case DP_LINK_BW_5_4
:
1152 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1158 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1160 if (intel_dp
->num_sink_rates
) {
1161 *sink_rates
= intel_dp
->sink_rates
;
1162 return intel_dp
->num_sink_rates
;
1165 *sink_rates
= default_rates
;
1167 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1171 intel_dp_source_rates(struct drm_device
*dev
, const int **source_rates
)
1173 if (IS_SKYLAKE(dev
)) {
1174 *source_rates
= skl_rates
;
1175 return ARRAY_SIZE(skl_rates
);
1176 } else if (IS_CHERRYVIEW(dev
)) {
1177 *source_rates
= chv_rates
;
1178 return ARRAY_SIZE(chv_rates
);
1181 *source_rates
= default_rates
;
1183 if (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
)
1184 /* WaDisableHBR2:skl */
1185 return (DP_LINK_BW_2_7
>> 3) + 1;
1186 else if (INTEL_INFO(dev
)->gen
>= 8 ||
1187 (IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)))
1188 return (DP_LINK_BW_5_4
>> 3) + 1;
1190 return (DP_LINK_BW_2_7
>> 3) + 1;
1194 intel_dp_set_clock(struct intel_encoder
*encoder
,
1195 struct intel_crtc_state
*pipe_config
, int link_bw
)
1197 struct drm_device
*dev
= encoder
->base
.dev
;
1198 const struct dp_link_dpll
*divisor
= NULL
;
1202 divisor
= gen4_dpll
;
1203 count
= ARRAY_SIZE(gen4_dpll
);
1204 } else if (HAS_PCH_SPLIT(dev
)) {
1206 count
= ARRAY_SIZE(pch_dpll
);
1207 } else if (IS_CHERRYVIEW(dev
)) {
1209 count
= ARRAY_SIZE(chv_dpll
);
1210 } else if (IS_VALLEYVIEW(dev
)) {
1212 count
= ARRAY_SIZE(vlv_dpll
);
1215 if (divisor
&& count
) {
1216 for (i
= 0; i
< count
; i
++) {
1217 if (link_bw
== divisor
[i
].link_bw
) {
1218 pipe_config
->dpll
= divisor
[i
].dpll
;
1219 pipe_config
->clock_set
= true;
1226 static int intersect_rates(const int *source_rates
, int source_len
,
1227 const int *sink_rates
, int sink_len
,
1230 int i
= 0, j
= 0, k
= 0;
1232 while (i
< source_len
&& j
< sink_len
) {
1233 if (source_rates
[i
] == sink_rates
[j
]) {
1234 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1236 common_rates
[k
] = source_rates
[i
];
1240 } else if (source_rates
[i
] < sink_rates
[j
]) {
1249 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1252 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1253 const int *source_rates
, *sink_rates
;
1254 int source_len
, sink_len
;
1256 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1257 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1259 return intersect_rates(source_rates
, source_len
,
1260 sink_rates
, sink_len
,
1264 static void snprintf_int_array(char *str
, size_t len
,
1265 const int *array
, int nelem
)
1271 for (i
= 0; i
< nelem
; i
++) {
1272 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1280 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1282 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1283 const int *source_rates
, *sink_rates
;
1284 int source_len
, sink_len
, common_len
;
1285 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1286 char str
[128]; /* FIXME: too big for stack? */
1288 if ((drm_debug
& DRM_UT_KMS
) == 0)
1291 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1292 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1293 DRM_DEBUG_KMS("source rates: %s\n", str
);
1295 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1296 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1297 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1299 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1300 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1301 DRM_DEBUG_KMS("common rates: %s\n", str
);
1304 static int rate_to_index(int find
, const int *rates
)
1308 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1309 if (find
== rates
[i
])
1316 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1318 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1321 len
= intel_dp_common_rates(intel_dp
, rates
);
1322 if (WARN_ON(len
<= 0))
1325 return rates
[rate_to_index(0, rates
) - 1];
1328 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1330 return rate_to_index(rate
, intel_dp
->sink_rates
);
1334 intel_dp_compute_config(struct intel_encoder
*encoder
,
1335 struct intel_crtc_state
*pipe_config
)
1337 struct drm_device
*dev
= encoder
->base
.dev
;
1338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1339 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1340 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1341 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1342 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1343 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1344 int lane_count
, clock
;
1345 int min_lane_count
= 1;
1346 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1347 /* Conveniently, the link BW constants become indices with a shift...*/
1351 int link_avail
, link_clock
;
1352 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1355 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1357 /* No common link rates between source and sink */
1358 WARN_ON(common_len
<= 0);
1360 max_clock
= common_len
- 1;
1362 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1363 pipe_config
->has_pch_encoder
= true;
1365 pipe_config
->has_dp_encoder
= true;
1366 pipe_config
->has_drrs
= false;
1367 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1369 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1370 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1373 if (INTEL_INFO(dev
)->gen
>= 9) {
1375 ret
= skl_update_scaler_users(intel_crtc
, pipe_config
, NULL
, NULL
, 0);
1380 if (!HAS_PCH_SPLIT(dev
))
1381 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1382 intel_connector
->panel
.fitting_mode
);
1384 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1385 intel_connector
->panel
.fitting_mode
);
1388 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1391 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1392 "max bw %d pixel clock %iKHz\n",
1393 max_lane_count
, common_rates
[max_clock
],
1394 adjusted_mode
->crtc_clock
);
1396 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1397 * bpc in between. */
1398 bpp
= pipe_config
->pipe_bpp
;
1399 if (is_edp(intel_dp
)) {
1400 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1401 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1402 dev_priv
->vbt
.edp_bpp
);
1403 bpp
= dev_priv
->vbt
.edp_bpp
;
1407 * Use the maximum clock and number of lanes the eDP panel
1408 * advertizes being capable of. The panels are generally
1409 * designed to support only a single clock and lane
1410 * configuration, and typically these values correspond to the
1411 * native resolution of the panel.
1413 min_lane_count
= max_lane_count
;
1414 min_clock
= max_clock
;
1417 for (; bpp
>= 6*3; bpp
-= 2*3) {
1418 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1421 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1422 for (lane_count
= min_lane_count
;
1423 lane_count
<= max_lane_count
;
1426 link_clock
= common_rates
[clock
];
1427 link_avail
= intel_dp_max_data_rate(link_clock
,
1430 if (mode_rate
<= link_avail
) {
1440 if (intel_dp
->color_range_auto
) {
1443 * CEA-861-E - 5.1 Default Encoding Parameters
1444 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1446 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1447 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1449 intel_dp
->color_range
= 0;
1452 if (intel_dp
->color_range
)
1453 pipe_config
->limited_color_range
= true;
1455 intel_dp
->lane_count
= lane_count
;
1457 if (intel_dp
->num_sink_rates
) {
1458 intel_dp
->link_bw
= 0;
1459 intel_dp
->rate_select
=
1460 intel_dp_rate_select(intel_dp
, common_rates
[clock
]);
1463 drm_dp_link_rate_to_bw_code(common_rates
[clock
]);
1464 intel_dp
->rate_select
= 0;
1467 pipe_config
->pipe_bpp
= bpp
;
1468 pipe_config
->port_clock
= common_rates
[clock
];
1470 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1471 intel_dp
->link_bw
, intel_dp
->lane_count
,
1472 pipe_config
->port_clock
, bpp
);
1473 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1474 mode_rate
, link_avail
);
1476 intel_link_compute_m_n(bpp
, lane_count
,
1477 adjusted_mode
->crtc_clock
,
1478 pipe_config
->port_clock
,
1479 &pipe_config
->dp_m_n
);
1481 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1482 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1483 pipe_config
->has_drrs
= true;
1484 intel_link_compute_m_n(bpp
, lane_count
,
1485 intel_connector
->panel
.downclock_mode
->clock
,
1486 pipe_config
->port_clock
,
1487 &pipe_config
->dp_m2_n2
);
1490 if (IS_SKYLAKE(dev
) && is_edp(intel_dp
))
1491 skl_edp_set_pll_config(pipe_config
, common_rates
[clock
]);
1492 else if (IS_BROXTON(dev
))
1493 /* handled in ddi */;
1494 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1495 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1497 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1502 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1504 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1505 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1506 struct drm_device
*dev
= crtc
->base
.dev
;
1507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1510 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1511 crtc
->config
->port_clock
);
1512 dpa_ctl
= I915_READ(DP_A
);
1513 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1515 if (crtc
->config
->port_clock
== 162000) {
1516 /* For a long time we've carried around a ILK-DevA w/a for the
1517 * 160MHz clock. If we're really unlucky, it's still required.
1519 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1520 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1521 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1523 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1524 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1527 I915_WRITE(DP_A
, dpa_ctl
);
1533 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1535 struct drm_device
*dev
= encoder
->base
.dev
;
1536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1537 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1538 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1539 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1540 struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1543 * There are four kinds of DP registers:
1550 * IBX PCH and CPU are the same for almost everything,
1551 * except that the CPU DP PLL is configured in this
1554 * CPT PCH is quite different, having many bits moved
1555 * to the TRANS_DP_CTL register instead. That
1556 * configuration happens (oddly) in ironlake_pch_enable
1559 /* Preserve the BIOS-computed detected bit. This is
1560 * supposed to be read-only.
1562 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1564 /* Handle DP bits in common between all three register formats */
1565 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1566 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1568 if (crtc
->config
->has_audio
)
1569 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1571 /* Split out the IBX/CPU vs CPT settings */
1573 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1574 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1575 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1576 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1577 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1578 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1580 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1581 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1583 intel_dp
->DP
|= crtc
->pipe
<< 29;
1584 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1585 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1586 intel_dp
->DP
|= intel_dp
->color_range
;
1588 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1589 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1590 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1591 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1592 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1594 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1595 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1597 if (!IS_CHERRYVIEW(dev
)) {
1598 if (crtc
->pipe
== 1)
1599 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1601 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1604 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1608 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1609 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1611 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1612 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1614 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1615 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1617 static void wait_panel_status(struct intel_dp
*intel_dp
,
1621 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1623 u32 pp_stat_reg
, pp_ctrl_reg
;
1625 lockdep_assert_held(&dev_priv
->pps_mutex
);
1627 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1628 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1630 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1632 I915_READ(pp_stat_reg
),
1633 I915_READ(pp_ctrl_reg
));
1635 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1636 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1637 I915_READ(pp_stat_reg
),
1638 I915_READ(pp_ctrl_reg
));
1641 DRM_DEBUG_KMS("Wait complete\n");
1644 static void wait_panel_on(struct intel_dp
*intel_dp
)
1646 DRM_DEBUG_KMS("Wait for panel power on\n");
1647 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1650 static void wait_panel_off(struct intel_dp
*intel_dp
)
1652 DRM_DEBUG_KMS("Wait for panel power off time\n");
1653 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1656 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1658 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1660 /* When we disable the VDD override bit last we have to do the manual
1662 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1663 intel_dp
->panel_power_cycle_delay
);
1665 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1668 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1670 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1671 intel_dp
->backlight_on_delay
);
1674 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1676 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1677 intel_dp
->backlight_off_delay
);
1680 /* Read the current pp_control value, unlocking the register if it
1684 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1686 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1690 lockdep_assert_held(&dev_priv
->pps_mutex
);
1692 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1693 control
&= ~PANEL_UNLOCK_MASK
;
1694 control
|= PANEL_UNLOCK_REGS
;
1699 * Must be paired with edp_panel_vdd_off().
1700 * Must hold pps_mutex around the whole on/off sequence.
1701 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1703 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1705 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1706 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1707 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1709 enum intel_display_power_domain power_domain
;
1711 u32 pp_stat_reg
, pp_ctrl_reg
;
1712 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1714 lockdep_assert_held(&dev_priv
->pps_mutex
);
1716 if (!is_edp(intel_dp
))
1719 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1720 intel_dp
->want_panel_vdd
= true;
1722 if (edp_have_panel_vdd(intel_dp
))
1723 return need_to_disable
;
1725 power_domain
= intel_display_port_power_domain(intel_encoder
);
1726 intel_display_power_get(dev_priv
, power_domain
);
1728 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1729 port_name(intel_dig_port
->port
));
1731 if (!edp_have_panel_power(intel_dp
))
1732 wait_panel_power_cycle(intel_dp
);
1734 pp
= ironlake_get_pp_control(intel_dp
);
1735 pp
|= EDP_FORCE_VDD
;
1737 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1738 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1740 I915_WRITE(pp_ctrl_reg
, pp
);
1741 POSTING_READ(pp_ctrl_reg
);
1742 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1743 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1745 * If the panel wasn't on, delay before accessing aux channel
1747 if (!edp_have_panel_power(intel_dp
)) {
1748 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1749 port_name(intel_dig_port
->port
));
1750 msleep(intel_dp
->panel_power_up_delay
);
1753 return need_to_disable
;
1757 * Must be paired with intel_edp_panel_vdd_off() or
1758 * intel_edp_panel_off().
1759 * Nested calls to these functions are not allowed since
1760 * we drop the lock. Caller must use some higher level
1761 * locking to prevent nested calls from other threads.
1763 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1767 if (!is_edp(intel_dp
))
1771 vdd
= edp_panel_vdd_on(intel_dp
);
1772 pps_unlock(intel_dp
);
1774 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1775 port_name(dp_to_dig_port(intel_dp
)->port
));
1778 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1780 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1782 struct intel_digital_port
*intel_dig_port
=
1783 dp_to_dig_port(intel_dp
);
1784 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1785 enum intel_display_power_domain power_domain
;
1787 u32 pp_stat_reg
, pp_ctrl_reg
;
1789 lockdep_assert_held(&dev_priv
->pps_mutex
);
1791 WARN_ON(intel_dp
->want_panel_vdd
);
1793 if (!edp_have_panel_vdd(intel_dp
))
1796 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1797 port_name(intel_dig_port
->port
));
1799 pp
= ironlake_get_pp_control(intel_dp
);
1800 pp
&= ~EDP_FORCE_VDD
;
1802 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1803 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1805 I915_WRITE(pp_ctrl_reg
, pp
);
1806 POSTING_READ(pp_ctrl_reg
);
1808 /* Make sure sequencer is idle before allowing subsequent activity */
1809 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1810 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1812 if ((pp
& POWER_TARGET_ON
) == 0)
1813 intel_dp
->last_power_cycle
= jiffies
;
1815 power_domain
= intel_display_port_power_domain(intel_encoder
);
1816 intel_display_power_put(dev_priv
, power_domain
);
1819 static void edp_panel_vdd_work(struct work_struct
*__work
)
1821 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1822 struct intel_dp
, panel_vdd_work
);
1825 if (!intel_dp
->want_panel_vdd
)
1826 edp_panel_vdd_off_sync(intel_dp
);
1827 pps_unlock(intel_dp
);
1830 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1832 unsigned long delay
;
1835 * Queue the timer to fire a long time from now (relative to the power
1836 * down delay) to keep the panel power up across a sequence of
1839 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1840 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1844 * Must be paired with edp_panel_vdd_on().
1845 * Must hold pps_mutex around the whole on/off sequence.
1846 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1848 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1850 struct drm_i915_private
*dev_priv
=
1851 intel_dp_to_dev(intel_dp
)->dev_private
;
1853 lockdep_assert_held(&dev_priv
->pps_mutex
);
1855 if (!is_edp(intel_dp
))
1858 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1859 port_name(dp_to_dig_port(intel_dp
)->port
));
1861 intel_dp
->want_panel_vdd
= false;
1864 edp_panel_vdd_off_sync(intel_dp
);
1866 edp_panel_vdd_schedule_off(intel_dp
);
1869 static void edp_panel_on(struct intel_dp
*intel_dp
)
1871 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1876 lockdep_assert_held(&dev_priv
->pps_mutex
);
1878 if (!is_edp(intel_dp
))
1881 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1882 port_name(dp_to_dig_port(intel_dp
)->port
));
1884 if (WARN(edp_have_panel_power(intel_dp
),
1885 "eDP port %c panel power already on\n",
1886 port_name(dp_to_dig_port(intel_dp
)->port
)))
1889 wait_panel_power_cycle(intel_dp
);
1891 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1892 pp
= ironlake_get_pp_control(intel_dp
);
1894 /* ILK workaround: disable reset around power sequence */
1895 pp
&= ~PANEL_POWER_RESET
;
1896 I915_WRITE(pp_ctrl_reg
, pp
);
1897 POSTING_READ(pp_ctrl_reg
);
1900 pp
|= POWER_TARGET_ON
;
1902 pp
|= PANEL_POWER_RESET
;
1904 I915_WRITE(pp_ctrl_reg
, pp
);
1905 POSTING_READ(pp_ctrl_reg
);
1907 wait_panel_on(intel_dp
);
1908 intel_dp
->last_power_on
= jiffies
;
1911 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1912 I915_WRITE(pp_ctrl_reg
, pp
);
1913 POSTING_READ(pp_ctrl_reg
);
1917 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1919 if (!is_edp(intel_dp
))
1923 edp_panel_on(intel_dp
);
1924 pps_unlock(intel_dp
);
1928 static void edp_panel_off(struct intel_dp
*intel_dp
)
1930 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1931 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1932 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1934 enum intel_display_power_domain power_domain
;
1938 lockdep_assert_held(&dev_priv
->pps_mutex
);
1940 if (!is_edp(intel_dp
))
1943 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1944 port_name(dp_to_dig_port(intel_dp
)->port
));
1946 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
1947 port_name(dp_to_dig_port(intel_dp
)->port
));
1949 pp
= ironlake_get_pp_control(intel_dp
);
1950 /* We need to switch off panel power _and_ force vdd, for otherwise some
1951 * panels get very unhappy and cease to work. */
1952 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1955 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1957 intel_dp
->want_panel_vdd
= false;
1959 I915_WRITE(pp_ctrl_reg
, pp
);
1960 POSTING_READ(pp_ctrl_reg
);
1962 intel_dp
->last_power_cycle
= jiffies
;
1963 wait_panel_off(intel_dp
);
1965 /* We got a reference when we enabled the VDD. */
1966 power_domain
= intel_display_port_power_domain(intel_encoder
);
1967 intel_display_power_put(dev_priv
, power_domain
);
1970 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1972 if (!is_edp(intel_dp
))
1976 edp_panel_off(intel_dp
);
1977 pps_unlock(intel_dp
);
1980 /* Enable backlight in the panel power control. */
1981 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1983 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1984 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1990 * If we enable the backlight right away following a panel power
1991 * on, we may see slight flicker as the panel syncs with the eDP
1992 * link. So delay a bit to make sure the image is solid before
1993 * allowing it to appear.
1995 wait_backlight_on(intel_dp
);
1999 pp
= ironlake_get_pp_control(intel_dp
);
2000 pp
|= EDP_BLC_ENABLE
;
2002 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2004 I915_WRITE(pp_ctrl_reg
, pp
);
2005 POSTING_READ(pp_ctrl_reg
);
2007 pps_unlock(intel_dp
);
2010 /* Enable backlight PWM and backlight PP control. */
2011 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2013 if (!is_edp(intel_dp
))
2016 DRM_DEBUG_KMS("\n");
2018 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2019 _intel_edp_backlight_on(intel_dp
);
2022 /* Disable backlight in the panel power control. */
2023 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2025 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2030 if (!is_edp(intel_dp
))
2035 pp
= ironlake_get_pp_control(intel_dp
);
2036 pp
&= ~EDP_BLC_ENABLE
;
2038 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2040 I915_WRITE(pp_ctrl_reg
, pp
);
2041 POSTING_READ(pp_ctrl_reg
);
2043 pps_unlock(intel_dp
);
2045 intel_dp
->last_backlight_off
= jiffies
;
2046 edp_wait_backlight_off(intel_dp
);
2049 /* Disable backlight PP control and backlight PWM. */
2050 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2052 if (!is_edp(intel_dp
))
2055 DRM_DEBUG_KMS("\n");
2057 _intel_edp_backlight_off(intel_dp
);
2058 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2062 * Hook for controlling the panel power control backlight through the bl_power
2063 * sysfs attribute. Take care to handle multiple calls.
2065 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2068 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2072 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2073 pps_unlock(intel_dp
);
2075 if (is_enabled
== enable
)
2078 DRM_DEBUG_KMS("panel power control backlight %s\n",
2079 enable
? "enable" : "disable");
2082 _intel_edp_backlight_on(intel_dp
);
2084 _intel_edp_backlight_off(intel_dp
);
2087 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2089 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2090 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2091 struct drm_device
*dev
= crtc
->dev
;
2092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2095 assert_pipe_disabled(dev_priv
,
2096 to_intel_crtc(crtc
)->pipe
);
2098 DRM_DEBUG_KMS("\n");
2099 dpa_ctl
= I915_READ(DP_A
);
2100 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
2101 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2103 /* We don't adjust intel_dp->DP while tearing down the link, to
2104 * facilitate link retraining (e.g. after hotplug). Hence clear all
2105 * enable bits here to ensure that we don't enable too much. */
2106 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
2107 intel_dp
->DP
|= DP_PLL_ENABLE
;
2108 I915_WRITE(DP_A
, intel_dp
->DP
);
2113 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2115 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2116 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2117 struct drm_device
*dev
= crtc
->dev
;
2118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2121 assert_pipe_disabled(dev_priv
,
2122 to_intel_crtc(crtc
)->pipe
);
2124 dpa_ctl
= I915_READ(DP_A
);
2125 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
2126 "dp pll off, should be on\n");
2127 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2129 /* We can't rely on the value tracked for the DP register in
2130 * intel_dp->DP because link_down must not change that (otherwise link
2131 * re-training will fail. */
2132 dpa_ctl
&= ~DP_PLL_ENABLE
;
2133 I915_WRITE(DP_A
, dpa_ctl
);
2138 /* If the sink supports it, try to set the power state appropriately */
2139 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2143 /* Should have a valid DPCD by this point */
2144 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2147 if (mode
!= DRM_MODE_DPMS_ON
) {
2148 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2152 * When turning on, we need to retry for 1ms to give the sink
2155 for (i
= 0; i
< 3; i
++) {
2156 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2165 DRM_DEBUG_KMS("failed to %s sink power state\n",
2166 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2169 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2172 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2173 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2174 struct drm_device
*dev
= encoder
->base
.dev
;
2175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2176 enum intel_display_power_domain power_domain
;
2179 power_domain
= intel_display_port_power_domain(encoder
);
2180 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2183 tmp
= I915_READ(intel_dp
->output_reg
);
2185 if (!(tmp
& DP_PORT_EN
))
2188 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
2189 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2190 } else if (IS_CHERRYVIEW(dev
)) {
2191 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2192 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
2193 *pipe
= PORT_TO_PIPE(tmp
);
2199 switch (intel_dp
->output_reg
) {
2201 trans_sel
= TRANS_DP_PORT_SEL_B
;
2204 trans_sel
= TRANS_DP_PORT_SEL_C
;
2207 trans_sel
= TRANS_DP_PORT_SEL_D
;
2213 for_each_pipe(dev_priv
, i
) {
2214 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
2215 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
2221 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2222 intel_dp
->output_reg
);
2228 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2229 struct intel_crtc_state
*pipe_config
)
2231 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2233 struct drm_device
*dev
= encoder
->base
.dev
;
2234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2235 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2236 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2239 tmp
= I915_READ(intel_dp
->output_reg
);
2241 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2243 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
2244 if (tmp
& DP_SYNC_HS_HIGH
)
2245 flags
|= DRM_MODE_FLAG_PHSYNC
;
2247 flags
|= DRM_MODE_FLAG_NHSYNC
;
2249 if (tmp
& DP_SYNC_VS_HIGH
)
2250 flags
|= DRM_MODE_FLAG_PVSYNC
;
2252 flags
|= DRM_MODE_FLAG_NVSYNC
;
2254 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2255 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2256 flags
|= DRM_MODE_FLAG_PHSYNC
;
2258 flags
|= DRM_MODE_FLAG_NHSYNC
;
2260 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2261 flags
|= DRM_MODE_FLAG_PVSYNC
;
2263 flags
|= DRM_MODE_FLAG_NVSYNC
;
2266 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2268 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2269 tmp
& DP_COLOR_RANGE_16_235
)
2270 pipe_config
->limited_color_range
= true;
2272 pipe_config
->has_dp_encoder
= true;
2274 intel_dp_get_m_n(crtc
, pipe_config
);
2276 if (port
== PORT_A
) {
2277 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2278 pipe_config
->port_clock
= 162000;
2280 pipe_config
->port_clock
= 270000;
2283 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2284 &pipe_config
->dp_m_n
);
2286 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2287 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2289 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
2291 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2292 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2294 * This is a big fat ugly hack.
2296 * Some machines in UEFI boot mode provide us a VBT that has 18
2297 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2298 * unknown we fail to light up. Yet the same BIOS boots up with
2299 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2300 * max, not what it tells us to use.
2302 * Note: This will still be broken if the eDP panel is not lit
2303 * up by the BIOS, and thus we can't get the mode at module
2306 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2307 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2308 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2312 static void intel_disable_dp(struct intel_encoder
*encoder
)
2314 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2315 struct drm_device
*dev
= encoder
->base
.dev
;
2316 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2318 if (crtc
->config
->has_audio
)
2319 intel_audio_codec_disable(encoder
);
2321 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2322 intel_psr_disable(intel_dp
);
2324 /* Make sure the panel is off before trying to change the mode. But also
2325 * ensure that we have vdd while we switch off the panel. */
2326 intel_edp_panel_vdd_on(intel_dp
);
2327 intel_edp_backlight_off(intel_dp
);
2328 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2329 intel_edp_panel_off(intel_dp
);
2331 /* disable the port before the pipe on g4x */
2332 if (INTEL_INFO(dev
)->gen
< 5)
2333 intel_dp_link_down(intel_dp
);
2336 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2338 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2339 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2341 intel_dp_link_down(intel_dp
);
2343 ironlake_edp_pll_off(intel_dp
);
2346 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2348 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2350 intel_dp_link_down(intel_dp
);
2353 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2355 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2356 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2357 struct drm_device
*dev
= encoder
->base
.dev
;
2358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2359 struct intel_crtc
*intel_crtc
=
2360 to_intel_crtc(encoder
->base
.crtc
);
2361 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2362 enum pipe pipe
= intel_crtc
->pipe
;
2365 intel_dp_link_down(intel_dp
);
2367 mutex_lock(&dev_priv
->dpio_lock
);
2369 /* Propagate soft reset to data lane reset */
2370 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2371 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2372 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2374 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2375 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2376 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2378 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2379 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2380 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2382 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2383 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2384 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2386 mutex_unlock(&dev_priv
->dpio_lock
);
2390 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2392 uint8_t dp_train_pat
)
2394 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2395 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2397 enum port port
= intel_dig_port
->port
;
2400 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2402 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2403 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2405 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2407 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2408 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2409 case DP_TRAINING_PATTERN_DISABLE
:
2410 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2413 case DP_TRAINING_PATTERN_1
:
2414 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2416 case DP_TRAINING_PATTERN_2
:
2417 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2419 case DP_TRAINING_PATTERN_3
:
2420 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2423 I915_WRITE(DP_TP_CTL(port
), temp
);
2425 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2426 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2428 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2429 case DP_TRAINING_PATTERN_DISABLE
:
2430 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2432 case DP_TRAINING_PATTERN_1
:
2433 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2435 case DP_TRAINING_PATTERN_2
:
2436 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2438 case DP_TRAINING_PATTERN_3
:
2439 DRM_ERROR("DP training pattern 3 not supported\n");
2440 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2445 if (IS_CHERRYVIEW(dev
))
2446 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2448 *DP
&= ~DP_LINK_TRAIN_MASK
;
2450 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2451 case DP_TRAINING_PATTERN_DISABLE
:
2452 *DP
|= DP_LINK_TRAIN_OFF
;
2454 case DP_TRAINING_PATTERN_1
:
2455 *DP
|= DP_LINK_TRAIN_PAT_1
;
2457 case DP_TRAINING_PATTERN_2
:
2458 *DP
|= DP_LINK_TRAIN_PAT_2
;
2460 case DP_TRAINING_PATTERN_3
:
2461 if (IS_CHERRYVIEW(dev
)) {
2462 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2464 DRM_ERROR("DP training pattern 3 not supported\n");
2465 *DP
|= DP_LINK_TRAIN_PAT_2
;
2472 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2474 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2477 /* enable with pattern 1 (as per spec) */
2478 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2479 DP_TRAINING_PATTERN_1
);
2481 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2482 POSTING_READ(intel_dp
->output_reg
);
2485 * Magic for VLV/CHV. We _must_ first set up the register
2486 * without actually enabling the port, and then do another
2487 * write to enable the port. Otherwise link training will
2488 * fail when the power sequencer is freshly used for this port.
2490 intel_dp
->DP
|= DP_PORT_EN
;
2492 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2493 POSTING_READ(intel_dp
->output_reg
);
2496 static void intel_enable_dp(struct intel_encoder
*encoder
)
2498 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2499 struct drm_device
*dev
= encoder
->base
.dev
;
2500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2501 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2502 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2503 unsigned int lane_mask
= 0x0;
2505 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2510 if (IS_VALLEYVIEW(dev
))
2511 vlv_init_panel_power_sequencer(intel_dp
);
2513 intel_dp_enable_port(intel_dp
);
2515 edp_panel_vdd_on(intel_dp
);
2516 edp_panel_on(intel_dp
);
2517 edp_panel_vdd_off(intel_dp
, true);
2519 pps_unlock(intel_dp
);
2521 if (IS_VALLEYVIEW(dev
))
2522 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2525 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2526 intel_dp_start_link_train(intel_dp
);
2527 intel_dp_complete_link_train(intel_dp
);
2528 intel_dp_stop_link_train(intel_dp
);
2530 if (crtc
->config
->has_audio
) {
2531 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2532 pipe_name(crtc
->pipe
));
2533 intel_audio_codec_enable(encoder
);
2537 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2539 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2541 intel_enable_dp(encoder
);
2542 intel_edp_backlight_on(intel_dp
);
2545 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2547 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2549 intel_edp_backlight_on(intel_dp
);
2550 intel_psr_enable(intel_dp
);
2553 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2555 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2556 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2558 intel_dp_prepare(encoder
);
2560 /* Only ilk+ has port A */
2561 if (dport
->port
== PORT_A
) {
2562 ironlake_set_pll_cpu_edp(intel_dp
);
2563 ironlake_edp_pll_on(intel_dp
);
2567 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2569 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2570 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2571 enum pipe pipe
= intel_dp
->pps_pipe
;
2572 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2574 edp_panel_vdd_off_sync(intel_dp
);
2577 * VLV seems to get confused when multiple power seqeuencers
2578 * have the same port selected (even if only one has power/vdd
2579 * enabled). The failure manifests as vlv_wait_port_ready() failing
2580 * CHV on the other hand doesn't seem to mind having the same port
2581 * selected in multiple power seqeuencers, but let's clear the
2582 * port select always when logically disconnecting a power sequencer
2585 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2586 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2587 I915_WRITE(pp_on_reg
, 0);
2588 POSTING_READ(pp_on_reg
);
2590 intel_dp
->pps_pipe
= INVALID_PIPE
;
2593 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2597 struct intel_encoder
*encoder
;
2599 lockdep_assert_held(&dev_priv
->pps_mutex
);
2601 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2604 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2606 struct intel_dp
*intel_dp
;
2609 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2612 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2613 port
= dp_to_dig_port(intel_dp
)->port
;
2615 if (intel_dp
->pps_pipe
!= pipe
)
2618 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2619 pipe_name(pipe
), port_name(port
));
2621 WARN(encoder
->connectors_active
,
2622 "stealing pipe %c power sequencer from active eDP port %c\n",
2623 pipe_name(pipe
), port_name(port
));
2625 /* make sure vdd is off before we steal it */
2626 vlv_detach_power_sequencer(intel_dp
);
2630 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2632 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2633 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2634 struct drm_device
*dev
= encoder
->base
.dev
;
2635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2636 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2638 lockdep_assert_held(&dev_priv
->pps_mutex
);
2640 if (!is_edp(intel_dp
))
2643 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2647 * If another power sequencer was being used on this
2648 * port previously make sure to turn off vdd there while
2649 * we still have control of it.
2651 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2652 vlv_detach_power_sequencer(intel_dp
);
2655 * We may be stealing the power
2656 * sequencer from another port.
2658 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2660 /* now it's all ours */
2661 intel_dp
->pps_pipe
= crtc
->pipe
;
2663 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2664 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2666 /* init power sequencer on this pipe and port */
2667 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2668 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2671 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2673 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2674 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2675 struct drm_device
*dev
= encoder
->base
.dev
;
2676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2677 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2678 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2679 int pipe
= intel_crtc
->pipe
;
2682 mutex_lock(&dev_priv
->dpio_lock
);
2684 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2691 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2692 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2693 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2695 mutex_unlock(&dev_priv
->dpio_lock
);
2697 intel_enable_dp(encoder
);
2700 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2702 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2703 struct drm_device
*dev
= encoder
->base
.dev
;
2704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2705 struct intel_crtc
*intel_crtc
=
2706 to_intel_crtc(encoder
->base
.crtc
);
2707 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2708 int pipe
= intel_crtc
->pipe
;
2710 intel_dp_prepare(encoder
);
2712 /* Program Tx lane resets to default */
2713 mutex_lock(&dev_priv
->dpio_lock
);
2714 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2715 DPIO_PCS_TX_LANE2_RESET
|
2716 DPIO_PCS_TX_LANE1_RESET
);
2717 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2718 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2719 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2720 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2721 DPIO_PCS_CLK_SOFT_RESET
);
2723 /* Fix up inter-pair skew failure */
2724 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2725 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2726 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2727 mutex_unlock(&dev_priv
->dpio_lock
);
2730 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2732 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2733 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2734 struct drm_device
*dev
= encoder
->base
.dev
;
2735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2736 struct intel_crtc
*intel_crtc
=
2737 to_intel_crtc(encoder
->base
.crtc
);
2738 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2739 int pipe
= intel_crtc
->pipe
;
2740 int data
, i
, stagger
;
2743 mutex_lock(&dev_priv
->dpio_lock
);
2745 /* allow hardware to manage TX FIFO reset source */
2746 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2747 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2748 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2750 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2751 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2752 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2754 /* Deassert soft data lane reset*/
2755 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2756 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2757 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2759 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2760 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2761 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2763 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2764 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2765 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2767 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2768 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2769 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2771 /* Program Tx lane latency optimal setting*/
2772 for (i
= 0; i
< 4; i
++) {
2773 /* Set the upar bit */
2774 data
= (i
== 1) ? 0x0 : 0x1;
2775 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2776 data
<< DPIO_UPAR_SHIFT
);
2779 /* Data lane stagger programming */
2780 if (intel_crtc
->config
->port_clock
> 270000)
2782 else if (intel_crtc
->config
->port_clock
> 135000)
2784 else if (intel_crtc
->config
->port_clock
> 67500)
2786 else if (intel_crtc
->config
->port_clock
> 33750)
2791 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2792 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2793 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2795 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2796 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2797 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2799 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW12(ch
),
2800 DPIO_LANESTAGGER_STRAP(stagger
) |
2801 DPIO_LANESTAGGER_STRAP_OVRD
|
2802 DPIO_TX1_STAGGER_MASK(0x1f) |
2803 DPIO_TX1_STAGGER_MULT(6) |
2804 DPIO_TX2_STAGGER_MULT(0));
2806 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW12(ch
),
2807 DPIO_LANESTAGGER_STRAP(stagger
) |
2808 DPIO_LANESTAGGER_STRAP_OVRD
|
2809 DPIO_TX1_STAGGER_MASK(0x1f) |
2810 DPIO_TX1_STAGGER_MULT(7) |
2811 DPIO_TX2_STAGGER_MULT(5));
2813 mutex_unlock(&dev_priv
->dpio_lock
);
2815 intel_enable_dp(encoder
);
2818 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2820 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2821 struct drm_device
*dev
= encoder
->base
.dev
;
2822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2823 struct intel_crtc
*intel_crtc
=
2824 to_intel_crtc(encoder
->base
.crtc
);
2825 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2826 enum pipe pipe
= intel_crtc
->pipe
;
2829 intel_dp_prepare(encoder
);
2831 mutex_lock(&dev_priv
->dpio_lock
);
2833 /* program left/right clock distribution */
2834 if (pipe
!= PIPE_B
) {
2835 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2836 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2838 val
|= CHV_BUFLEFTENA1_FORCE
;
2840 val
|= CHV_BUFRIGHTENA1_FORCE
;
2841 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2843 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2844 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2846 val
|= CHV_BUFLEFTENA2_FORCE
;
2848 val
|= CHV_BUFRIGHTENA2_FORCE
;
2849 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2852 /* program clock channel usage */
2853 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2854 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2856 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2858 val
|= CHV_PCS_USEDCLKCHANNEL
;
2859 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2861 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2862 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2864 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2866 val
|= CHV_PCS_USEDCLKCHANNEL
;
2867 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2870 * This a a bit weird since generally CL
2871 * matches the pipe, but here we need to
2872 * pick the CL based on the port.
2874 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2876 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2878 val
|= CHV_CMN_USEDCLKCHANNEL
;
2879 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2881 mutex_unlock(&dev_priv
->dpio_lock
);
2885 * Native read with retry for link status and receiver capability reads for
2886 * cases where the sink may still be asleep.
2888 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2889 * supposed to retry 3 times per the spec.
2892 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2893 void *buffer
, size_t size
)
2899 * Sometime we just get the same incorrect byte repeated
2900 * over the entire buffer. Doing just one throw away read
2901 * initially seems to "solve" it.
2903 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
2905 for (i
= 0; i
< 3; i
++) {
2906 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2916 * Fetch AUX CH registers 0x202 - 0x207 which contain
2917 * link status information
2920 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2922 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2925 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2928 /* These are source-specific values. */
2930 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2932 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2934 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2936 if (IS_BROXTON(dev
))
2937 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2938 else if (INTEL_INFO(dev
)->gen
>= 9) {
2939 if (dev_priv
->edp_low_vswing
&& port
== PORT_A
)
2940 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2941 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2942 } else if (IS_VALLEYVIEW(dev
))
2943 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2944 else if (IS_GEN7(dev
) && port
== PORT_A
)
2945 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2946 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2947 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2949 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2953 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2955 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2956 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2958 if (INTEL_INFO(dev
)->gen
>= 9) {
2959 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2961 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2963 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2964 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2965 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2966 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2967 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2969 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2971 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2972 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2974 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2975 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2976 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2977 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2978 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2979 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2981 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2983 } else if (IS_VALLEYVIEW(dev
)) {
2984 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2985 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2986 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2987 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2988 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2990 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2993 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2995 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2996 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2998 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3000 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3001 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3003 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3006 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3008 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3010 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3015 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3020 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3022 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3024 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3025 struct intel_crtc
*intel_crtc
=
3026 to_intel_crtc(dport
->base
.base
.crtc
);
3027 unsigned long demph_reg_value
, preemph_reg_value
,
3028 uniqtranscale_reg_value
;
3029 uint8_t train_set
= intel_dp
->train_set
[0];
3030 enum dpio_channel port
= vlv_dport_to_channel(dport
);
3031 int pipe
= intel_crtc
->pipe
;
3033 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3034 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3035 preemph_reg_value
= 0x0004000;
3036 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3038 demph_reg_value
= 0x2B405555;
3039 uniqtranscale_reg_value
= 0x552AB83A;
3041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3042 demph_reg_value
= 0x2B404040;
3043 uniqtranscale_reg_value
= 0x5548B83A;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3046 demph_reg_value
= 0x2B245555;
3047 uniqtranscale_reg_value
= 0x5560B83A;
3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3050 demph_reg_value
= 0x2B405555;
3051 uniqtranscale_reg_value
= 0x5598DA3A;
3057 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3058 preemph_reg_value
= 0x0002000;
3059 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3061 demph_reg_value
= 0x2B404040;
3062 uniqtranscale_reg_value
= 0x5552B83A;
3064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3065 demph_reg_value
= 0x2B404848;
3066 uniqtranscale_reg_value
= 0x5580B83A;
3068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3069 demph_reg_value
= 0x2B404040;
3070 uniqtranscale_reg_value
= 0x55ADDA3A;
3076 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3077 preemph_reg_value
= 0x0000000;
3078 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3079 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3080 demph_reg_value
= 0x2B305555;
3081 uniqtranscale_reg_value
= 0x5570B83A;
3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3084 demph_reg_value
= 0x2B2B4040;
3085 uniqtranscale_reg_value
= 0x55ADDA3A;
3091 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3092 preemph_reg_value
= 0x0006000;
3093 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3095 demph_reg_value
= 0x1B405555;
3096 uniqtranscale_reg_value
= 0x55ADDA3A;
3106 mutex_lock(&dev_priv
->dpio_lock
);
3107 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3108 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3109 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3110 uniqtranscale_reg_value
);
3111 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3112 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3113 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3114 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3115 mutex_unlock(&dev_priv
->dpio_lock
);
3120 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3122 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3124 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3125 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3126 u32 deemph_reg_value
, margin_reg_value
, val
;
3127 uint8_t train_set
= intel_dp
->train_set
[0];
3128 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3129 enum pipe pipe
= intel_crtc
->pipe
;
3132 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3133 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3134 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3136 deemph_reg_value
= 128;
3137 margin_reg_value
= 52;
3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3140 deemph_reg_value
= 128;
3141 margin_reg_value
= 77;
3143 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3144 deemph_reg_value
= 128;
3145 margin_reg_value
= 102;
3147 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3148 deemph_reg_value
= 128;
3149 margin_reg_value
= 154;
3150 /* FIXME extra to set for 1200 */
3156 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3157 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3159 deemph_reg_value
= 85;
3160 margin_reg_value
= 78;
3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3163 deemph_reg_value
= 85;
3164 margin_reg_value
= 116;
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3167 deemph_reg_value
= 85;
3168 margin_reg_value
= 154;
3174 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3175 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3176 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3177 deemph_reg_value
= 64;
3178 margin_reg_value
= 104;
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3181 deemph_reg_value
= 64;
3182 margin_reg_value
= 154;
3188 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3189 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3191 deemph_reg_value
= 43;
3192 margin_reg_value
= 154;
3202 mutex_lock(&dev_priv
->dpio_lock
);
3204 /* Clear calc init */
3205 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3206 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3207 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3208 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3209 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3211 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3212 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3213 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3214 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3215 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3217 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3218 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3219 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3220 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3222 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3223 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3224 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3225 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3227 /* Program swing deemph */
3228 for (i
= 0; i
< 4; i
++) {
3229 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3230 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3231 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3232 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3235 /* Program swing margin */
3236 for (i
= 0; i
< 4; i
++) {
3237 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3238 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3239 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3240 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3243 /* Disable unique transition scale */
3244 for (i
= 0; i
< 4; i
++) {
3245 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3246 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3247 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3250 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3251 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3252 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3253 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3256 * The document said it needs to set bit 27 for ch0 and bit 26
3257 * for ch1. Might be a typo in the doc.
3258 * For now, for this unique transition scale selection, set bit
3259 * 27 for ch0 and ch1.
3261 for (i
= 0; i
< 4; i
++) {
3262 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3263 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3264 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3267 for (i
= 0; i
< 4; i
++) {
3268 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3269 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3270 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3271 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3275 /* Start swing calculation */
3276 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3277 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3278 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3280 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3281 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3282 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3285 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3286 val
|= DPIO_LRC_BYPASS
;
3287 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3289 mutex_unlock(&dev_priv
->dpio_lock
);
3295 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3296 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3301 uint8_t voltage_max
;
3302 uint8_t preemph_max
;
3304 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3305 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3306 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3314 voltage_max
= intel_dp_voltage_max(intel_dp
);
3315 if (v
>= voltage_max
)
3316 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3318 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3319 if (p
>= preemph_max
)
3320 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3322 for (lane
= 0; lane
< 4; lane
++)
3323 intel_dp
->train_set
[lane
] = v
| p
;
3327 gen4_signal_levels(uint8_t train_set
)
3329 uint32_t signal_levels
= 0;
3331 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3334 signal_levels
|= DP_VOLTAGE_0_4
;
3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3337 signal_levels
|= DP_VOLTAGE_0_6
;
3339 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3340 signal_levels
|= DP_VOLTAGE_0_8
;
3342 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3343 signal_levels
|= DP_VOLTAGE_1_2
;
3346 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3347 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3349 signal_levels
|= DP_PRE_EMPHASIS_0
;
3351 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3352 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3354 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3355 signal_levels
|= DP_PRE_EMPHASIS_6
;
3357 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3358 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3361 return signal_levels
;
3364 /* Gen6's DP voltage swing and pre-emphasis control */
3366 gen6_edp_signal_levels(uint8_t train_set
)
3368 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3369 DP_TRAIN_PRE_EMPHASIS_MASK
);
3370 switch (signal_levels
) {
3371 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3372 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3373 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3374 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3375 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3376 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3377 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3378 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3379 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3381 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3382 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3383 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3384 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3386 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3387 "0x%x\n", signal_levels
);
3388 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3392 /* Gen7's DP voltage swing and pre-emphasis control */
3394 gen7_edp_signal_levels(uint8_t train_set
)
3396 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3397 DP_TRAIN_PRE_EMPHASIS_MASK
);
3398 switch (signal_levels
) {
3399 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3400 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3401 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3402 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3403 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3404 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3406 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3407 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3408 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3409 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3411 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3412 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3413 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3414 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3417 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3418 "0x%x\n", signal_levels
);
3419 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3423 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3425 hsw_signal_levels(uint8_t train_set
)
3427 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3428 DP_TRAIN_PRE_EMPHASIS_MASK
);
3429 switch (signal_levels
) {
3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3431 return DDI_BUF_TRANS_SELECT(0);
3432 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3433 return DDI_BUF_TRANS_SELECT(1);
3434 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3435 return DDI_BUF_TRANS_SELECT(2);
3436 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3437 return DDI_BUF_TRANS_SELECT(3);
3439 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3440 return DDI_BUF_TRANS_SELECT(4);
3441 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3442 return DDI_BUF_TRANS_SELECT(5);
3443 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3444 return DDI_BUF_TRANS_SELECT(6);
3446 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3447 return DDI_BUF_TRANS_SELECT(7);
3448 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3449 return DDI_BUF_TRANS_SELECT(8);
3451 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3452 return DDI_BUF_TRANS_SELECT(9);
3454 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3455 "0x%x\n", signal_levels
);
3456 return DDI_BUF_TRANS_SELECT(0);
3460 static void bxt_signal_levels(struct intel_dp
*intel_dp
)
3462 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3463 enum port port
= dport
->port
;
3464 struct drm_device
*dev
= dport
->base
.base
.dev
;
3465 struct intel_encoder
*encoder
= &dport
->base
;
3466 uint8_t train_set
= intel_dp
->train_set
[0];
3469 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3470 DP_TRAIN_PRE_EMPHASIS_MASK
);
3471 switch (signal_levels
) {
3473 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n");
3474 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3477 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3480 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3483 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3486 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3489 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3492 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3495 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3498 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3501 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3506 bxt_ddi_vswing_sequence(dev
, level
, port
, encoder
->type
);
3509 /* Properly updates "DP" with the correct signal levels. */
3511 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3513 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3514 enum port port
= intel_dig_port
->port
;
3515 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3516 uint32_t signal_levels
, mask
;
3517 uint8_t train_set
= intel_dp
->train_set
[0];
3519 if (IS_BROXTON(dev
)) {
3521 bxt_signal_levels(intel_dp
);
3523 } else if (HAS_DDI(dev
)) {
3524 signal_levels
= hsw_signal_levels(train_set
);
3525 mask
= DDI_BUF_EMP_MASK
;
3526 } else if (IS_CHERRYVIEW(dev
)) {
3527 signal_levels
= chv_signal_levels(intel_dp
);
3529 } else if (IS_VALLEYVIEW(dev
)) {
3530 signal_levels
= vlv_signal_levels(intel_dp
);
3532 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3533 signal_levels
= gen7_edp_signal_levels(train_set
);
3534 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3535 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3536 signal_levels
= gen6_edp_signal_levels(train_set
);
3537 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3539 signal_levels
= gen4_signal_levels(train_set
);
3540 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3544 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3546 DRM_DEBUG_KMS("Using vswing level %d\n",
3547 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3548 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3549 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3550 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3552 *DP
= (*DP
& ~mask
) | signal_levels
;
3556 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3558 uint8_t dp_train_pat
)
3560 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3561 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3563 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3566 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3568 I915_WRITE(intel_dp
->output_reg
, *DP
);
3569 POSTING_READ(intel_dp
->output_reg
);
3571 buf
[0] = dp_train_pat
;
3572 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3573 DP_TRAINING_PATTERN_DISABLE
) {
3574 /* don't write DP_TRAINING_LANEx_SET on disable */
3577 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3578 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3579 len
= intel_dp
->lane_count
+ 1;
3582 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3589 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3590 uint8_t dp_train_pat
)
3592 if (!intel_dp
->train_set_valid
)
3593 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3594 intel_dp_set_signal_levels(intel_dp
, DP
);
3595 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3599 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3600 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3602 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3603 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3607 intel_get_adjust_train(intel_dp
, link_status
);
3608 intel_dp_set_signal_levels(intel_dp
, DP
);
3610 I915_WRITE(intel_dp
->output_reg
, *DP
);
3611 POSTING_READ(intel_dp
->output_reg
);
3613 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3614 intel_dp
->train_set
, intel_dp
->lane_count
);
3616 return ret
== intel_dp
->lane_count
;
3619 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3621 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3622 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3624 enum port port
= intel_dig_port
->port
;
3630 val
= I915_READ(DP_TP_CTL(port
));
3631 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3632 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3633 I915_WRITE(DP_TP_CTL(port
), val
);
3636 * On PORT_A we can have only eDP in SST mode. There the only reason
3637 * we need to set idle transmission mode is to work around a HW issue
3638 * where we enable the pipe while not in idle link-training mode.
3639 * In this case there is requirement to wait for a minimum number of
3640 * idle patterns to be sent.
3645 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3647 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3650 /* Enable corresponding port and start training pattern 1 */
3652 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3654 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3655 struct drm_device
*dev
= encoder
->dev
;
3658 int voltage_tries
, loop_tries
;
3659 uint32_t DP
= intel_dp
->DP
;
3660 uint8_t link_config
[2];
3663 intel_ddi_prepare_link_retrain(encoder
);
3665 /* Write the link configuration data */
3666 link_config
[0] = intel_dp
->link_bw
;
3667 link_config
[1] = intel_dp
->lane_count
;
3668 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3669 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3670 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3671 if (intel_dp
->num_sink_rates
)
3672 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_RATE_SET
,
3673 &intel_dp
->rate_select
, 1);
3676 link_config
[1] = DP_SET_ANSI_8B10B
;
3677 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3681 /* clock recovery */
3682 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3683 DP_TRAINING_PATTERN_1
|
3684 DP_LINK_SCRAMBLING_DISABLE
)) {
3685 DRM_ERROR("failed to enable link training\n");
3693 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3695 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3696 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3697 DRM_ERROR("failed to get link status\n");
3701 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3702 DRM_DEBUG_KMS("clock recovery OK\n");
3707 * if we used previously trained voltage and pre-emphasis values
3708 * and we don't get clock recovery, reset link training values
3710 if (intel_dp
->train_set_valid
) {
3711 DRM_DEBUG_KMS("clock recovery not ok, reset");
3712 /* clear the flag as we are not reusing train set */
3713 intel_dp
->train_set_valid
= false;
3714 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3715 DP_TRAINING_PATTERN_1
|
3716 DP_LINK_SCRAMBLING_DISABLE
)) {
3717 DRM_ERROR("failed to enable link training\n");
3723 /* Check to see if we've tried the max voltage */
3724 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3725 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3727 if (i
== intel_dp
->lane_count
) {
3729 if (loop_tries
== 5) {
3730 DRM_ERROR("too many full retries, give up\n");
3733 intel_dp_reset_link_train(intel_dp
, &DP
,
3734 DP_TRAINING_PATTERN_1
|
3735 DP_LINK_SCRAMBLING_DISABLE
);
3740 /* Check to see if we've tried the same voltage 5 times */
3741 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3743 if (voltage_tries
== 5) {
3744 DRM_ERROR("too many voltage retries, give up\n");
3749 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3751 /* Update training set as requested by target */
3752 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3753 DRM_ERROR("failed to update link training\n");
3762 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3764 bool channel_eq
= false;
3765 int tries
, cr_tries
;
3766 uint32_t DP
= intel_dp
->DP
;
3767 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3769 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3770 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3771 training_pattern
= DP_TRAINING_PATTERN_3
;
3773 /* channel equalization */
3774 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3776 DP_LINK_SCRAMBLING_DISABLE
)) {
3777 DRM_ERROR("failed to start channel equalization\n");
3785 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3788 DRM_ERROR("failed to train DP, aborting\n");
3792 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3793 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3794 DRM_ERROR("failed to get link status\n");
3798 /* Make sure clock is still ok */
3799 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3800 intel_dp
->train_set_valid
= false;
3801 intel_dp_start_link_train(intel_dp
);
3802 intel_dp_set_link_train(intel_dp
, &DP
,
3804 DP_LINK_SCRAMBLING_DISABLE
);
3809 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3814 /* Try 5 times, then try clock recovery if that fails */
3816 intel_dp
->train_set_valid
= false;
3817 intel_dp_start_link_train(intel_dp
);
3818 intel_dp_set_link_train(intel_dp
, &DP
,
3820 DP_LINK_SCRAMBLING_DISABLE
);
3826 /* Update training set as requested by target */
3827 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3828 DRM_ERROR("failed to update link training\n");
3834 intel_dp_set_idle_link_train(intel_dp
);
3839 intel_dp
->train_set_valid
= true;
3840 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3844 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3846 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3847 DP_TRAINING_PATTERN_DISABLE
);
3851 intel_dp_link_down(struct intel_dp
*intel_dp
)
3853 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3854 enum port port
= intel_dig_port
->port
;
3855 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3857 uint32_t DP
= intel_dp
->DP
;
3859 if (WARN_ON(HAS_DDI(dev
)))
3862 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3865 DRM_DEBUG_KMS("\n");
3867 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3868 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3869 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3871 if (IS_CHERRYVIEW(dev
))
3872 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3874 DP
&= ~DP_LINK_TRAIN_MASK
;
3875 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3877 POSTING_READ(intel_dp
->output_reg
);
3879 if (HAS_PCH_IBX(dev
) &&
3880 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3881 /* Hardware workaround: leaving our transcoder select
3882 * set to transcoder B while it's off will prevent the
3883 * corresponding HDMI output on transcoder A.
3885 * Combine this with another hardware workaround:
3886 * transcoder select bit can only be cleared while the
3889 DP
&= ~DP_PIPEB_SELECT
;
3890 I915_WRITE(intel_dp
->output_reg
, DP
);
3891 POSTING_READ(intel_dp
->output_reg
);
3894 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3895 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3896 POSTING_READ(intel_dp
->output_reg
);
3897 msleep(intel_dp
->panel_power_down_delay
);
3901 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3903 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3904 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3908 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3909 sizeof(intel_dp
->dpcd
)) < 0)
3910 return false; /* aux transfer failed */
3912 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3914 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3915 return false; /* DPCD not present */
3917 /* Check if the panel supports PSR */
3918 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3919 if (is_edp(intel_dp
)) {
3920 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3922 sizeof(intel_dp
->psr_dpcd
));
3923 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3924 dev_priv
->psr
.sink_support
= true;
3925 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3928 if (INTEL_INFO(dev
)->gen
>= 9 &&
3929 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3930 uint8_t frame_sync_cap
;
3932 dev_priv
->psr
.sink_support
= true;
3933 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3934 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3935 &frame_sync_cap
, 1);
3936 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3937 /* PSR2 needs frame sync as well */
3938 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3939 DRM_DEBUG_KMS("PSR2 %s on sink",
3940 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3944 /* Training Pattern 3 support, both source and sink */
3945 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3946 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
&&
3947 (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)) {
3948 intel_dp
->use_tps3
= true;
3949 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3951 intel_dp
->use_tps3
= false;
3953 /* Intermediate frequency support */
3954 if (is_edp(intel_dp
) &&
3955 (intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3956 (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_EDP_DPCD_REV
, &rev
, 1) == 1) &&
3957 (rev
>= 0x03)) { /* eDp v1.4 or higher */
3958 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3961 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3962 DP_SUPPORTED_LINK_RATES
,
3964 sizeof(sink_rates
));
3966 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3967 int val
= le16_to_cpu(sink_rates
[i
]);
3972 /* Value read is in kHz while drm clock is saved in deca-kHz */
3973 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3975 intel_dp
->num_sink_rates
= i
;
3978 intel_dp_print_rates(intel_dp
);
3980 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3981 DP_DWN_STRM_PORT_PRESENT
))
3982 return true; /* native DP sink */
3984 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3985 return true; /* no per-port downstream info */
3987 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3988 intel_dp
->downstream_ports
,
3989 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3990 return false; /* downstream port status fetch failed */
3996 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
4000 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
4003 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
4004 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
4005 buf
[0], buf
[1], buf
[2]);
4007 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
4008 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
4009 buf
[0], buf
[1], buf
[2]);
4013 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
4017 if (!intel_dp
->can_mst
)
4020 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
4023 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
4024 if (buf
[0] & DP_MST_CAP
) {
4025 DRM_DEBUG_KMS("Sink is MST capable\n");
4026 intel_dp
->is_mst
= true;
4028 DRM_DEBUG_KMS("Sink is not MST capable\n");
4029 intel_dp
->is_mst
= false;
4033 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4034 return intel_dp
->is_mst
;
4037 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
4039 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4040 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4041 struct intel_crtc
*intel_crtc
=
4042 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
4047 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
4050 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
4053 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
4056 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4057 buf
| DP_TEST_SINK_START
) < 0)
4060 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
4062 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
4065 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4066 DP_TEST_SINK_MISC
, &buf
) < 0)
4068 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4069 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
4071 if (attempts
== 0) {
4072 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4076 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
4079 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
4081 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4082 buf
& ~DP_TEST_SINK_START
) < 0)
4089 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4091 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4092 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4093 sink_irq_vector
, 1) == 1;
4097 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4101 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4103 sink_irq_vector
, 14);
4110 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4112 uint8_t test_result
= DP_TEST_ACK
;
4116 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4118 uint8_t test_result
= DP_TEST_NAK
;
4122 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4124 uint8_t test_result
= DP_TEST_NAK
;
4125 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4126 struct drm_connector
*connector
= &intel_connector
->base
;
4128 if (intel_connector
->detect_edid
== NULL
||
4129 connector
->edid_corrupt
||
4130 intel_dp
->aux
.i2c_defer_count
> 6) {
4131 /* Check EDID read for NACKs, DEFERs and corruption
4132 * (DP CTS 1.2 Core r1.1)
4133 * 4.2.2.4 : Failed EDID read, I2C_NAK
4134 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4135 * 4.2.2.6 : EDID corruption detected
4136 * Use failsafe mode for all cases
4138 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4139 intel_dp
->aux
.i2c_defer_count
> 0)
4140 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4141 intel_dp
->aux
.i2c_nack_count
,
4142 intel_dp
->aux
.i2c_defer_count
);
4143 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
4145 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
4146 DP_TEST_EDID_CHECKSUM
,
4147 &intel_connector
->detect_edid
->checksum
,
4149 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4151 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4152 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
4155 /* Set test active flag here so userspace doesn't interrupt things */
4156 intel_dp
->compliance_test_active
= 1;
4161 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4163 uint8_t test_result
= DP_TEST_NAK
;
4167 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4169 uint8_t response
= DP_TEST_NAK
;
4173 intel_dp
->compliance_test_active
= 0;
4174 intel_dp
->compliance_test_type
= 0;
4175 intel_dp
->compliance_test_data
= 0;
4177 intel_dp
->aux
.i2c_nack_count
= 0;
4178 intel_dp
->aux
.i2c_defer_count
= 0;
4180 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
4182 DRM_DEBUG_KMS("Could not read test request from sink\n");
4187 case DP_TEST_LINK_TRAINING
:
4188 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4189 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
4190 response
= intel_dp_autotest_link_training(intel_dp
);
4192 case DP_TEST_LINK_VIDEO_PATTERN
:
4193 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4194 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
4195 response
= intel_dp_autotest_video_pattern(intel_dp
);
4197 case DP_TEST_LINK_EDID_READ
:
4198 DRM_DEBUG_KMS("EDID test requested\n");
4199 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
4200 response
= intel_dp_autotest_edid(intel_dp
);
4202 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4203 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4204 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
4205 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4208 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
4213 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
4217 DRM_DEBUG_KMS("Could not write test response to sink\n");
4221 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4225 if (intel_dp
->is_mst
) {
4230 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4234 /* check link status - esi[10] = 0x200c */
4235 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4236 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4237 intel_dp_start_link_train(intel_dp
);
4238 intel_dp_complete_link_train(intel_dp
);
4239 intel_dp_stop_link_train(intel_dp
);
4242 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4243 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4246 for (retry
= 0; retry
< 3; retry
++) {
4248 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4249 DP_SINK_COUNT_ESI
+1,
4256 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4258 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4266 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4267 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4268 intel_dp
->is_mst
= false;
4269 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4270 /* send a hotplug event */
4271 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4278 * According to DP spec
4281 * 2. Configure link according to Receiver Capabilities
4282 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4283 * 4. Check link status on receipt of hot-plug interrupt
4286 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4288 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4289 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4291 u8 link_status
[DP_LINK_STATUS_SIZE
];
4293 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4295 if (!intel_encoder
->connectors_active
)
4298 if (WARN_ON(!intel_encoder
->base
.crtc
))
4301 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4304 /* Try to read receiver status if the link appears to be up */
4305 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4309 /* Now read the DPCD to see if it's actually running */
4310 if (!intel_dp_get_dpcd(intel_dp
)) {
4314 /* Try to read the source of the interrupt */
4315 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4316 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4317 /* Clear interrupt source */
4318 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4319 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4322 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4323 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4324 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4325 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4328 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4329 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4330 intel_encoder
->base
.name
);
4331 intel_dp_start_link_train(intel_dp
);
4332 intel_dp_complete_link_train(intel_dp
);
4333 intel_dp_stop_link_train(intel_dp
);
4337 /* XXX this is probably wrong for multiple downstream ports */
4338 static enum drm_connector_status
4339 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4341 uint8_t *dpcd
= intel_dp
->dpcd
;
4344 if (!intel_dp_get_dpcd(intel_dp
))
4345 return connector_status_disconnected
;
4347 /* if there's no downstream port, we're done */
4348 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4349 return connector_status_connected
;
4351 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4352 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4353 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4356 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4358 return connector_status_unknown
;
4360 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4361 : connector_status_disconnected
;
4364 /* If no HPD, poke DDC gently */
4365 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4366 return connector_status_connected
;
4368 /* Well we tried, say unknown for unreliable port types */
4369 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4370 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4371 if (type
== DP_DS_PORT_TYPE_VGA
||
4372 type
== DP_DS_PORT_TYPE_NON_EDID
)
4373 return connector_status_unknown
;
4375 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4376 DP_DWN_STRM_PORT_TYPE_MASK
;
4377 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4378 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4379 return connector_status_unknown
;
4382 /* Anything else is out of spec, warn and ignore */
4383 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4384 return connector_status_disconnected
;
4387 static enum drm_connector_status
4388 edp_detect(struct intel_dp
*intel_dp
)
4390 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4391 enum drm_connector_status status
;
4393 status
= intel_panel_detect(dev
);
4394 if (status
== connector_status_unknown
)
4395 status
= connector_status_connected
;
4400 static enum drm_connector_status
4401 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4403 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4405 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4407 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4408 return connector_status_disconnected
;
4410 return intel_dp_detect_dpcd(intel_dp
);
4413 static int g4x_digital_port_connected(struct drm_device
*dev
,
4414 struct intel_digital_port
*intel_dig_port
)
4416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4419 if (IS_VALLEYVIEW(dev
)) {
4420 switch (intel_dig_port
->port
) {
4422 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4425 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4428 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4434 switch (intel_dig_port
->port
) {
4436 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4439 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4442 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4449 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4454 static enum drm_connector_status
4455 g4x_dp_detect(struct intel_dp
*intel_dp
)
4457 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4458 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4461 /* Can't disconnect eDP, but you can close the lid... */
4462 if (is_edp(intel_dp
)) {
4463 enum drm_connector_status status
;
4465 status
= intel_panel_detect(dev
);
4466 if (status
== connector_status_unknown
)
4467 status
= connector_status_connected
;
4471 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4473 return connector_status_unknown
;
4475 return connector_status_disconnected
;
4477 return intel_dp_detect_dpcd(intel_dp
);
4480 static struct edid
*
4481 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4483 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4485 /* use cached edid if we have one */
4486 if (intel_connector
->edid
) {
4488 if (IS_ERR(intel_connector
->edid
))
4491 return drm_edid_duplicate(intel_connector
->edid
);
4493 return drm_get_edid(&intel_connector
->base
,
4494 &intel_dp
->aux
.ddc
);
4498 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4500 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4503 edid
= intel_dp_get_edid(intel_dp
);
4504 intel_connector
->detect_edid
= edid
;
4506 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4507 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4509 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4513 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4515 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4517 kfree(intel_connector
->detect_edid
);
4518 intel_connector
->detect_edid
= NULL
;
4520 intel_dp
->has_audio
= false;
4523 static enum intel_display_power_domain
4524 intel_dp_power_get(struct intel_dp
*dp
)
4526 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4527 enum intel_display_power_domain power_domain
;
4529 power_domain
= intel_display_port_power_domain(encoder
);
4530 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4532 return power_domain
;
4536 intel_dp_power_put(struct intel_dp
*dp
,
4537 enum intel_display_power_domain power_domain
)
4539 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4540 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4543 static enum drm_connector_status
4544 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4546 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4547 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4548 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4549 struct drm_device
*dev
= connector
->dev
;
4550 enum drm_connector_status status
;
4551 enum intel_display_power_domain power_domain
;
4555 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4556 connector
->base
.id
, connector
->name
);
4557 intel_dp_unset_edid(intel_dp
);
4559 if (intel_dp
->is_mst
) {
4560 /* MST devices are disconnected from a monitor POV */
4561 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4562 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4563 return connector_status_disconnected
;
4566 power_domain
= intel_dp_power_get(intel_dp
);
4568 /* Can't disconnect eDP, but you can close the lid... */
4569 if (is_edp(intel_dp
))
4570 status
= edp_detect(intel_dp
);
4571 else if (HAS_PCH_SPLIT(dev
))
4572 status
= ironlake_dp_detect(intel_dp
);
4574 status
= g4x_dp_detect(intel_dp
);
4575 if (status
!= connector_status_connected
)
4578 intel_dp_probe_oui(intel_dp
);
4580 ret
= intel_dp_probe_mst(intel_dp
);
4582 /* if we are in MST mode then this connector
4583 won't appear connected or have anything with EDID on it */
4584 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4585 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4586 status
= connector_status_disconnected
;
4590 intel_dp_set_edid(intel_dp
);
4592 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4593 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4594 status
= connector_status_connected
;
4596 /* Try to read the source of the interrupt */
4597 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4598 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4599 /* Clear interrupt source */
4600 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4601 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4604 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4605 intel_dp_handle_test_request(intel_dp
);
4606 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4607 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4611 intel_dp_power_put(intel_dp
, power_domain
);
4616 intel_dp_force(struct drm_connector
*connector
)
4618 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4619 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4620 enum intel_display_power_domain power_domain
;
4622 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4623 connector
->base
.id
, connector
->name
);
4624 intel_dp_unset_edid(intel_dp
);
4626 if (connector
->status
!= connector_status_connected
)
4629 power_domain
= intel_dp_power_get(intel_dp
);
4631 intel_dp_set_edid(intel_dp
);
4633 intel_dp_power_put(intel_dp
, power_domain
);
4635 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4636 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4639 static int intel_dp_get_modes(struct drm_connector
*connector
)
4641 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4644 edid
= intel_connector
->detect_edid
;
4646 int ret
= intel_connector_update_modes(connector
, edid
);
4651 /* if eDP has no EDID, fall back to fixed mode */
4652 if (is_edp(intel_attached_dp(connector
)) &&
4653 intel_connector
->panel
.fixed_mode
) {
4654 struct drm_display_mode
*mode
;
4656 mode
= drm_mode_duplicate(connector
->dev
,
4657 intel_connector
->panel
.fixed_mode
);
4659 drm_mode_probed_add(connector
, mode
);
4668 intel_dp_detect_audio(struct drm_connector
*connector
)
4670 bool has_audio
= false;
4673 edid
= to_intel_connector(connector
)->detect_edid
;
4675 has_audio
= drm_detect_monitor_audio(edid
);
4681 intel_dp_set_property(struct drm_connector
*connector
,
4682 struct drm_property
*property
,
4685 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4686 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4687 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4688 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4691 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4695 if (property
== dev_priv
->force_audio_property
) {
4699 if (i
== intel_dp
->force_audio
)
4702 intel_dp
->force_audio
= i
;
4704 if (i
== HDMI_AUDIO_AUTO
)
4705 has_audio
= intel_dp_detect_audio(connector
);
4707 has_audio
= (i
== HDMI_AUDIO_ON
);
4709 if (has_audio
== intel_dp
->has_audio
)
4712 intel_dp
->has_audio
= has_audio
;
4716 if (property
== dev_priv
->broadcast_rgb_property
) {
4717 bool old_auto
= intel_dp
->color_range_auto
;
4718 uint32_t old_range
= intel_dp
->color_range
;
4721 case INTEL_BROADCAST_RGB_AUTO
:
4722 intel_dp
->color_range_auto
= true;
4724 case INTEL_BROADCAST_RGB_FULL
:
4725 intel_dp
->color_range_auto
= false;
4726 intel_dp
->color_range
= 0;
4728 case INTEL_BROADCAST_RGB_LIMITED
:
4729 intel_dp
->color_range_auto
= false;
4730 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4736 if (old_auto
== intel_dp
->color_range_auto
&&
4737 old_range
== intel_dp
->color_range
)
4743 if (is_edp(intel_dp
) &&
4744 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4745 if (val
== DRM_MODE_SCALE_NONE
) {
4746 DRM_DEBUG_KMS("no scaling not supported\n");
4750 if (intel_connector
->panel
.fitting_mode
== val
) {
4751 /* the eDP scaling property is not changed */
4754 intel_connector
->panel
.fitting_mode
= val
;
4762 if (intel_encoder
->base
.crtc
)
4763 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4769 intel_dp_connector_destroy(struct drm_connector
*connector
)
4771 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4773 kfree(intel_connector
->detect_edid
);
4775 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4776 kfree(intel_connector
->edid
);
4778 /* Can't call is_edp() since the encoder may have been destroyed
4780 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4781 intel_panel_fini(&intel_connector
->panel
);
4783 drm_connector_cleanup(connector
);
4787 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4789 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4790 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4792 drm_dp_aux_unregister(&intel_dp
->aux
);
4793 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4794 if (is_edp(intel_dp
)) {
4795 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4797 * vdd might still be enabled do to the delayed vdd off.
4798 * Make sure vdd is actually turned off here.
4801 edp_panel_vdd_off_sync(intel_dp
);
4802 pps_unlock(intel_dp
);
4804 if (intel_dp
->edp_notifier
.notifier_call
) {
4805 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4806 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4809 drm_encoder_cleanup(encoder
);
4810 kfree(intel_dig_port
);
4813 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4815 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4817 if (!is_edp(intel_dp
))
4821 * vdd might still be enabled do to the delayed vdd off.
4822 * Make sure vdd is actually turned off here.
4824 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4826 edp_panel_vdd_off_sync(intel_dp
);
4827 pps_unlock(intel_dp
);
4830 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4832 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4833 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4835 enum intel_display_power_domain power_domain
;
4837 lockdep_assert_held(&dev_priv
->pps_mutex
);
4839 if (!edp_have_panel_vdd(intel_dp
))
4843 * The VDD bit needs a power domain reference, so if the bit is
4844 * already enabled when we boot or resume, grab this reference and
4845 * schedule a vdd off, so we don't hold on to the reference
4848 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4849 power_domain
= intel_display_port_power_domain(&intel_dig_port
->base
);
4850 intel_display_power_get(dev_priv
, power_domain
);
4852 edp_panel_vdd_schedule_off(intel_dp
);
4855 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4857 struct intel_dp
*intel_dp
;
4859 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4862 intel_dp
= enc_to_intel_dp(encoder
);
4867 * Read out the current power sequencer assignment,
4868 * in case the BIOS did something with it.
4870 if (IS_VALLEYVIEW(encoder
->dev
))
4871 vlv_initial_power_sequencer_setup(intel_dp
);
4873 intel_edp_panel_vdd_sanitize(intel_dp
);
4875 pps_unlock(intel_dp
);
4878 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4879 .dpms
= intel_connector_dpms
,
4880 .detect
= intel_dp_detect
,
4881 .force
= intel_dp_force
,
4882 .fill_modes
= drm_helper_probe_single_connector_modes
,
4883 .set_property
= intel_dp_set_property
,
4884 .atomic_get_property
= intel_connector_atomic_get_property
,
4885 .destroy
= intel_dp_connector_destroy
,
4886 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4887 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4890 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4891 .get_modes
= intel_dp_get_modes
,
4892 .mode_valid
= intel_dp_mode_valid
,
4893 .best_encoder
= intel_best_encoder
,
4896 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4897 .reset
= intel_dp_encoder_reset
,
4898 .destroy
= intel_dp_encoder_destroy
,
4902 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4908 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4910 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4911 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4912 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4914 enum intel_display_power_domain power_domain
;
4915 enum irqreturn ret
= IRQ_NONE
;
4917 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4918 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4920 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4922 * vdd off can generate a long pulse on eDP which
4923 * would require vdd on to handle it, and thus we
4924 * would end up in an endless cycle of
4925 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4927 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4928 port_name(intel_dig_port
->port
));
4932 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4933 port_name(intel_dig_port
->port
),
4934 long_hpd
? "long" : "short");
4936 power_domain
= intel_display_port_power_domain(intel_encoder
);
4937 intel_display_power_get(dev_priv
, power_domain
);
4940 /* indicate that we need to restart link training */
4941 intel_dp
->train_set_valid
= false;
4943 if (HAS_PCH_SPLIT(dev
)) {
4944 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4947 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4951 if (!intel_dp_get_dpcd(intel_dp
)) {
4955 intel_dp_probe_oui(intel_dp
);
4957 if (!intel_dp_probe_mst(intel_dp
))
4961 if (intel_dp
->is_mst
) {
4962 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4966 if (!intel_dp
->is_mst
) {
4968 * we'll check the link status via the normal hot plug path later -
4969 * but for short hpds we should check it now
4971 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4972 intel_dp_check_link_status(intel_dp
);
4973 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4981 /* if we were in MST mode, and device is not there get out of MST mode */
4982 if (intel_dp
->is_mst
) {
4983 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4984 intel_dp
->is_mst
= false;
4985 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4988 intel_display_power_put(dev_priv
, power_domain
);
4993 /* Return which DP Port should be selected for Transcoder DP control */
4995 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4997 struct drm_device
*dev
= crtc
->dev
;
4998 struct intel_encoder
*intel_encoder
;
4999 struct intel_dp
*intel_dp
;
5001 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5002 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5004 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
5005 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
5006 return intel_dp
->output_reg
;
5012 /* check the VBT to see whether the eDP is on DP-D port */
5013 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
5015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5016 union child_device_config
*p_child
;
5018 static const short port_mapping
[] = {
5019 [PORT_B
] = PORT_IDPB
,
5020 [PORT_C
] = PORT_IDPC
,
5021 [PORT_D
] = PORT_IDPD
,
5027 if (!dev_priv
->vbt
.child_dev_num
)
5030 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
5031 p_child
= dev_priv
->vbt
.child_dev
+ i
;
5033 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
5034 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
5035 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
5042 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5044 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5046 intel_attach_force_audio_property(connector
);
5047 intel_attach_broadcast_rgb_property(connector
);
5048 intel_dp
->color_range_auto
= true;
5050 if (is_edp(intel_dp
)) {
5051 drm_mode_create_scaling_mode_property(connector
->dev
);
5052 drm_object_attach_property(
5054 connector
->dev
->mode_config
.scaling_mode_property
,
5055 DRM_MODE_SCALE_ASPECT
);
5056 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
5060 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5062 intel_dp
->last_power_cycle
= jiffies
;
5063 intel_dp
->last_power_on
= jiffies
;
5064 intel_dp
->last_backlight_off
= jiffies
;
5068 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5069 struct intel_dp
*intel_dp
)
5071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5072 struct edp_power_seq cur
, vbt
, spec
,
5073 *final
= &intel_dp
->pps_delays
;
5074 u32 pp_on
, pp_off
, pp_div
, pp
;
5075 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
5077 lockdep_assert_held(&dev_priv
->pps_mutex
);
5079 /* already initialized? */
5080 if (final
->t11_t12
!= 0)
5083 if (HAS_PCH_SPLIT(dev
)) {
5084 pp_ctrl_reg
= PCH_PP_CONTROL
;
5085 pp_on_reg
= PCH_PP_ON_DELAYS
;
5086 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5087 pp_div_reg
= PCH_PP_DIVISOR
;
5089 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5091 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
5092 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5093 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5094 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5097 /* Workaround: Need to write PP_CONTROL with the unlock key as
5098 * the very first thing. */
5099 pp
= ironlake_get_pp_control(intel_dp
);
5100 I915_WRITE(pp_ctrl_reg
, pp
);
5102 pp_on
= I915_READ(pp_on_reg
);
5103 pp_off
= I915_READ(pp_off_reg
);
5104 pp_div
= I915_READ(pp_div_reg
);
5106 /* Pull timing values out of registers */
5107 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5108 PANEL_POWER_UP_DELAY_SHIFT
;
5110 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5111 PANEL_LIGHT_ON_DELAY_SHIFT
;
5113 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5114 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5116 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5117 PANEL_POWER_DOWN_DELAY_SHIFT
;
5119 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5120 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5122 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5123 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
5125 vbt
= dev_priv
->vbt
.edp_pps
;
5127 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5128 * our hw here, which are all in 100usec. */
5129 spec
.t1_t3
= 210 * 10;
5130 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5131 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5132 spec
.t10
= 500 * 10;
5133 /* This one is special and actually in units of 100ms, but zero
5134 * based in the hw (so we need to add 100 ms). But the sw vbt
5135 * table multiplies it with 1000 to make it in units of 100usec,
5137 spec
.t11_t12
= (510 + 100) * 10;
5139 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5140 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
5142 /* Use the max of the register settings and vbt. If both are
5143 * unset, fall back to the spec limits. */
5144 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5146 max(cur.field, vbt.field))
5147 assign_final(t1_t3
);
5151 assign_final(t11_t12
);
5154 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5155 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5156 intel_dp
->backlight_on_delay
= get_delay(t8
);
5157 intel_dp
->backlight_off_delay
= get_delay(t9
);
5158 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5159 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5162 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5163 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5164 intel_dp
->panel_power_cycle_delay
);
5166 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5167 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5171 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5172 struct intel_dp
*intel_dp
)
5174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5175 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5176 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
5177 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
5178 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5179 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5181 lockdep_assert_held(&dev_priv
->pps_mutex
);
5183 if (HAS_PCH_SPLIT(dev
)) {
5184 pp_on_reg
= PCH_PP_ON_DELAYS
;
5185 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5186 pp_div_reg
= PCH_PP_DIVISOR
;
5188 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5190 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5191 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5192 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5196 * And finally store the new values in the power sequencer. The
5197 * backlight delays are set to 1 because we do manual waits on them. For
5198 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5199 * we'll end up waiting for the backlight off delay twice: once when we
5200 * do the manual sleep, and once when we disable the panel and wait for
5201 * the PP_STATUS bit to become zero.
5203 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5204 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
5205 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5206 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5207 /* Compute the divisor for the pp clock, simply match the Bspec
5209 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5210 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5211 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5213 /* Haswell doesn't have any port selection bits for the panel
5214 * power sequencer any more. */
5215 if (IS_VALLEYVIEW(dev
)) {
5216 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5217 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5219 port_sel
= PANEL_PORT_SELECT_DPA
;
5221 port_sel
= PANEL_PORT_SELECT_DPD
;
5226 I915_WRITE(pp_on_reg
, pp_on
);
5227 I915_WRITE(pp_off_reg
, pp_off
);
5228 I915_WRITE(pp_div_reg
, pp_div
);
5230 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5231 I915_READ(pp_on_reg
),
5232 I915_READ(pp_off_reg
),
5233 I915_READ(pp_div_reg
));
5237 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5239 * @refresh_rate: RR to be programmed
5241 * This function gets called when refresh rate (RR) has to be changed from
5242 * one frequency to another. Switches can be between high and low RR
5243 * supported by the panel or to any other RR based on media playback (in
5244 * this case, RR value needs to be passed from user space).
5246 * The caller of this function needs to take a lock on dev_priv->drrs.
5248 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5251 struct intel_encoder
*encoder
;
5252 struct intel_digital_port
*dig_port
= NULL
;
5253 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5254 struct intel_crtc_state
*config
= NULL
;
5255 struct intel_crtc
*intel_crtc
= NULL
;
5257 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5259 if (refresh_rate
<= 0) {
5260 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5264 if (intel_dp
== NULL
) {
5265 DRM_DEBUG_KMS("DRRS not supported.\n");
5270 * FIXME: This needs proper synchronization with psr state for some
5271 * platforms that cannot have PSR and DRRS enabled at the same time.
5274 dig_port
= dp_to_dig_port(intel_dp
);
5275 encoder
= &dig_port
->base
;
5276 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5279 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5283 config
= intel_crtc
->config
;
5285 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5286 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5290 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5292 index
= DRRS_LOW_RR
;
5294 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5296 "DRRS requested for previously set RR...ignoring\n");
5300 if (!intel_crtc
->active
) {
5301 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5305 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5308 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5311 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5315 DRM_ERROR("Unsupported refreshrate type\n");
5317 } else if (INTEL_INFO(dev
)->gen
> 6) {
5318 reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5319 val
= I915_READ(reg
);
5321 if (index
> DRRS_HIGH_RR
) {
5322 if (IS_VALLEYVIEW(dev
))
5323 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5325 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5327 if (IS_VALLEYVIEW(dev
))
5328 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5330 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5332 I915_WRITE(reg
, val
);
5335 dev_priv
->drrs
.refresh_rate_type
= index
;
5337 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5341 * intel_edp_drrs_enable - init drrs struct if supported
5342 * @intel_dp: DP struct
5344 * Initializes frontbuffer_bits and drrs.dp
5346 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5348 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5350 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5351 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5352 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5354 if (!intel_crtc
->config
->has_drrs
) {
5355 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5359 mutex_lock(&dev_priv
->drrs
.mutex
);
5360 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5361 DRM_ERROR("DRRS already enabled\n");
5365 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5367 dev_priv
->drrs
.dp
= intel_dp
;
5370 mutex_unlock(&dev_priv
->drrs
.mutex
);
5374 * intel_edp_drrs_disable - Disable DRRS
5375 * @intel_dp: DP struct
5378 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5380 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5382 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5383 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5384 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5386 if (!intel_crtc
->config
->has_drrs
)
5389 mutex_lock(&dev_priv
->drrs
.mutex
);
5390 if (!dev_priv
->drrs
.dp
) {
5391 mutex_unlock(&dev_priv
->drrs
.mutex
);
5395 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5396 intel_dp_set_drrs_state(dev_priv
->dev
,
5397 intel_dp
->attached_connector
->panel
.
5398 fixed_mode
->vrefresh
);
5400 dev_priv
->drrs
.dp
= NULL
;
5401 mutex_unlock(&dev_priv
->drrs
.mutex
);
5403 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5406 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5408 struct drm_i915_private
*dev_priv
=
5409 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5410 struct intel_dp
*intel_dp
;
5412 mutex_lock(&dev_priv
->drrs
.mutex
);
5414 intel_dp
= dev_priv
->drrs
.dp
;
5420 * The delayed work can race with an invalidate hence we need to
5424 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5427 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5428 intel_dp_set_drrs_state(dev_priv
->dev
,
5429 intel_dp
->attached_connector
->panel
.
5430 downclock_mode
->vrefresh
);
5433 mutex_unlock(&dev_priv
->drrs
.mutex
);
5437 * intel_edp_drrs_invalidate - Invalidate DRRS
5439 * @frontbuffer_bits: frontbuffer plane tracking bits
5441 * When there is a disturbance on screen (due to cursor movement/time
5442 * update etc), DRRS needs to be invalidated, i.e. need to switch to
5445 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5447 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5448 unsigned frontbuffer_bits
)
5450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5451 struct drm_crtc
*crtc
;
5454 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5457 cancel_delayed_work(&dev_priv
->drrs
.work
);
5459 mutex_lock(&dev_priv
->drrs
.mutex
);
5460 if (!dev_priv
->drrs
.dp
) {
5461 mutex_unlock(&dev_priv
->drrs
.mutex
);
5465 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5466 pipe
= to_intel_crtc(crtc
)->pipe
;
5468 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
) {
5469 intel_dp_set_drrs_state(dev_priv
->dev
,
5470 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5471 fixed_mode
->vrefresh
);
5474 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5476 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5477 mutex_unlock(&dev_priv
->drrs
.mutex
);
5481 * intel_edp_drrs_flush - Flush DRRS
5483 * @frontbuffer_bits: frontbuffer plane tracking bits
5485 * When there is no movement on screen, DRRS work can be scheduled.
5486 * This DRRS work is responsible for setting relevant registers after a
5487 * timeout of 1 second.
5489 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5491 void intel_edp_drrs_flush(struct drm_device
*dev
,
5492 unsigned frontbuffer_bits
)
5494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5495 struct drm_crtc
*crtc
;
5498 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5501 cancel_delayed_work(&dev_priv
->drrs
.work
);
5503 mutex_lock(&dev_priv
->drrs
.mutex
);
5504 if (!dev_priv
->drrs
.dp
) {
5505 mutex_unlock(&dev_priv
->drrs
.mutex
);
5509 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5510 pipe
= to_intel_crtc(crtc
)->pipe
;
5511 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5513 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
&&
5514 !dev_priv
->drrs
.busy_frontbuffer_bits
)
5515 schedule_delayed_work(&dev_priv
->drrs
.work
,
5516 msecs_to_jiffies(1000));
5517 mutex_unlock(&dev_priv
->drrs
.mutex
);
5521 * DOC: Display Refresh Rate Switching (DRRS)
5523 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5524 * which enables swtching between low and high refresh rates,
5525 * dynamically, based on the usage scenario. This feature is applicable
5526 * for internal panels.
5528 * Indication that the panel supports DRRS is given by the panel EDID, which
5529 * would list multiple refresh rates for one resolution.
5531 * DRRS is of 2 types - static and seamless.
5532 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5533 * (may appear as a blink on screen) and is used in dock-undock scenario.
5534 * Seamless DRRS involves changing RR without any visual effect to the user
5535 * and can be used during normal system usage. This is done by programming
5536 * certain registers.
5538 * Support for static/seamless DRRS may be indicated in the VBT based on
5539 * inputs from the panel spec.
5541 * DRRS saves power by switching to low RR based on usage scenarios.
5544 * The implementation is based on frontbuffer tracking implementation.
5545 * When there is a disturbance on the screen triggered by user activity or a
5546 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5547 * When there is no movement on screen, after a timeout of 1 second, a switch
5548 * to low RR is made.
5549 * For integration with frontbuffer tracking code,
5550 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5552 * DRRS can be further extended to support other internal panels and also
5553 * the scenario of video playback wherein RR is set based on the rate
5554 * requested by userspace.
5558 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5559 * @intel_connector: eDP connector
5560 * @fixed_mode: preferred mode of panel
5562 * This function is called only once at driver load to initialize basic
5566 * Downclock mode if panel supports it, else return NULL.
5567 * DRRS support is determined by the presence of downclock mode (apart
5568 * from VBT setting).
5570 static struct drm_display_mode
*
5571 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5572 struct drm_display_mode
*fixed_mode
)
5574 struct drm_connector
*connector
= &intel_connector
->base
;
5575 struct drm_device
*dev
= connector
->dev
;
5576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5577 struct drm_display_mode
*downclock_mode
= NULL
;
5579 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5580 mutex_init(&dev_priv
->drrs
.mutex
);
5582 if (INTEL_INFO(dev
)->gen
<= 6) {
5583 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5587 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5588 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5592 downclock_mode
= intel_find_panel_downclock
5593 (dev
, fixed_mode
, connector
);
5595 if (!downclock_mode
) {
5596 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5600 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5602 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5603 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5604 return downclock_mode
;
5607 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5608 struct intel_connector
*intel_connector
)
5610 struct drm_connector
*connector
= &intel_connector
->base
;
5611 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5612 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5613 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5615 struct drm_display_mode
*fixed_mode
= NULL
;
5616 struct drm_display_mode
*downclock_mode
= NULL
;
5618 struct drm_display_mode
*scan
;
5620 enum pipe pipe
= INVALID_PIPE
;
5622 if (!is_edp(intel_dp
))
5626 intel_edp_panel_vdd_sanitize(intel_dp
);
5627 pps_unlock(intel_dp
);
5629 /* Cache DPCD and EDID for edp. */
5630 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5633 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5634 dev_priv
->no_aux_handshake
=
5635 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5636 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5638 /* if this fails, presume the device is a ghost */
5639 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5643 /* We now know it's not a ghost, init power sequence regs. */
5645 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5646 pps_unlock(intel_dp
);
5648 mutex_lock(&dev
->mode_config
.mutex
);
5649 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5651 if (drm_add_edid_modes(connector
, edid
)) {
5652 drm_mode_connector_update_edid_property(connector
,
5654 drm_edid_to_eld(connector
, edid
);
5657 edid
= ERR_PTR(-EINVAL
);
5660 edid
= ERR_PTR(-ENOENT
);
5662 intel_connector
->edid
= edid
;
5664 /* prefer fixed mode from EDID if available */
5665 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5666 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5667 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5668 downclock_mode
= intel_dp_drrs_init(
5669 intel_connector
, fixed_mode
);
5674 /* fallback to VBT if available for eDP */
5675 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5676 fixed_mode
= drm_mode_duplicate(dev
,
5677 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5679 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5681 mutex_unlock(&dev
->mode_config
.mutex
);
5683 if (IS_VALLEYVIEW(dev
)) {
5684 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5685 register_reboot_notifier(&intel_dp
->edp_notifier
);
5688 * Figure out the current pipe for the initial backlight setup.
5689 * If the current pipe isn't valid, try the PPS pipe, and if that
5690 * fails just assume pipe A.
5692 if (IS_CHERRYVIEW(dev
))
5693 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5695 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5697 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5698 pipe
= intel_dp
->pps_pipe
;
5700 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5703 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5707 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5708 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5709 intel_panel_setup_backlight(connector
, pipe
);
5715 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5716 struct intel_connector
*intel_connector
)
5718 struct drm_connector
*connector
= &intel_connector
->base
;
5719 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5720 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5721 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5723 enum port port
= intel_dig_port
->port
;
5726 intel_dp
->pps_pipe
= INVALID_PIPE
;
5728 /* intel_dp vfuncs */
5729 if (INTEL_INFO(dev
)->gen
>= 9)
5730 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5731 else if (IS_VALLEYVIEW(dev
))
5732 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5733 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5734 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5735 else if (HAS_PCH_SPLIT(dev
))
5736 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5738 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5740 if (INTEL_INFO(dev
)->gen
>= 9)
5741 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5743 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5745 /* Preserve the current hw state. */
5746 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5747 intel_dp
->attached_connector
= intel_connector
;
5749 if (intel_dp_is_edp(dev
, port
))
5750 type
= DRM_MODE_CONNECTOR_eDP
;
5752 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5755 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5756 * for DP the encoder type can be set by the caller to
5757 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5759 if (type
== DRM_MODE_CONNECTOR_eDP
)
5760 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5762 /* eDP only on port B and/or C on vlv/chv */
5763 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5764 port
!= PORT_B
&& port
!= PORT_C
))
5767 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5768 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5771 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5772 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5774 connector
->interlace_allowed
= true;
5775 connector
->doublescan_allowed
= 0;
5777 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5778 edp_panel_vdd_work
);
5780 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5781 drm_connector_register(connector
);
5784 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5786 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5787 intel_connector
->unregister
= intel_dp_connector_unregister
;
5789 /* Set up the hotplug pin. */
5792 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5795 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5798 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5801 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5807 if (is_edp(intel_dp
)) {
5809 intel_dp_init_panel_power_timestamps(intel_dp
);
5810 if (IS_VALLEYVIEW(dev
))
5811 vlv_initial_power_sequencer_setup(intel_dp
);
5813 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5814 pps_unlock(intel_dp
);
5817 intel_dp_aux_init(intel_dp
, intel_connector
);
5819 /* init MST on ports that can support it */
5820 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
5821 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5822 intel_dp_mst_encoder_init(intel_dig_port
,
5823 intel_connector
->base
.base
.id
);
5827 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5828 drm_dp_aux_unregister(&intel_dp
->aux
);
5829 if (is_edp(intel_dp
)) {
5830 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5832 * vdd might still be enabled do to the delayed vdd off.
5833 * Make sure vdd is actually turned off here.
5836 edp_panel_vdd_off_sync(intel_dp
);
5837 pps_unlock(intel_dp
);
5839 drm_connector_unregister(connector
);
5840 drm_connector_cleanup(connector
);
5844 intel_dp_add_properties(intel_dp
, connector
);
5846 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5847 * 0xd. Failure to do so will result in spurious interrupts being
5848 * generated on the port when a cable is not attached.
5850 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5851 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5852 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5855 i915_debugfs_connector_add(connector
);
5861 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5864 struct intel_digital_port
*intel_dig_port
;
5865 struct intel_encoder
*intel_encoder
;
5866 struct drm_encoder
*encoder
;
5867 struct intel_connector
*intel_connector
;
5869 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5870 if (!intel_dig_port
)
5873 intel_connector
= intel_connector_alloc();
5874 if (!intel_connector
) {
5875 kfree(intel_dig_port
);
5879 intel_encoder
= &intel_dig_port
->base
;
5880 encoder
= &intel_encoder
->base
;
5882 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5883 DRM_MODE_ENCODER_TMDS
);
5885 intel_encoder
->compute_config
= intel_dp_compute_config
;
5886 intel_encoder
->disable
= intel_disable_dp
;
5887 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5888 intel_encoder
->get_config
= intel_dp_get_config
;
5889 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5890 if (IS_CHERRYVIEW(dev
)) {
5891 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5892 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5893 intel_encoder
->enable
= vlv_enable_dp
;
5894 intel_encoder
->post_disable
= chv_post_disable_dp
;
5895 } else if (IS_VALLEYVIEW(dev
)) {
5896 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5897 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5898 intel_encoder
->enable
= vlv_enable_dp
;
5899 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5901 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5902 intel_encoder
->enable
= g4x_enable_dp
;
5903 if (INTEL_INFO(dev
)->gen
>= 5)
5904 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5907 intel_dig_port
->port
= port
;
5908 intel_dig_port
->dp
.output_reg
= output_reg
;
5910 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5911 if (IS_CHERRYVIEW(dev
)) {
5913 intel_encoder
->crtc_mask
= 1 << 2;
5915 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5917 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5919 intel_encoder
->cloneable
= 0;
5920 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5922 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5923 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5925 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5926 drm_encoder_cleanup(encoder
);
5927 kfree(intel_dig_port
);
5928 kfree(intel_connector
);
5932 void intel_dp_mst_suspend(struct drm_device
*dev
)
5934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5938 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5939 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5940 if (!intel_dig_port
)
5943 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5944 if (!intel_dig_port
->dp
.can_mst
)
5946 if (intel_dig_port
->dp
.is_mst
)
5947 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5952 void intel_dp_mst_resume(struct drm_device
*dev
)
5954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5957 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5958 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5959 if (!intel_dig_port
)
5961 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5964 if (!intel_dig_port
->dp
.can_mst
)
5967 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5969 intel_dp_check_mst_status(&intel_dig_port
->dp
);