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drm/i915: Disable eDP VDD in a delayed work proc instead of synchronously
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "drm_dp_helper.h"
38
39
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 #define DP_LINK_CONFIGURATION_SIZE 9
44
45 struct intel_dp {
46 struct intel_encoder base;
47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
50 bool has_audio;
51 int force_audio;
52 uint32_t color_range;
53 int dpms_mode;
54 uint8_t link_bw;
55 uint8_t lane_count;
56 uint8_t dpcd[8];
57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
59 bool is_pch_edp;
60 uint8_t train_set[4];
61 uint8_t link_status[DP_LINK_STATUS_SIZE];
62 int panel_power_up_delay;
63 int panel_power_down_delay;
64 int panel_power_cycle_delay;
65 int backlight_on_delay;
66 int backlight_off_delay;
67 struct drm_display_mode *panel_fixed_mode; /* for eDP */
68 struct delayed_work panel_vdd_work;
69 bool want_panel_vdd;
70 unsigned long panel_off_jiffies;
71 };
72
73 /**
74 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
75 * @intel_dp: DP struct
76 *
77 * If a CPU or PCH DP output is attached to an eDP panel, this function
78 * will return true, and false otherwise.
79 */
80 static bool is_edp(struct intel_dp *intel_dp)
81 {
82 return intel_dp->base.type == INTEL_OUTPUT_EDP;
83 }
84
85 /**
86 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
87 * @intel_dp: DP struct
88 *
89 * Returns true if the given DP struct corresponds to a PCH DP port attached
90 * to an eDP panel, false otherwise. Helpful for determining whether we
91 * may need FDI resources for a given DP output or not.
92 */
93 static bool is_pch_edp(struct intel_dp *intel_dp)
94 {
95 return intel_dp->is_pch_edp;
96 }
97
98 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
99 {
100 return container_of(encoder, struct intel_dp, base.base);
101 }
102
103 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
104 {
105 return container_of(intel_attached_encoder(connector),
106 struct intel_dp, base);
107 }
108
109 /**
110 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
111 * @encoder: DRM encoder
112 *
113 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
114 * by intel_display.c.
115 */
116 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
117 {
118 struct intel_dp *intel_dp;
119
120 if (!encoder)
121 return false;
122
123 intel_dp = enc_to_intel_dp(encoder);
124
125 return is_pch_edp(intel_dp);
126 }
127
128 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
129 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
130 static void intel_dp_link_down(struct intel_dp *intel_dp);
131
132 void
133 intel_edp_link_config (struct intel_encoder *intel_encoder,
134 int *lane_num, int *link_bw)
135 {
136 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
137
138 *lane_num = intel_dp->lane_count;
139 if (intel_dp->link_bw == DP_LINK_BW_1_62)
140 *link_bw = 162000;
141 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
142 *link_bw = 270000;
143 }
144
145 static int
146 intel_dp_max_lane_count(struct intel_dp *intel_dp)
147 {
148 int max_lane_count = 4;
149
150 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
151 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
152 switch (max_lane_count) {
153 case 1: case 2: case 4:
154 break;
155 default:
156 max_lane_count = 4;
157 }
158 }
159 return max_lane_count;
160 }
161
162 static int
163 intel_dp_max_link_bw(struct intel_dp *intel_dp)
164 {
165 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
166
167 switch (max_link_bw) {
168 case DP_LINK_BW_1_62:
169 case DP_LINK_BW_2_7:
170 break;
171 default:
172 max_link_bw = DP_LINK_BW_1_62;
173 break;
174 }
175 return max_link_bw;
176 }
177
178 static int
179 intel_dp_link_clock(uint8_t link_bw)
180 {
181 if (link_bw == DP_LINK_BW_2_7)
182 return 270000;
183 else
184 return 162000;
185 }
186
187 /* I think this is a fiction */
188 static int
189 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
190 {
191 struct drm_crtc *crtc = intel_dp->base.base.crtc;
192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
193 int bpp = 24;
194
195 if (intel_crtc)
196 bpp = intel_crtc->bpp;
197
198 return (pixel_clock * bpp + 7) / 8;
199 }
200
201 static int
202 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
203 {
204 return (max_link_clock * max_lanes * 8) / 10;
205 }
206
207 static int
208 intel_dp_mode_valid(struct drm_connector *connector,
209 struct drm_display_mode *mode)
210 {
211 struct intel_dp *intel_dp = intel_attached_dp(connector);
212 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
213 int max_lanes = intel_dp_max_lane_count(intel_dp);
214
215 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
216 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
217 return MODE_PANEL;
218
219 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
220 return MODE_PANEL;
221 }
222
223 /* only refuse the mode on non eDP since we have seen some weird eDP panels
224 which are outside spec tolerances but somehow work by magic */
225 if (!is_edp(intel_dp) &&
226 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
227 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
228 return MODE_CLOCK_HIGH;
229
230 if (mode->clock < 10000)
231 return MODE_CLOCK_LOW;
232
233 return MODE_OK;
234 }
235
236 static uint32_t
237 pack_aux(uint8_t *src, int src_bytes)
238 {
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247 }
248
249 static void
250 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251 {
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257 }
258
259 /* hrawclock is 1/4 the FSB frequency */
260 static int
261 intel_hrawclk(struct drm_device *dev)
262 {
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
266 clkcfg = I915_READ(CLKCFG);
267 switch (clkcfg & CLKCFG_FSB_MASK) {
268 case CLKCFG_FSB_400:
269 return 100;
270 case CLKCFG_FSB_533:
271 return 133;
272 case CLKCFG_FSB_667:
273 return 166;
274 case CLKCFG_FSB_800:
275 return 200;
276 case CLKCFG_FSB_1067:
277 return 266;
278 case CLKCFG_FSB_1333:
279 return 333;
280 /* these two are just a guess; one of them might be right */
281 case CLKCFG_FSB_1600:
282 case CLKCFG_FSB_1600_ALT:
283 return 400;
284 default:
285 return 133;
286 }
287 }
288
289 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
290 {
291 struct drm_device *dev = intel_dp->base.base.dev;
292 struct drm_i915_private *dev_priv = dev->dev_private;
293
294 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
295 }
296
297 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
298 {
299 struct drm_device *dev = intel_dp->base.base.dev;
300 struct drm_i915_private *dev_priv = dev->dev_private;
301
302 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
303 }
304
305 static void
306 intel_dp_check_edp(struct intel_dp *intel_dp)
307 {
308 struct drm_device *dev = intel_dp->base.base.dev;
309 struct drm_i915_private *dev_priv = dev->dev_private;
310
311 if (!is_edp(intel_dp))
312 return;
313 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
314 WARN(1, "eDP powered off while attempting aux channel communication.\n");
315 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
316 I915_READ(PCH_PP_STATUS),
317 I915_READ(PCH_PP_CONTROL));
318 }
319 }
320
321 static int
322 intel_dp_aux_ch(struct intel_dp *intel_dp,
323 uint8_t *send, int send_bytes,
324 uint8_t *recv, int recv_size)
325 {
326 uint32_t output_reg = intel_dp->output_reg;
327 struct drm_device *dev = intel_dp->base.base.dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
329 uint32_t ch_ctl = output_reg + 0x10;
330 uint32_t ch_data = ch_ctl + 4;
331 int i;
332 int recv_bytes;
333 uint32_t status;
334 uint32_t aux_clock_divider;
335 int try, precharge;
336
337 intel_dp_check_edp(intel_dp);
338 /* The clock divider is based off the hrawclk,
339 * and would like to run at 2MHz. So, take the
340 * hrawclk value and divide by 2 and use that
341 *
342 * Note that PCH attached eDP panels should use a 125MHz input
343 * clock divider.
344 */
345 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
346 if (IS_GEN6(dev))
347 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
348 else
349 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
350 } else if (HAS_PCH_SPLIT(dev))
351 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
352 else
353 aux_clock_divider = intel_hrawclk(dev) / 2;
354
355 if (IS_GEN6(dev))
356 precharge = 3;
357 else
358 precharge = 5;
359
360 /* Try to wait for any previous AUX channel activity */
361 for (try = 0; try < 3; try++) {
362 status = I915_READ(ch_ctl);
363 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
364 break;
365 msleep(1);
366 }
367
368 if (try == 3) {
369 WARN(1, "dp_aux_ch not started status 0x%08x\n",
370 I915_READ(ch_ctl));
371 return -EBUSY;
372 }
373
374 /* Must try at least 3 times according to DP spec */
375 for (try = 0; try < 5; try++) {
376 /* Load the send data into the aux channel data registers */
377 for (i = 0; i < send_bytes; i += 4)
378 I915_WRITE(ch_data + i,
379 pack_aux(send + i, send_bytes - i));
380
381 /* Send the command and wait for it to complete */
382 I915_WRITE(ch_ctl,
383 DP_AUX_CH_CTL_SEND_BUSY |
384 DP_AUX_CH_CTL_TIME_OUT_400us |
385 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
386 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
387 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
388 DP_AUX_CH_CTL_DONE |
389 DP_AUX_CH_CTL_TIME_OUT_ERROR |
390 DP_AUX_CH_CTL_RECEIVE_ERROR);
391 for (;;) {
392 status = I915_READ(ch_ctl);
393 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
394 break;
395 udelay(100);
396 }
397
398 /* Clear done status and any errors */
399 I915_WRITE(ch_ctl,
400 status |
401 DP_AUX_CH_CTL_DONE |
402 DP_AUX_CH_CTL_TIME_OUT_ERROR |
403 DP_AUX_CH_CTL_RECEIVE_ERROR);
404 if (status & DP_AUX_CH_CTL_DONE)
405 break;
406 }
407
408 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
409 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
410 return -EBUSY;
411 }
412
413 /* Check for timeout or receive error.
414 * Timeouts occur when the sink is not connected
415 */
416 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
417 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
418 return -EIO;
419 }
420
421 /* Timeouts occur when the device isn't connected, so they're
422 * "normal" -- don't fill the kernel log with these */
423 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
424 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
425 return -ETIMEDOUT;
426 }
427
428 /* Unload any bytes sent back from the other side */
429 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
430 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
431 if (recv_bytes > recv_size)
432 recv_bytes = recv_size;
433
434 for (i = 0; i < recv_bytes; i += 4)
435 unpack_aux(I915_READ(ch_data + i),
436 recv + i, recv_bytes - i);
437
438 return recv_bytes;
439 }
440
441 /* Write data to the aux channel in native mode */
442 static int
443 intel_dp_aux_native_write(struct intel_dp *intel_dp,
444 uint16_t address, uint8_t *send, int send_bytes)
445 {
446 int ret;
447 uint8_t msg[20];
448 int msg_bytes;
449 uint8_t ack;
450
451 intel_dp_check_edp(intel_dp);
452 if (send_bytes > 16)
453 return -1;
454 msg[0] = AUX_NATIVE_WRITE << 4;
455 msg[1] = address >> 8;
456 msg[2] = address & 0xff;
457 msg[3] = send_bytes - 1;
458 memcpy(&msg[4], send, send_bytes);
459 msg_bytes = send_bytes + 4;
460 for (;;) {
461 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
462 if (ret < 0)
463 return ret;
464 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
465 break;
466 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
467 udelay(100);
468 else
469 return -EIO;
470 }
471 return send_bytes;
472 }
473
474 /* Write a single byte to the aux channel in native mode */
475 static int
476 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
477 uint16_t address, uint8_t byte)
478 {
479 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
480 }
481
482 /* read bytes from a native aux channel */
483 static int
484 intel_dp_aux_native_read(struct intel_dp *intel_dp,
485 uint16_t address, uint8_t *recv, int recv_bytes)
486 {
487 uint8_t msg[4];
488 int msg_bytes;
489 uint8_t reply[20];
490 int reply_bytes;
491 uint8_t ack;
492 int ret;
493
494 intel_dp_check_edp(intel_dp);
495 msg[0] = AUX_NATIVE_READ << 4;
496 msg[1] = address >> 8;
497 msg[2] = address & 0xff;
498 msg[3] = recv_bytes - 1;
499
500 msg_bytes = 4;
501 reply_bytes = recv_bytes + 1;
502
503 for (;;) {
504 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
505 reply, reply_bytes);
506 if (ret == 0)
507 return -EPROTO;
508 if (ret < 0)
509 return ret;
510 ack = reply[0];
511 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
512 memcpy(recv, reply + 1, ret - 1);
513 return ret - 1;
514 }
515 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
516 udelay(100);
517 else
518 return -EIO;
519 }
520 }
521
522 static int
523 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
524 uint8_t write_byte, uint8_t *read_byte)
525 {
526 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
527 struct intel_dp *intel_dp = container_of(adapter,
528 struct intel_dp,
529 adapter);
530 uint16_t address = algo_data->address;
531 uint8_t msg[5];
532 uint8_t reply[2];
533 unsigned retry;
534 int msg_bytes;
535 int reply_bytes;
536 int ret;
537
538 intel_dp_check_edp(intel_dp);
539 /* Set up the command byte */
540 if (mode & MODE_I2C_READ)
541 msg[0] = AUX_I2C_READ << 4;
542 else
543 msg[0] = AUX_I2C_WRITE << 4;
544
545 if (!(mode & MODE_I2C_STOP))
546 msg[0] |= AUX_I2C_MOT << 4;
547
548 msg[1] = address >> 8;
549 msg[2] = address;
550
551 switch (mode) {
552 case MODE_I2C_WRITE:
553 msg[3] = 0;
554 msg[4] = write_byte;
555 msg_bytes = 5;
556 reply_bytes = 1;
557 break;
558 case MODE_I2C_READ:
559 msg[3] = 0;
560 msg_bytes = 4;
561 reply_bytes = 2;
562 break;
563 default:
564 msg_bytes = 3;
565 reply_bytes = 1;
566 break;
567 }
568
569 for (retry = 0; retry < 5; retry++) {
570 ret = intel_dp_aux_ch(intel_dp,
571 msg, msg_bytes,
572 reply, reply_bytes);
573 if (ret < 0) {
574 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
575 return ret;
576 }
577
578 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
579 case AUX_NATIVE_REPLY_ACK:
580 /* I2C-over-AUX Reply field is only valid
581 * when paired with AUX ACK.
582 */
583 break;
584 case AUX_NATIVE_REPLY_NACK:
585 DRM_DEBUG_KMS("aux_ch native nack\n");
586 return -EREMOTEIO;
587 case AUX_NATIVE_REPLY_DEFER:
588 udelay(100);
589 continue;
590 default:
591 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
592 reply[0]);
593 return -EREMOTEIO;
594 }
595
596 switch (reply[0] & AUX_I2C_REPLY_MASK) {
597 case AUX_I2C_REPLY_ACK:
598 if (mode == MODE_I2C_READ) {
599 *read_byte = reply[1];
600 }
601 return reply_bytes - 1;
602 case AUX_I2C_REPLY_NACK:
603 DRM_DEBUG_KMS("aux_i2c nack\n");
604 return -EREMOTEIO;
605 case AUX_I2C_REPLY_DEFER:
606 DRM_DEBUG_KMS("aux_i2c defer\n");
607 udelay(100);
608 break;
609 default:
610 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
611 return -EREMOTEIO;
612 }
613 }
614
615 DRM_ERROR("too many retries, giving up\n");
616 return -EREMOTEIO;
617 }
618
619 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
620 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
621
622 static int
623 intel_dp_i2c_init(struct intel_dp *intel_dp,
624 struct intel_connector *intel_connector, const char *name)
625 {
626 int ret;
627
628 DRM_DEBUG_KMS("i2c_init %s\n", name);
629 intel_dp->algo.running = false;
630 intel_dp->algo.address = 0;
631 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
632
633 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
634 intel_dp->adapter.owner = THIS_MODULE;
635 intel_dp->adapter.class = I2C_CLASS_DDC;
636 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
637 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
638 intel_dp->adapter.algo_data = &intel_dp->algo;
639 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
640
641 ironlake_edp_panel_vdd_on(intel_dp);
642 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
643 ironlake_edp_panel_vdd_off(intel_dp, false);
644 return ret;
645 }
646
647 static bool
648 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
649 struct drm_display_mode *adjusted_mode)
650 {
651 struct drm_device *dev = encoder->dev;
652 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
653 int lane_count, clock;
654 int max_lane_count = intel_dp_max_lane_count(intel_dp);
655 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
656 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
657
658 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
659 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
660 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
661 mode, adjusted_mode);
662 /*
663 * the mode->clock is used to calculate the Data&Link M/N
664 * of the pipe. For the eDP the fixed clock should be used.
665 */
666 mode->clock = intel_dp->panel_fixed_mode->clock;
667 }
668
669 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
670 for (clock = 0; clock <= max_clock; clock++) {
671 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
672
673 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
674 <= link_avail) {
675 intel_dp->link_bw = bws[clock];
676 intel_dp->lane_count = lane_count;
677 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
678 DRM_DEBUG_KMS("Display port link bw %02x lane "
679 "count %d clock %d\n",
680 intel_dp->link_bw, intel_dp->lane_count,
681 adjusted_mode->clock);
682 return true;
683 }
684 }
685 }
686
687 if (is_edp(intel_dp)) {
688 /* okay we failed just pick the highest */
689 intel_dp->lane_count = max_lane_count;
690 intel_dp->link_bw = bws[max_clock];
691 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
692 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
693 "count %d clock %d\n",
694 intel_dp->link_bw, intel_dp->lane_count,
695 adjusted_mode->clock);
696
697 return true;
698 }
699
700 return false;
701 }
702
703 struct intel_dp_m_n {
704 uint32_t tu;
705 uint32_t gmch_m;
706 uint32_t gmch_n;
707 uint32_t link_m;
708 uint32_t link_n;
709 };
710
711 static void
712 intel_reduce_ratio(uint32_t *num, uint32_t *den)
713 {
714 while (*num > 0xffffff || *den > 0xffffff) {
715 *num >>= 1;
716 *den >>= 1;
717 }
718 }
719
720 static void
721 intel_dp_compute_m_n(int bpp,
722 int nlanes,
723 int pixel_clock,
724 int link_clock,
725 struct intel_dp_m_n *m_n)
726 {
727 m_n->tu = 64;
728 m_n->gmch_m = (pixel_clock * bpp) >> 3;
729 m_n->gmch_n = link_clock * nlanes;
730 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
731 m_n->link_m = pixel_clock;
732 m_n->link_n = link_clock;
733 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
734 }
735
736 void
737 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
738 struct drm_display_mode *adjusted_mode)
739 {
740 struct drm_device *dev = crtc->dev;
741 struct drm_mode_config *mode_config = &dev->mode_config;
742 struct drm_encoder *encoder;
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
745 int lane_count = 4;
746 struct intel_dp_m_n m_n;
747 int pipe = intel_crtc->pipe;
748
749 /*
750 * Find the lane count in the intel_encoder private
751 */
752 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
753 struct intel_dp *intel_dp;
754
755 if (encoder->crtc != crtc)
756 continue;
757
758 intel_dp = enc_to_intel_dp(encoder);
759 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
760 lane_count = intel_dp->lane_count;
761 break;
762 } else if (is_edp(intel_dp)) {
763 lane_count = dev_priv->edp.lanes;
764 break;
765 }
766 }
767
768 /*
769 * Compute the GMCH and Link ratios. The '3' here is
770 * the number of bytes_per_pixel post-LUT, which we always
771 * set up for 8-bits of R/G/B, or 3 bytes total.
772 */
773 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
774 mode->clock, adjusted_mode->clock, &m_n);
775
776 if (HAS_PCH_SPLIT(dev)) {
777 I915_WRITE(TRANSDATA_M1(pipe),
778 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
779 m_n.gmch_m);
780 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
781 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
782 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
783 } else {
784 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
785 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
786 m_n.gmch_m);
787 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
788 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
789 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
790 }
791 }
792
793 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
794 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
795
796 static void
797 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
798 struct drm_display_mode *adjusted_mode)
799 {
800 struct drm_device *dev = encoder->dev;
801 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
802 struct drm_crtc *crtc = intel_dp->base.base.crtc;
803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
804
805 /* Turn on the eDP PLL if needed */
806 if (is_edp(intel_dp)) {
807 if (!is_pch_edp(intel_dp))
808 ironlake_edp_pll_on(encoder);
809 else
810 ironlake_edp_pll_off(encoder);
811 }
812
813 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
814 intel_dp->DP |= intel_dp->color_range;
815
816 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
817 intel_dp->DP |= DP_SYNC_HS_HIGH;
818 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
819 intel_dp->DP |= DP_SYNC_VS_HIGH;
820
821 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
822 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
823 else
824 intel_dp->DP |= DP_LINK_TRAIN_OFF;
825
826 switch (intel_dp->lane_count) {
827 case 1:
828 intel_dp->DP |= DP_PORT_WIDTH_1;
829 break;
830 case 2:
831 intel_dp->DP |= DP_PORT_WIDTH_2;
832 break;
833 case 4:
834 intel_dp->DP |= DP_PORT_WIDTH_4;
835 break;
836 }
837 if (intel_dp->has_audio)
838 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
839
840 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
841 intel_dp->link_configuration[0] = intel_dp->link_bw;
842 intel_dp->link_configuration[1] = intel_dp->lane_count;
843 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
844
845 /*
846 * Check for DPCD version > 1.1 and enhanced framing support
847 */
848 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
849 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
850 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
851 intel_dp->DP |= DP_ENHANCED_FRAMING;
852 }
853
854 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
855 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
856 intel_dp->DP |= DP_PIPEB_SELECT;
857
858 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
859 /* don't miss out required setting for eDP */
860 intel_dp->DP |= DP_PLL_ENABLE;
861 if (adjusted_mode->clock < 200000)
862 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
863 else
864 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
865 }
866 }
867
868 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
869 {
870 unsigned long off_time;
871 unsigned long delay;
872 DRM_DEBUG_KMS("Wait for panel power off time\n");
873 off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay);
874 if (time_after(jiffies, off_time)) {
875 DRM_DEBUG_KMS("Time already passed");
876 return;
877 }
878 delay = jiffies_to_msecs(off_time - jiffies);
879 if (delay > intel_dp->panel_power_down_delay)
880 delay = intel_dp->panel_power_down_delay;
881 DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay);
882 msleep(delay);
883 }
884
885 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
886 {
887 struct drm_device *dev = intel_dp->base.base.dev;
888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 pp;
890
891 if (!is_edp(intel_dp))
892 return;
893 DRM_DEBUG_KMS("Turn eDP VDD on\n");
894
895 WARN(intel_dp->want_panel_vdd,
896 "eDP VDD already requested on\n");
897
898 intel_dp->want_panel_vdd = true;
899 if (ironlake_edp_have_panel_vdd(intel_dp)) {
900 DRM_DEBUG_KMS("eDP VDD already on\n");
901 return;
902 }
903
904 ironlake_wait_panel_off(intel_dp);
905 pp = I915_READ(PCH_PP_CONTROL);
906 pp &= ~PANEL_UNLOCK_MASK;
907 pp |= PANEL_UNLOCK_REGS;
908 pp |= EDP_FORCE_VDD;
909 I915_WRITE(PCH_PP_CONTROL, pp);
910 POSTING_READ(PCH_PP_CONTROL);
911 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
912 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
913
914 /*
915 * If the panel wasn't on, delay before accessing aux channel
916 */
917 if (!ironlake_edp_have_panel_power(intel_dp)) {
918 DRM_DEBUG_KMS("eDP was not running\n");
919 msleep(intel_dp->panel_power_up_delay);
920 }
921 }
922
923 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
924 {
925 struct drm_device *dev = intel_dp->base.base.dev;
926 struct drm_i915_private *dev_priv = dev->dev_private;
927 u32 pp;
928
929 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
930 pp = I915_READ(PCH_PP_CONTROL);
931 pp &= ~PANEL_UNLOCK_MASK;
932 pp |= PANEL_UNLOCK_REGS;
933 pp &= ~EDP_FORCE_VDD;
934 I915_WRITE(PCH_PP_CONTROL, pp);
935 POSTING_READ(PCH_PP_CONTROL);
936
937 /* Make sure sequencer is idle before allowing subsequent activity */
938 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
939 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
940 intel_dp->panel_off_jiffies = jiffies;
941 }
942 }
943
944 static void ironlake_panel_vdd_work(struct work_struct *__work)
945 {
946 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
947 struct intel_dp, panel_vdd_work);
948 struct drm_device *dev = intel_dp->base.base.dev;
949
950 mutex_lock(&dev->struct_mutex);
951 ironlake_panel_vdd_off_sync(intel_dp);
952 mutex_unlock(&dev->struct_mutex);
953 }
954
955 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
956 {
957 if (!is_edp(intel_dp))
958 return;
959
960 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
961 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
962
963 intel_dp->want_panel_vdd = false;
964
965 if (sync) {
966 ironlake_panel_vdd_off_sync(intel_dp);
967 } else {
968 /*
969 * Queue the timer to fire a long
970 * time from now (relative to the power down delay)
971 * to keep the panel power up across a sequence of operations
972 */
973 schedule_delayed_work(&intel_dp->panel_vdd_work,
974 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
975 }
976 }
977
978 /* Returns true if the panel was already on when called */
979 static void ironlake_edp_panel_on (struct intel_dp *intel_dp)
980 {
981 struct drm_device *dev = intel_dp->base.base.dev;
982 struct drm_i915_private *dev_priv = dev->dev_private;
983 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
984
985 if (!is_edp(intel_dp))
986 return;
987 if (ironlake_edp_have_panel_power(intel_dp))
988 return;
989
990 ironlake_wait_panel_off(intel_dp);
991 pp = I915_READ(PCH_PP_CONTROL);
992 pp &= ~PANEL_UNLOCK_MASK;
993 pp |= PANEL_UNLOCK_REGS;
994
995 /* ILK workaround: disable reset around power sequence */
996 pp &= ~PANEL_POWER_RESET;
997 I915_WRITE(PCH_PP_CONTROL, pp);
998 POSTING_READ(PCH_PP_CONTROL);
999
1000 pp |= POWER_TARGET_ON;
1001 I915_WRITE(PCH_PP_CONTROL, pp);
1002 POSTING_READ(PCH_PP_CONTROL);
1003
1004 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
1005 5000))
1006 DRM_ERROR("panel on wait timed out: 0x%08x\n",
1007 I915_READ(PCH_PP_STATUS));
1008
1009 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1010 I915_WRITE(PCH_PP_CONTROL, pp);
1011 POSTING_READ(PCH_PP_CONTROL);
1012 }
1013
1014 static void ironlake_edp_panel_off(struct drm_encoder *encoder)
1015 {
1016 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1017 struct drm_device *dev = encoder->dev;
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
1020 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
1021
1022 if (!is_edp(intel_dp))
1023 return;
1024 pp = I915_READ(PCH_PP_CONTROL);
1025 pp &= ~PANEL_UNLOCK_MASK;
1026 pp |= PANEL_UNLOCK_REGS;
1027
1028 /* ILK workaround: disable reset around power sequence */
1029 pp &= ~PANEL_POWER_RESET;
1030 I915_WRITE(PCH_PP_CONTROL, pp);
1031 POSTING_READ(PCH_PP_CONTROL);
1032
1033 pp &= ~POWER_TARGET_ON;
1034 I915_WRITE(PCH_PP_CONTROL, pp);
1035 POSTING_READ(PCH_PP_CONTROL);
1036 msleep(intel_dp->panel_power_cycle_delay);
1037
1038 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
1039 DRM_ERROR("panel off wait timed out: 0x%08x\n",
1040 I915_READ(PCH_PP_STATUS));
1041
1042 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1043 I915_WRITE(PCH_PP_CONTROL, pp);
1044 POSTING_READ(PCH_PP_CONTROL);
1045 intel_dp->panel_off_jiffies = jiffies;
1046 }
1047
1048 static void ironlake_edp_backlight_on (struct intel_dp *intel_dp)
1049 {
1050 struct drm_device *dev = intel_dp->base.base.dev;
1051 struct drm_i915_private *dev_priv = dev->dev_private;
1052 u32 pp;
1053
1054 if (!is_edp(intel_dp))
1055 return;
1056
1057 DRM_DEBUG_KMS("\n");
1058 /*
1059 * If we enable the backlight right away following a panel power
1060 * on, we may see slight flicker as the panel syncs with the eDP
1061 * link. So delay a bit to make sure the image is solid before
1062 * allowing it to appear.
1063 */
1064 msleep(intel_dp->backlight_on_delay);
1065 pp = I915_READ(PCH_PP_CONTROL);
1066 pp &= ~PANEL_UNLOCK_MASK;
1067 pp |= PANEL_UNLOCK_REGS;
1068 pp |= EDP_BLC_ENABLE;
1069 I915_WRITE(PCH_PP_CONTROL, pp);
1070 POSTING_READ(PCH_PP_CONTROL);
1071 }
1072
1073 static void ironlake_edp_backlight_off (struct intel_dp *intel_dp)
1074 {
1075 struct drm_device *dev = intel_dp->base.base.dev;
1076 struct drm_i915_private *dev_priv = dev->dev_private;
1077 u32 pp;
1078
1079 if (!is_edp(intel_dp))
1080 return;
1081
1082 DRM_DEBUG_KMS("\n");
1083 pp = I915_READ(PCH_PP_CONTROL);
1084 pp &= ~PANEL_UNLOCK_MASK;
1085 pp |= PANEL_UNLOCK_REGS;
1086 pp &= ~EDP_BLC_ENABLE;
1087 I915_WRITE(PCH_PP_CONTROL, pp);
1088 POSTING_READ(PCH_PP_CONTROL);
1089 msleep(intel_dp->backlight_off_delay);
1090 }
1091
1092 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1093 {
1094 struct drm_device *dev = encoder->dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 u32 dpa_ctl;
1097
1098 DRM_DEBUG_KMS("\n");
1099 dpa_ctl = I915_READ(DP_A);
1100 dpa_ctl |= DP_PLL_ENABLE;
1101 I915_WRITE(DP_A, dpa_ctl);
1102 POSTING_READ(DP_A);
1103 udelay(200);
1104 }
1105
1106 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1107 {
1108 struct drm_device *dev = encoder->dev;
1109 struct drm_i915_private *dev_priv = dev->dev_private;
1110 u32 dpa_ctl;
1111
1112 dpa_ctl = I915_READ(DP_A);
1113 dpa_ctl &= ~DP_PLL_ENABLE;
1114 I915_WRITE(DP_A, dpa_ctl);
1115 POSTING_READ(DP_A);
1116 udelay(200);
1117 }
1118
1119 /* If the sink supports it, try to set the power state appropriately */
1120 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1121 {
1122 int ret, i;
1123
1124 /* Should have a valid DPCD by this point */
1125 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1126 return;
1127
1128 if (mode != DRM_MODE_DPMS_ON) {
1129 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1130 DP_SET_POWER_D3);
1131 if (ret != 1)
1132 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1133 } else {
1134 /*
1135 * When turning on, we need to retry for 1ms to give the sink
1136 * time to wake up.
1137 */
1138 for (i = 0; i < 3; i++) {
1139 ret = intel_dp_aux_native_write_1(intel_dp,
1140 DP_SET_POWER,
1141 DP_SET_POWER_D0);
1142 if (ret == 1)
1143 break;
1144 msleep(1);
1145 }
1146 }
1147 }
1148
1149 static void intel_dp_prepare(struct drm_encoder *encoder)
1150 {
1151 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1152
1153 /* Wake up the sink first */
1154 ironlake_edp_panel_vdd_on(intel_dp);
1155 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1156 ironlake_edp_panel_vdd_off(intel_dp, false);
1157
1158 /* Make sure the panel is off before trying to
1159 * change the mode
1160 */
1161 ironlake_edp_backlight_off(intel_dp);
1162 intel_dp_link_down(intel_dp);
1163 ironlake_edp_panel_off(encoder);
1164 }
1165
1166 static void intel_dp_commit(struct drm_encoder *encoder)
1167 {
1168 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1169
1170 ironlake_edp_panel_vdd_on(intel_dp);
1171 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1172 intel_dp_start_link_train(intel_dp);
1173 ironlake_edp_panel_on(intel_dp);
1174 ironlake_edp_panel_vdd_off(intel_dp, true);
1175
1176 intel_dp_complete_link_train(intel_dp);
1177 ironlake_edp_backlight_on(intel_dp);
1178
1179 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1180 }
1181
1182 static void
1183 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1184 {
1185 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1186 struct drm_device *dev = encoder->dev;
1187 struct drm_i915_private *dev_priv = dev->dev_private;
1188 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1189
1190 if (mode != DRM_MODE_DPMS_ON) {
1191 ironlake_edp_panel_vdd_on(intel_dp);
1192 if (is_edp(intel_dp))
1193 ironlake_edp_backlight_off(intel_dp);
1194 intel_dp_sink_dpms(intel_dp, mode);
1195 intel_dp_link_down(intel_dp);
1196 ironlake_edp_panel_off(encoder);
1197 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1198 ironlake_edp_pll_off(encoder);
1199 ironlake_edp_panel_vdd_off(intel_dp, false);
1200 } else {
1201 ironlake_edp_panel_vdd_on(intel_dp);
1202 intel_dp_sink_dpms(intel_dp, mode);
1203 if (!(dp_reg & DP_PORT_EN)) {
1204 intel_dp_start_link_train(intel_dp);
1205 ironlake_edp_panel_on(intel_dp);
1206 ironlake_edp_panel_vdd_off(intel_dp, true);
1207 intel_dp_complete_link_train(intel_dp);
1208 ironlake_edp_backlight_on(intel_dp);
1209 } else
1210 ironlake_edp_panel_vdd_off(intel_dp, false);
1211 ironlake_edp_backlight_on(intel_dp);
1212 }
1213 intel_dp->dpms_mode = mode;
1214 }
1215
1216 /*
1217 * Native read with retry for link status and receiver capability reads for
1218 * cases where the sink may still be asleep.
1219 */
1220 static bool
1221 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1222 uint8_t *recv, int recv_bytes)
1223 {
1224 int ret, i;
1225
1226 /*
1227 * Sinks are *supposed* to come up within 1ms from an off state,
1228 * but we're also supposed to retry 3 times per the spec.
1229 */
1230 for (i = 0; i < 3; i++) {
1231 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1232 recv_bytes);
1233 if (ret == recv_bytes)
1234 return true;
1235 msleep(1);
1236 }
1237
1238 return false;
1239 }
1240
1241 /*
1242 * Fetch AUX CH registers 0x202 - 0x207 which contain
1243 * link status information
1244 */
1245 static bool
1246 intel_dp_get_link_status(struct intel_dp *intel_dp)
1247 {
1248 return intel_dp_aux_native_read_retry(intel_dp,
1249 DP_LANE0_1_STATUS,
1250 intel_dp->link_status,
1251 DP_LINK_STATUS_SIZE);
1252 }
1253
1254 static uint8_t
1255 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1256 int r)
1257 {
1258 return link_status[r - DP_LANE0_1_STATUS];
1259 }
1260
1261 static uint8_t
1262 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1263 int lane)
1264 {
1265 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1266 int s = ((lane & 1) ?
1267 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1268 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1269 uint8_t l = intel_dp_link_status(link_status, i);
1270
1271 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1272 }
1273
1274 static uint8_t
1275 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1276 int lane)
1277 {
1278 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1279 int s = ((lane & 1) ?
1280 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1281 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1282 uint8_t l = intel_dp_link_status(link_status, i);
1283
1284 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1285 }
1286
1287
1288 #if 0
1289 static char *voltage_names[] = {
1290 "0.4V", "0.6V", "0.8V", "1.2V"
1291 };
1292 static char *pre_emph_names[] = {
1293 "0dB", "3.5dB", "6dB", "9.5dB"
1294 };
1295 static char *link_train_names[] = {
1296 "pattern 1", "pattern 2", "idle", "off"
1297 };
1298 #endif
1299
1300 /*
1301 * These are source-specific values; current Intel hardware supports
1302 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1303 */
1304 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1305
1306 static uint8_t
1307 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1308 {
1309 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1310 case DP_TRAIN_VOLTAGE_SWING_400:
1311 return DP_TRAIN_PRE_EMPHASIS_6;
1312 case DP_TRAIN_VOLTAGE_SWING_600:
1313 return DP_TRAIN_PRE_EMPHASIS_6;
1314 case DP_TRAIN_VOLTAGE_SWING_800:
1315 return DP_TRAIN_PRE_EMPHASIS_3_5;
1316 case DP_TRAIN_VOLTAGE_SWING_1200:
1317 default:
1318 return DP_TRAIN_PRE_EMPHASIS_0;
1319 }
1320 }
1321
1322 static void
1323 intel_get_adjust_train(struct intel_dp *intel_dp)
1324 {
1325 uint8_t v = 0;
1326 uint8_t p = 0;
1327 int lane;
1328
1329 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1330 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1331 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1332
1333 if (this_v > v)
1334 v = this_v;
1335 if (this_p > p)
1336 p = this_p;
1337 }
1338
1339 if (v >= I830_DP_VOLTAGE_MAX)
1340 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1341
1342 if (p >= intel_dp_pre_emphasis_max(v))
1343 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1344
1345 for (lane = 0; lane < 4; lane++)
1346 intel_dp->train_set[lane] = v | p;
1347 }
1348
1349 static uint32_t
1350 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1351 {
1352 uint32_t signal_levels = 0;
1353
1354 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1355 case DP_TRAIN_VOLTAGE_SWING_400:
1356 default:
1357 signal_levels |= DP_VOLTAGE_0_4;
1358 break;
1359 case DP_TRAIN_VOLTAGE_SWING_600:
1360 signal_levels |= DP_VOLTAGE_0_6;
1361 break;
1362 case DP_TRAIN_VOLTAGE_SWING_800:
1363 signal_levels |= DP_VOLTAGE_0_8;
1364 break;
1365 case DP_TRAIN_VOLTAGE_SWING_1200:
1366 signal_levels |= DP_VOLTAGE_1_2;
1367 break;
1368 }
1369 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1370 case DP_TRAIN_PRE_EMPHASIS_0:
1371 default:
1372 signal_levels |= DP_PRE_EMPHASIS_0;
1373 break;
1374 case DP_TRAIN_PRE_EMPHASIS_3_5:
1375 signal_levels |= DP_PRE_EMPHASIS_3_5;
1376 break;
1377 case DP_TRAIN_PRE_EMPHASIS_6:
1378 signal_levels |= DP_PRE_EMPHASIS_6;
1379 break;
1380 case DP_TRAIN_PRE_EMPHASIS_9_5:
1381 signal_levels |= DP_PRE_EMPHASIS_9_5;
1382 break;
1383 }
1384 return signal_levels;
1385 }
1386
1387 /* Gen6's DP voltage swing and pre-emphasis control */
1388 static uint32_t
1389 intel_gen6_edp_signal_levels(uint8_t train_set)
1390 {
1391 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1392 DP_TRAIN_PRE_EMPHASIS_MASK);
1393 switch (signal_levels) {
1394 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1395 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1396 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1397 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1398 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1399 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1400 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1401 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1402 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1403 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1404 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1405 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1406 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1407 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1408 default:
1409 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1410 "0x%x\n", signal_levels);
1411 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1412 }
1413 }
1414
1415 static uint8_t
1416 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1417 int lane)
1418 {
1419 int i = DP_LANE0_1_STATUS + (lane >> 1);
1420 int s = (lane & 1) * 4;
1421 uint8_t l = intel_dp_link_status(link_status, i);
1422
1423 return (l >> s) & 0xf;
1424 }
1425
1426 /* Check for clock recovery is done on all channels */
1427 static bool
1428 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1429 {
1430 int lane;
1431 uint8_t lane_status;
1432
1433 for (lane = 0; lane < lane_count; lane++) {
1434 lane_status = intel_get_lane_status(link_status, lane);
1435 if ((lane_status & DP_LANE_CR_DONE) == 0)
1436 return false;
1437 }
1438 return true;
1439 }
1440
1441 /* Check to see if channel eq is done on all channels */
1442 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1443 DP_LANE_CHANNEL_EQ_DONE|\
1444 DP_LANE_SYMBOL_LOCKED)
1445 static bool
1446 intel_channel_eq_ok(struct intel_dp *intel_dp)
1447 {
1448 uint8_t lane_align;
1449 uint8_t lane_status;
1450 int lane;
1451
1452 lane_align = intel_dp_link_status(intel_dp->link_status,
1453 DP_LANE_ALIGN_STATUS_UPDATED);
1454 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1455 return false;
1456 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1457 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1458 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1459 return false;
1460 }
1461 return true;
1462 }
1463
1464 static bool
1465 intel_dp_set_link_train(struct intel_dp *intel_dp,
1466 uint32_t dp_reg_value,
1467 uint8_t dp_train_pat)
1468 {
1469 struct drm_device *dev = intel_dp->base.base.dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 int ret;
1472
1473 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1474 POSTING_READ(intel_dp->output_reg);
1475
1476 intel_dp_aux_native_write_1(intel_dp,
1477 DP_TRAINING_PATTERN_SET,
1478 dp_train_pat);
1479
1480 ret = intel_dp_aux_native_write(intel_dp,
1481 DP_TRAINING_LANE0_SET,
1482 intel_dp->train_set, 4);
1483 if (ret != 4)
1484 return false;
1485
1486 return true;
1487 }
1488
1489 /* Enable corresponding port and start training pattern 1 */
1490 static void
1491 intel_dp_start_link_train(struct intel_dp *intel_dp)
1492 {
1493 struct drm_device *dev = intel_dp->base.base.dev;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1496 int i;
1497 uint8_t voltage;
1498 bool clock_recovery = false;
1499 int tries;
1500 u32 reg;
1501 uint32_t DP = intel_dp->DP;
1502
1503 /*
1504 * On CPT we have to enable the port in training pattern 1, which
1505 * will happen below in intel_dp_set_link_train. Otherwise, enable
1506 * the port and wait for it to become active.
1507 */
1508 if (!HAS_PCH_CPT(dev)) {
1509 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1510 POSTING_READ(intel_dp->output_reg);
1511 intel_wait_for_vblank(dev, intel_crtc->pipe);
1512 }
1513
1514 /* Write the link configuration data */
1515 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1516 intel_dp->link_configuration,
1517 DP_LINK_CONFIGURATION_SIZE);
1518
1519 DP |= DP_PORT_EN;
1520 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1521 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1522 else
1523 DP &= ~DP_LINK_TRAIN_MASK;
1524 memset(intel_dp->train_set, 0, 4);
1525 voltage = 0xff;
1526 tries = 0;
1527 clock_recovery = false;
1528 for (;;) {
1529 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1530 uint32_t signal_levels;
1531 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1532 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1533 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1534 } else {
1535 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1536 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1537 }
1538
1539 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1540 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1541 else
1542 reg = DP | DP_LINK_TRAIN_PAT_1;
1543
1544 if (!intel_dp_set_link_train(intel_dp, reg,
1545 DP_TRAINING_PATTERN_1 |
1546 DP_LINK_SCRAMBLING_DISABLE))
1547 break;
1548 /* Set training pattern 1 */
1549
1550 udelay(100);
1551 if (!intel_dp_get_link_status(intel_dp))
1552 break;
1553
1554 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1555 clock_recovery = true;
1556 break;
1557 }
1558
1559 /* Check to see if we've tried the max voltage */
1560 for (i = 0; i < intel_dp->lane_count; i++)
1561 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1562 break;
1563 if (i == intel_dp->lane_count)
1564 break;
1565
1566 /* Check to see if we've tried the same voltage 5 times */
1567 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1568 ++tries;
1569 if (tries == 5)
1570 break;
1571 } else
1572 tries = 0;
1573 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1574
1575 /* Compute new intel_dp->train_set as requested by target */
1576 intel_get_adjust_train(intel_dp);
1577 }
1578
1579 intel_dp->DP = DP;
1580 }
1581
1582 static void
1583 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1584 {
1585 struct drm_device *dev = intel_dp->base.base.dev;
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1587 bool channel_eq = false;
1588 int tries, cr_tries;
1589 u32 reg;
1590 uint32_t DP = intel_dp->DP;
1591
1592 /* channel equalization */
1593 tries = 0;
1594 cr_tries = 0;
1595 channel_eq = false;
1596 for (;;) {
1597 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1598 uint32_t signal_levels;
1599
1600 if (cr_tries > 5) {
1601 DRM_ERROR("failed to train DP, aborting\n");
1602 intel_dp_link_down(intel_dp);
1603 break;
1604 }
1605
1606 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1607 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1608 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1609 } else {
1610 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1611 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1612 }
1613
1614 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1615 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1616 else
1617 reg = DP | DP_LINK_TRAIN_PAT_2;
1618
1619 /* channel eq pattern */
1620 if (!intel_dp_set_link_train(intel_dp, reg,
1621 DP_TRAINING_PATTERN_2 |
1622 DP_LINK_SCRAMBLING_DISABLE))
1623 break;
1624
1625 udelay(400);
1626 if (!intel_dp_get_link_status(intel_dp))
1627 break;
1628
1629 /* Make sure clock is still ok */
1630 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1631 intel_dp_start_link_train(intel_dp);
1632 cr_tries++;
1633 continue;
1634 }
1635
1636 if (intel_channel_eq_ok(intel_dp)) {
1637 channel_eq = true;
1638 break;
1639 }
1640
1641 /* Try 5 times, then try clock recovery if that fails */
1642 if (tries > 5) {
1643 intel_dp_link_down(intel_dp);
1644 intel_dp_start_link_train(intel_dp);
1645 tries = 0;
1646 cr_tries++;
1647 continue;
1648 }
1649
1650 /* Compute new intel_dp->train_set as requested by target */
1651 intel_get_adjust_train(intel_dp);
1652 ++tries;
1653 }
1654
1655 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1656 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1657 else
1658 reg = DP | DP_LINK_TRAIN_OFF;
1659
1660 I915_WRITE(intel_dp->output_reg, reg);
1661 POSTING_READ(intel_dp->output_reg);
1662 intel_dp_aux_native_write_1(intel_dp,
1663 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1664 }
1665
1666 static void
1667 intel_dp_link_down(struct intel_dp *intel_dp)
1668 {
1669 struct drm_device *dev = intel_dp->base.base.dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 uint32_t DP = intel_dp->DP;
1672
1673 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1674 return;
1675
1676 DRM_DEBUG_KMS("\n");
1677
1678 if (is_edp(intel_dp)) {
1679 DP &= ~DP_PLL_ENABLE;
1680 I915_WRITE(intel_dp->output_reg, DP);
1681 POSTING_READ(intel_dp->output_reg);
1682 udelay(100);
1683 }
1684
1685 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1686 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1687 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1688 } else {
1689 DP &= ~DP_LINK_TRAIN_MASK;
1690 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1691 }
1692 POSTING_READ(intel_dp->output_reg);
1693
1694 msleep(17);
1695
1696 if (is_edp(intel_dp))
1697 DP |= DP_LINK_TRAIN_OFF;
1698
1699 if (!HAS_PCH_CPT(dev) &&
1700 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1701 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1702
1703 /* Hardware workaround: leaving our transcoder select
1704 * set to transcoder B while it's off will prevent the
1705 * corresponding HDMI output on transcoder A.
1706 *
1707 * Combine this with another hardware workaround:
1708 * transcoder select bit can only be cleared while the
1709 * port is enabled.
1710 */
1711 DP &= ~DP_PIPEB_SELECT;
1712 I915_WRITE(intel_dp->output_reg, DP);
1713
1714 /* Changes to enable or select take place the vblank
1715 * after being written.
1716 */
1717 if (crtc == NULL) {
1718 /* We can arrive here never having been attached
1719 * to a CRTC, for instance, due to inheriting
1720 * random state from the BIOS.
1721 *
1722 * If the pipe is not running, play safe and
1723 * wait for the clocks to stabilise before
1724 * continuing.
1725 */
1726 POSTING_READ(intel_dp->output_reg);
1727 msleep(50);
1728 } else
1729 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1730 }
1731
1732 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1733 POSTING_READ(intel_dp->output_reg);
1734 msleep(intel_dp->panel_power_down_delay);
1735 }
1736
1737 static bool
1738 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1739 {
1740 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1741 sizeof (intel_dp->dpcd)) &&
1742 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1743 return true;
1744 }
1745
1746 return false;
1747 }
1748
1749 /*
1750 * According to DP spec
1751 * 5.1.2:
1752 * 1. Read DPCD
1753 * 2. Configure link according to Receiver Capabilities
1754 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1755 * 4. Check link status on receipt of hot-plug interrupt
1756 */
1757
1758 static void
1759 intel_dp_check_link_status(struct intel_dp *intel_dp)
1760 {
1761 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1762 return;
1763
1764 if (!intel_dp->base.base.crtc)
1765 return;
1766
1767 /* Try to read receiver status if the link appears to be up */
1768 if (!intel_dp_get_link_status(intel_dp)) {
1769 intel_dp_link_down(intel_dp);
1770 return;
1771 }
1772
1773 /* Now read the DPCD to see if it's actually running */
1774 if (!intel_dp_get_dpcd(intel_dp)) {
1775 intel_dp_link_down(intel_dp);
1776 return;
1777 }
1778
1779 if (!intel_channel_eq_ok(intel_dp)) {
1780 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1781 drm_get_encoder_name(&intel_dp->base.base));
1782 intel_dp_start_link_train(intel_dp);
1783 intel_dp_complete_link_train(intel_dp);
1784 }
1785 }
1786
1787 static enum drm_connector_status
1788 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1789 {
1790 if (intel_dp_get_dpcd(intel_dp))
1791 return connector_status_connected;
1792 return connector_status_disconnected;
1793 }
1794
1795 static enum drm_connector_status
1796 ironlake_dp_detect(struct intel_dp *intel_dp)
1797 {
1798 enum drm_connector_status status;
1799
1800 /* Can't disconnect eDP, but you can close the lid... */
1801 if (is_edp(intel_dp)) {
1802 status = intel_panel_detect(intel_dp->base.base.dev);
1803 if (status == connector_status_unknown)
1804 status = connector_status_connected;
1805 return status;
1806 }
1807
1808 return intel_dp_detect_dpcd(intel_dp);
1809 }
1810
1811 static enum drm_connector_status
1812 g4x_dp_detect(struct intel_dp *intel_dp)
1813 {
1814 struct drm_device *dev = intel_dp->base.base.dev;
1815 struct drm_i915_private *dev_priv = dev->dev_private;
1816 uint32_t temp, bit;
1817
1818 switch (intel_dp->output_reg) {
1819 case DP_B:
1820 bit = DPB_HOTPLUG_INT_STATUS;
1821 break;
1822 case DP_C:
1823 bit = DPC_HOTPLUG_INT_STATUS;
1824 break;
1825 case DP_D:
1826 bit = DPD_HOTPLUG_INT_STATUS;
1827 break;
1828 default:
1829 return connector_status_unknown;
1830 }
1831
1832 temp = I915_READ(PORT_HOTPLUG_STAT);
1833
1834 if ((temp & bit) == 0)
1835 return connector_status_disconnected;
1836
1837 return intel_dp_detect_dpcd(intel_dp);
1838 }
1839
1840 static struct edid *
1841 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1842 {
1843 struct intel_dp *intel_dp = intel_attached_dp(connector);
1844 struct edid *edid;
1845
1846 ironlake_edp_panel_vdd_on(intel_dp);
1847 edid = drm_get_edid(connector, adapter);
1848 ironlake_edp_panel_vdd_off(intel_dp, false);
1849 return edid;
1850 }
1851
1852 static int
1853 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
1854 {
1855 struct intel_dp *intel_dp = intel_attached_dp(connector);
1856 int ret;
1857
1858 ironlake_edp_panel_vdd_on(intel_dp);
1859 ret = intel_ddc_get_modes(connector, adapter);
1860 ironlake_edp_panel_vdd_off(intel_dp, false);
1861 return ret;
1862 }
1863
1864
1865 /**
1866 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1867 *
1868 * \return true if DP port is connected.
1869 * \return false if DP port is disconnected.
1870 */
1871 static enum drm_connector_status
1872 intel_dp_detect(struct drm_connector *connector, bool force)
1873 {
1874 struct intel_dp *intel_dp = intel_attached_dp(connector);
1875 struct drm_device *dev = intel_dp->base.base.dev;
1876 enum drm_connector_status status;
1877 struct edid *edid = NULL;
1878
1879 intel_dp->has_audio = false;
1880
1881 if (HAS_PCH_SPLIT(dev))
1882 status = ironlake_dp_detect(intel_dp);
1883 else
1884 status = g4x_dp_detect(intel_dp);
1885
1886 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1887 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1888 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1889 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1890
1891 if (status != connector_status_connected)
1892 return status;
1893
1894 if (intel_dp->force_audio) {
1895 intel_dp->has_audio = intel_dp->force_audio > 0;
1896 } else {
1897 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1898 if (edid) {
1899 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1900 connector->display_info.raw_edid = NULL;
1901 kfree(edid);
1902 }
1903 }
1904
1905 return connector_status_connected;
1906 }
1907
1908 static int intel_dp_get_modes(struct drm_connector *connector)
1909 {
1910 struct intel_dp *intel_dp = intel_attached_dp(connector);
1911 struct drm_device *dev = intel_dp->base.base.dev;
1912 struct drm_i915_private *dev_priv = dev->dev_private;
1913 int ret;
1914
1915 /* We should parse the EDID data and find out if it has an audio sink
1916 */
1917
1918 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
1919 if (ret) {
1920 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
1921 struct drm_display_mode *newmode;
1922 list_for_each_entry(newmode, &connector->probed_modes,
1923 head) {
1924 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
1925 intel_dp->panel_fixed_mode =
1926 drm_mode_duplicate(dev, newmode);
1927 break;
1928 }
1929 }
1930 }
1931 return ret;
1932 }
1933
1934 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1935 if (is_edp(intel_dp)) {
1936 /* initialize panel mode from VBT if available for eDP */
1937 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
1938 intel_dp->panel_fixed_mode =
1939 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1940 if (intel_dp->panel_fixed_mode) {
1941 intel_dp->panel_fixed_mode->type |=
1942 DRM_MODE_TYPE_PREFERRED;
1943 }
1944 }
1945 if (intel_dp->panel_fixed_mode) {
1946 struct drm_display_mode *mode;
1947 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
1948 drm_mode_probed_add(connector, mode);
1949 return 1;
1950 }
1951 }
1952 return 0;
1953 }
1954
1955 static bool
1956 intel_dp_detect_audio(struct drm_connector *connector)
1957 {
1958 struct intel_dp *intel_dp = intel_attached_dp(connector);
1959 struct edid *edid;
1960 bool has_audio = false;
1961
1962 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1963 if (edid) {
1964 has_audio = drm_detect_monitor_audio(edid);
1965
1966 connector->display_info.raw_edid = NULL;
1967 kfree(edid);
1968 }
1969
1970 return has_audio;
1971 }
1972
1973 static int
1974 intel_dp_set_property(struct drm_connector *connector,
1975 struct drm_property *property,
1976 uint64_t val)
1977 {
1978 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1979 struct intel_dp *intel_dp = intel_attached_dp(connector);
1980 int ret;
1981
1982 ret = drm_connector_property_set_value(connector, property, val);
1983 if (ret)
1984 return ret;
1985
1986 if (property == dev_priv->force_audio_property) {
1987 int i = val;
1988 bool has_audio;
1989
1990 if (i == intel_dp->force_audio)
1991 return 0;
1992
1993 intel_dp->force_audio = i;
1994
1995 if (i == 0)
1996 has_audio = intel_dp_detect_audio(connector);
1997 else
1998 has_audio = i > 0;
1999
2000 if (has_audio == intel_dp->has_audio)
2001 return 0;
2002
2003 intel_dp->has_audio = has_audio;
2004 goto done;
2005 }
2006
2007 if (property == dev_priv->broadcast_rgb_property) {
2008 if (val == !!intel_dp->color_range)
2009 return 0;
2010
2011 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2012 goto done;
2013 }
2014
2015 return -EINVAL;
2016
2017 done:
2018 if (intel_dp->base.base.crtc) {
2019 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2020 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2021 crtc->x, crtc->y,
2022 crtc->fb);
2023 }
2024
2025 return 0;
2026 }
2027
2028 static void
2029 intel_dp_destroy (struct drm_connector *connector)
2030 {
2031 struct drm_device *dev = connector->dev;
2032
2033 if (intel_dpd_is_edp(dev))
2034 intel_panel_destroy_backlight(dev);
2035
2036 drm_sysfs_connector_remove(connector);
2037 drm_connector_cleanup(connector);
2038 kfree(connector);
2039 }
2040
2041 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2042 {
2043 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2044
2045 i2c_del_adapter(&intel_dp->adapter);
2046 drm_encoder_cleanup(encoder);
2047 if (is_edp(intel_dp)) {
2048 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2049 ironlake_panel_vdd_off_sync(intel_dp);
2050 }
2051 kfree(intel_dp);
2052 }
2053
2054 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2055 .dpms = intel_dp_dpms,
2056 .mode_fixup = intel_dp_mode_fixup,
2057 .prepare = intel_dp_prepare,
2058 .mode_set = intel_dp_mode_set,
2059 .commit = intel_dp_commit,
2060 };
2061
2062 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2063 .dpms = drm_helper_connector_dpms,
2064 .detect = intel_dp_detect,
2065 .fill_modes = drm_helper_probe_single_connector_modes,
2066 .set_property = intel_dp_set_property,
2067 .destroy = intel_dp_destroy,
2068 };
2069
2070 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2071 .get_modes = intel_dp_get_modes,
2072 .mode_valid = intel_dp_mode_valid,
2073 .best_encoder = intel_best_encoder,
2074 };
2075
2076 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2077 .destroy = intel_dp_encoder_destroy,
2078 };
2079
2080 static void
2081 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2082 {
2083 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2084
2085 intel_dp_check_link_status(intel_dp);
2086 }
2087
2088 /* Return which DP Port should be selected for Transcoder DP control */
2089 int
2090 intel_trans_dp_port_sel (struct drm_crtc *crtc)
2091 {
2092 struct drm_device *dev = crtc->dev;
2093 struct drm_mode_config *mode_config = &dev->mode_config;
2094 struct drm_encoder *encoder;
2095
2096 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2097 struct intel_dp *intel_dp;
2098
2099 if (encoder->crtc != crtc)
2100 continue;
2101
2102 intel_dp = enc_to_intel_dp(encoder);
2103 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
2104 return intel_dp->output_reg;
2105 }
2106
2107 return -1;
2108 }
2109
2110 /* check the VBT to see whether the eDP is on DP-D port */
2111 bool intel_dpd_is_edp(struct drm_device *dev)
2112 {
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114 struct child_device_config *p_child;
2115 int i;
2116
2117 if (!dev_priv->child_dev_num)
2118 return false;
2119
2120 for (i = 0; i < dev_priv->child_dev_num; i++) {
2121 p_child = dev_priv->child_dev + i;
2122
2123 if (p_child->dvo_port == PORT_IDPD &&
2124 p_child->device_type == DEVICE_TYPE_eDP)
2125 return true;
2126 }
2127 return false;
2128 }
2129
2130 static void
2131 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2132 {
2133 intel_attach_force_audio_property(connector);
2134 intel_attach_broadcast_rgb_property(connector);
2135 }
2136
2137 void
2138 intel_dp_init(struct drm_device *dev, int output_reg)
2139 {
2140 struct drm_i915_private *dev_priv = dev->dev_private;
2141 struct drm_connector *connector;
2142 struct intel_dp *intel_dp;
2143 struct intel_encoder *intel_encoder;
2144 struct intel_connector *intel_connector;
2145 const char *name = NULL;
2146 int type;
2147
2148 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2149 if (!intel_dp)
2150 return;
2151
2152 intel_dp->output_reg = output_reg;
2153 intel_dp->dpms_mode = -1;
2154
2155 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2156 if (!intel_connector) {
2157 kfree(intel_dp);
2158 return;
2159 }
2160 intel_encoder = &intel_dp->base;
2161
2162 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2163 if (intel_dpd_is_edp(dev))
2164 intel_dp->is_pch_edp = true;
2165
2166 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2167 type = DRM_MODE_CONNECTOR_eDP;
2168 intel_encoder->type = INTEL_OUTPUT_EDP;
2169 } else {
2170 type = DRM_MODE_CONNECTOR_DisplayPort;
2171 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2172 }
2173
2174 connector = &intel_connector->base;
2175 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2176 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2177
2178 connector->polled = DRM_CONNECTOR_POLL_HPD;
2179
2180 if (output_reg == DP_B || output_reg == PCH_DP_B)
2181 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2182 else if (output_reg == DP_C || output_reg == PCH_DP_C)
2183 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2184 else if (output_reg == DP_D || output_reg == PCH_DP_D)
2185 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2186
2187 if (is_edp(intel_dp)) {
2188 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2189 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2190 ironlake_panel_vdd_work);
2191 }
2192
2193 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2194 connector->interlace_allowed = true;
2195 connector->doublescan_allowed = 0;
2196
2197 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2198 DRM_MODE_ENCODER_TMDS);
2199 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2200
2201 intel_connector_attach_encoder(intel_connector, intel_encoder);
2202 drm_sysfs_connector_add(connector);
2203
2204 /* Set up the DDC bus. */
2205 switch (output_reg) {
2206 case DP_A:
2207 name = "DPDDC-A";
2208 break;
2209 case DP_B:
2210 case PCH_DP_B:
2211 dev_priv->hotplug_supported_mask |=
2212 HDMIB_HOTPLUG_INT_STATUS;
2213 name = "DPDDC-B";
2214 break;
2215 case DP_C:
2216 case PCH_DP_C:
2217 dev_priv->hotplug_supported_mask |=
2218 HDMIC_HOTPLUG_INT_STATUS;
2219 name = "DPDDC-C";
2220 break;
2221 case DP_D:
2222 case PCH_DP_D:
2223 dev_priv->hotplug_supported_mask |=
2224 HDMID_HOTPLUG_INT_STATUS;
2225 name = "DPDDC-D";
2226 break;
2227 }
2228
2229 /* Cache some DPCD data in the eDP case */
2230 if (is_edp(intel_dp)) {
2231 bool ret;
2232 struct edp_power_seq cur, vbt;
2233 u32 pp_on, pp_off, pp_div;
2234
2235 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2236 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2237 pp_div = I915_READ(PCH_PP_DIVISOR);
2238
2239 /* Pull timing values out of registers */
2240 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2241 PANEL_POWER_UP_DELAY_SHIFT;
2242
2243 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2244 PANEL_LIGHT_ON_DELAY_SHIFT;
2245
2246 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2247 PANEL_LIGHT_OFF_DELAY_SHIFT;
2248
2249 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2250 PANEL_POWER_DOWN_DELAY_SHIFT;
2251
2252 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2253 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2254
2255 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2256 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2257
2258 vbt = dev_priv->edp.pps;
2259
2260 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2261 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2262
2263 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2264
2265 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2266 intel_dp->backlight_on_delay = get_delay(t8);
2267 intel_dp->backlight_off_delay = get_delay(t9);
2268 intel_dp->panel_power_down_delay = get_delay(t10);
2269 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2270
2271 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2272 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2273 intel_dp->panel_power_cycle_delay);
2274
2275 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2276 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2277
2278 intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay;
2279
2280 ironlake_edp_panel_vdd_on(intel_dp);
2281 ret = intel_dp_get_dpcd(intel_dp);
2282 ironlake_edp_panel_vdd_off(intel_dp, false);
2283 if (ret) {
2284 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2285 dev_priv->no_aux_handshake =
2286 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2287 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2288 } else {
2289 /* if this fails, presume the device is a ghost */
2290 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2291 intel_dp_encoder_destroy(&intel_dp->base.base);
2292 intel_dp_destroy(&intel_connector->base);
2293 return;
2294 }
2295 }
2296
2297 intel_dp_i2c_init(intel_dp, intel_connector, name);
2298
2299 intel_encoder->hot_plug = intel_dp_hot_plug;
2300
2301 if (is_edp(intel_dp)) {
2302 dev_priv->int_edp_connector = connector;
2303 intel_panel_setup_backlight(dev);
2304 }
2305
2306 intel_dp_add_properties(intel_dp, connector);
2307
2308 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2309 * 0xd. Failure to do so will result in spurious interrupts being
2310 * generated on the port when a cable is not attached.
2311 */
2312 if (IS_G4X(dev) && !IS_GM45(dev)) {
2313 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2314 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2315 }
2316 }
Linux kernel - Deliverables
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