2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int chv_rates
[] = { 162000, 202500, 210000, 216000,
99 243000, 270000, 324000, 405000,
100 420000, 432000, 540000 };
101 static const int default_rates
[] = { 162000, 270000, 540000 };
104 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
105 * @intel_dp: DP struct
107 * If a CPU or PCH DP output is attached to an eDP panel, this function
108 * will return true, and false otherwise.
110 static bool is_edp(struct intel_dp
*intel_dp
)
112 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
114 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
117 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
119 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
121 return intel_dig_port
->base
.base
.dev
;
124 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
126 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
129 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
130 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
131 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
132 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
133 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
137 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
139 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
141 switch (max_link_bw
) {
142 case DP_LINK_BW_1_62
:
147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
149 max_link_bw
= DP_LINK_BW_1_62
;
155 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
157 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
158 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
159 u8 source_max
, sink_max
;
162 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
163 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
166 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
168 return min(source_max
, sink_max
);
172 * The units on the numbers in the next two are... bizarre. Examples will
173 * make it clearer; this one parallels an example in the eDP spec.
175 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
177 * 270000 * 1 * 8 / 10 == 216000
179 * The actual data capacity of that configuration is 2.16Gbit/s, so the
180 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
181 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
182 * 119000. At 18bpp that's 2142000 kilobits per second.
184 * Thus the strange-looking division by 10 in intel_dp_link_required, to
185 * get the result in decakilobits instead of kilobits.
189 intel_dp_link_required(int pixel_clock
, int bpp
)
191 return (pixel_clock
* bpp
+ 9) / 10;
195 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
197 return (max_link_clock
* max_lanes
* 8) / 10;
200 static enum drm_mode_status
201 intel_dp_mode_valid(struct drm_connector
*connector
,
202 struct drm_display_mode
*mode
)
204 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
205 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
206 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
207 int target_clock
= mode
->clock
;
208 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
210 if (is_edp(intel_dp
) && fixed_mode
) {
211 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
214 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
217 target_clock
= fixed_mode
->clock
;
220 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
221 max_lanes
= intel_dp_max_lane_count(intel_dp
);
223 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
224 mode_rate
= intel_dp_link_required(target_clock
, 18);
226 if (mode_rate
> max_rate
)
227 return MODE_CLOCK_HIGH
;
229 if (mode
->clock
< 10000)
230 return MODE_CLOCK_LOW
;
232 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
233 return MODE_H_ILLEGAL
;
238 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
245 for (i
= 0; i
< src_bytes
; i
++)
246 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
250 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
255 for (i
= 0; i
< dst_bytes
; i
++)
256 dst
[i
] = src
>> ((3-i
) * 8);
259 /* hrawclock is 1/4 the FSB frequency */
261 intel_hrawclk(struct drm_device
*dev
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev
))
270 clkcfg
= I915_READ(CLKCFG
);
271 switch (clkcfg
& CLKCFG_FSB_MASK
) {
280 case CLKCFG_FSB_1067
:
282 case CLKCFG_FSB_1333
:
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600
:
286 case CLKCFG_FSB_1600_ALT
:
294 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
295 struct intel_dp
*intel_dp
);
297 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
298 struct intel_dp
*intel_dp
);
300 static void pps_lock(struct intel_dp
*intel_dp
)
302 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
303 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
304 struct drm_device
*dev
= encoder
->base
.dev
;
305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 enum intel_display_power_domain power_domain
;
309 * See vlv_power_sequencer_reset() why we need
310 * a power domain reference here.
312 power_domain
= intel_display_port_power_domain(encoder
);
313 intel_display_power_get(dev_priv
, power_domain
);
315 mutex_lock(&dev_priv
->pps_mutex
);
318 static void pps_unlock(struct intel_dp
*intel_dp
)
320 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
321 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
322 struct drm_device
*dev
= encoder
->base
.dev
;
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 enum intel_display_power_domain power_domain
;
326 mutex_unlock(&dev_priv
->pps_mutex
);
328 power_domain
= intel_display_port_power_domain(encoder
);
329 intel_display_power_put(dev_priv
, power_domain
);
333 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
335 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
336 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
338 enum pipe pipe
= intel_dp
->pps_pipe
;
342 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
343 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
344 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
347 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
348 pipe_name(pipe
), port_name(intel_dig_port
->port
));
350 /* Preserve the BIOS-computed detected bit. This is
351 * supposed to be read-only.
353 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
354 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
355 DP
|= DP_PORT_WIDTH(1);
356 DP
|= DP_LINK_TRAIN_PAT_1
;
358 if (IS_CHERRYVIEW(dev
))
359 DP
|= DP_PIPE_SELECT_CHV(pipe
);
360 else if (pipe
== PIPE_B
)
361 DP
|= DP_PIPEB_SELECT
;
363 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
366 * The DPLL for the pipe must be enabled for this to work.
367 * So enable temporarily it if it's not already enabled.
370 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
371 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
374 * Similar magic as in intel_dp_enable_port().
375 * We _must_ do this port enable + disable trick
376 * to make this power seqeuencer lock onto the port.
377 * Otherwise even VDD force bit won't work.
379 I915_WRITE(intel_dp
->output_reg
, DP
);
380 POSTING_READ(intel_dp
->output_reg
);
382 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
383 POSTING_READ(intel_dp
->output_reg
);
385 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
386 POSTING_READ(intel_dp
->output_reg
);
389 vlv_force_pll_off(dev
, pipe
);
393 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
395 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
396 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
398 struct intel_encoder
*encoder
;
399 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
402 lockdep_assert_held(&dev_priv
->pps_mutex
);
404 /* We should never land here with regular DP ports */
405 WARN_ON(!is_edp(intel_dp
));
407 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
408 return intel_dp
->pps_pipe
;
411 * We don't have power sequencer currently.
412 * Pick one that's not used by other ports.
414 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
416 struct intel_dp
*tmp
;
418 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
421 tmp
= enc_to_intel_dp(&encoder
->base
);
423 if (tmp
->pps_pipe
!= INVALID_PIPE
)
424 pipes
&= ~(1 << tmp
->pps_pipe
);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes
== 0))
434 pipe
= ffs(pipes
) - 1;
436 vlv_steal_power_sequencer(dev
, pipe
);
437 intel_dp
->pps_pipe
= pipe
;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp
->pps_pipe
),
441 port_name(intel_dig_port
->port
));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
445 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp
);
453 return intel_dp
->pps_pipe
;
456 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
459 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
462 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
465 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
468 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
471 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
478 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
480 vlv_pipe_check pipe_check
)
484 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
485 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
486 PANEL_PORT_SELECT_MASK
;
488 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
491 if (!pipe_check(dev_priv
, pipe
))
501 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
503 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
504 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
506 enum port port
= intel_dig_port
->port
;
508 lockdep_assert_held(&dev_priv
->pps_mutex
);
510 /* try to find a pipe with this port selected */
511 /* first pick one where the panel is on */
512 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
514 /* didn't find one? pick one where vdd is on */
515 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
516 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
517 vlv_pipe_has_vdd_on
);
518 /* didn't find one? pick one with just the correct port */
519 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
520 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
523 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
524 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
525 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
530 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
531 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
533 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
534 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
537 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
539 struct drm_device
*dev
= dev_priv
->dev
;
540 struct intel_encoder
*encoder
;
542 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
546 * We can't grab pps_mutex here due to deadlock with power_domain
547 * mutex when power_domain functions are called while holding pps_mutex.
548 * That also means that in order to use pps_pipe the code needs to
549 * hold both a power domain reference and pps_mutex, and the power domain
550 * reference get/put must be done while _not_ holding pps_mutex.
551 * pps_{lock,unlock}() do these steps in the correct order, so one
552 * should use them always.
555 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
556 struct intel_dp
*intel_dp
;
558 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
561 intel_dp
= enc_to_intel_dp(&encoder
->base
);
562 intel_dp
->pps_pipe
= INVALID_PIPE
;
566 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
568 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
570 if (HAS_PCH_SPLIT(dev
))
571 return PCH_PP_CONTROL
;
573 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
576 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
578 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
580 if (HAS_PCH_SPLIT(dev
))
581 return PCH_PP_STATUS
;
583 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
586 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
587 This function only applicable when panel PM state is not to be tracked */
588 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
591 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
593 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
596 u32 pp_ctrl_reg
, pp_div_reg
;
598 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
603 if (IS_VALLEYVIEW(dev
)) {
604 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
606 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
607 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
608 pp_div
= I915_READ(pp_div_reg
);
609 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
611 /* 0x1F write to PP_DIV_REG sets max cycle delay */
612 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
613 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
614 msleep(intel_dp
->panel_power_cycle_delay
);
617 pps_unlock(intel_dp
);
622 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
624 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
627 lockdep_assert_held(&dev_priv
->pps_mutex
);
629 if (IS_VALLEYVIEW(dev
) &&
630 intel_dp
->pps_pipe
== INVALID_PIPE
)
633 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
636 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
638 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
641 lockdep_assert_held(&dev_priv
->pps_mutex
);
643 if (IS_VALLEYVIEW(dev
) &&
644 intel_dp
->pps_pipe
== INVALID_PIPE
)
647 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
651 intel_dp_check_edp(struct intel_dp
*intel_dp
)
653 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
656 if (!is_edp(intel_dp
))
659 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
660 WARN(1, "eDP powered off while attempting aux channel communication.\n");
661 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
662 I915_READ(_pp_stat_reg(intel_dp
)),
663 I915_READ(_pp_ctrl_reg(intel_dp
)));
668 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
670 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
671 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
673 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
677 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
679 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
680 msecs_to_jiffies_timeout(10));
682 done
= wait_for_atomic(C
, 10) == 0;
684 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
691 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
693 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
694 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
697 * The clock divider is based off the hrawclk, and would like to run at
698 * 2MHz. So, take the hrawclk value and divide by 2 and use that
700 return index
? 0 : intel_hrawclk(dev
) / 2;
703 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
705 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
706 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
712 if (intel_dig_port
->port
== PORT_A
) {
713 return DIV_ROUND_UP(dev_priv
->display
.get_display_clock_speed(dev
), 2000);
715 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
719 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
721 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
722 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
725 if (intel_dig_port
->port
== PORT_A
) {
728 return DIV_ROUND_CLOSEST(dev_priv
->display
.get_display_clock_speed(dev
), 2000);
729 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
730 /* Workaround for non-ULT HSW */
737 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
741 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
743 return index
? 0 : 100;
746 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
749 * SKL doesn't need us to program the AUX clock divider (Hardware will
750 * derive the clock from CDCLK automatically). We still implement the
751 * get_aux_clock_divider vfunc to plug-in into the existing code.
753 return index
? 0 : 1;
756 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
759 uint32_t aux_clock_divider
)
761 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
762 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
763 uint32_t precharge
, timeout
;
770 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
771 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
773 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
775 return DP_AUX_CH_CTL_SEND_BUSY
|
777 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
778 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
780 DP_AUX_CH_CTL_RECEIVE_ERROR
|
781 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
782 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
783 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
786 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
791 return DP_AUX_CH_CTL_SEND_BUSY
|
793 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
794 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
795 DP_AUX_CH_CTL_TIME_OUT_1600us
|
796 DP_AUX_CH_CTL_RECEIVE_ERROR
|
797 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
798 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
802 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
803 const uint8_t *send
, int send_bytes
,
804 uint8_t *recv
, int recv_size
)
806 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
807 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
809 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
810 uint32_t ch_data
= ch_ctl
+ 4;
811 uint32_t aux_clock_divider
;
812 int i
, ret
, recv_bytes
;
815 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
821 * We will be called with VDD already enabled for dpcd/edid/oui reads.
822 * In such cases we want to leave VDD enabled and it's up to upper layers
823 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
826 vdd
= edp_panel_vdd_on(intel_dp
);
828 /* dp aux is extremely sensitive to irq latency, hence request the
829 * lowest possible wakeup latency and so prevent the cpu from going into
832 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
834 intel_dp_check_edp(intel_dp
);
836 intel_aux_display_runtime_get(dev_priv
);
838 /* Try to wait for any previous AUX channel activity */
839 for (try = 0; try < 3; try++) {
840 status
= I915_READ_NOTRACE(ch_ctl
);
841 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
847 WARN(1, "dp_aux_ch not started status 0x%08x\n",
853 /* Only 5 data registers! */
854 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
859 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
860 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
865 /* Must try at least 3 times according to DP spec */
866 for (try = 0; try < 5; try++) {
867 /* Load the send data into the aux channel data registers */
868 for (i
= 0; i
< send_bytes
; i
+= 4)
869 I915_WRITE(ch_data
+ i
,
870 intel_dp_pack_aux(send
+ i
,
873 /* Send the command and wait for it to complete */
874 I915_WRITE(ch_ctl
, send_ctl
);
876 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
878 /* Clear done status and any errors */
882 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
883 DP_AUX_CH_CTL_RECEIVE_ERROR
);
885 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
888 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
889 * 400us delay required for errors and timeouts
890 * Timeout errors from the HW already meet this
891 * requirement so skip to next iteration
893 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
894 usleep_range(400, 500);
897 if (status
& DP_AUX_CH_CTL_DONE
)
900 if (status
& DP_AUX_CH_CTL_DONE
)
904 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
905 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
910 /* Check for timeout or receive error.
911 * Timeouts occur when the sink is not connected
913 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
914 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
919 /* Timeouts occur when the device isn't connected, so they're
920 * "normal" -- don't fill the kernel log with these */
921 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
922 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
927 /* Unload any bytes sent back from the other side */
928 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
929 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
930 if (recv_bytes
> recv_size
)
931 recv_bytes
= recv_size
;
933 for (i
= 0; i
< recv_bytes
; i
+= 4)
934 intel_dp_unpack_aux(I915_READ(ch_data
+ i
),
935 recv
+ i
, recv_bytes
- i
);
939 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
940 intel_aux_display_runtime_put(dev_priv
);
943 edp_panel_vdd_off(intel_dp
, false);
945 pps_unlock(intel_dp
);
950 #define BARE_ADDRESS_SIZE 3
951 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
953 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
955 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
956 uint8_t txbuf
[20], rxbuf
[20];
957 size_t txsize
, rxsize
;
960 txbuf
[0] = (msg
->request
<< 4) |
961 ((msg
->address
>> 16) & 0xf);
962 txbuf
[1] = (msg
->address
>> 8) & 0xff;
963 txbuf
[2] = msg
->address
& 0xff;
964 txbuf
[3] = msg
->size
- 1;
966 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
967 case DP_AUX_NATIVE_WRITE
:
968 case DP_AUX_I2C_WRITE
:
969 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
970 rxsize
= 2; /* 0 or 1 data bytes */
972 if (WARN_ON(txsize
> 20))
975 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
977 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
979 msg
->reply
= rxbuf
[0] >> 4;
982 /* Number of bytes written in a short write. */
983 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
985 /* Return payload size. */
991 case DP_AUX_NATIVE_READ
:
992 case DP_AUX_I2C_READ
:
993 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
994 rxsize
= msg
->size
+ 1;
996 if (WARN_ON(rxsize
> 20))
999 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1001 msg
->reply
= rxbuf
[0] >> 4;
1003 * Assume happy day, and copy the data. The caller is
1004 * expected to check msg->reply before touching it.
1006 * Return payload size.
1009 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1022 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1024 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1025 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1026 enum port port
= intel_dig_port
->port
;
1027 const char *name
= NULL
;
1032 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1036 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1040 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1044 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1052 * The AUX_CTL register is usually DP_CTL + 0x10.
1054 * On Haswell and Broadwell though:
1055 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1056 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1058 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1060 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
1061 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1063 intel_dp
->aux
.name
= name
;
1064 intel_dp
->aux
.dev
= dev
->dev
;
1065 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1067 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1068 connector
->base
.kdev
->kobj
.name
);
1070 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1072 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1077 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1078 &intel_dp
->aux
.ddc
.dev
.kobj
,
1079 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1081 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1082 drm_dp_aux_unregister(&intel_dp
->aux
);
1087 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1089 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1091 if (!intel_connector
->mst_port
)
1092 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1093 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1094 intel_connector_unregister(intel_connector
);
1098 skl_edp_set_pll_config(struct intel_crtc_state
*pipe_config
, int link_clock
)
1102 memset(&pipe_config
->dpll_hw_state
, 0,
1103 sizeof(pipe_config
->dpll_hw_state
));
1105 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
1106 pipe_config
->dpll_hw_state
.cfgcr1
= 0;
1107 pipe_config
->dpll_hw_state
.cfgcr2
= 0;
1109 ctrl1
= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
1110 switch (link_clock
/ 2) {
1112 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
1116 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
,
1120 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
,
1124 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
,
1127 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1128 results in CDCLK change. Need to handle the change of CDCLK by
1129 disabling pipes and re-enabling them */
1131 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
1135 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
,
1140 pipe_config
->dpll_hw_state
.ctrl1
= ctrl1
;
1144 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state
*pipe_config
, int link_bw
)
1147 case DP_LINK_BW_1_62
:
1148 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1150 case DP_LINK_BW_2_7
:
1151 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1153 case DP_LINK_BW_5_4
:
1154 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1160 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1162 if (intel_dp
->num_sink_rates
) {
1163 *sink_rates
= intel_dp
->sink_rates
;
1164 return intel_dp
->num_sink_rates
;
1167 *sink_rates
= default_rates
;
1169 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1173 intel_dp_source_rates(struct drm_device
*dev
, const int **source_rates
)
1175 if (IS_BROXTON(dev
)) {
1176 *source_rates
= bxt_rates
;
1177 return ARRAY_SIZE(bxt_rates
);
1178 } else if (IS_SKYLAKE(dev
)) {
1179 *source_rates
= skl_rates
;
1180 return ARRAY_SIZE(skl_rates
);
1181 } else if (IS_CHERRYVIEW(dev
)) {
1182 *source_rates
= chv_rates
;
1183 return ARRAY_SIZE(chv_rates
);
1186 *source_rates
= default_rates
;
1188 if (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
)
1189 /* WaDisableHBR2:skl */
1190 return (DP_LINK_BW_2_7
>> 3) + 1;
1191 else if (INTEL_INFO(dev
)->gen
>= 8 ||
1192 (IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)))
1193 return (DP_LINK_BW_5_4
>> 3) + 1;
1195 return (DP_LINK_BW_2_7
>> 3) + 1;
1199 intel_dp_set_clock(struct intel_encoder
*encoder
,
1200 struct intel_crtc_state
*pipe_config
, int link_bw
)
1202 struct drm_device
*dev
= encoder
->base
.dev
;
1203 const struct dp_link_dpll
*divisor
= NULL
;
1207 divisor
= gen4_dpll
;
1208 count
= ARRAY_SIZE(gen4_dpll
);
1209 } else if (HAS_PCH_SPLIT(dev
)) {
1211 count
= ARRAY_SIZE(pch_dpll
);
1212 } else if (IS_CHERRYVIEW(dev
)) {
1214 count
= ARRAY_SIZE(chv_dpll
);
1215 } else if (IS_VALLEYVIEW(dev
)) {
1217 count
= ARRAY_SIZE(vlv_dpll
);
1220 if (divisor
&& count
) {
1221 for (i
= 0; i
< count
; i
++) {
1222 if (link_bw
== divisor
[i
].link_bw
) {
1223 pipe_config
->dpll
= divisor
[i
].dpll
;
1224 pipe_config
->clock_set
= true;
1231 static int intersect_rates(const int *source_rates
, int source_len
,
1232 const int *sink_rates
, int sink_len
,
1235 int i
= 0, j
= 0, k
= 0;
1237 while (i
< source_len
&& j
< sink_len
) {
1238 if (source_rates
[i
] == sink_rates
[j
]) {
1239 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1241 common_rates
[k
] = source_rates
[i
];
1245 } else if (source_rates
[i
] < sink_rates
[j
]) {
1254 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1257 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1258 const int *source_rates
, *sink_rates
;
1259 int source_len
, sink_len
;
1261 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1262 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1264 return intersect_rates(source_rates
, source_len
,
1265 sink_rates
, sink_len
,
1269 static void snprintf_int_array(char *str
, size_t len
,
1270 const int *array
, int nelem
)
1276 for (i
= 0; i
< nelem
; i
++) {
1277 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1285 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1287 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1288 const int *source_rates
, *sink_rates
;
1289 int source_len
, sink_len
, common_len
;
1290 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1291 char str
[128]; /* FIXME: too big for stack? */
1293 if ((drm_debug
& DRM_UT_KMS
) == 0)
1296 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1297 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1298 DRM_DEBUG_KMS("source rates: %s\n", str
);
1300 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1301 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1302 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1304 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1305 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1306 DRM_DEBUG_KMS("common rates: %s\n", str
);
1309 static int rate_to_index(int find
, const int *rates
)
1313 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1314 if (find
== rates
[i
])
1321 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1323 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1326 len
= intel_dp_common_rates(intel_dp
, rates
);
1327 if (WARN_ON(len
<= 0))
1330 return rates
[rate_to_index(0, rates
) - 1];
1333 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1335 return rate_to_index(rate
, intel_dp
->sink_rates
);
1339 intel_dp_compute_config(struct intel_encoder
*encoder
,
1340 struct intel_crtc_state
*pipe_config
)
1342 struct drm_device
*dev
= encoder
->base
.dev
;
1343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1344 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1345 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1346 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1347 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1348 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1349 int lane_count
, clock
;
1350 int min_lane_count
= 1;
1351 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1352 /* Conveniently, the link BW constants become indices with a shift...*/
1356 int link_avail
, link_clock
;
1357 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1360 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1362 /* No common link rates between source and sink */
1363 WARN_ON(common_len
<= 0);
1365 max_clock
= common_len
- 1;
1367 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1368 pipe_config
->has_pch_encoder
= true;
1370 pipe_config
->has_dp_encoder
= true;
1371 pipe_config
->has_drrs
= false;
1372 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1374 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1375 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1378 if (INTEL_INFO(dev
)->gen
>= 9) {
1380 ret
= skl_update_scaler_users(intel_crtc
, pipe_config
, NULL
, NULL
, 0);
1385 if (!HAS_PCH_SPLIT(dev
))
1386 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1387 intel_connector
->panel
.fitting_mode
);
1389 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1390 intel_connector
->panel
.fitting_mode
);
1393 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1396 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1397 "max bw %d pixel clock %iKHz\n",
1398 max_lane_count
, common_rates
[max_clock
],
1399 adjusted_mode
->crtc_clock
);
1401 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1402 * bpc in between. */
1403 bpp
= pipe_config
->pipe_bpp
;
1404 if (is_edp(intel_dp
)) {
1405 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1406 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1407 dev_priv
->vbt
.edp_bpp
);
1408 bpp
= dev_priv
->vbt
.edp_bpp
;
1412 * Use the maximum clock and number of lanes the eDP panel
1413 * advertizes being capable of. The panels are generally
1414 * designed to support only a single clock and lane
1415 * configuration, and typically these values correspond to the
1416 * native resolution of the panel.
1418 min_lane_count
= max_lane_count
;
1419 min_clock
= max_clock
;
1422 for (; bpp
>= 6*3; bpp
-= 2*3) {
1423 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1426 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1427 for (lane_count
= min_lane_count
;
1428 lane_count
<= max_lane_count
;
1431 link_clock
= common_rates
[clock
];
1432 link_avail
= intel_dp_max_data_rate(link_clock
,
1435 if (mode_rate
<= link_avail
) {
1445 if (intel_dp
->color_range_auto
) {
1448 * CEA-861-E - 5.1 Default Encoding Parameters
1449 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1451 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1452 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1454 intel_dp
->color_range
= 0;
1457 if (intel_dp
->color_range
)
1458 pipe_config
->limited_color_range
= true;
1460 intel_dp
->lane_count
= lane_count
;
1462 if (intel_dp
->num_sink_rates
) {
1463 intel_dp
->link_bw
= 0;
1464 intel_dp
->rate_select
=
1465 intel_dp_rate_select(intel_dp
, common_rates
[clock
]);
1468 drm_dp_link_rate_to_bw_code(common_rates
[clock
]);
1469 intel_dp
->rate_select
= 0;
1472 pipe_config
->pipe_bpp
= bpp
;
1473 pipe_config
->port_clock
= common_rates
[clock
];
1475 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1476 intel_dp
->link_bw
, intel_dp
->lane_count
,
1477 pipe_config
->port_clock
, bpp
);
1478 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1479 mode_rate
, link_avail
);
1481 intel_link_compute_m_n(bpp
, lane_count
,
1482 adjusted_mode
->crtc_clock
,
1483 pipe_config
->port_clock
,
1484 &pipe_config
->dp_m_n
);
1486 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1487 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1488 pipe_config
->has_drrs
= true;
1489 intel_link_compute_m_n(bpp
, lane_count
,
1490 intel_connector
->panel
.downclock_mode
->clock
,
1491 pipe_config
->port_clock
,
1492 &pipe_config
->dp_m2_n2
);
1495 if (IS_SKYLAKE(dev
) && is_edp(intel_dp
))
1496 skl_edp_set_pll_config(pipe_config
, common_rates
[clock
]);
1497 else if (IS_BROXTON(dev
))
1498 /* handled in ddi */;
1499 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1500 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1502 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1507 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1509 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1510 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1511 struct drm_device
*dev
= crtc
->base
.dev
;
1512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1515 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1516 crtc
->config
->port_clock
);
1517 dpa_ctl
= I915_READ(DP_A
);
1518 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1520 if (crtc
->config
->port_clock
== 162000) {
1521 /* For a long time we've carried around a ILK-DevA w/a for the
1522 * 160MHz clock. If we're really unlucky, it's still required.
1524 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1525 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1526 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1528 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1529 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1532 I915_WRITE(DP_A
, dpa_ctl
);
1538 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1540 struct drm_device
*dev
= encoder
->base
.dev
;
1541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1542 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1543 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1544 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1545 struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1548 * There are four kinds of DP registers:
1555 * IBX PCH and CPU are the same for almost everything,
1556 * except that the CPU DP PLL is configured in this
1559 * CPT PCH is quite different, having many bits moved
1560 * to the TRANS_DP_CTL register instead. That
1561 * configuration happens (oddly) in ironlake_pch_enable
1564 /* Preserve the BIOS-computed detected bit. This is
1565 * supposed to be read-only.
1567 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1569 /* Handle DP bits in common between all three register formats */
1570 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1571 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1573 if (crtc
->config
->has_audio
)
1574 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1576 /* Split out the IBX/CPU vs CPT settings */
1578 if (IS_GEN7(dev
) && port
== PORT_A
) {
1579 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1580 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1581 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1582 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1583 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1585 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1586 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1588 intel_dp
->DP
|= crtc
->pipe
<< 29;
1589 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1592 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1594 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1595 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1596 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1598 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1599 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1601 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1602 intel_dp
->DP
|= intel_dp
->color_range
;
1604 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1605 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1606 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1607 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1608 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1610 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1611 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1613 if (IS_CHERRYVIEW(dev
))
1614 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1615 else if (crtc
->pipe
== PIPE_B
)
1616 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1620 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1621 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1623 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1624 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1626 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1627 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1629 static void wait_panel_status(struct intel_dp
*intel_dp
,
1633 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1635 u32 pp_stat_reg
, pp_ctrl_reg
;
1637 lockdep_assert_held(&dev_priv
->pps_mutex
);
1639 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1640 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1642 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1644 I915_READ(pp_stat_reg
),
1645 I915_READ(pp_ctrl_reg
));
1647 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1648 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1649 I915_READ(pp_stat_reg
),
1650 I915_READ(pp_ctrl_reg
));
1653 DRM_DEBUG_KMS("Wait complete\n");
1656 static void wait_panel_on(struct intel_dp
*intel_dp
)
1658 DRM_DEBUG_KMS("Wait for panel power on\n");
1659 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1662 static void wait_panel_off(struct intel_dp
*intel_dp
)
1664 DRM_DEBUG_KMS("Wait for panel power off time\n");
1665 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1668 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1670 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1672 /* When we disable the VDD override bit last we have to do the manual
1674 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1675 intel_dp
->panel_power_cycle_delay
);
1677 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1680 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1682 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1683 intel_dp
->backlight_on_delay
);
1686 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1688 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1689 intel_dp
->backlight_off_delay
);
1692 /* Read the current pp_control value, unlocking the register if it
1696 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1698 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1702 lockdep_assert_held(&dev_priv
->pps_mutex
);
1704 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1705 control
&= ~PANEL_UNLOCK_MASK
;
1706 control
|= PANEL_UNLOCK_REGS
;
1711 * Must be paired with edp_panel_vdd_off().
1712 * Must hold pps_mutex around the whole on/off sequence.
1713 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1715 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1717 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1718 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1719 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1721 enum intel_display_power_domain power_domain
;
1723 u32 pp_stat_reg
, pp_ctrl_reg
;
1724 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1726 lockdep_assert_held(&dev_priv
->pps_mutex
);
1728 if (!is_edp(intel_dp
))
1731 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1732 intel_dp
->want_panel_vdd
= true;
1734 if (edp_have_panel_vdd(intel_dp
))
1735 return need_to_disable
;
1737 power_domain
= intel_display_port_power_domain(intel_encoder
);
1738 intel_display_power_get(dev_priv
, power_domain
);
1740 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1741 port_name(intel_dig_port
->port
));
1743 if (!edp_have_panel_power(intel_dp
))
1744 wait_panel_power_cycle(intel_dp
);
1746 pp
= ironlake_get_pp_control(intel_dp
);
1747 pp
|= EDP_FORCE_VDD
;
1749 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1750 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1752 I915_WRITE(pp_ctrl_reg
, pp
);
1753 POSTING_READ(pp_ctrl_reg
);
1754 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1755 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1757 * If the panel wasn't on, delay before accessing aux channel
1759 if (!edp_have_panel_power(intel_dp
)) {
1760 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1761 port_name(intel_dig_port
->port
));
1762 msleep(intel_dp
->panel_power_up_delay
);
1765 return need_to_disable
;
1769 * Must be paired with intel_edp_panel_vdd_off() or
1770 * intel_edp_panel_off().
1771 * Nested calls to these functions are not allowed since
1772 * we drop the lock. Caller must use some higher level
1773 * locking to prevent nested calls from other threads.
1775 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1779 if (!is_edp(intel_dp
))
1783 vdd
= edp_panel_vdd_on(intel_dp
);
1784 pps_unlock(intel_dp
);
1786 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1787 port_name(dp_to_dig_port(intel_dp
)->port
));
1790 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1792 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1794 struct intel_digital_port
*intel_dig_port
=
1795 dp_to_dig_port(intel_dp
);
1796 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1797 enum intel_display_power_domain power_domain
;
1799 u32 pp_stat_reg
, pp_ctrl_reg
;
1801 lockdep_assert_held(&dev_priv
->pps_mutex
);
1803 WARN_ON(intel_dp
->want_panel_vdd
);
1805 if (!edp_have_panel_vdd(intel_dp
))
1808 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1809 port_name(intel_dig_port
->port
));
1811 pp
= ironlake_get_pp_control(intel_dp
);
1812 pp
&= ~EDP_FORCE_VDD
;
1814 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1815 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1817 I915_WRITE(pp_ctrl_reg
, pp
);
1818 POSTING_READ(pp_ctrl_reg
);
1820 /* Make sure sequencer is idle before allowing subsequent activity */
1821 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1822 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1824 if ((pp
& POWER_TARGET_ON
) == 0)
1825 intel_dp
->last_power_cycle
= jiffies
;
1827 power_domain
= intel_display_port_power_domain(intel_encoder
);
1828 intel_display_power_put(dev_priv
, power_domain
);
1831 static void edp_panel_vdd_work(struct work_struct
*__work
)
1833 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1834 struct intel_dp
, panel_vdd_work
);
1837 if (!intel_dp
->want_panel_vdd
)
1838 edp_panel_vdd_off_sync(intel_dp
);
1839 pps_unlock(intel_dp
);
1842 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1844 unsigned long delay
;
1847 * Queue the timer to fire a long time from now (relative to the power
1848 * down delay) to keep the panel power up across a sequence of
1851 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1852 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1856 * Must be paired with edp_panel_vdd_on().
1857 * Must hold pps_mutex around the whole on/off sequence.
1858 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1860 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1862 struct drm_i915_private
*dev_priv
=
1863 intel_dp_to_dev(intel_dp
)->dev_private
;
1865 lockdep_assert_held(&dev_priv
->pps_mutex
);
1867 if (!is_edp(intel_dp
))
1870 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1871 port_name(dp_to_dig_port(intel_dp
)->port
));
1873 intel_dp
->want_panel_vdd
= false;
1876 edp_panel_vdd_off_sync(intel_dp
);
1878 edp_panel_vdd_schedule_off(intel_dp
);
1881 static void edp_panel_on(struct intel_dp
*intel_dp
)
1883 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1888 lockdep_assert_held(&dev_priv
->pps_mutex
);
1890 if (!is_edp(intel_dp
))
1893 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1894 port_name(dp_to_dig_port(intel_dp
)->port
));
1896 if (WARN(edp_have_panel_power(intel_dp
),
1897 "eDP port %c panel power already on\n",
1898 port_name(dp_to_dig_port(intel_dp
)->port
)))
1901 wait_panel_power_cycle(intel_dp
);
1903 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1904 pp
= ironlake_get_pp_control(intel_dp
);
1906 /* ILK workaround: disable reset around power sequence */
1907 pp
&= ~PANEL_POWER_RESET
;
1908 I915_WRITE(pp_ctrl_reg
, pp
);
1909 POSTING_READ(pp_ctrl_reg
);
1912 pp
|= POWER_TARGET_ON
;
1914 pp
|= PANEL_POWER_RESET
;
1916 I915_WRITE(pp_ctrl_reg
, pp
);
1917 POSTING_READ(pp_ctrl_reg
);
1919 wait_panel_on(intel_dp
);
1920 intel_dp
->last_power_on
= jiffies
;
1923 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1924 I915_WRITE(pp_ctrl_reg
, pp
);
1925 POSTING_READ(pp_ctrl_reg
);
1929 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1931 if (!is_edp(intel_dp
))
1935 edp_panel_on(intel_dp
);
1936 pps_unlock(intel_dp
);
1940 static void edp_panel_off(struct intel_dp
*intel_dp
)
1942 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1943 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1944 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1946 enum intel_display_power_domain power_domain
;
1950 lockdep_assert_held(&dev_priv
->pps_mutex
);
1952 if (!is_edp(intel_dp
))
1955 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1956 port_name(dp_to_dig_port(intel_dp
)->port
));
1958 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
1959 port_name(dp_to_dig_port(intel_dp
)->port
));
1961 pp
= ironlake_get_pp_control(intel_dp
);
1962 /* We need to switch off panel power _and_ force vdd, for otherwise some
1963 * panels get very unhappy and cease to work. */
1964 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1967 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1969 intel_dp
->want_panel_vdd
= false;
1971 I915_WRITE(pp_ctrl_reg
, pp
);
1972 POSTING_READ(pp_ctrl_reg
);
1974 intel_dp
->last_power_cycle
= jiffies
;
1975 wait_panel_off(intel_dp
);
1977 /* We got a reference when we enabled the VDD. */
1978 power_domain
= intel_display_port_power_domain(intel_encoder
);
1979 intel_display_power_put(dev_priv
, power_domain
);
1982 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1984 if (!is_edp(intel_dp
))
1988 edp_panel_off(intel_dp
);
1989 pps_unlock(intel_dp
);
1992 /* Enable backlight in the panel power control. */
1993 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1995 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1996 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2002 * If we enable the backlight right away following a panel power
2003 * on, we may see slight flicker as the panel syncs with the eDP
2004 * link. So delay a bit to make sure the image is solid before
2005 * allowing it to appear.
2007 wait_backlight_on(intel_dp
);
2011 pp
= ironlake_get_pp_control(intel_dp
);
2012 pp
|= EDP_BLC_ENABLE
;
2014 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2016 I915_WRITE(pp_ctrl_reg
, pp
);
2017 POSTING_READ(pp_ctrl_reg
);
2019 pps_unlock(intel_dp
);
2022 /* Enable backlight PWM and backlight PP control. */
2023 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2025 if (!is_edp(intel_dp
))
2028 DRM_DEBUG_KMS("\n");
2030 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2031 _intel_edp_backlight_on(intel_dp
);
2034 /* Disable backlight in the panel power control. */
2035 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2037 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2042 if (!is_edp(intel_dp
))
2047 pp
= ironlake_get_pp_control(intel_dp
);
2048 pp
&= ~EDP_BLC_ENABLE
;
2050 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2052 I915_WRITE(pp_ctrl_reg
, pp
);
2053 POSTING_READ(pp_ctrl_reg
);
2055 pps_unlock(intel_dp
);
2057 intel_dp
->last_backlight_off
= jiffies
;
2058 edp_wait_backlight_off(intel_dp
);
2061 /* Disable backlight PP control and backlight PWM. */
2062 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2064 if (!is_edp(intel_dp
))
2067 DRM_DEBUG_KMS("\n");
2069 _intel_edp_backlight_off(intel_dp
);
2070 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2074 * Hook for controlling the panel power control backlight through the bl_power
2075 * sysfs attribute. Take care to handle multiple calls.
2077 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2080 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2084 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2085 pps_unlock(intel_dp
);
2087 if (is_enabled
== enable
)
2090 DRM_DEBUG_KMS("panel power control backlight %s\n",
2091 enable
? "enable" : "disable");
2094 _intel_edp_backlight_on(intel_dp
);
2096 _intel_edp_backlight_off(intel_dp
);
2099 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2101 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2102 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2103 struct drm_device
*dev
= crtc
->dev
;
2104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2107 assert_pipe_disabled(dev_priv
,
2108 to_intel_crtc(crtc
)->pipe
);
2110 DRM_DEBUG_KMS("\n");
2111 dpa_ctl
= I915_READ(DP_A
);
2112 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
2113 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2115 /* We don't adjust intel_dp->DP while tearing down the link, to
2116 * facilitate link retraining (e.g. after hotplug). Hence clear all
2117 * enable bits here to ensure that we don't enable too much. */
2118 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
2119 intel_dp
->DP
|= DP_PLL_ENABLE
;
2120 I915_WRITE(DP_A
, intel_dp
->DP
);
2125 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2127 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2128 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2129 struct drm_device
*dev
= crtc
->dev
;
2130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2133 assert_pipe_disabled(dev_priv
,
2134 to_intel_crtc(crtc
)->pipe
);
2136 dpa_ctl
= I915_READ(DP_A
);
2137 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
2138 "dp pll off, should be on\n");
2139 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2141 /* We can't rely on the value tracked for the DP register in
2142 * intel_dp->DP because link_down must not change that (otherwise link
2143 * re-training will fail. */
2144 dpa_ctl
&= ~DP_PLL_ENABLE
;
2145 I915_WRITE(DP_A
, dpa_ctl
);
2150 /* If the sink supports it, try to set the power state appropriately */
2151 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2155 /* Should have a valid DPCD by this point */
2156 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2159 if (mode
!= DRM_MODE_DPMS_ON
) {
2160 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2164 * When turning on, we need to retry for 1ms to give the sink
2167 for (i
= 0; i
< 3; i
++) {
2168 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2177 DRM_DEBUG_KMS("failed to %s sink power state\n",
2178 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2181 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2184 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2185 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2186 struct drm_device
*dev
= encoder
->base
.dev
;
2187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2188 enum intel_display_power_domain power_domain
;
2191 power_domain
= intel_display_port_power_domain(encoder
);
2192 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2195 tmp
= I915_READ(intel_dp
->output_reg
);
2197 if (!(tmp
& DP_PORT_EN
))
2200 if (IS_GEN7(dev
) && port
== PORT_A
) {
2201 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2202 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2205 for_each_pipe(dev_priv
, p
) {
2206 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2207 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2213 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2214 intel_dp
->output_reg
);
2215 } else if (IS_CHERRYVIEW(dev
)) {
2216 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2218 *pipe
= PORT_TO_PIPE(tmp
);
2224 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2225 struct intel_crtc_state
*pipe_config
)
2227 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2229 struct drm_device
*dev
= encoder
->base
.dev
;
2230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2231 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2232 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2235 tmp
= I915_READ(intel_dp
->output_reg
);
2237 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2239 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2240 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2241 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2242 flags
|= DRM_MODE_FLAG_PHSYNC
;
2244 flags
|= DRM_MODE_FLAG_NHSYNC
;
2246 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2247 flags
|= DRM_MODE_FLAG_PVSYNC
;
2249 flags
|= DRM_MODE_FLAG_NVSYNC
;
2251 if (tmp
& DP_SYNC_HS_HIGH
)
2252 flags
|= DRM_MODE_FLAG_PHSYNC
;
2254 flags
|= DRM_MODE_FLAG_NHSYNC
;
2256 if (tmp
& DP_SYNC_VS_HIGH
)
2257 flags
|= DRM_MODE_FLAG_PVSYNC
;
2259 flags
|= DRM_MODE_FLAG_NVSYNC
;
2262 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2264 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2265 tmp
& DP_COLOR_RANGE_16_235
)
2266 pipe_config
->limited_color_range
= true;
2268 pipe_config
->has_dp_encoder
= true;
2270 intel_dp_get_m_n(crtc
, pipe_config
);
2272 if (port
== PORT_A
) {
2273 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2274 pipe_config
->port_clock
= 162000;
2276 pipe_config
->port_clock
= 270000;
2279 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2280 &pipe_config
->dp_m_n
);
2282 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2283 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2285 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
2287 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2288 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2290 * This is a big fat ugly hack.
2292 * Some machines in UEFI boot mode provide us a VBT that has 18
2293 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2294 * unknown we fail to light up. Yet the same BIOS boots up with
2295 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2296 * max, not what it tells us to use.
2298 * Note: This will still be broken if the eDP panel is not lit
2299 * up by the BIOS, and thus we can't get the mode at module
2302 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2303 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2304 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2308 static void intel_disable_dp(struct intel_encoder
*encoder
)
2310 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2311 struct drm_device
*dev
= encoder
->base
.dev
;
2312 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2314 if (crtc
->config
->has_audio
)
2315 intel_audio_codec_disable(encoder
);
2317 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2318 intel_psr_disable(intel_dp
);
2320 /* Make sure the panel is off before trying to change the mode. But also
2321 * ensure that we have vdd while we switch off the panel. */
2322 intel_edp_panel_vdd_on(intel_dp
);
2323 intel_edp_backlight_off(intel_dp
);
2324 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2325 intel_edp_panel_off(intel_dp
);
2327 /* disable the port before the pipe on g4x */
2328 if (INTEL_INFO(dev
)->gen
< 5)
2329 intel_dp_link_down(intel_dp
);
2332 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2334 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2335 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2337 intel_dp_link_down(intel_dp
);
2339 ironlake_edp_pll_off(intel_dp
);
2342 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2344 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2346 intel_dp_link_down(intel_dp
);
2349 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2351 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2352 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2353 struct drm_device
*dev
= encoder
->base
.dev
;
2354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2355 struct intel_crtc
*intel_crtc
=
2356 to_intel_crtc(encoder
->base
.crtc
);
2357 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2358 enum pipe pipe
= intel_crtc
->pipe
;
2361 intel_dp_link_down(intel_dp
);
2363 mutex_lock(&dev_priv
->sb_lock
);
2365 /* Propagate soft reset to data lane reset */
2366 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2367 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2368 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2370 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2371 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2372 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2374 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2375 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2376 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2378 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2379 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2380 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2382 mutex_unlock(&dev_priv
->sb_lock
);
2386 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2388 uint8_t dp_train_pat
)
2390 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2391 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2393 enum port port
= intel_dig_port
->port
;
2396 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2398 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2399 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2401 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2403 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2404 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2405 case DP_TRAINING_PATTERN_DISABLE
:
2406 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2409 case DP_TRAINING_PATTERN_1
:
2410 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2412 case DP_TRAINING_PATTERN_2
:
2413 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2415 case DP_TRAINING_PATTERN_3
:
2416 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2419 I915_WRITE(DP_TP_CTL(port
), temp
);
2421 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2422 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2423 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2425 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2426 case DP_TRAINING_PATTERN_DISABLE
:
2427 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2429 case DP_TRAINING_PATTERN_1
:
2430 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2432 case DP_TRAINING_PATTERN_2
:
2433 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2435 case DP_TRAINING_PATTERN_3
:
2436 DRM_ERROR("DP training pattern 3 not supported\n");
2437 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2442 if (IS_CHERRYVIEW(dev
))
2443 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2445 *DP
&= ~DP_LINK_TRAIN_MASK
;
2447 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2448 case DP_TRAINING_PATTERN_DISABLE
:
2449 *DP
|= DP_LINK_TRAIN_OFF
;
2451 case DP_TRAINING_PATTERN_1
:
2452 *DP
|= DP_LINK_TRAIN_PAT_1
;
2454 case DP_TRAINING_PATTERN_2
:
2455 *DP
|= DP_LINK_TRAIN_PAT_2
;
2457 case DP_TRAINING_PATTERN_3
:
2458 if (IS_CHERRYVIEW(dev
)) {
2459 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2461 DRM_ERROR("DP training pattern 3 not supported\n");
2462 *DP
|= DP_LINK_TRAIN_PAT_2
;
2469 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2471 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2474 /* enable with pattern 1 (as per spec) */
2475 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2476 DP_TRAINING_PATTERN_1
);
2478 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2479 POSTING_READ(intel_dp
->output_reg
);
2482 * Magic for VLV/CHV. We _must_ first set up the register
2483 * without actually enabling the port, and then do another
2484 * write to enable the port. Otherwise link training will
2485 * fail when the power sequencer is freshly used for this port.
2487 intel_dp
->DP
|= DP_PORT_EN
;
2489 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2490 POSTING_READ(intel_dp
->output_reg
);
2493 static void intel_enable_dp(struct intel_encoder
*encoder
)
2495 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2496 struct drm_device
*dev
= encoder
->base
.dev
;
2497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2498 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2499 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2500 unsigned int lane_mask
= 0x0;
2502 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2507 if (IS_VALLEYVIEW(dev
))
2508 vlv_init_panel_power_sequencer(intel_dp
);
2510 intel_dp_enable_port(intel_dp
);
2512 edp_panel_vdd_on(intel_dp
);
2513 edp_panel_on(intel_dp
);
2514 edp_panel_vdd_off(intel_dp
, true);
2516 pps_unlock(intel_dp
);
2518 if (IS_VALLEYVIEW(dev
))
2519 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2522 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2523 intel_dp_start_link_train(intel_dp
);
2524 intel_dp_complete_link_train(intel_dp
);
2525 intel_dp_stop_link_train(intel_dp
);
2527 if (crtc
->config
->has_audio
) {
2528 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2529 pipe_name(crtc
->pipe
));
2530 intel_audio_codec_enable(encoder
);
2534 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2536 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2538 intel_enable_dp(encoder
);
2539 intel_edp_backlight_on(intel_dp
);
2542 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2544 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2546 intel_edp_backlight_on(intel_dp
);
2547 intel_psr_enable(intel_dp
);
2550 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2552 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2553 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2555 intel_dp_prepare(encoder
);
2557 /* Only ilk+ has port A */
2558 if (dport
->port
== PORT_A
) {
2559 ironlake_set_pll_cpu_edp(intel_dp
);
2560 ironlake_edp_pll_on(intel_dp
);
2564 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2566 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2567 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2568 enum pipe pipe
= intel_dp
->pps_pipe
;
2569 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2571 edp_panel_vdd_off_sync(intel_dp
);
2574 * VLV seems to get confused when multiple power seqeuencers
2575 * have the same port selected (even if only one has power/vdd
2576 * enabled). The failure manifests as vlv_wait_port_ready() failing
2577 * CHV on the other hand doesn't seem to mind having the same port
2578 * selected in multiple power seqeuencers, but let's clear the
2579 * port select always when logically disconnecting a power sequencer
2582 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2583 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2584 I915_WRITE(pp_on_reg
, 0);
2585 POSTING_READ(pp_on_reg
);
2587 intel_dp
->pps_pipe
= INVALID_PIPE
;
2590 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2594 struct intel_encoder
*encoder
;
2596 lockdep_assert_held(&dev_priv
->pps_mutex
);
2598 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2601 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2603 struct intel_dp
*intel_dp
;
2606 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2609 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2610 port
= dp_to_dig_port(intel_dp
)->port
;
2612 if (intel_dp
->pps_pipe
!= pipe
)
2615 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2616 pipe_name(pipe
), port_name(port
));
2618 WARN(encoder
->connectors_active
,
2619 "stealing pipe %c power sequencer from active eDP port %c\n",
2620 pipe_name(pipe
), port_name(port
));
2622 /* make sure vdd is off before we steal it */
2623 vlv_detach_power_sequencer(intel_dp
);
2627 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2629 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2630 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2631 struct drm_device
*dev
= encoder
->base
.dev
;
2632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2633 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2635 lockdep_assert_held(&dev_priv
->pps_mutex
);
2637 if (!is_edp(intel_dp
))
2640 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2644 * If another power sequencer was being used on this
2645 * port previously make sure to turn off vdd there while
2646 * we still have control of it.
2648 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2649 vlv_detach_power_sequencer(intel_dp
);
2652 * We may be stealing the power
2653 * sequencer from another port.
2655 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2657 /* now it's all ours */
2658 intel_dp
->pps_pipe
= crtc
->pipe
;
2660 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2661 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2663 /* init power sequencer on this pipe and port */
2664 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2665 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2668 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2670 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2671 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2672 struct drm_device
*dev
= encoder
->base
.dev
;
2673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2674 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2675 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2676 int pipe
= intel_crtc
->pipe
;
2679 mutex_lock(&dev_priv
->sb_lock
);
2681 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2688 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2689 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2690 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2692 mutex_unlock(&dev_priv
->sb_lock
);
2694 intel_enable_dp(encoder
);
2697 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2699 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2700 struct drm_device
*dev
= encoder
->base
.dev
;
2701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2702 struct intel_crtc
*intel_crtc
=
2703 to_intel_crtc(encoder
->base
.crtc
);
2704 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2705 int pipe
= intel_crtc
->pipe
;
2707 intel_dp_prepare(encoder
);
2709 /* Program Tx lane resets to default */
2710 mutex_lock(&dev_priv
->sb_lock
);
2711 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2712 DPIO_PCS_TX_LANE2_RESET
|
2713 DPIO_PCS_TX_LANE1_RESET
);
2714 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2715 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2716 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2717 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2718 DPIO_PCS_CLK_SOFT_RESET
);
2720 /* Fix up inter-pair skew failure */
2721 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2722 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2723 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2724 mutex_unlock(&dev_priv
->sb_lock
);
2727 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2729 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2730 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2731 struct drm_device
*dev
= encoder
->base
.dev
;
2732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2733 struct intel_crtc
*intel_crtc
=
2734 to_intel_crtc(encoder
->base
.crtc
);
2735 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2736 int pipe
= intel_crtc
->pipe
;
2737 int data
, i
, stagger
;
2740 mutex_lock(&dev_priv
->sb_lock
);
2742 /* allow hardware to manage TX FIFO reset source */
2743 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2744 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2745 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2747 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2748 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2749 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2751 /* Deassert soft data lane reset*/
2752 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2753 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2754 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2756 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2757 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2758 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2760 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2761 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2762 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2764 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2765 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2766 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2768 /* Program Tx lane latency optimal setting*/
2769 for (i
= 0; i
< 4; i
++) {
2770 /* Set the upar bit */
2771 data
= (i
== 1) ? 0x0 : 0x1;
2772 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2773 data
<< DPIO_UPAR_SHIFT
);
2776 /* Data lane stagger programming */
2777 if (intel_crtc
->config
->port_clock
> 270000)
2779 else if (intel_crtc
->config
->port_clock
> 135000)
2781 else if (intel_crtc
->config
->port_clock
> 67500)
2783 else if (intel_crtc
->config
->port_clock
> 33750)
2788 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2789 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2790 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2792 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2793 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2794 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2796 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW12(ch
),
2797 DPIO_LANESTAGGER_STRAP(stagger
) |
2798 DPIO_LANESTAGGER_STRAP_OVRD
|
2799 DPIO_TX1_STAGGER_MASK(0x1f) |
2800 DPIO_TX1_STAGGER_MULT(6) |
2801 DPIO_TX2_STAGGER_MULT(0));
2803 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW12(ch
),
2804 DPIO_LANESTAGGER_STRAP(stagger
) |
2805 DPIO_LANESTAGGER_STRAP_OVRD
|
2806 DPIO_TX1_STAGGER_MASK(0x1f) |
2807 DPIO_TX1_STAGGER_MULT(7) |
2808 DPIO_TX2_STAGGER_MULT(5));
2810 mutex_unlock(&dev_priv
->sb_lock
);
2812 intel_enable_dp(encoder
);
2815 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2817 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2818 struct drm_device
*dev
= encoder
->base
.dev
;
2819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2820 struct intel_crtc
*intel_crtc
=
2821 to_intel_crtc(encoder
->base
.crtc
);
2822 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2823 enum pipe pipe
= intel_crtc
->pipe
;
2826 intel_dp_prepare(encoder
);
2828 mutex_lock(&dev_priv
->sb_lock
);
2830 /* program left/right clock distribution */
2831 if (pipe
!= PIPE_B
) {
2832 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2833 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2835 val
|= CHV_BUFLEFTENA1_FORCE
;
2837 val
|= CHV_BUFRIGHTENA1_FORCE
;
2838 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2840 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2841 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2843 val
|= CHV_BUFLEFTENA2_FORCE
;
2845 val
|= CHV_BUFRIGHTENA2_FORCE
;
2846 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2849 /* program clock channel usage */
2850 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2851 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2853 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2855 val
|= CHV_PCS_USEDCLKCHANNEL
;
2856 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2858 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2859 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2861 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2863 val
|= CHV_PCS_USEDCLKCHANNEL
;
2864 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2867 * This a a bit weird since generally CL
2868 * matches the pipe, but here we need to
2869 * pick the CL based on the port.
2871 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2873 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2875 val
|= CHV_CMN_USEDCLKCHANNEL
;
2876 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2878 mutex_unlock(&dev_priv
->sb_lock
);
2882 * Native read with retry for link status and receiver capability reads for
2883 * cases where the sink may still be asleep.
2885 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2886 * supposed to retry 3 times per the spec.
2889 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2890 void *buffer
, size_t size
)
2896 * Sometime we just get the same incorrect byte repeated
2897 * over the entire buffer. Doing just one throw away read
2898 * initially seems to "solve" it.
2900 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
2902 for (i
= 0; i
< 3; i
++) {
2903 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2913 * Fetch AUX CH registers 0x202 - 0x207 which contain
2914 * link status information
2917 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2919 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2922 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2925 /* These are source-specific values. */
2927 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2929 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2931 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2933 if (IS_BROXTON(dev
))
2934 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2935 else if (INTEL_INFO(dev
)->gen
>= 9) {
2936 if (dev_priv
->edp_low_vswing
&& port
== PORT_A
)
2937 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2938 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2939 } else if (IS_VALLEYVIEW(dev
))
2940 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2941 else if (IS_GEN7(dev
) && port
== PORT_A
)
2942 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2943 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2944 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2946 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2950 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2952 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2953 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2955 if (INTEL_INFO(dev
)->gen
>= 9) {
2956 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2958 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2960 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2962 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2963 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2964 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2966 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2968 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2969 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2971 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2972 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2973 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2975 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2976 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2978 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2980 } else if (IS_VALLEYVIEW(dev
)) {
2981 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2983 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2984 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2985 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2986 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2987 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2988 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2990 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2992 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2993 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2994 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2995 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2996 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2998 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3000 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3003 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3005 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3007 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3009 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3017 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3019 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3021 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3022 struct intel_crtc
*intel_crtc
=
3023 to_intel_crtc(dport
->base
.base
.crtc
);
3024 unsigned long demph_reg_value
, preemph_reg_value
,
3025 uniqtranscale_reg_value
;
3026 uint8_t train_set
= intel_dp
->train_set
[0];
3027 enum dpio_channel port
= vlv_dport_to_channel(dport
);
3028 int pipe
= intel_crtc
->pipe
;
3030 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3031 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3032 preemph_reg_value
= 0x0004000;
3033 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3035 demph_reg_value
= 0x2B405555;
3036 uniqtranscale_reg_value
= 0x552AB83A;
3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3039 demph_reg_value
= 0x2B404040;
3040 uniqtranscale_reg_value
= 0x5548B83A;
3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3043 demph_reg_value
= 0x2B245555;
3044 uniqtranscale_reg_value
= 0x5560B83A;
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3047 demph_reg_value
= 0x2B405555;
3048 uniqtranscale_reg_value
= 0x5598DA3A;
3054 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3055 preemph_reg_value
= 0x0002000;
3056 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3058 demph_reg_value
= 0x2B404040;
3059 uniqtranscale_reg_value
= 0x5552B83A;
3061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3062 demph_reg_value
= 0x2B404848;
3063 uniqtranscale_reg_value
= 0x5580B83A;
3065 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3066 demph_reg_value
= 0x2B404040;
3067 uniqtranscale_reg_value
= 0x55ADDA3A;
3073 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3074 preemph_reg_value
= 0x0000000;
3075 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3076 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3077 demph_reg_value
= 0x2B305555;
3078 uniqtranscale_reg_value
= 0x5570B83A;
3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3081 demph_reg_value
= 0x2B2B4040;
3082 uniqtranscale_reg_value
= 0x55ADDA3A;
3088 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3089 preemph_reg_value
= 0x0006000;
3090 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3092 demph_reg_value
= 0x1B405555;
3093 uniqtranscale_reg_value
= 0x55ADDA3A;
3103 mutex_lock(&dev_priv
->sb_lock
);
3104 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3105 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3106 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3107 uniqtranscale_reg_value
);
3108 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3109 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3110 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3111 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3112 mutex_unlock(&dev_priv
->sb_lock
);
3117 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3119 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3121 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3122 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3123 u32 deemph_reg_value
, margin_reg_value
, val
;
3124 uint8_t train_set
= intel_dp
->train_set
[0];
3125 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3126 enum pipe pipe
= intel_crtc
->pipe
;
3129 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3130 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3131 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3133 deemph_reg_value
= 128;
3134 margin_reg_value
= 52;
3136 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3137 deemph_reg_value
= 128;
3138 margin_reg_value
= 77;
3140 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3141 deemph_reg_value
= 128;
3142 margin_reg_value
= 102;
3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3145 deemph_reg_value
= 128;
3146 margin_reg_value
= 154;
3147 /* FIXME extra to set for 1200 */
3153 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3154 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3155 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3156 deemph_reg_value
= 85;
3157 margin_reg_value
= 78;
3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3160 deemph_reg_value
= 85;
3161 margin_reg_value
= 116;
3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3164 deemph_reg_value
= 85;
3165 margin_reg_value
= 154;
3171 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3172 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3174 deemph_reg_value
= 64;
3175 margin_reg_value
= 104;
3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3178 deemph_reg_value
= 64;
3179 margin_reg_value
= 154;
3185 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3186 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3188 deemph_reg_value
= 43;
3189 margin_reg_value
= 154;
3199 mutex_lock(&dev_priv
->sb_lock
);
3201 /* Clear calc init */
3202 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3203 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3204 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3205 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3206 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3208 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3209 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3210 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3211 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3212 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3214 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3215 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3216 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3217 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3219 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3220 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3221 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3222 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3224 /* Program swing deemph */
3225 for (i
= 0; i
< 4; i
++) {
3226 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3227 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3228 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3229 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3232 /* Program swing margin */
3233 for (i
= 0; i
< 4; i
++) {
3234 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3235 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3236 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3237 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3240 /* Disable unique transition scale */
3241 for (i
= 0; i
< 4; i
++) {
3242 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3243 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3244 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3247 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3248 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3249 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3250 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3253 * The document said it needs to set bit 27 for ch0 and bit 26
3254 * for ch1. Might be a typo in the doc.
3255 * For now, for this unique transition scale selection, set bit
3256 * 27 for ch0 and ch1.
3258 for (i
= 0; i
< 4; i
++) {
3259 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3260 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3261 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3264 for (i
= 0; i
< 4; i
++) {
3265 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3266 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3267 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3268 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3272 /* Start swing calculation */
3273 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3274 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3275 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3277 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3278 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3279 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3282 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3283 val
|= DPIO_LRC_BYPASS
;
3284 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3286 mutex_unlock(&dev_priv
->sb_lock
);
3292 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3293 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3298 uint8_t voltage_max
;
3299 uint8_t preemph_max
;
3301 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3302 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3303 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3311 voltage_max
= intel_dp_voltage_max(intel_dp
);
3312 if (v
>= voltage_max
)
3313 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3315 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3316 if (p
>= preemph_max
)
3317 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3319 for (lane
= 0; lane
< 4; lane
++)
3320 intel_dp
->train_set
[lane
] = v
| p
;
3324 gen4_signal_levels(uint8_t train_set
)
3326 uint32_t signal_levels
= 0;
3328 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3331 signal_levels
|= DP_VOLTAGE_0_4
;
3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3334 signal_levels
|= DP_VOLTAGE_0_6
;
3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3337 signal_levels
|= DP_VOLTAGE_0_8
;
3339 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3340 signal_levels
|= DP_VOLTAGE_1_2
;
3343 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3344 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3346 signal_levels
|= DP_PRE_EMPHASIS_0
;
3348 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3349 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3351 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3352 signal_levels
|= DP_PRE_EMPHASIS_6
;
3354 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3355 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3358 return signal_levels
;
3361 /* Gen6's DP voltage swing and pre-emphasis control */
3363 gen6_edp_signal_levels(uint8_t train_set
)
3365 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3366 DP_TRAIN_PRE_EMPHASIS_MASK
);
3367 switch (signal_levels
) {
3368 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3369 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3370 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3371 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3372 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3373 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3374 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3375 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3376 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3377 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3378 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3379 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3381 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3383 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3384 "0x%x\n", signal_levels
);
3385 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3389 /* Gen7's DP voltage swing and pre-emphasis control */
3391 gen7_edp_signal_levels(uint8_t train_set
)
3393 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3394 DP_TRAIN_PRE_EMPHASIS_MASK
);
3395 switch (signal_levels
) {
3396 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3397 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3398 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3399 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3400 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3401 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3403 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3404 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3405 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3406 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3408 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3409 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3411 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3414 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3415 "0x%x\n", signal_levels
);
3416 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3420 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3422 hsw_signal_levels(uint8_t train_set
)
3424 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3425 DP_TRAIN_PRE_EMPHASIS_MASK
);
3426 switch (signal_levels
) {
3427 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3428 return DDI_BUF_TRANS_SELECT(0);
3429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3430 return DDI_BUF_TRANS_SELECT(1);
3431 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3432 return DDI_BUF_TRANS_SELECT(2);
3433 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3434 return DDI_BUF_TRANS_SELECT(3);
3436 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3437 return DDI_BUF_TRANS_SELECT(4);
3438 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3439 return DDI_BUF_TRANS_SELECT(5);
3440 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3441 return DDI_BUF_TRANS_SELECT(6);
3443 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3444 return DDI_BUF_TRANS_SELECT(7);
3445 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3446 return DDI_BUF_TRANS_SELECT(8);
3448 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3449 return DDI_BUF_TRANS_SELECT(9);
3451 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3452 "0x%x\n", signal_levels
);
3453 return DDI_BUF_TRANS_SELECT(0);
3457 static void bxt_signal_levels(struct intel_dp
*intel_dp
)
3459 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3460 enum port port
= dport
->port
;
3461 struct drm_device
*dev
= dport
->base
.base
.dev
;
3462 struct intel_encoder
*encoder
= &dport
->base
;
3463 uint8_t train_set
= intel_dp
->train_set
[0];
3466 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3467 DP_TRAIN_PRE_EMPHASIS_MASK
);
3468 switch (signal_levels
) {
3470 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n");
3471 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3474 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3477 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3480 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3483 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3486 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3489 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3492 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3495 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3498 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3503 bxt_ddi_vswing_sequence(dev
, level
, port
, encoder
->type
);
3506 /* Properly updates "DP" with the correct signal levels. */
3508 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3510 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3511 enum port port
= intel_dig_port
->port
;
3512 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3513 uint32_t signal_levels
, mask
;
3514 uint8_t train_set
= intel_dp
->train_set
[0];
3516 if (IS_BROXTON(dev
)) {
3518 bxt_signal_levels(intel_dp
);
3520 } else if (HAS_DDI(dev
)) {
3521 signal_levels
= hsw_signal_levels(train_set
);
3522 mask
= DDI_BUF_EMP_MASK
;
3523 } else if (IS_CHERRYVIEW(dev
)) {
3524 signal_levels
= chv_signal_levels(intel_dp
);
3526 } else if (IS_VALLEYVIEW(dev
)) {
3527 signal_levels
= vlv_signal_levels(intel_dp
);
3529 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3530 signal_levels
= gen7_edp_signal_levels(train_set
);
3531 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3532 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3533 signal_levels
= gen6_edp_signal_levels(train_set
);
3534 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3536 signal_levels
= gen4_signal_levels(train_set
);
3537 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3541 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3543 DRM_DEBUG_KMS("Using vswing level %d\n",
3544 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3545 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3546 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3547 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3549 *DP
= (*DP
& ~mask
) | signal_levels
;
3553 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3555 uint8_t dp_train_pat
)
3557 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3558 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3560 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3563 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3565 I915_WRITE(intel_dp
->output_reg
, *DP
);
3566 POSTING_READ(intel_dp
->output_reg
);
3568 buf
[0] = dp_train_pat
;
3569 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3570 DP_TRAINING_PATTERN_DISABLE
) {
3571 /* don't write DP_TRAINING_LANEx_SET on disable */
3574 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3575 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3576 len
= intel_dp
->lane_count
+ 1;
3579 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3586 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3587 uint8_t dp_train_pat
)
3589 if (!intel_dp
->train_set_valid
)
3590 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3591 intel_dp_set_signal_levels(intel_dp
, DP
);
3592 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3596 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3597 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3599 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3600 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3604 intel_get_adjust_train(intel_dp
, link_status
);
3605 intel_dp_set_signal_levels(intel_dp
, DP
);
3607 I915_WRITE(intel_dp
->output_reg
, *DP
);
3608 POSTING_READ(intel_dp
->output_reg
);
3610 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3611 intel_dp
->train_set
, intel_dp
->lane_count
);
3613 return ret
== intel_dp
->lane_count
;
3616 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3618 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3619 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3621 enum port port
= intel_dig_port
->port
;
3627 val
= I915_READ(DP_TP_CTL(port
));
3628 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3629 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3630 I915_WRITE(DP_TP_CTL(port
), val
);
3633 * On PORT_A we can have only eDP in SST mode. There the only reason
3634 * we need to set idle transmission mode is to work around a HW issue
3635 * where we enable the pipe while not in idle link-training mode.
3636 * In this case there is requirement to wait for a minimum number of
3637 * idle patterns to be sent.
3642 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3644 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3647 /* Enable corresponding port and start training pattern 1 */
3649 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3651 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3652 struct drm_device
*dev
= encoder
->dev
;
3655 int voltage_tries
, loop_tries
;
3656 uint32_t DP
= intel_dp
->DP
;
3657 uint8_t link_config
[2];
3660 intel_ddi_prepare_link_retrain(encoder
);
3662 /* Write the link configuration data */
3663 link_config
[0] = intel_dp
->link_bw
;
3664 link_config
[1] = intel_dp
->lane_count
;
3665 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3666 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3667 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3668 if (intel_dp
->num_sink_rates
)
3669 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_RATE_SET
,
3670 &intel_dp
->rate_select
, 1);
3673 link_config
[1] = DP_SET_ANSI_8B10B
;
3674 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3678 /* clock recovery */
3679 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3680 DP_TRAINING_PATTERN_1
|
3681 DP_LINK_SCRAMBLING_DISABLE
)) {
3682 DRM_ERROR("failed to enable link training\n");
3690 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3692 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3693 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3694 DRM_ERROR("failed to get link status\n");
3698 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3699 DRM_DEBUG_KMS("clock recovery OK\n");
3704 * if we used previously trained voltage and pre-emphasis values
3705 * and we don't get clock recovery, reset link training values
3707 if (intel_dp
->train_set_valid
) {
3708 DRM_DEBUG_KMS("clock recovery not ok, reset");
3709 /* clear the flag as we are not reusing train set */
3710 intel_dp
->train_set_valid
= false;
3711 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3712 DP_TRAINING_PATTERN_1
|
3713 DP_LINK_SCRAMBLING_DISABLE
)) {
3714 DRM_ERROR("failed to enable link training\n");
3720 /* Check to see if we've tried the max voltage */
3721 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3722 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3724 if (i
== intel_dp
->lane_count
) {
3726 if (loop_tries
== 5) {
3727 DRM_ERROR("too many full retries, give up\n");
3730 intel_dp_reset_link_train(intel_dp
, &DP
,
3731 DP_TRAINING_PATTERN_1
|
3732 DP_LINK_SCRAMBLING_DISABLE
);
3737 /* Check to see if we've tried the same voltage 5 times */
3738 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3740 if (voltage_tries
== 5) {
3741 DRM_ERROR("too many voltage retries, give up\n");
3746 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3748 /* Update training set as requested by target */
3749 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3750 DRM_ERROR("failed to update link training\n");
3759 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3761 bool channel_eq
= false;
3762 int tries
, cr_tries
;
3763 uint32_t DP
= intel_dp
->DP
;
3764 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3766 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3767 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3768 training_pattern
= DP_TRAINING_PATTERN_3
;
3770 /* channel equalization */
3771 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3773 DP_LINK_SCRAMBLING_DISABLE
)) {
3774 DRM_ERROR("failed to start channel equalization\n");
3782 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3785 DRM_ERROR("failed to train DP, aborting\n");
3789 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3790 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3791 DRM_ERROR("failed to get link status\n");
3795 /* Make sure clock is still ok */
3796 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3797 intel_dp
->train_set_valid
= false;
3798 intel_dp_start_link_train(intel_dp
);
3799 intel_dp_set_link_train(intel_dp
, &DP
,
3801 DP_LINK_SCRAMBLING_DISABLE
);
3806 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3811 /* Try 5 times, then try clock recovery if that fails */
3813 intel_dp
->train_set_valid
= false;
3814 intel_dp_start_link_train(intel_dp
);
3815 intel_dp_set_link_train(intel_dp
, &DP
,
3817 DP_LINK_SCRAMBLING_DISABLE
);
3823 /* Update training set as requested by target */
3824 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3825 DRM_ERROR("failed to update link training\n");
3831 intel_dp_set_idle_link_train(intel_dp
);
3836 intel_dp
->train_set_valid
= true;
3837 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3841 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3843 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3844 DP_TRAINING_PATTERN_DISABLE
);
3848 intel_dp_link_down(struct intel_dp
*intel_dp
)
3850 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3851 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3852 enum port port
= intel_dig_port
->port
;
3853 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3855 uint32_t DP
= intel_dp
->DP
;
3857 if (WARN_ON(HAS_DDI(dev
)))
3860 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3863 DRM_DEBUG_KMS("\n");
3865 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3866 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3867 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3868 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3870 if (IS_CHERRYVIEW(dev
))
3871 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3873 DP
&= ~DP_LINK_TRAIN_MASK
;
3874 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3876 I915_WRITE(intel_dp
->output_reg
, DP
);
3877 POSTING_READ(intel_dp
->output_reg
);
3879 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3880 I915_WRITE(intel_dp
->output_reg
, DP
);
3881 POSTING_READ(intel_dp
->output_reg
);
3884 * HW workaround for IBX, we need to move the port
3885 * to transcoder A after disabling it to allow the
3886 * matching HDMI port to be enabled on transcoder A.
3888 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3889 /* always enable with pattern 1 (as per spec) */
3890 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3891 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3892 I915_WRITE(intel_dp
->output_reg
, DP
);
3893 POSTING_READ(intel_dp
->output_reg
);
3896 I915_WRITE(intel_dp
->output_reg
, DP
);
3897 POSTING_READ(intel_dp
->output_reg
);
3900 msleep(intel_dp
->panel_power_down_delay
);
3904 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3906 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3907 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3911 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3912 sizeof(intel_dp
->dpcd
)) < 0)
3913 return false; /* aux transfer failed */
3915 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3917 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3918 return false; /* DPCD not present */
3920 /* Check if the panel supports PSR */
3921 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3922 if (is_edp(intel_dp
)) {
3923 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3925 sizeof(intel_dp
->psr_dpcd
));
3926 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3927 dev_priv
->psr
.sink_support
= true;
3928 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3931 if (INTEL_INFO(dev
)->gen
>= 9 &&
3932 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3933 uint8_t frame_sync_cap
;
3935 dev_priv
->psr
.sink_support
= true;
3936 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3937 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3938 &frame_sync_cap
, 1);
3939 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3940 /* PSR2 needs frame sync as well */
3941 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3942 DRM_DEBUG_KMS("PSR2 %s on sink",
3943 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3947 /* Training Pattern 3 support, both source and sink */
3948 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3949 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
&&
3950 (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)) {
3951 intel_dp
->use_tps3
= true;
3952 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3954 intel_dp
->use_tps3
= false;
3956 /* Intermediate frequency support */
3957 if (is_edp(intel_dp
) &&
3958 (intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3959 (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_EDP_DPCD_REV
, &rev
, 1) == 1) &&
3960 (rev
>= 0x03)) { /* eDp v1.4 or higher */
3961 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3964 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3965 DP_SUPPORTED_LINK_RATES
,
3967 sizeof(sink_rates
));
3969 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3970 int val
= le16_to_cpu(sink_rates
[i
]);
3975 /* Value read is in kHz while drm clock is saved in deca-kHz */
3976 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3978 intel_dp
->num_sink_rates
= i
;
3981 intel_dp_print_rates(intel_dp
);
3983 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3984 DP_DWN_STRM_PORT_PRESENT
))
3985 return true; /* native DP sink */
3987 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3988 return true; /* no per-port downstream info */
3990 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3991 intel_dp
->downstream_ports
,
3992 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3993 return false; /* downstream port status fetch failed */
3999 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
4003 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
4006 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
4007 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
4008 buf
[0], buf
[1], buf
[2]);
4010 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
4011 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
4012 buf
[0], buf
[1], buf
[2]);
4016 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
4020 if (!intel_dp
->can_mst
)
4023 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
4026 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
4027 if (buf
[0] & DP_MST_CAP
) {
4028 DRM_DEBUG_KMS("Sink is MST capable\n");
4029 intel_dp
->is_mst
= true;
4031 DRM_DEBUG_KMS("Sink is not MST capable\n");
4032 intel_dp
->is_mst
= false;
4036 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4037 return intel_dp
->is_mst
;
4040 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
4042 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4043 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4044 struct intel_crtc
*intel_crtc
=
4045 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
4051 hsw_disable_ips(intel_crtc
);
4053 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0) {
4058 if (!(buf
& DP_TEST_CRC_SUPPORTED
)) {
4063 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
4068 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4069 buf
| DP_TEST_SINK_START
) < 0) {
4074 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0) {
4079 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
4082 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4083 DP_TEST_SINK_MISC
, &buf
) < 0) {
4087 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4088 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
4090 if (attempts
== 0) {
4091 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4096 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
4101 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
4105 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4106 buf
& ~DP_TEST_SINK_START
) < 0) {
4111 hsw_enable_ips(intel_crtc
);
4116 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4118 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4119 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4120 sink_irq_vector
, 1) == 1;
4124 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4128 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4130 sink_irq_vector
, 14);
4137 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4139 uint8_t test_result
= DP_TEST_ACK
;
4143 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4145 uint8_t test_result
= DP_TEST_NAK
;
4149 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4151 uint8_t test_result
= DP_TEST_NAK
;
4152 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4153 struct drm_connector
*connector
= &intel_connector
->base
;
4155 if (intel_connector
->detect_edid
== NULL
||
4156 connector
->edid_corrupt
||
4157 intel_dp
->aux
.i2c_defer_count
> 6) {
4158 /* Check EDID read for NACKs, DEFERs and corruption
4159 * (DP CTS 1.2 Core r1.1)
4160 * 4.2.2.4 : Failed EDID read, I2C_NAK
4161 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4162 * 4.2.2.6 : EDID corruption detected
4163 * Use failsafe mode for all cases
4165 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4166 intel_dp
->aux
.i2c_defer_count
> 0)
4167 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4168 intel_dp
->aux
.i2c_nack_count
,
4169 intel_dp
->aux
.i2c_defer_count
);
4170 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
4172 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
4173 DP_TEST_EDID_CHECKSUM
,
4174 &intel_connector
->detect_edid
->checksum
,
4176 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4178 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4179 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
4182 /* Set test active flag here so userspace doesn't interrupt things */
4183 intel_dp
->compliance_test_active
= 1;
4188 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4190 uint8_t test_result
= DP_TEST_NAK
;
4194 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4196 uint8_t response
= DP_TEST_NAK
;
4200 intel_dp
->compliance_test_active
= 0;
4201 intel_dp
->compliance_test_type
= 0;
4202 intel_dp
->compliance_test_data
= 0;
4204 intel_dp
->aux
.i2c_nack_count
= 0;
4205 intel_dp
->aux
.i2c_defer_count
= 0;
4207 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
4209 DRM_DEBUG_KMS("Could not read test request from sink\n");
4214 case DP_TEST_LINK_TRAINING
:
4215 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4216 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
4217 response
= intel_dp_autotest_link_training(intel_dp
);
4219 case DP_TEST_LINK_VIDEO_PATTERN
:
4220 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4221 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
4222 response
= intel_dp_autotest_video_pattern(intel_dp
);
4224 case DP_TEST_LINK_EDID_READ
:
4225 DRM_DEBUG_KMS("EDID test requested\n");
4226 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
4227 response
= intel_dp_autotest_edid(intel_dp
);
4229 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4230 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4231 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
4232 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4235 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
4240 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
4244 DRM_DEBUG_KMS("Could not write test response to sink\n");
4248 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4252 if (intel_dp
->is_mst
) {
4257 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4261 /* check link status - esi[10] = 0x200c */
4262 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4263 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4264 intel_dp_start_link_train(intel_dp
);
4265 intel_dp_complete_link_train(intel_dp
);
4266 intel_dp_stop_link_train(intel_dp
);
4269 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4270 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4273 for (retry
= 0; retry
< 3; retry
++) {
4275 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4276 DP_SINK_COUNT_ESI
+1,
4283 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4285 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4293 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4294 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4295 intel_dp
->is_mst
= false;
4296 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4297 /* send a hotplug event */
4298 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4305 * According to DP spec
4308 * 2. Configure link according to Receiver Capabilities
4309 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4310 * 4. Check link status on receipt of hot-plug interrupt
4313 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4315 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4316 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4318 u8 link_status
[DP_LINK_STATUS_SIZE
];
4320 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4322 if (!intel_encoder
->connectors_active
)
4325 if (WARN_ON(!intel_encoder
->base
.crtc
))
4328 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4331 /* Try to read receiver status if the link appears to be up */
4332 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4336 /* Now read the DPCD to see if it's actually running */
4337 if (!intel_dp_get_dpcd(intel_dp
)) {
4341 /* Try to read the source of the interrupt */
4342 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4343 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4344 /* Clear interrupt source */
4345 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4346 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4349 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4350 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4351 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4352 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4355 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4356 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4357 intel_encoder
->base
.name
);
4358 intel_dp_start_link_train(intel_dp
);
4359 intel_dp_complete_link_train(intel_dp
);
4360 intel_dp_stop_link_train(intel_dp
);
4364 /* XXX this is probably wrong for multiple downstream ports */
4365 static enum drm_connector_status
4366 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4368 uint8_t *dpcd
= intel_dp
->dpcd
;
4371 if (!intel_dp_get_dpcd(intel_dp
))
4372 return connector_status_disconnected
;
4374 /* if there's no downstream port, we're done */
4375 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4376 return connector_status_connected
;
4378 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4379 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4380 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4383 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4385 return connector_status_unknown
;
4387 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4388 : connector_status_disconnected
;
4391 /* If no HPD, poke DDC gently */
4392 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4393 return connector_status_connected
;
4395 /* Well we tried, say unknown for unreliable port types */
4396 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4397 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4398 if (type
== DP_DS_PORT_TYPE_VGA
||
4399 type
== DP_DS_PORT_TYPE_NON_EDID
)
4400 return connector_status_unknown
;
4402 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4403 DP_DWN_STRM_PORT_TYPE_MASK
;
4404 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4405 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4406 return connector_status_unknown
;
4409 /* Anything else is out of spec, warn and ignore */
4410 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4411 return connector_status_disconnected
;
4414 static enum drm_connector_status
4415 edp_detect(struct intel_dp
*intel_dp
)
4417 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4418 enum drm_connector_status status
;
4420 status
= intel_panel_detect(dev
);
4421 if (status
== connector_status_unknown
)
4422 status
= connector_status_connected
;
4427 static enum drm_connector_status
4428 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4430 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4432 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4434 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4435 return connector_status_disconnected
;
4437 return intel_dp_detect_dpcd(intel_dp
);
4440 static int g4x_digital_port_connected(struct drm_device
*dev
,
4441 struct intel_digital_port
*intel_dig_port
)
4443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4446 if (IS_VALLEYVIEW(dev
)) {
4447 switch (intel_dig_port
->port
) {
4449 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4452 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4455 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4461 switch (intel_dig_port
->port
) {
4463 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4466 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4469 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4476 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4481 static enum drm_connector_status
4482 g4x_dp_detect(struct intel_dp
*intel_dp
)
4484 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4485 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4488 /* Can't disconnect eDP, but you can close the lid... */
4489 if (is_edp(intel_dp
)) {
4490 enum drm_connector_status status
;
4492 status
= intel_panel_detect(dev
);
4493 if (status
== connector_status_unknown
)
4494 status
= connector_status_connected
;
4498 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4500 return connector_status_unknown
;
4502 return connector_status_disconnected
;
4504 return intel_dp_detect_dpcd(intel_dp
);
4507 static struct edid
*
4508 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4510 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4512 /* use cached edid if we have one */
4513 if (intel_connector
->edid
) {
4515 if (IS_ERR(intel_connector
->edid
))
4518 return drm_edid_duplicate(intel_connector
->edid
);
4520 return drm_get_edid(&intel_connector
->base
,
4521 &intel_dp
->aux
.ddc
);
4525 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4527 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4530 edid
= intel_dp_get_edid(intel_dp
);
4531 intel_connector
->detect_edid
= edid
;
4533 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4534 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4536 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4540 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4542 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4544 kfree(intel_connector
->detect_edid
);
4545 intel_connector
->detect_edid
= NULL
;
4547 intel_dp
->has_audio
= false;
4550 static enum intel_display_power_domain
4551 intel_dp_power_get(struct intel_dp
*dp
)
4553 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4554 enum intel_display_power_domain power_domain
;
4556 power_domain
= intel_display_port_power_domain(encoder
);
4557 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4559 return power_domain
;
4563 intel_dp_power_put(struct intel_dp
*dp
,
4564 enum intel_display_power_domain power_domain
)
4566 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4567 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4570 static enum drm_connector_status
4571 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4573 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4574 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4575 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4576 struct drm_device
*dev
= connector
->dev
;
4577 enum drm_connector_status status
;
4578 enum intel_display_power_domain power_domain
;
4582 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4583 connector
->base
.id
, connector
->name
);
4584 intel_dp_unset_edid(intel_dp
);
4586 if (intel_dp
->is_mst
) {
4587 /* MST devices are disconnected from a monitor POV */
4588 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4589 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4590 return connector_status_disconnected
;
4593 power_domain
= intel_dp_power_get(intel_dp
);
4595 /* Can't disconnect eDP, but you can close the lid... */
4596 if (is_edp(intel_dp
))
4597 status
= edp_detect(intel_dp
);
4598 else if (HAS_PCH_SPLIT(dev
))
4599 status
= ironlake_dp_detect(intel_dp
);
4601 status
= g4x_dp_detect(intel_dp
);
4602 if (status
!= connector_status_connected
)
4605 intel_dp_probe_oui(intel_dp
);
4607 ret
= intel_dp_probe_mst(intel_dp
);
4609 /* if we are in MST mode then this connector
4610 won't appear connected or have anything with EDID on it */
4611 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4612 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4613 status
= connector_status_disconnected
;
4617 intel_dp_set_edid(intel_dp
);
4619 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4620 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4621 status
= connector_status_connected
;
4623 /* Try to read the source of the interrupt */
4624 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4625 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4626 /* Clear interrupt source */
4627 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4628 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4631 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4632 intel_dp_handle_test_request(intel_dp
);
4633 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4634 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4638 intel_dp_power_put(intel_dp
, power_domain
);
4643 intel_dp_force(struct drm_connector
*connector
)
4645 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4646 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4647 enum intel_display_power_domain power_domain
;
4649 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4650 connector
->base
.id
, connector
->name
);
4651 intel_dp_unset_edid(intel_dp
);
4653 if (connector
->status
!= connector_status_connected
)
4656 power_domain
= intel_dp_power_get(intel_dp
);
4658 intel_dp_set_edid(intel_dp
);
4660 intel_dp_power_put(intel_dp
, power_domain
);
4662 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4663 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4666 static int intel_dp_get_modes(struct drm_connector
*connector
)
4668 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4671 edid
= intel_connector
->detect_edid
;
4673 int ret
= intel_connector_update_modes(connector
, edid
);
4678 /* if eDP has no EDID, fall back to fixed mode */
4679 if (is_edp(intel_attached_dp(connector
)) &&
4680 intel_connector
->panel
.fixed_mode
) {
4681 struct drm_display_mode
*mode
;
4683 mode
= drm_mode_duplicate(connector
->dev
,
4684 intel_connector
->panel
.fixed_mode
);
4686 drm_mode_probed_add(connector
, mode
);
4695 intel_dp_detect_audio(struct drm_connector
*connector
)
4697 bool has_audio
= false;
4700 edid
= to_intel_connector(connector
)->detect_edid
;
4702 has_audio
= drm_detect_monitor_audio(edid
);
4708 intel_dp_set_property(struct drm_connector
*connector
,
4709 struct drm_property
*property
,
4712 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4713 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4714 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4715 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4718 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4722 if (property
== dev_priv
->force_audio_property
) {
4726 if (i
== intel_dp
->force_audio
)
4729 intel_dp
->force_audio
= i
;
4731 if (i
== HDMI_AUDIO_AUTO
)
4732 has_audio
= intel_dp_detect_audio(connector
);
4734 has_audio
= (i
== HDMI_AUDIO_ON
);
4736 if (has_audio
== intel_dp
->has_audio
)
4739 intel_dp
->has_audio
= has_audio
;
4743 if (property
== dev_priv
->broadcast_rgb_property
) {
4744 bool old_auto
= intel_dp
->color_range_auto
;
4745 uint32_t old_range
= intel_dp
->color_range
;
4748 case INTEL_BROADCAST_RGB_AUTO
:
4749 intel_dp
->color_range_auto
= true;
4751 case INTEL_BROADCAST_RGB_FULL
:
4752 intel_dp
->color_range_auto
= false;
4753 intel_dp
->color_range
= 0;
4755 case INTEL_BROADCAST_RGB_LIMITED
:
4756 intel_dp
->color_range_auto
= false;
4757 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4763 if (old_auto
== intel_dp
->color_range_auto
&&
4764 old_range
== intel_dp
->color_range
)
4770 if (is_edp(intel_dp
) &&
4771 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4772 if (val
== DRM_MODE_SCALE_NONE
) {
4773 DRM_DEBUG_KMS("no scaling not supported\n");
4777 if (intel_connector
->panel
.fitting_mode
== val
) {
4778 /* the eDP scaling property is not changed */
4781 intel_connector
->panel
.fitting_mode
= val
;
4789 if (intel_encoder
->base
.crtc
)
4790 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4796 intel_dp_connector_destroy(struct drm_connector
*connector
)
4798 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4800 kfree(intel_connector
->detect_edid
);
4802 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4803 kfree(intel_connector
->edid
);
4805 /* Can't call is_edp() since the encoder may have been destroyed
4807 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4808 intel_panel_fini(&intel_connector
->panel
);
4810 drm_connector_cleanup(connector
);
4814 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4816 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4817 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4819 drm_dp_aux_unregister(&intel_dp
->aux
);
4820 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4821 if (is_edp(intel_dp
)) {
4822 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4824 * vdd might still be enabled do to the delayed vdd off.
4825 * Make sure vdd is actually turned off here.
4828 edp_panel_vdd_off_sync(intel_dp
);
4829 pps_unlock(intel_dp
);
4831 if (intel_dp
->edp_notifier
.notifier_call
) {
4832 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4833 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4836 drm_encoder_cleanup(encoder
);
4837 kfree(intel_dig_port
);
4840 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4842 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4844 if (!is_edp(intel_dp
))
4848 * vdd might still be enabled do to the delayed vdd off.
4849 * Make sure vdd is actually turned off here.
4851 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4853 edp_panel_vdd_off_sync(intel_dp
);
4854 pps_unlock(intel_dp
);
4857 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4859 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4860 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4862 enum intel_display_power_domain power_domain
;
4864 lockdep_assert_held(&dev_priv
->pps_mutex
);
4866 if (!edp_have_panel_vdd(intel_dp
))
4870 * The VDD bit needs a power domain reference, so if the bit is
4871 * already enabled when we boot or resume, grab this reference and
4872 * schedule a vdd off, so we don't hold on to the reference
4875 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4876 power_domain
= intel_display_port_power_domain(&intel_dig_port
->base
);
4877 intel_display_power_get(dev_priv
, power_domain
);
4879 edp_panel_vdd_schedule_off(intel_dp
);
4882 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4884 struct intel_dp
*intel_dp
;
4886 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4889 intel_dp
= enc_to_intel_dp(encoder
);
4894 * Read out the current power sequencer assignment,
4895 * in case the BIOS did something with it.
4897 if (IS_VALLEYVIEW(encoder
->dev
))
4898 vlv_initial_power_sequencer_setup(intel_dp
);
4900 intel_edp_panel_vdd_sanitize(intel_dp
);
4902 pps_unlock(intel_dp
);
4905 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4906 .dpms
= intel_connector_dpms
,
4907 .detect
= intel_dp_detect
,
4908 .force
= intel_dp_force
,
4909 .fill_modes
= drm_helper_probe_single_connector_modes
,
4910 .set_property
= intel_dp_set_property
,
4911 .atomic_get_property
= intel_connector_atomic_get_property
,
4912 .destroy
= intel_dp_connector_destroy
,
4913 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4914 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4917 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4918 .get_modes
= intel_dp_get_modes
,
4919 .mode_valid
= intel_dp_mode_valid
,
4920 .best_encoder
= intel_best_encoder
,
4923 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4924 .reset
= intel_dp_encoder_reset
,
4925 .destroy
= intel_dp_encoder_destroy
,
4929 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4931 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4932 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4933 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4935 enum intel_display_power_domain power_domain
;
4936 enum irqreturn ret
= IRQ_NONE
;
4938 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4939 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4941 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4943 * vdd off can generate a long pulse on eDP which
4944 * would require vdd on to handle it, and thus we
4945 * would end up in an endless cycle of
4946 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4948 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4949 port_name(intel_dig_port
->port
));
4953 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4954 port_name(intel_dig_port
->port
),
4955 long_hpd
? "long" : "short");
4957 power_domain
= intel_display_port_power_domain(intel_encoder
);
4958 intel_display_power_get(dev_priv
, power_domain
);
4961 /* indicate that we need to restart link training */
4962 intel_dp
->train_set_valid
= false;
4964 if (HAS_PCH_SPLIT(dev
)) {
4965 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4968 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4972 if (!intel_dp_get_dpcd(intel_dp
)) {
4976 intel_dp_probe_oui(intel_dp
);
4978 if (!intel_dp_probe_mst(intel_dp
))
4982 if (intel_dp
->is_mst
) {
4983 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4987 if (!intel_dp
->is_mst
) {
4989 * we'll check the link status via the normal hot plug path later -
4990 * but for short hpds we should check it now
4992 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4993 intel_dp_check_link_status(intel_dp
);
4994 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
5002 /* if we were in MST mode, and device is not there get out of MST mode */
5003 if (intel_dp
->is_mst
) {
5004 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5005 intel_dp
->is_mst
= false;
5006 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
5009 intel_display_power_put(dev_priv
, power_domain
);
5014 /* Return which DP Port should be selected for Transcoder DP control */
5016 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
5018 struct drm_device
*dev
= crtc
->dev
;
5019 struct intel_encoder
*intel_encoder
;
5020 struct intel_dp
*intel_dp
;
5022 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5023 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5025 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
5026 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
5027 return intel_dp
->output_reg
;
5033 /* check the VBT to see whether the eDP is on DP-D port */
5034 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
5036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5037 union child_device_config
*p_child
;
5039 static const short port_mapping
[] = {
5040 [PORT_B
] = PORT_IDPB
,
5041 [PORT_C
] = PORT_IDPC
,
5042 [PORT_D
] = PORT_IDPD
,
5048 if (!dev_priv
->vbt
.child_dev_num
)
5051 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
5052 p_child
= dev_priv
->vbt
.child_dev
+ i
;
5054 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
5055 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
5056 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
5063 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5065 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5067 intel_attach_force_audio_property(connector
);
5068 intel_attach_broadcast_rgb_property(connector
);
5069 intel_dp
->color_range_auto
= true;
5071 if (is_edp(intel_dp
)) {
5072 drm_mode_create_scaling_mode_property(connector
->dev
);
5073 drm_object_attach_property(
5075 connector
->dev
->mode_config
.scaling_mode_property
,
5076 DRM_MODE_SCALE_ASPECT
);
5077 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
5081 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5083 intel_dp
->last_power_cycle
= jiffies
;
5084 intel_dp
->last_power_on
= jiffies
;
5085 intel_dp
->last_backlight_off
= jiffies
;
5089 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5090 struct intel_dp
*intel_dp
)
5092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5093 struct edp_power_seq cur
, vbt
, spec
,
5094 *final
= &intel_dp
->pps_delays
;
5095 u32 pp_on
, pp_off
, pp_div
, pp
;
5096 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
5098 lockdep_assert_held(&dev_priv
->pps_mutex
);
5100 /* already initialized? */
5101 if (final
->t11_t12
!= 0)
5104 if (HAS_PCH_SPLIT(dev
)) {
5105 pp_ctrl_reg
= PCH_PP_CONTROL
;
5106 pp_on_reg
= PCH_PP_ON_DELAYS
;
5107 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5108 pp_div_reg
= PCH_PP_DIVISOR
;
5110 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5112 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
5113 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5114 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5115 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5118 /* Workaround: Need to write PP_CONTROL with the unlock key as
5119 * the very first thing. */
5120 pp
= ironlake_get_pp_control(intel_dp
);
5121 I915_WRITE(pp_ctrl_reg
, pp
);
5123 pp_on
= I915_READ(pp_on_reg
);
5124 pp_off
= I915_READ(pp_off_reg
);
5125 pp_div
= I915_READ(pp_div_reg
);
5127 /* Pull timing values out of registers */
5128 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5129 PANEL_POWER_UP_DELAY_SHIFT
;
5131 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5132 PANEL_LIGHT_ON_DELAY_SHIFT
;
5134 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5135 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5137 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5138 PANEL_POWER_DOWN_DELAY_SHIFT
;
5140 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5141 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5143 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5144 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
5146 vbt
= dev_priv
->vbt
.edp_pps
;
5148 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5149 * our hw here, which are all in 100usec. */
5150 spec
.t1_t3
= 210 * 10;
5151 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5152 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5153 spec
.t10
= 500 * 10;
5154 /* This one is special and actually in units of 100ms, but zero
5155 * based in the hw (so we need to add 100 ms). But the sw vbt
5156 * table multiplies it with 1000 to make it in units of 100usec,
5158 spec
.t11_t12
= (510 + 100) * 10;
5160 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5161 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
5163 /* Use the max of the register settings and vbt. If both are
5164 * unset, fall back to the spec limits. */
5165 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5167 max(cur.field, vbt.field))
5168 assign_final(t1_t3
);
5172 assign_final(t11_t12
);
5175 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5176 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5177 intel_dp
->backlight_on_delay
= get_delay(t8
);
5178 intel_dp
->backlight_off_delay
= get_delay(t9
);
5179 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5180 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5183 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5184 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5185 intel_dp
->panel_power_cycle_delay
);
5187 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5188 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5192 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5193 struct intel_dp
*intel_dp
)
5195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5196 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5197 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
5198 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
5199 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5200 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5202 lockdep_assert_held(&dev_priv
->pps_mutex
);
5204 if (HAS_PCH_SPLIT(dev
)) {
5205 pp_on_reg
= PCH_PP_ON_DELAYS
;
5206 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5207 pp_div_reg
= PCH_PP_DIVISOR
;
5209 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5211 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5212 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5213 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5217 * And finally store the new values in the power sequencer. The
5218 * backlight delays are set to 1 because we do manual waits on them. For
5219 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5220 * we'll end up waiting for the backlight off delay twice: once when we
5221 * do the manual sleep, and once when we disable the panel and wait for
5222 * the PP_STATUS bit to become zero.
5224 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5225 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
5226 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5227 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5228 /* Compute the divisor for the pp clock, simply match the Bspec
5230 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5231 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5232 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5234 /* Haswell doesn't have any port selection bits for the panel
5235 * power sequencer any more. */
5236 if (IS_VALLEYVIEW(dev
)) {
5237 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5238 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5240 port_sel
= PANEL_PORT_SELECT_DPA
;
5242 port_sel
= PANEL_PORT_SELECT_DPD
;
5247 I915_WRITE(pp_on_reg
, pp_on
);
5248 I915_WRITE(pp_off_reg
, pp_off
);
5249 I915_WRITE(pp_div_reg
, pp_div
);
5251 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5252 I915_READ(pp_on_reg
),
5253 I915_READ(pp_off_reg
),
5254 I915_READ(pp_div_reg
));
5258 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5260 * @refresh_rate: RR to be programmed
5262 * This function gets called when refresh rate (RR) has to be changed from
5263 * one frequency to another. Switches can be between high and low RR
5264 * supported by the panel or to any other RR based on media playback (in
5265 * this case, RR value needs to be passed from user space).
5267 * The caller of this function needs to take a lock on dev_priv->drrs.
5269 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5272 struct intel_encoder
*encoder
;
5273 struct intel_digital_port
*dig_port
= NULL
;
5274 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5275 struct intel_crtc_state
*config
= NULL
;
5276 struct intel_crtc
*intel_crtc
= NULL
;
5278 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5280 if (refresh_rate
<= 0) {
5281 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5285 if (intel_dp
== NULL
) {
5286 DRM_DEBUG_KMS("DRRS not supported.\n");
5291 * FIXME: This needs proper synchronization with psr state for some
5292 * platforms that cannot have PSR and DRRS enabled at the same time.
5295 dig_port
= dp_to_dig_port(intel_dp
);
5296 encoder
= &dig_port
->base
;
5297 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5300 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5304 config
= intel_crtc
->config
;
5306 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5307 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5311 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5313 index
= DRRS_LOW_RR
;
5315 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5317 "DRRS requested for previously set RR...ignoring\n");
5321 if (!intel_crtc
->active
) {
5322 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5326 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5329 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5332 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5336 DRM_ERROR("Unsupported refreshrate type\n");
5338 } else if (INTEL_INFO(dev
)->gen
> 6) {
5339 reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5340 val
= I915_READ(reg
);
5342 if (index
> DRRS_HIGH_RR
) {
5343 if (IS_VALLEYVIEW(dev
))
5344 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5346 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5348 if (IS_VALLEYVIEW(dev
))
5349 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5351 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5353 I915_WRITE(reg
, val
);
5356 dev_priv
->drrs
.refresh_rate_type
= index
;
5358 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5362 * intel_edp_drrs_enable - init drrs struct if supported
5363 * @intel_dp: DP struct
5365 * Initializes frontbuffer_bits and drrs.dp
5367 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5369 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5371 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5372 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5373 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5375 if (!intel_crtc
->config
->has_drrs
) {
5376 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5380 mutex_lock(&dev_priv
->drrs
.mutex
);
5381 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5382 DRM_ERROR("DRRS already enabled\n");
5386 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5388 dev_priv
->drrs
.dp
= intel_dp
;
5391 mutex_unlock(&dev_priv
->drrs
.mutex
);
5395 * intel_edp_drrs_disable - Disable DRRS
5396 * @intel_dp: DP struct
5399 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5401 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5403 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5404 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5405 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5407 if (!intel_crtc
->config
->has_drrs
)
5410 mutex_lock(&dev_priv
->drrs
.mutex
);
5411 if (!dev_priv
->drrs
.dp
) {
5412 mutex_unlock(&dev_priv
->drrs
.mutex
);
5416 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5417 intel_dp_set_drrs_state(dev_priv
->dev
,
5418 intel_dp
->attached_connector
->panel
.
5419 fixed_mode
->vrefresh
);
5421 dev_priv
->drrs
.dp
= NULL
;
5422 mutex_unlock(&dev_priv
->drrs
.mutex
);
5424 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5427 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5429 struct drm_i915_private
*dev_priv
=
5430 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5431 struct intel_dp
*intel_dp
;
5433 mutex_lock(&dev_priv
->drrs
.mutex
);
5435 intel_dp
= dev_priv
->drrs
.dp
;
5441 * The delayed work can race with an invalidate hence we need to
5445 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5448 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5449 intel_dp_set_drrs_state(dev_priv
->dev
,
5450 intel_dp
->attached_connector
->panel
.
5451 downclock_mode
->vrefresh
);
5454 mutex_unlock(&dev_priv
->drrs
.mutex
);
5458 * intel_edp_drrs_invalidate - Invalidate DRRS
5460 * @frontbuffer_bits: frontbuffer plane tracking bits
5462 * When there is a disturbance on screen (due to cursor movement/time
5463 * update etc), DRRS needs to be invalidated, i.e. need to switch to
5466 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5468 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5469 unsigned frontbuffer_bits
)
5471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5472 struct drm_crtc
*crtc
;
5475 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5478 cancel_delayed_work(&dev_priv
->drrs
.work
);
5480 mutex_lock(&dev_priv
->drrs
.mutex
);
5481 if (!dev_priv
->drrs
.dp
) {
5482 mutex_unlock(&dev_priv
->drrs
.mutex
);
5486 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5487 pipe
= to_intel_crtc(crtc
)->pipe
;
5489 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
) {
5490 intel_dp_set_drrs_state(dev_priv
->dev
,
5491 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5492 fixed_mode
->vrefresh
);
5495 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5497 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5498 mutex_unlock(&dev_priv
->drrs
.mutex
);
5502 * intel_edp_drrs_flush - Flush DRRS
5504 * @frontbuffer_bits: frontbuffer plane tracking bits
5506 * When there is no movement on screen, DRRS work can be scheduled.
5507 * This DRRS work is responsible for setting relevant registers after a
5508 * timeout of 1 second.
5510 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5512 void intel_edp_drrs_flush(struct drm_device
*dev
,
5513 unsigned frontbuffer_bits
)
5515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5516 struct drm_crtc
*crtc
;
5519 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5522 cancel_delayed_work(&dev_priv
->drrs
.work
);
5524 mutex_lock(&dev_priv
->drrs
.mutex
);
5525 if (!dev_priv
->drrs
.dp
) {
5526 mutex_unlock(&dev_priv
->drrs
.mutex
);
5530 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5531 pipe
= to_intel_crtc(crtc
)->pipe
;
5532 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5534 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
&&
5535 !dev_priv
->drrs
.busy_frontbuffer_bits
)
5536 schedule_delayed_work(&dev_priv
->drrs
.work
,
5537 msecs_to_jiffies(1000));
5538 mutex_unlock(&dev_priv
->drrs
.mutex
);
5542 * DOC: Display Refresh Rate Switching (DRRS)
5544 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5545 * which enables swtching between low and high refresh rates,
5546 * dynamically, based on the usage scenario. This feature is applicable
5547 * for internal panels.
5549 * Indication that the panel supports DRRS is given by the panel EDID, which
5550 * would list multiple refresh rates for one resolution.
5552 * DRRS is of 2 types - static and seamless.
5553 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5554 * (may appear as a blink on screen) and is used in dock-undock scenario.
5555 * Seamless DRRS involves changing RR without any visual effect to the user
5556 * and can be used during normal system usage. This is done by programming
5557 * certain registers.
5559 * Support for static/seamless DRRS may be indicated in the VBT based on
5560 * inputs from the panel spec.
5562 * DRRS saves power by switching to low RR based on usage scenarios.
5565 * The implementation is based on frontbuffer tracking implementation.
5566 * When there is a disturbance on the screen triggered by user activity or a
5567 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5568 * When there is no movement on screen, after a timeout of 1 second, a switch
5569 * to low RR is made.
5570 * For integration with frontbuffer tracking code,
5571 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5573 * DRRS can be further extended to support other internal panels and also
5574 * the scenario of video playback wherein RR is set based on the rate
5575 * requested by userspace.
5579 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5580 * @intel_connector: eDP connector
5581 * @fixed_mode: preferred mode of panel
5583 * This function is called only once at driver load to initialize basic
5587 * Downclock mode if panel supports it, else return NULL.
5588 * DRRS support is determined by the presence of downclock mode (apart
5589 * from VBT setting).
5591 static struct drm_display_mode
*
5592 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5593 struct drm_display_mode
*fixed_mode
)
5595 struct drm_connector
*connector
= &intel_connector
->base
;
5596 struct drm_device
*dev
= connector
->dev
;
5597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5598 struct drm_display_mode
*downclock_mode
= NULL
;
5600 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5601 mutex_init(&dev_priv
->drrs
.mutex
);
5603 if (INTEL_INFO(dev
)->gen
<= 6) {
5604 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5608 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5609 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5613 downclock_mode
= intel_find_panel_downclock
5614 (dev
, fixed_mode
, connector
);
5616 if (!downclock_mode
) {
5617 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5621 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5623 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5624 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5625 return downclock_mode
;
5628 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5629 struct intel_connector
*intel_connector
)
5631 struct drm_connector
*connector
= &intel_connector
->base
;
5632 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5633 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5634 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5636 struct drm_display_mode
*fixed_mode
= NULL
;
5637 struct drm_display_mode
*downclock_mode
= NULL
;
5639 struct drm_display_mode
*scan
;
5641 enum pipe pipe
= INVALID_PIPE
;
5643 if (!is_edp(intel_dp
))
5647 intel_edp_panel_vdd_sanitize(intel_dp
);
5648 pps_unlock(intel_dp
);
5650 /* Cache DPCD and EDID for edp. */
5651 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5654 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5655 dev_priv
->no_aux_handshake
=
5656 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5657 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5659 /* if this fails, presume the device is a ghost */
5660 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5664 /* We now know it's not a ghost, init power sequence regs. */
5666 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5667 pps_unlock(intel_dp
);
5669 mutex_lock(&dev
->mode_config
.mutex
);
5670 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5672 if (drm_add_edid_modes(connector
, edid
)) {
5673 drm_mode_connector_update_edid_property(connector
,
5675 drm_edid_to_eld(connector
, edid
);
5678 edid
= ERR_PTR(-EINVAL
);
5681 edid
= ERR_PTR(-ENOENT
);
5683 intel_connector
->edid
= edid
;
5685 /* prefer fixed mode from EDID if available */
5686 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5687 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5688 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5689 downclock_mode
= intel_dp_drrs_init(
5690 intel_connector
, fixed_mode
);
5695 /* fallback to VBT if available for eDP */
5696 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5697 fixed_mode
= drm_mode_duplicate(dev
,
5698 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5700 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5702 mutex_unlock(&dev
->mode_config
.mutex
);
5704 if (IS_VALLEYVIEW(dev
)) {
5705 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5706 register_reboot_notifier(&intel_dp
->edp_notifier
);
5709 * Figure out the current pipe for the initial backlight setup.
5710 * If the current pipe isn't valid, try the PPS pipe, and if that
5711 * fails just assume pipe A.
5713 if (IS_CHERRYVIEW(dev
))
5714 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5716 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5718 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5719 pipe
= intel_dp
->pps_pipe
;
5721 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5724 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5728 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5729 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5730 intel_panel_setup_backlight(connector
, pipe
);
5736 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5737 struct intel_connector
*intel_connector
)
5739 struct drm_connector
*connector
= &intel_connector
->base
;
5740 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5741 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5742 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5744 enum port port
= intel_dig_port
->port
;
5747 intel_dp
->pps_pipe
= INVALID_PIPE
;
5749 /* intel_dp vfuncs */
5750 if (INTEL_INFO(dev
)->gen
>= 9)
5751 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5752 else if (IS_VALLEYVIEW(dev
))
5753 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5754 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5755 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5756 else if (HAS_PCH_SPLIT(dev
))
5757 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5759 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5761 if (INTEL_INFO(dev
)->gen
>= 9)
5762 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5764 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5766 /* Preserve the current hw state. */
5767 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5768 intel_dp
->attached_connector
= intel_connector
;
5770 if (intel_dp_is_edp(dev
, port
))
5771 type
= DRM_MODE_CONNECTOR_eDP
;
5773 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5776 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5777 * for DP the encoder type can be set by the caller to
5778 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5780 if (type
== DRM_MODE_CONNECTOR_eDP
)
5781 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5783 /* eDP only on port B and/or C on vlv/chv */
5784 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5785 port
!= PORT_B
&& port
!= PORT_C
))
5788 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5789 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5792 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5793 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5795 connector
->interlace_allowed
= true;
5796 connector
->doublescan_allowed
= 0;
5798 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5799 edp_panel_vdd_work
);
5801 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5802 drm_connector_register(connector
);
5805 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5807 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5808 intel_connector
->unregister
= intel_dp_connector_unregister
;
5810 /* Set up the hotplug pin. */
5813 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5816 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5819 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5822 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5828 if (is_edp(intel_dp
)) {
5830 intel_dp_init_panel_power_timestamps(intel_dp
);
5831 if (IS_VALLEYVIEW(dev
))
5832 vlv_initial_power_sequencer_setup(intel_dp
);
5834 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5835 pps_unlock(intel_dp
);
5838 intel_dp_aux_init(intel_dp
, intel_connector
);
5840 /* init MST on ports that can support it */
5841 if (HAS_DP_MST(dev
) &&
5842 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5843 intel_dp_mst_encoder_init(intel_dig_port
,
5844 intel_connector
->base
.base
.id
);
5846 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5847 drm_dp_aux_unregister(&intel_dp
->aux
);
5848 if (is_edp(intel_dp
)) {
5849 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5851 * vdd might still be enabled do to the delayed vdd off.
5852 * Make sure vdd is actually turned off here.
5855 edp_panel_vdd_off_sync(intel_dp
);
5856 pps_unlock(intel_dp
);
5858 drm_connector_unregister(connector
);
5859 drm_connector_cleanup(connector
);
5863 intel_dp_add_properties(intel_dp
, connector
);
5865 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5866 * 0xd. Failure to do so will result in spurious interrupts being
5867 * generated on the port when a cable is not attached.
5869 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5870 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5871 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5874 i915_debugfs_connector_add(connector
);
5880 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5882 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5883 struct intel_digital_port
*intel_dig_port
;
5884 struct intel_encoder
*intel_encoder
;
5885 struct drm_encoder
*encoder
;
5886 struct intel_connector
*intel_connector
;
5888 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5889 if (!intel_dig_port
)
5892 intel_connector
= intel_connector_alloc();
5893 if (!intel_connector
) {
5894 kfree(intel_dig_port
);
5898 intel_encoder
= &intel_dig_port
->base
;
5899 encoder
= &intel_encoder
->base
;
5901 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5902 DRM_MODE_ENCODER_TMDS
);
5904 intel_encoder
->compute_config
= intel_dp_compute_config
;
5905 intel_encoder
->disable
= intel_disable_dp
;
5906 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5907 intel_encoder
->get_config
= intel_dp_get_config
;
5908 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5909 if (IS_CHERRYVIEW(dev
)) {
5910 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5911 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5912 intel_encoder
->enable
= vlv_enable_dp
;
5913 intel_encoder
->post_disable
= chv_post_disable_dp
;
5914 } else if (IS_VALLEYVIEW(dev
)) {
5915 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5916 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5917 intel_encoder
->enable
= vlv_enable_dp
;
5918 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5920 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5921 intel_encoder
->enable
= g4x_enable_dp
;
5922 if (INTEL_INFO(dev
)->gen
>= 5)
5923 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5926 intel_dig_port
->port
= port
;
5927 intel_dig_port
->dp
.output_reg
= output_reg
;
5929 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5930 if (IS_CHERRYVIEW(dev
)) {
5932 intel_encoder
->crtc_mask
= 1 << 2;
5934 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5936 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5938 intel_encoder
->cloneable
= 0;
5940 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5941 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5943 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5944 drm_encoder_cleanup(encoder
);
5945 kfree(intel_dig_port
);
5946 kfree(intel_connector
);
5950 void intel_dp_mst_suspend(struct drm_device
*dev
)
5952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5956 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5957 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5958 if (!intel_dig_port
)
5961 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5962 if (!intel_dig_port
->dp
.can_mst
)
5964 if (intel_dig_port
->dp
.is_mst
)
5965 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5970 void intel_dp_mst_resume(struct drm_device
*dev
)
5972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5975 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5976 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5977 if (!intel_dig_port
)
5979 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5982 if (!intel_dig_port
->dp
.can_mst
)
5985 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5987 intel_dp_check_mst_status(&intel_dig_port
->dp
);