2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_RECEIVER_CAP_SIZE 0xf
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
45 * @intel_dp: DP struct
47 * If a CPU or PCH DP output is attached to an eDP panel, this function
48 * will return true, and false otherwise.
50 static bool is_edp(struct intel_dp
*intel_dp
)
52 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
63 static bool is_pch_edp(struct intel_dp
*intel_dp
)
65 return intel_dp
->is_pch_edp
;
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
76 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
79 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
81 return container_of(intel_attached_encoder(connector
),
82 struct intel_dp
, base
);
86 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
87 * @encoder: DRM encoder
89 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
92 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
94 struct intel_dp
*intel_dp
;
99 intel_dp
= enc_to_intel_dp(encoder
);
101 return is_pch_edp(intel_dp
);
104 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
107 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
108 int *lane_num
, int *link_bw
)
110 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
112 *lane_num
= intel_dp
->lane_count
;
113 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
115 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
120 intel_edp_target_clock(struct intel_encoder
*intel_encoder
,
121 struct drm_display_mode
*mode
)
123 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
124 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
126 if (intel_connector
->panel
.fixed_mode
)
127 return intel_connector
->panel
.fixed_mode
->clock
;
133 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
135 int max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
136 switch (max_lane_count
) {
137 case 1: case 2: case 4:
142 return max_lane_count
;
146 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
148 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
150 switch (max_link_bw
) {
151 case DP_LINK_BW_1_62
:
155 max_link_bw
= DP_LINK_BW_1_62
;
162 intel_dp_link_clock(uint8_t link_bw
)
164 if (link_bw
== DP_LINK_BW_2_7
)
171 * The units on the numbers in the next two are... bizarre. Examples will
172 * make it clearer; this one parallels an example in the eDP spec.
174 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
176 * 270000 * 1 * 8 / 10 == 216000
178 * The actual data capacity of that configuration is 2.16Gbit/s, so the
179 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
180 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
181 * 119000. At 18bpp that's 2142000 kilobits per second.
183 * Thus the strange-looking division by 10 in intel_dp_link_required, to
184 * get the result in decakilobits instead of kilobits.
188 intel_dp_link_required(int pixel_clock
, int bpp
)
190 return (pixel_clock
* bpp
+ 9) / 10;
194 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
196 return (max_link_clock
* max_lanes
* 8) / 10;
200 intel_dp_adjust_dithering(struct intel_dp
*intel_dp
,
201 struct drm_display_mode
*mode
,
204 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
205 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
206 int max_rate
, mode_rate
;
208 mode_rate
= intel_dp_link_required(mode
->clock
, 24);
209 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
211 if (mode_rate
> max_rate
) {
212 mode_rate
= intel_dp_link_required(mode
->clock
, 18);
213 if (mode_rate
> max_rate
)
218 |= INTEL_MODE_DP_FORCE_6BPC
;
227 intel_dp_mode_valid(struct drm_connector
*connector
,
228 struct drm_display_mode
*mode
)
230 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
231 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
232 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
234 if (is_edp(intel_dp
) && fixed_mode
) {
235 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
238 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
242 if (!intel_dp_adjust_dithering(intel_dp
, mode
, false))
243 return MODE_CLOCK_HIGH
;
245 if (mode
->clock
< 10000)
246 return MODE_CLOCK_LOW
;
248 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
249 return MODE_H_ILLEGAL
;
255 pack_aux(uint8_t *src
, int src_bytes
)
262 for (i
= 0; i
< src_bytes
; i
++)
263 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
268 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
273 for (i
= 0; i
< dst_bytes
; i
++)
274 dst
[i
] = src
>> ((3-i
) * 8);
277 /* hrawclock is 1/4 the FSB frequency */
279 intel_hrawclk(struct drm_device
*dev
)
281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
284 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
285 if (IS_VALLEYVIEW(dev
))
288 clkcfg
= I915_READ(CLKCFG
);
289 switch (clkcfg
& CLKCFG_FSB_MASK
) {
298 case CLKCFG_FSB_1067
:
300 case CLKCFG_FSB_1333
:
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600
:
304 case CLKCFG_FSB_1600_ALT
:
311 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
313 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
316 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
319 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
321 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
328 intel_dp_check_edp(struct intel_dp
*intel_dp
)
330 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
333 if (!is_edp(intel_dp
))
335 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
338 I915_READ(PCH_PP_STATUS
),
339 I915_READ(PCH_PP_CONTROL
));
344 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
345 uint8_t *send
, int send_bytes
,
346 uint8_t *recv
, int recv_size
)
348 uint32_t output_reg
= intel_dp
->output_reg
;
349 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 uint32_t ch_ctl
= output_reg
+ 0x10;
352 uint32_t ch_data
= ch_ctl
+ 4;
356 uint32_t aux_clock_divider
;
359 if (IS_HASWELL(dev
)) {
360 switch (intel_dp
->port
) {
362 ch_ctl
= DPA_AUX_CH_CTL
;
363 ch_data
= DPA_AUX_CH_DATA1
;
366 ch_ctl
= PCH_DPB_AUX_CH_CTL
;
367 ch_data
= PCH_DPB_AUX_CH_DATA1
;
370 ch_ctl
= PCH_DPC_AUX_CH_CTL
;
371 ch_data
= PCH_DPC_AUX_CH_DATA1
;
374 ch_ctl
= PCH_DPD_AUX_CH_CTL
;
375 ch_data
= PCH_DPD_AUX_CH_DATA1
;
382 intel_dp_check_edp(intel_dp
);
383 /* The clock divider is based off the hrawclk,
384 * and would like to run at 2MHz. So, take the
385 * hrawclk value and divide by 2 and use that
387 * Note that PCH attached eDP panels should use a 125MHz input
390 if (is_cpu_edp(intel_dp
)) {
391 if (IS_VALLEYVIEW(dev
))
392 aux_clock_divider
= 100;
393 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
394 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
396 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
397 } else if (HAS_PCH_SPLIT(dev
))
398 aux_clock_divider
= 63; /* IRL input clock fixed at 125Mhz */
400 aux_clock_divider
= intel_hrawclk(dev
) / 2;
407 /* Try to wait for any previous AUX channel activity */
408 for (try = 0; try < 3; try++) {
409 status
= I915_READ(ch_ctl
);
410 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
416 WARN(1, "dp_aux_ch not started status 0x%08x\n",
421 /* Must try at least 3 times according to DP spec */
422 for (try = 0; try < 5; try++) {
423 /* Load the send data into the aux channel data registers */
424 for (i
= 0; i
< send_bytes
; i
+= 4)
425 I915_WRITE(ch_data
+ i
,
426 pack_aux(send
+ i
, send_bytes
- i
));
428 /* Send the command and wait for it to complete */
430 DP_AUX_CH_CTL_SEND_BUSY
|
431 DP_AUX_CH_CTL_TIME_OUT_400us
|
432 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
433 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
434 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
436 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
437 DP_AUX_CH_CTL_RECEIVE_ERROR
);
439 status
= I915_READ(ch_ctl
);
440 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
445 /* Clear done status and any errors */
449 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
450 DP_AUX_CH_CTL_RECEIVE_ERROR
);
452 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
453 DP_AUX_CH_CTL_RECEIVE_ERROR
))
455 if (status
& DP_AUX_CH_CTL_DONE
)
459 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
460 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
464 /* Check for timeout or receive error.
465 * Timeouts occur when the sink is not connected
467 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
468 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
472 /* Timeouts occur when the device isn't connected, so they're
473 * "normal" -- don't fill the kernel log with these */
474 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
475 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
479 /* Unload any bytes sent back from the other side */
480 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
481 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
482 if (recv_bytes
> recv_size
)
483 recv_bytes
= recv_size
;
485 for (i
= 0; i
< recv_bytes
; i
+= 4)
486 unpack_aux(I915_READ(ch_data
+ i
),
487 recv
+ i
, recv_bytes
- i
);
492 /* Write data to the aux channel in native mode */
494 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
495 uint16_t address
, uint8_t *send
, int send_bytes
)
502 intel_dp_check_edp(intel_dp
);
505 msg
[0] = AUX_NATIVE_WRITE
<< 4;
506 msg
[1] = address
>> 8;
507 msg
[2] = address
& 0xff;
508 msg
[3] = send_bytes
- 1;
509 memcpy(&msg
[4], send
, send_bytes
);
510 msg_bytes
= send_bytes
+ 4;
512 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
515 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
517 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
525 /* Write a single byte to the aux channel in native mode */
527 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
528 uint16_t address
, uint8_t byte
)
530 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
533 /* read bytes from a native aux channel */
535 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
536 uint16_t address
, uint8_t *recv
, int recv_bytes
)
545 intel_dp_check_edp(intel_dp
);
546 msg
[0] = AUX_NATIVE_READ
<< 4;
547 msg
[1] = address
>> 8;
548 msg
[2] = address
& 0xff;
549 msg
[3] = recv_bytes
- 1;
552 reply_bytes
= recv_bytes
+ 1;
555 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
562 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
563 memcpy(recv
, reply
+ 1, ret
- 1);
566 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
574 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
575 uint8_t write_byte
, uint8_t *read_byte
)
577 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
578 struct intel_dp
*intel_dp
= container_of(adapter
,
581 uint16_t address
= algo_data
->address
;
589 intel_dp_check_edp(intel_dp
);
590 /* Set up the command byte */
591 if (mode
& MODE_I2C_READ
)
592 msg
[0] = AUX_I2C_READ
<< 4;
594 msg
[0] = AUX_I2C_WRITE
<< 4;
596 if (!(mode
& MODE_I2C_STOP
))
597 msg
[0] |= AUX_I2C_MOT
<< 4;
599 msg
[1] = address
>> 8;
620 for (retry
= 0; retry
< 5; retry
++) {
621 ret
= intel_dp_aux_ch(intel_dp
,
625 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
629 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
630 case AUX_NATIVE_REPLY_ACK
:
631 /* I2C-over-AUX Reply field is only valid
632 * when paired with AUX ACK.
635 case AUX_NATIVE_REPLY_NACK
:
636 DRM_DEBUG_KMS("aux_ch native nack\n");
638 case AUX_NATIVE_REPLY_DEFER
:
642 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
647 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
648 case AUX_I2C_REPLY_ACK
:
649 if (mode
== MODE_I2C_READ
) {
650 *read_byte
= reply
[1];
652 return reply_bytes
- 1;
653 case AUX_I2C_REPLY_NACK
:
654 DRM_DEBUG_KMS("aux_i2c nack\n");
656 case AUX_I2C_REPLY_DEFER
:
657 DRM_DEBUG_KMS("aux_i2c defer\n");
661 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
666 DRM_ERROR("too many retries, giving up\n");
670 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
671 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
674 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
675 struct intel_connector
*intel_connector
, const char *name
)
679 DRM_DEBUG_KMS("i2c_init %s\n", name
);
680 intel_dp
->algo
.running
= false;
681 intel_dp
->algo
.address
= 0;
682 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
684 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
685 intel_dp
->adapter
.owner
= THIS_MODULE
;
686 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
687 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
688 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
689 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
690 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
692 ironlake_edp_panel_vdd_on(intel_dp
);
693 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
694 ironlake_edp_panel_vdd_off(intel_dp
, false);
699 intel_dp_mode_fixup(struct drm_encoder
*encoder
,
700 const struct drm_display_mode
*mode
,
701 struct drm_display_mode
*adjusted_mode
)
703 struct drm_device
*dev
= encoder
->dev
;
704 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
705 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
706 int lane_count
, clock
;
707 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
708 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
710 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
712 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
713 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
715 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
716 mode
, adjusted_mode
);
719 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
722 DRM_DEBUG_KMS("DP link computation with max lane count %i "
723 "max bw %02x pixel clock %iKHz\n",
724 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
726 if (!intel_dp_adjust_dithering(intel_dp
, adjusted_mode
, true))
729 bpp
= adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
? 18 : 24;
730 mode_rate
= intel_dp_link_required(adjusted_mode
->clock
, bpp
);
732 for (clock
= 0; clock
<= max_clock
; clock
++) {
733 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
734 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
736 if (mode_rate
<= link_avail
) {
737 intel_dp
->link_bw
= bws
[clock
];
738 intel_dp
->lane_count
= lane_count
;
739 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
740 DRM_DEBUG_KMS("DP link bw %02x lane "
741 "count %d clock %d bpp %d\n",
742 intel_dp
->link_bw
, intel_dp
->lane_count
,
743 adjusted_mode
->clock
, bpp
);
744 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
745 mode_rate
, link_avail
);
754 struct intel_dp_m_n
{
763 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
765 while (*num
> 0xffffff || *den
> 0xffffff) {
772 intel_dp_compute_m_n(int bpp
,
776 struct intel_dp_m_n
*m_n
)
779 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
780 m_n
->gmch_n
= link_clock
* nlanes
;
781 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
782 m_n
->link_m
= pixel_clock
;
783 m_n
->link_n
= link_clock
;
784 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
788 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
789 struct drm_display_mode
*adjusted_mode
)
791 struct drm_device
*dev
= crtc
->dev
;
792 struct intel_encoder
*encoder
;
793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
794 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
796 struct intel_dp_m_n m_n
;
797 int pipe
= intel_crtc
->pipe
;
800 * Find the lane count in the intel_encoder private
802 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
803 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
805 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
806 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
808 lane_count
= intel_dp
->lane_count
;
814 * Compute the GMCH and Link ratios. The '3' here is
815 * the number of bytes_per_pixel post-LUT, which we always
816 * set up for 8-bits of R/G/B, or 3 bytes total.
818 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
819 mode
->clock
, adjusted_mode
->clock
, &m_n
);
821 if (IS_HASWELL(dev
)) {
822 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
823 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
824 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
825 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
826 } else if (HAS_PCH_SPLIT(dev
)) {
827 I915_WRITE(TRANSDATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
828 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
829 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
830 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
831 } else if (IS_VALLEYVIEW(dev
)) {
832 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
833 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
834 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
835 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
837 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
838 TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
839 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
840 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
841 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
845 void intel_dp_init_link_config(struct intel_dp
*intel_dp
)
847 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
848 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
849 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
850 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
852 * Check for DPCD version > 1.1 and enhanced framing support
854 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
855 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
856 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
861 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
862 struct drm_display_mode
*adjusted_mode
)
864 struct drm_device
*dev
= encoder
->dev
;
865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
866 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
867 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
868 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
871 * There are four kinds of DP registers:
878 * IBX PCH and CPU are the same for almost everything,
879 * except that the CPU DP PLL is configured in this
882 * CPT PCH is quite different, having many bits moved
883 * to the TRANS_DP_CTL register instead. That
884 * configuration happens (oddly) in ironlake_pch_enable
887 /* Preserve the BIOS-computed detected bit. This is
888 * supposed to be read-only.
890 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
892 /* Handle DP bits in common between all three register formats */
893 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
895 switch (intel_dp
->lane_count
) {
897 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
900 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
903 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
906 if (intel_dp
->has_audio
) {
907 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
908 pipe_name(intel_crtc
->pipe
));
909 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
910 intel_write_eld(encoder
, adjusted_mode
);
913 intel_dp_init_link_config(intel_dp
);
915 /* Split out the IBX/CPU vs CPT settings */
917 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
918 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
919 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
920 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
921 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
922 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
924 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
925 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
927 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
929 /* don't miss out required setting for eDP */
930 if (adjusted_mode
->clock
< 200000)
931 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
933 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
934 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
935 intel_dp
->DP
|= intel_dp
->color_range
;
937 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
938 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
939 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
940 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
941 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
943 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
944 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
946 if (intel_crtc
->pipe
== 1)
947 intel_dp
->DP
|= DP_PIPEB_SELECT
;
949 if (is_cpu_edp(intel_dp
)) {
950 /* don't miss out required setting for eDP */
951 if (adjusted_mode
->clock
< 200000)
952 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
954 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
957 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
961 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
962 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
964 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
965 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
967 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
968 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
970 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
974 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
977 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
979 I915_READ(PCH_PP_STATUS
),
980 I915_READ(PCH_PP_CONTROL
));
982 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
983 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
984 I915_READ(PCH_PP_STATUS
),
985 I915_READ(PCH_PP_CONTROL
));
989 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
991 DRM_DEBUG_KMS("Wait for panel power on\n");
992 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
995 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
997 DRM_DEBUG_KMS("Wait for panel power off time\n");
998 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1001 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1003 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1004 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1008 /* Read the current pp_control value, unlocking the register if it
1012 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
1014 u32 control
= I915_READ(PCH_PP_CONTROL
);
1016 control
&= ~PANEL_UNLOCK_MASK
;
1017 control
|= PANEL_UNLOCK_REGS
;
1021 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1023 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1027 if (!is_edp(intel_dp
))
1029 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1031 WARN(intel_dp
->want_panel_vdd
,
1032 "eDP VDD already requested on\n");
1034 intel_dp
->want_panel_vdd
= true;
1036 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1037 DRM_DEBUG_KMS("eDP VDD already on\n");
1041 if (!ironlake_edp_have_panel_power(intel_dp
))
1042 ironlake_wait_panel_power_cycle(intel_dp
);
1044 pp
= ironlake_get_pp_control(dev_priv
);
1045 pp
|= EDP_FORCE_VDD
;
1046 I915_WRITE(PCH_PP_CONTROL
, pp
);
1047 POSTING_READ(PCH_PP_CONTROL
);
1048 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1049 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1052 * If the panel wasn't on, delay before accessing aux channel
1054 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1055 DRM_DEBUG_KMS("eDP was not running\n");
1056 msleep(intel_dp
->panel_power_up_delay
);
1060 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1062 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1066 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1067 pp
= ironlake_get_pp_control(dev_priv
);
1068 pp
&= ~EDP_FORCE_VDD
;
1069 I915_WRITE(PCH_PP_CONTROL
, pp
);
1070 POSTING_READ(PCH_PP_CONTROL
);
1072 /* Make sure sequencer is idle before allowing subsequent activity */
1073 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1074 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1076 msleep(intel_dp
->panel_power_down_delay
);
1080 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1082 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1083 struct intel_dp
, panel_vdd_work
);
1084 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1086 mutex_lock(&dev
->mode_config
.mutex
);
1087 ironlake_panel_vdd_off_sync(intel_dp
);
1088 mutex_unlock(&dev
->mode_config
.mutex
);
1091 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1093 if (!is_edp(intel_dp
))
1096 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1097 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1099 intel_dp
->want_panel_vdd
= false;
1102 ironlake_panel_vdd_off_sync(intel_dp
);
1105 * Queue the timer to fire a long
1106 * time from now (relative to the power down delay)
1107 * to keep the panel power up across a sequence of operations
1109 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1110 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1114 static void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1116 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1120 if (!is_edp(intel_dp
))
1123 DRM_DEBUG_KMS("Turn eDP power on\n");
1125 if (ironlake_edp_have_panel_power(intel_dp
)) {
1126 DRM_DEBUG_KMS("eDP power already on\n");
1130 ironlake_wait_panel_power_cycle(intel_dp
);
1132 pp
= ironlake_get_pp_control(dev_priv
);
1134 /* ILK workaround: disable reset around power sequence */
1135 pp
&= ~PANEL_POWER_RESET
;
1136 I915_WRITE(PCH_PP_CONTROL
, pp
);
1137 POSTING_READ(PCH_PP_CONTROL
);
1140 pp
|= POWER_TARGET_ON
;
1142 pp
|= PANEL_POWER_RESET
;
1144 I915_WRITE(PCH_PP_CONTROL
, pp
);
1145 POSTING_READ(PCH_PP_CONTROL
);
1147 ironlake_wait_panel_on(intel_dp
);
1150 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1151 I915_WRITE(PCH_PP_CONTROL
, pp
);
1152 POSTING_READ(PCH_PP_CONTROL
);
1156 static void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1158 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1162 if (!is_edp(intel_dp
))
1165 DRM_DEBUG_KMS("Turn eDP power off\n");
1167 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1169 pp
= ironlake_get_pp_control(dev_priv
);
1170 /* We need to switch off panel power _and_ force vdd, for otherwise some
1171 * panels get very unhappy and cease to work. */
1172 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1173 I915_WRITE(PCH_PP_CONTROL
, pp
);
1174 POSTING_READ(PCH_PP_CONTROL
);
1176 intel_dp
->want_panel_vdd
= false;
1178 ironlake_wait_panel_off(intel_dp
);
1181 static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1183 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1187 if (!is_edp(intel_dp
))
1190 DRM_DEBUG_KMS("\n");
1192 * If we enable the backlight right away following a panel power
1193 * on, we may see slight flicker as the panel syncs with the eDP
1194 * link. So delay a bit to make sure the image is solid before
1195 * allowing it to appear.
1197 msleep(intel_dp
->backlight_on_delay
);
1198 pp
= ironlake_get_pp_control(dev_priv
);
1199 pp
|= EDP_BLC_ENABLE
;
1200 I915_WRITE(PCH_PP_CONTROL
, pp
);
1201 POSTING_READ(PCH_PP_CONTROL
);
1204 static void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1206 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1210 if (!is_edp(intel_dp
))
1213 DRM_DEBUG_KMS("\n");
1214 pp
= ironlake_get_pp_control(dev_priv
);
1215 pp
&= ~EDP_BLC_ENABLE
;
1216 I915_WRITE(PCH_PP_CONTROL
, pp
);
1217 POSTING_READ(PCH_PP_CONTROL
);
1218 msleep(intel_dp
->backlight_off_delay
);
1221 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1223 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1224 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1228 assert_pipe_disabled(dev_priv
,
1229 to_intel_crtc(crtc
)->pipe
);
1231 DRM_DEBUG_KMS("\n");
1232 dpa_ctl
= I915_READ(DP_A
);
1233 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1234 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1236 /* We don't adjust intel_dp->DP while tearing down the link, to
1237 * facilitate link retraining (e.g. after hotplug). Hence clear all
1238 * enable bits here to ensure that we don't enable too much. */
1239 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1240 intel_dp
->DP
|= DP_PLL_ENABLE
;
1241 I915_WRITE(DP_A
, intel_dp
->DP
);
1246 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1248 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1249 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1253 assert_pipe_disabled(dev_priv
,
1254 to_intel_crtc(crtc
)->pipe
);
1256 dpa_ctl
= I915_READ(DP_A
);
1257 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1258 "dp pll off, should be on\n");
1259 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1261 /* We can't rely on the value tracked for the DP register in
1262 * intel_dp->DP because link_down must not change that (otherwise link
1263 * re-training will fail. */
1264 dpa_ctl
&= ~DP_PLL_ENABLE
;
1265 I915_WRITE(DP_A
, dpa_ctl
);
1270 /* If the sink supports it, try to set the power state appropriately */
1271 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1275 /* Should have a valid DPCD by this point */
1276 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1279 if (mode
!= DRM_MODE_DPMS_ON
) {
1280 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1283 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1286 * When turning on, we need to retry for 1ms to give the sink
1289 for (i
= 0; i
< 3; i
++) {
1290 ret
= intel_dp_aux_native_write_1(intel_dp
,
1300 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1303 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1304 struct drm_device
*dev
= encoder
->base
.dev
;
1305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1306 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1308 if (!(tmp
& DP_PORT_EN
))
1311 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
)) {
1312 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1313 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
1314 *pipe
= PORT_TO_PIPE(tmp
);
1320 switch (intel_dp
->output_reg
) {
1322 trans_sel
= TRANS_DP_PORT_SEL_B
;
1325 trans_sel
= TRANS_DP_PORT_SEL_C
;
1328 trans_sel
= TRANS_DP_PORT_SEL_D
;
1335 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1336 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1343 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp
->output_reg
);
1348 static void intel_disable_dp(struct intel_encoder
*encoder
)
1350 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1352 /* Make sure the panel is off before trying to change the mode. But also
1353 * ensure that we have vdd while we switch off the panel. */
1354 ironlake_edp_panel_vdd_on(intel_dp
);
1355 ironlake_edp_backlight_off(intel_dp
);
1356 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1357 ironlake_edp_panel_off(intel_dp
);
1359 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1360 if (!is_cpu_edp(intel_dp
))
1361 intel_dp_link_down(intel_dp
);
1364 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1366 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1368 if (is_cpu_edp(intel_dp
)) {
1369 intel_dp_link_down(intel_dp
);
1370 ironlake_edp_pll_off(intel_dp
);
1374 static void intel_enable_dp(struct intel_encoder
*encoder
)
1376 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1377 struct drm_device
*dev
= encoder
->base
.dev
;
1378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1379 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1381 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1384 ironlake_edp_panel_vdd_on(intel_dp
);
1385 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1386 intel_dp_start_link_train(intel_dp
);
1387 ironlake_edp_panel_on(intel_dp
);
1388 ironlake_edp_panel_vdd_off(intel_dp
, true);
1389 intel_dp_complete_link_train(intel_dp
);
1390 ironlake_edp_backlight_on(intel_dp
);
1393 static void intel_pre_enable_dp(struct intel_encoder
*encoder
)
1395 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1397 if (is_cpu_edp(intel_dp
))
1398 ironlake_edp_pll_on(intel_dp
);
1402 * Native read with retry for link status and receiver capability reads for
1403 * cases where the sink may still be asleep.
1406 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1407 uint8_t *recv
, int recv_bytes
)
1412 * Sinks are *supposed* to come up within 1ms from an off state,
1413 * but we're also supposed to retry 3 times per the spec.
1415 for (i
= 0; i
< 3; i
++) {
1416 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1418 if (ret
== recv_bytes
)
1427 * Fetch AUX CH registers 0x202 - 0x207 which contain
1428 * link status information
1431 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1433 return intel_dp_aux_native_read_retry(intel_dp
,
1436 DP_LINK_STATUS_SIZE
);
1440 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1443 return link_status
[r
- DP_LANE0_1_STATUS
];
1447 intel_get_adjust_request_voltage(uint8_t adjust_request
[2],
1450 int s
= ((lane
& 1) ?
1451 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1452 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1453 uint8_t l
= adjust_request
[lane
>>1];
1455 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1459 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request
[2],
1462 int s
= ((lane
& 1) ?
1463 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1464 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1465 uint8_t l
= adjust_request
[lane
>>1];
1467 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1472 static char *voltage_names
[] = {
1473 "0.4V", "0.6V", "0.8V", "1.2V"
1475 static char *pre_emph_names
[] = {
1476 "0dB", "3.5dB", "6dB", "9.5dB"
1478 static char *link_train_names
[] = {
1479 "pattern 1", "pattern 2", "idle", "off"
1484 * These are source-specific values; current Intel hardware supports
1485 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1489 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1491 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1493 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1494 return DP_TRAIN_VOLTAGE_SWING_800
;
1495 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1496 return DP_TRAIN_VOLTAGE_SWING_1200
;
1498 return DP_TRAIN_VOLTAGE_SWING_800
;
1502 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1504 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1506 if (IS_HASWELL(dev
)) {
1507 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1508 case DP_TRAIN_VOLTAGE_SWING_400
:
1509 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1510 case DP_TRAIN_VOLTAGE_SWING_600
:
1511 return DP_TRAIN_PRE_EMPHASIS_6
;
1512 case DP_TRAIN_VOLTAGE_SWING_800
:
1513 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1514 case DP_TRAIN_VOLTAGE_SWING_1200
:
1516 return DP_TRAIN_PRE_EMPHASIS_0
;
1518 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1519 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1520 case DP_TRAIN_VOLTAGE_SWING_400
:
1521 return DP_TRAIN_PRE_EMPHASIS_6
;
1522 case DP_TRAIN_VOLTAGE_SWING_600
:
1523 case DP_TRAIN_VOLTAGE_SWING_800
:
1524 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1526 return DP_TRAIN_PRE_EMPHASIS_0
;
1529 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1530 case DP_TRAIN_VOLTAGE_SWING_400
:
1531 return DP_TRAIN_PRE_EMPHASIS_6
;
1532 case DP_TRAIN_VOLTAGE_SWING_600
:
1533 return DP_TRAIN_PRE_EMPHASIS_6
;
1534 case DP_TRAIN_VOLTAGE_SWING_800
:
1535 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1536 case DP_TRAIN_VOLTAGE_SWING_1200
:
1538 return DP_TRAIN_PRE_EMPHASIS_0
;
1544 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1549 uint8_t *adjust_request
= link_status
+ (DP_ADJUST_REQUEST_LANE0_1
- DP_LANE0_1_STATUS
);
1550 uint8_t voltage_max
;
1551 uint8_t preemph_max
;
1553 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1554 uint8_t this_v
= intel_get_adjust_request_voltage(adjust_request
, lane
);
1555 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(adjust_request
, lane
);
1563 voltage_max
= intel_dp_voltage_max(intel_dp
);
1564 if (v
>= voltage_max
)
1565 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1567 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1568 if (p
>= preemph_max
)
1569 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1571 for (lane
= 0; lane
< 4; lane
++)
1572 intel_dp
->train_set
[lane
] = v
| p
;
1576 intel_dp_signal_levels(uint8_t train_set
)
1578 uint32_t signal_levels
= 0;
1580 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1581 case DP_TRAIN_VOLTAGE_SWING_400
:
1583 signal_levels
|= DP_VOLTAGE_0_4
;
1585 case DP_TRAIN_VOLTAGE_SWING_600
:
1586 signal_levels
|= DP_VOLTAGE_0_6
;
1588 case DP_TRAIN_VOLTAGE_SWING_800
:
1589 signal_levels
|= DP_VOLTAGE_0_8
;
1591 case DP_TRAIN_VOLTAGE_SWING_1200
:
1592 signal_levels
|= DP_VOLTAGE_1_2
;
1595 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1596 case DP_TRAIN_PRE_EMPHASIS_0
:
1598 signal_levels
|= DP_PRE_EMPHASIS_0
;
1600 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1601 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1603 case DP_TRAIN_PRE_EMPHASIS_6
:
1604 signal_levels
|= DP_PRE_EMPHASIS_6
;
1606 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1607 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1610 return signal_levels
;
1613 /* Gen6's DP voltage swing and pre-emphasis control */
1615 intel_gen6_edp_signal_levels(uint8_t train_set
)
1617 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1618 DP_TRAIN_PRE_EMPHASIS_MASK
);
1619 switch (signal_levels
) {
1620 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1621 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1622 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1623 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1624 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1625 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1626 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1627 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1628 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1629 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1630 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1631 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1632 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1633 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1635 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1636 "0x%x\n", signal_levels
);
1637 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1641 /* Gen7's DP voltage swing and pre-emphasis control */
1643 intel_gen7_edp_signal_levels(uint8_t train_set
)
1645 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1646 DP_TRAIN_PRE_EMPHASIS_MASK
);
1647 switch (signal_levels
) {
1648 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1649 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1650 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1651 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1652 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1653 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1655 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1656 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1657 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1658 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1660 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1661 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1662 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1663 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1666 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1667 "0x%x\n", signal_levels
);
1668 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1672 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1674 intel_dp_signal_levels_hsw(uint8_t train_set
)
1676 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1677 DP_TRAIN_PRE_EMPHASIS_MASK
);
1678 switch (signal_levels
) {
1679 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1680 return DDI_BUF_EMP_400MV_0DB_HSW
;
1681 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1682 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
1683 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1684 return DDI_BUF_EMP_400MV_6DB_HSW
;
1685 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
1686 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
1688 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1689 return DDI_BUF_EMP_600MV_0DB_HSW
;
1690 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1691 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
1692 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1693 return DDI_BUF_EMP_600MV_6DB_HSW
;
1695 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1696 return DDI_BUF_EMP_800MV_0DB_HSW
;
1697 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1698 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
1700 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1701 "0x%x\n", signal_levels
);
1702 return DDI_BUF_EMP_400MV_0DB_HSW
;
1707 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1710 int s
= (lane
& 1) * 4;
1711 uint8_t l
= link_status
[lane
>>1];
1713 return (l
>> s
) & 0xf;
1716 /* Check for clock recovery is done on all channels */
1718 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1721 uint8_t lane_status
;
1723 for (lane
= 0; lane
< lane_count
; lane
++) {
1724 lane_status
= intel_get_lane_status(link_status
, lane
);
1725 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1731 /* Check to see if channel eq is done on all channels */
1732 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1733 DP_LANE_CHANNEL_EQ_DONE|\
1734 DP_LANE_SYMBOL_LOCKED)
1736 intel_channel_eq_ok(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1739 uint8_t lane_status
;
1742 lane_align
= intel_dp_link_status(link_status
,
1743 DP_LANE_ALIGN_STATUS_UPDATED
);
1744 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1746 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1747 lane_status
= intel_get_lane_status(link_status
, lane
);
1748 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1755 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1756 uint32_t dp_reg_value
,
1757 uint8_t dp_train_pat
)
1759 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1764 if (IS_HASWELL(dev
)) {
1765 temp
= I915_READ(DP_TP_CTL(intel_dp
->port
));
1767 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
1768 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
1770 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
1772 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1773 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1774 case DP_TRAINING_PATTERN_DISABLE
:
1775 temp
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
1776 I915_WRITE(DP_TP_CTL(intel_dp
->port
), temp
);
1778 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp
->port
)) &
1779 DP_TP_STATUS_IDLE_DONE
), 1))
1780 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1782 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1783 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
1786 case DP_TRAINING_PATTERN_1
:
1787 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1789 case DP_TRAINING_PATTERN_2
:
1790 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
1792 case DP_TRAINING_PATTERN_3
:
1793 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
1796 I915_WRITE(DP_TP_CTL(intel_dp
->port
), temp
);
1798 } else if (HAS_PCH_CPT(dev
) &&
1799 (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1800 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
1802 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1803 case DP_TRAINING_PATTERN_DISABLE
:
1804 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
1806 case DP_TRAINING_PATTERN_1
:
1807 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
1809 case DP_TRAINING_PATTERN_2
:
1810 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1812 case DP_TRAINING_PATTERN_3
:
1813 DRM_ERROR("DP training pattern 3 not supported\n");
1814 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1819 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
1821 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1822 case DP_TRAINING_PATTERN_DISABLE
:
1823 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
1825 case DP_TRAINING_PATTERN_1
:
1826 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
1828 case DP_TRAINING_PATTERN_2
:
1829 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1831 case DP_TRAINING_PATTERN_3
:
1832 DRM_ERROR("DP training pattern 3 not supported\n");
1833 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1838 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1839 POSTING_READ(intel_dp
->output_reg
);
1841 intel_dp_aux_native_write_1(intel_dp
,
1842 DP_TRAINING_PATTERN_SET
,
1845 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
1846 DP_TRAINING_PATTERN_DISABLE
) {
1847 ret
= intel_dp_aux_native_write(intel_dp
,
1848 DP_TRAINING_LANE0_SET
,
1849 intel_dp
->train_set
,
1850 intel_dp
->lane_count
);
1851 if (ret
!= intel_dp
->lane_count
)
1858 /* Enable corresponding port and start training pattern 1 */
1860 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1862 struct drm_encoder
*encoder
= &intel_dp
->base
.base
;
1863 struct drm_device
*dev
= encoder
->dev
;
1866 bool clock_recovery
= false;
1867 int voltage_tries
, loop_tries
;
1868 uint32_t DP
= intel_dp
->DP
;
1870 if (IS_HASWELL(dev
))
1871 intel_ddi_prepare_link_retrain(encoder
);
1873 /* Write the link configuration data */
1874 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1875 intel_dp
->link_configuration
,
1876 DP_LINK_CONFIGURATION_SIZE
);
1880 memset(intel_dp
->train_set
, 0, 4);
1884 clock_recovery
= false;
1886 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1887 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1888 uint32_t signal_levels
;
1890 if (IS_HASWELL(dev
)) {
1891 signal_levels
= intel_dp_signal_levels_hsw(
1892 intel_dp
->train_set
[0]);
1893 DP
= (DP
& ~DDI_BUF_EMP_MASK
) | signal_levels
;
1894 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1895 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1896 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1897 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1898 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1899 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1901 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1902 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1904 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1907 if (!intel_dp_set_link_train(intel_dp
, DP
,
1908 DP_TRAINING_PATTERN_1
|
1909 DP_LINK_SCRAMBLING_DISABLE
))
1911 /* Set training pattern 1 */
1914 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1915 DRM_ERROR("failed to get link status\n");
1919 if (intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1920 DRM_DEBUG_KMS("clock recovery OK\n");
1921 clock_recovery
= true;
1925 /* Check to see if we've tried the max voltage */
1926 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1927 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1929 if (i
== intel_dp
->lane_count
&& voltage_tries
== 5) {
1930 if (++loop_tries
== 5) {
1931 DRM_DEBUG_KMS("too many full retries, give up\n");
1934 memset(intel_dp
->train_set
, 0, 4);
1939 /* Check to see if we've tried the same voltage 5 times */
1940 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) != voltage
) {
1941 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1946 /* Compute new intel_dp->train_set as requested by target */
1947 intel_get_adjust_train(intel_dp
, link_status
);
1954 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1956 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1957 bool channel_eq
= false;
1958 int tries
, cr_tries
;
1959 uint32_t DP
= intel_dp
->DP
;
1961 /* channel equalization */
1966 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1967 uint32_t signal_levels
;
1968 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1971 DRM_ERROR("failed to train DP, aborting\n");
1972 intel_dp_link_down(intel_dp
);
1976 if (IS_HASWELL(dev
)) {
1977 signal_levels
= intel_dp_signal_levels_hsw(intel_dp
->train_set
[0]);
1978 DP
= (DP
& ~DDI_BUF_EMP_MASK
) | signal_levels
;
1979 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1980 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1981 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1982 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1983 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1984 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1986 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1987 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1990 /* channel eq pattern */
1991 if (!intel_dp_set_link_train(intel_dp
, DP
,
1992 DP_TRAINING_PATTERN_2
|
1993 DP_LINK_SCRAMBLING_DISABLE
))
1997 if (!intel_dp_get_link_status(intel_dp
, link_status
))
2000 /* Make sure clock is still ok */
2001 if (!intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2002 intel_dp_start_link_train(intel_dp
);
2007 if (intel_channel_eq_ok(intel_dp
, link_status
)) {
2012 /* Try 5 times, then try clock recovery if that fails */
2014 intel_dp_link_down(intel_dp
);
2015 intel_dp_start_link_train(intel_dp
);
2021 /* Compute new intel_dp->train_set as requested by target */
2022 intel_get_adjust_train(intel_dp
, link_status
);
2027 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2029 intel_dp_set_link_train(intel_dp
, DP
, DP_TRAINING_PATTERN_DISABLE
);
2033 intel_dp_link_down(struct intel_dp
*intel_dp
)
2035 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2037 uint32_t DP
= intel_dp
->DP
;
2040 * DDI code has a strict mode set sequence and we should try to respect
2041 * it, otherwise we might hang the machine in many different ways. So we
2042 * really should be disabling the port only on a complete crtc_disable
2043 * sequence. This function is just called under two conditions on DDI
2045 * - Link train failed while doing crtc_enable, and on this case we
2046 * really should respect the mode set sequence and wait for a
2048 * - Someone turned the monitor off and intel_dp_check_link_status
2049 * called us. We don't need to disable the whole port on this case, so
2050 * when someone turns the monitor on again,
2051 * intel_ddi_prepare_link_retrain will take care of redoing the link
2054 if (IS_HASWELL(dev
))
2057 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2060 DRM_DEBUG_KMS("\n");
2062 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
2063 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2064 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2066 DP
&= ~DP_LINK_TRAIN_MASK
;
2067 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2069 POSTING_READ(intel_dp
->output_reg
);
2073 if (HAS_PCH_IBX(dev
) &&
2074 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2075 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2077 /* Hardware workaround: leaving our transcoder select
2078 * set to transcoder B while it's off will prevent the
2079 * corresponding HDMI output on transcoder A.
2081 * Combine this with another hardware workaround:
2082 * transcoder select bit can only be cleared while the
2085 DP
&= ~DP_PIPEB_SELECT
;
2086 I915_WRITE(intel_dp
->output_reg
, DP
);
2088 /* Changes to enable or select take place the vblank
2089 * after being written.
2092 /* We can arrive here never having been attached
2093 * to a CRTC, for instance, due to inheriting
2094 * random state from the BIOS.
2096 * If the pipe is not running, play safe and
2097 * wait for the clocks to stabilise before
2100 POSTING_READ(intel_dp
->output_reg
);
2103 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
2106 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2107 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2108 POSTING_READ(intel_dp
->output_reg
);
2109 msleep(intel_dp
->panel_power_down_delay
);
2113 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2115 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2116 sizeof(intel_dp
->dpcd
)) == 0)
2117 return false; /* aux transfer failed */
2119 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2120 return false; /* DPCD not present */
2122 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2123 DP_DWN_STRM_PORT_PRESENT
))
2124 return true; /* native DP sink */
2126 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2127 return true; /* no per-port downstream info */
2129 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2130 intel_dp
->downstream_ports
,
2131 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2132 return false; /* downstream port status fetch failed */
2138 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2142 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2145 ironlake_edp_panel_vdd_on(intel_dp
);
2147 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2148 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2149 buf
[0], buf
[1], buf
[2]);
2151 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2152 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2153 buf
[0], buf
[1], buf
[2]);
2155 ironlake_edp_panel_vdd_off(intel_dp
, false);
2159 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2163 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2164 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2165 sink_irq_vector
, 1);
2173 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2175 /* NAK by default */
2176 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_ACK
);
2180 * According to DP spec
2183 * 2. Configure link according to Receiver Capabilities
2184 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2185 * 4. Check link status on receipt of hot-plug interrupt
2189 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2192 u8 link_status
[DP_LINK_STATUS_SIZE
];
2194 if (!intel_dp
->base
.connectors_active
)
2197 if (WARN_ON(!intel_dp
->base
.base
.crtc
))
2200 /* Try to read receiver status if the link appears to be up */
2201 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2202 intel_dp_link_down(intel_dp
);
2206 /* Now read the DPCD to see if it's actually running */
2207 if (!intel_dp_get_dpcd(intel_dp
)) {
2208 intel_dp_link_down(intel_dp
);
2212 /* Try to read the source of the interrupt */
2213 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2214 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2215 /* Clear interrupt source */
2216 intel_dp_aux_native_write_1(intel_dp
,
2217 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2220 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2221 intel_dp_handle_test_request(intel_dp
);
2222 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2223 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2226 if (!intel_channel_eq_ok(intel_dp
, link_status
)) {
2227 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2228 drm_get_encoder_name(&intel_dp
->base
.base
));
2229 intel_dp_start_link_train(intel_dp
);
2230 intel_dp_complete_link_train(intel_dp
);
2234 /* XXX this is probably wrong for multiple downstream ports */
2235 static enum drm_connector_status
2236 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2238 uint8_t *dpcd
= intel_dp
->dpcd
;
2242 if (!intel_dp_get_dpcd(intel_dp
))
2243 return connector_status_disconnected
;
2245 /* if there's no downstream port, we're done */
2246 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2247 return connector_status_connected
;
2249 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2250 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2253 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2255 return connector_status_unknown
;
2256 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2257 : connector_status_disconnected
;
2260 /* If no HPD, poke DDC gently */
2261 if (drm_probe_ddc(&intel_dp
->adapter
))
2262 return connector_status_connected
;
2264 /* Well we tried, say unknown for unreliable port types */
2265 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2266 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2267 return connector_status_unknown
;
2269 /* Anything else is out of spec, warn and ignore */
2270 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2271 return connector_status_disconnected
;
2274 static enum drm_connector_status
2275 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2277 enum drm_connector_status status
;
2279 /* Can't disconnect eDP, but you can close the lid... */
2280 if (is_edp(intel_dp
)) {
2281 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
2282 if (status
== connector_status_unknown
)
2283 status
= connector_status_connected
;
2287 return intel_dp_detect_dpcd(intel_dp
);
2290 static enum drm_connector_status
2291 g4x_dp_detect(struct intel_dp
*intel_dp
)
2293 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2297 switch (intel_dp
->output_reg
) {
2299 bit
= DPB_HOTPLUG_LIVE_STATUS
;
2302 bit
= DPC_HOTPLUG_LIVE_STATUS
;
2305 bit
= DPD_HOTPLUG_LIVE_STATUS
;
2308 return connector_status_unknown
;
2311 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2312 return connector_status_disconnected
;
2314 return intel_dp_detect_dpcd(intel_dp
);
2317 static struct edid
*
2318 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2320 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2324 if (is_edp(intel_dp
)) {
2325 if (!intel_dp
->edid
)
2328 size
= (intel_dp
->edid
->extensions
+ 1) * EDID_LENGTH
;
2329 edid
= kmalloc(size
, GFP_KERNEL
);
2333 memcpy(edid
, intel_dp
->edid
, size
);
2337 edid
= drm_get_edid(connector
, adapter
);
2342 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2344 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2347 if (is_edp(intel_dp
)) {
2348 drm_mode_connector_update_edid_property(connector
,
2350 ret
= drm_add_edid_modes(connector
, intel_dp
->edid
);
2351 drm_edid_to_eld(connector
,
2353 return intel_dp
->edid_mode_count
;
2356 ret
= intel_ddc_get_modes(connector
, adapter
);
2362 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2364 * \return true if DP port is connected.
2365 * \return false if DP port is disconnected.
2367 static enum drm_connector_status
2368 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2370 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2371 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2372 enum drm_connector_status status
;
2373 struct edid
*edid
= NULL
;
2375 intel_dp
->has_audio
= false;
2377 if (HAS_PCH_SPLIT(dev
))
2378 status
= ironlake_dp_detect(intel_dp
);
2380 status
= g4x_dp_detect(intel_dp
);
2382 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2383 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
2384 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
2385 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
2387 if (status
!= connector_status_connected
)
2390 intel_dp_probe_oui(intel_dp
);
2392 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2393 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2395 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2397 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2402 return connector_status_connected
;
2405 static int intel_dp_get_modes(struct drm_connector
*connector
)
2407 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2408 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2409 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2412 /* We should parse the EDID data and find out if it has an audio sink
2415 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2419 /* if eDP has no EDID, fall back to fixed mode */
2420 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
2421 struct drm_display_mode
*mode
;
2422 mode
= drm_mode_duplicate(dev
,
2423 intel_connector
->panel
.fixed_mode
);
2425 drm_mode_probed_add(connector
, mode
);
2433 intel_dp_detect_audio(struct drm_connector
*connector
)
2435 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2437 bool has_audio
= false;
2439 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2441 has_audio
= drm_detect_monitor_audio(edid
);
2449 intel_dp_set_property(struct drm_connector
*connector
,
2450 struct drm_property
*property
,
2453 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2454 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2457 ret
= drm_connector_property_set_value(connector
, property
, val
);
2461 if (property
== dev_priv
->force_audio_property
) {
2465 if (i
== intel_dp
->force_audio
)
2468 intel_dp
->force_audio
= i
;
2470 if (i
== HDMI_AUDIO_AUTO
)
2471 has_audio
= intel_dp_detect_audio(connector
);
2473 has_audio
= (i
== HDMI_AUDIO_ON
);
2475 if (has_audio
== intel_dp
->has_audio
)
2478 intel_dp
->has_audio
= has_audio
;
2482 if (property
== dev_priv
->broadcast_rgb_property
) {
2483 if (val
== !!intel_dp
->color_range
)
2486 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2493 if (intel_dp
->base
.base
.crtc
) {
2494 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2495 intel_set_mode(crtc
, &crtc
->mode
,
2496 crtc
->x
, crtc
->y
, crtc
->fb
);
2503 intel_dp_destroy(struct drm_connector
*connector
)
2505 struct drm_device
*dev
= connector
->dev
;
2506 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2507 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2509 if (is_edp(intel_dp
)) {
2510 intel_panel_destroy_backlight(dev
);
2511 intel_panel_fini(&intel_connector
->panel
);
2514 drm_sysfs_connector_remove(connector
);
2515 drm_connector_cleanup(connector
);
2519 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2521 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2523 i2c_del_adapter(&intel_dp
->adapter
);
2524 drm_encoder_cleanup(encoder
);
2525 if (is_edp(intel_dp
)) {
2526 kfree(intel_dp
->edid
);
2527 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2528 ironlake_panel_vdd_off_sync(intel_dp
);
2533 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2534 .mode_fixup
= intel_dp_mode_fixup
,
2535 .mode_set
= intel_dp_mode_set
,
2536 .disable
= intel_encoder_noop
,
2539 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw
= {
2540 .mode_fixup
= intel_dp_mode_fixup
,
2541 .mode_set
= intel_ddi_mode_set
,
2542 .disable
= intel_encoder_noop
,
2545 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2546 .dpms
= intel_connector_dpms
,
2547 .detect
= intel_dp_detect
,
2548 .fill_modes
= drm_helper_probe_single_connector_modes
,
2549 .set_property
= intel_dp_set_property
,
2550 .destroy
= intel_dp_destroy
,
2553 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2554 .get_modes
= intel_dp_get_modes
,
2555 .mode_valid
= intel_dp_mode_valid
,
2556 .best_encoder
= intel_best_encoder
,
2559 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2560 .destroy
= intel_dp_encoder_destroy
,
2564 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2566 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
2568 intel_dp_check_link_status(intel_dp
);
2571 /* Return which DP Port should be selected for Transcoder DP control */
2573 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2575 struct drm_device
*dev
= crtc
->dev
;
2576 struct intel_encoder
*encoder
;
2578 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
2579 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2581 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
2582 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
2583 return intel_dp
->output_reg
;
2589 /* check the VBT to see whether the eDP is on DP-D port */
2590 bool intel_dpd_is_edp(struct drm_device
*dev
)
2592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2593 struct child_device_config
*p_child
;
2596 if (!dev_priv
->child_dev_num
)
2599 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2600 p_child
= dev_priv
->child_dev
+ i
;
2602 if (p_child
->dvo_port
== PORT_IDPD
&&
2603 p_child
->device_type
== DEVICE_TYPE_eDP
)
2610 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2612 intel_attach_force_audio_property(connector
);
2613 intel_attach_broadcast_rgb_property(connector
);
2617 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
2619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2620 struct drm_connector
*connector
;
2621 struct intel_dp
*intel_dp
;
2622 struct intel_encoder
*intel_encoder
;
2623 struct intel_connector
*intel_connector
;
2624 struct drm_display_mode
*fixed_mode
= NULL
;
2625 const char *name
= NULL
;
2628 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
2632 intel_dp
->output_reg
= output_reg
;
2633 intel_dp
->port
= port
;
2634 /* Preserve the current hw state. */
2635 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
2637 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2638 if (!intel_connector
) {
2642 intel_encoder
= &intel_dp
->base
;
2643 intel_dp
->attached_connector
= intel_connector
;
2645 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
2646 if (intel_dpd_is_edp(dev
))
2647 intel_dp
->is_pch_edp
= true;
2650 * FIXME : We need to initialize built-in panels before external panels.
2651 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2653 if (IS_VALLEYVIEW(dev
) && output_reg
== DP_C
) {
2654 type
= DRM_MODE_CONNECTOR_eDP
;
2655 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2656 } else if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
2657 type
= DRM_MODE_CONNECTOR_eDP
;
2658 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2660 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2661 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2664 connector
= &intel_connector
->base
;
2665 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2666 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2668 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2670 intel_encoder
->cloneable
= false;
2672 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2673 ironlake_panel_vdd_work
);
2675 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2677 connector
->interlace_allowed
= true;
2678 connector
->doublescan_allowed
= 0;
2680 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2681 DRM_MODE_ENCODER_TMDS
);
2683 if (IS_HASWELL(dev
))
2684 drm_encoder_helper_add(&intel_encoder
->base
,
2685 &intel_dp_helper_funcs_hsw
);
2687 drm_encoder_helper_add(&intel_encoder
->base
,
2688 &intel_dp_helper_funcs
);
2690 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2691 drm_sysfs_connector_add(connector
);
2693 if (IS_HASWELL(dev
)) {
2694 intel_encoder
->enable
= intel_enable_ddi
;
2695 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
2696 intel_encoder
->disable
= intel_disable_ddi
;
2697 intel_encoder
->post_disable
= intel_ddi_post_disable
;
2698 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
2700 intel_encoder
->enable
= intel_enable_dp
;
2701 intel_encoder
->pre_enable
= intel_pre_enable_dp
;
2702 intel_encoder
->disable
= intel_disable_dp
;
2703 intel_encoder
->post_disable
= intel_post_disable_dp
;
2704 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
2706 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2708 /* Set up the DDC bus. */
2714 dev_priv
->hotplug_supported_mask
|= DPB_HOTPLUG_INT_STATUS
;
2718 dev_priv
->hotplug_supported_mask
|= DPC_HOTPLUG_INT_STATUS
;
2722 dev_priv
->hotplug_supported_mask
|= DPD_HOTPLUG_INT_STATUS
;
2726 WARN(1, "Invalid port %c\n", port_name(port
));
2730 /* Cache some DPCD data in the eDP case */
2731 if (is_edp(intel_dp
)) {
2732 struct edp_power_seq cur
, vbt
;
2733 u32 pp_on
, pp_off
, pp_div
;
2735 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2736 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2737 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2739 if (!pp_on
|| !pp_off
|| !pp_div
) {
2740 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2741 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2742 intel_dp_destroy(&intel_connector
->base
);
2746 /* Pull timing values out of registers */
2747 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2748 PANEL_POWER_UP_DELAY_SHIFT
;
2750 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2751 PANEL_LIGHT_ON_DELAY_SHIFT
;
2753 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2754 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2756 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2757 PANEL_POWER_DOWN_DELAY_SHIFT
;
2759 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2760 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2762 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2763 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2765 vbt
= dev_priv
->edp
.pps
;
2767 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2768 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2770 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2772 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2773 intel_dp
->backlight_on_delay
= get_delay(t8
);
2774 intel_dp
->backlight_off_delay
= get_delay(t9
);
2775 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2776 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2778 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2779 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2780 intel_dp
->panel_power_cycle_delay
);
2782 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2783 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2786 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2788 if (is_edp(intel_dp
)) {
2790 struct drm_display_mode
*scan
;
2793 ironlake_edp_panel_vdd_on(intel_dp
);
2794 ret
= intel_dp_get_dpcd(intel_dp
);
2795 ironlake_edp_panel_vdd_off(intel_dp
, false);
2798 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2799 dev_priv
->no_aux_handshake
=
2800 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2801 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2803 /* if this fails, presume the device is a ghost */
2804 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2805 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2806 intel_dp_destroy(&intel_connector
->base
);
2810 ironlake_edp_panel_vdd_on(intel_dp
);
2811 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2813 drm_mode_connector_update_edid_property(connector
,
2815 intel_dp
->edid_mode_count
=
2816 drm_add_edid_modes(connector
, edid
);
2817 drm_edid_to_eld(connector
, edid
);
2818 intel_dp
->edid
= edid
;
2821 /* prefer fixed mode from EDID if available */
2822 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
2823 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2824 fixed_mode
= drm_mode_duplicate(dev
, scan
);
2829 /* fallback to VBT if available for eDP */
2830 if (!fixed_mode
&& dev_priv
->lfp_lvds_vbt_mode
) {
2831 fixed_mode
= drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2833 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
2836 ironlake_edp_panel_vdd_off(intel_dp
, false);
2839 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2841 if (is_edp(intel_dp
)) {
2842 intel_panel_init(&intel_connector
->panel
, fixed_mode
);
2843 intel_panel_setup_backlight(connector
);
2846 intel_dp_add_properties(intel_dp
, connector
);
2848 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2849 * 0xd. Failure to do so will result in spurious interrupts being
2850 * generated on the port when a cable is not attached.
2852 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2853 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2854 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);