2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
118 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
120 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
121 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
123 switch (max_link_bw
) {
124 case DP_LINK_BW_1_62
:
127 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
129 INTEL_INFO(dev
)->gen
>= 8) &&
130 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
131 max_link_bw
= DP_LINK_BW_5_4
;
133 max_link_bw
= DP_LINK_BW_2_7
;
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw
= DP_LINK_BW_1_62
;
144 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
147 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
148 u8 source_max
, sink_max
;
151 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
152 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
155 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
157 return min(source_max
, sink_max
);
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock
, int bpp
)
180 return (pixel_clock
* bpp
+ 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
186 return (max_link_clock
* max_lanes
* 8) / 10;
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector
*connector
,
191 struct drm_display_mode
*mode
)
193 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
194 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
195 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
196 int target_clock
= mode
->clock
;
197 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
199 if (is_edp(intel_dp
) && fixed_mode
) {
200 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
203 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
206 target_clock
= fixed_mode
->clock
;
209 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
210 max_lanes
= intel_dp_max_lane_count(intel_dp
);
212 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 mode_rate
= intel_dp_link_required(target_clock
, 18);
215 if (mode_rate
> max_rate
)
216 return MODE_CLOCK_HIGH
;
218 if (mode
->clock
< 10000)
219 return MODE_CLOCK_LOW
;
221 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
222 return MODE_H_ILLEGAL
;
228 pack_aux(uint8_t *src
, int src_bytes
)
235 for (i
= 0; i
< src_bytes
; i
++)
236 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
241 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
246 for (i
= 0; i
< dst_bytes
; i
++)
247 dst
[i
] = src
>> ((3-i
) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device
*dev
)
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev
))
261 clkcfg
= I915_READ(CLKCFG
);
262 switch (clkcfg
& CLKCFG_FSB_MASK
) {
271 case CLKCFG_FSB_1067
:
273 case CLKCFG_FSB_1333
:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600
:
277 case CLKCFG_FSB_1600_ALT
:
285 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
286 struct intel_dp
*intel_dp
,
287 struct edp_power_seq
*out
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
,
291 struct edp_power_seq
*out
);
294 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
296 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
297 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
298 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
300 enum port port
= intel_dig_port
->port
;
303 /* modeset should have pipe */
305 return to_intel_crtc(crtc
)->pipe
;
307 /* init time, try to find a pipe with this port selected */
308 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
309 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
310 PANEL_PORT_SELECT_MASK
;
311 if (port_sel
== PANEL_PORT_SELECT_DPB_VLV
&& port
== PORT_B
)
313 if (port_sel
== PANEL_PORT_SELECT_DPC_VLV
&& port
== PORT_C
)
321 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
323 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
325 if (HAS_PCH_SPLIT(dev
))
326 return PCH_PP_CONTROL
;
328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
331 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
333 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
335 if (HAS_PCH_SPLIT(dev
))
336 return PCH_PP_STATUS
;
338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
341 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
342 This function only applicable when panel PM state is not to be tracked */
343 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
346 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
348 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 u32 pp_ctrl_reg
, pp_div_reg
;
352 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
354 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
357 if (IS_VALLEYVIEW(dev
)) {
358 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
359 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
360 pp_div
= I915_READ(pp_div_reg
);
361 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
363 /* 0x1F write to PP_DIV_REG sets max cycle delay */
364 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
365 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
366 msleep(intel_dp
->panel_power_cycle_delay
);
372 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
374 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
377 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
380 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
382 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
384 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
385 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
386 enum intel_display_power_domain power_domain
;
388 power_domain
= intel_display_port_power_domain(intel_encoder
);
389 return intel_display_power_enabled(dev_priv
, power_domain
) &&
390 (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
394 intel_dp_check_edp(struct intel_dp
*intel_dp
)
396 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
399 if (!is_edp(intel_dp
))
402 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
403 WARN(1, "eDP powered off while attempting aux channel communication.\n");
404 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
405 I915_READ(_pp_stat_reg(intel_dp
)),
406 I915_READ(_pp_ctrl_reg(intel_dp
)));
411 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
413 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
414 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
416 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
420 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
422 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
423 msecs_to_jiffies_timeout(10));
425 done
= wait_for_atomic(C
, 10) == 0;
427 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
434 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
436 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
437 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
440 * The clock divider is based off the hrawclk, and would like to run at
441 * 2MHz. So, take the hrawclk value and divide by 2 and use that
443 return index
? 0 : intel_hrawclk(dev
) / 2;
446 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
448 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
449 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
454 if (intel_dig_port
->port
== PORT_A
) {
455 if (IS_GEN6(dev
) || IS_GEN7(dev
))
456 return 200; /* SNB & IVB eDP input clock at 400Mhz */
458 return 225; /* eDP input clock at 450Mhz */
460 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
464 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
466 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
467 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
470 if (intel_dig_port
->port
== PORT_A
) {
473 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
474 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
475 /* Workaround for non-ULT HSW */
482 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
486 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
488 return index
? 0 : 100;
491 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
494 uint32_t aux_clock_divider
)
496 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
497 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
498 uint32_t precharge
, timeout
;
505 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
506 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
508 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
510 return DP_AUX_CH_CTL_SEND_BUSY
|
512 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
513 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
515 DP_AUX_CH_CTL_RECEIVE_ERROR
|
516 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
517 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
518 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
522 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
523 uint8_t *send
, int send_bytes
,
524 uint8_t *recv
, int recv_size
)
526 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
527 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
529 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
530 uint32_t ch_data
= ch_ctl
+ 4;
531 uint32_t aux_clock_divider
;
532 int i
, ret
, recv_bytes
;
535 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
538 vdd
= _edp_panel_vdd_on(intel_dp
);
540 /* dp aux is extremely sensitive to irq latency, hence request the
541 * lowest possible wakeup latency and so prevent the cpu from going into
544 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
546 intel_dp_check_edp(intel_dp
);
548 intel_aux_display_runtime_get(dev_priv
);
550 /* Try to wait for any previous AUX channel activity */
551 for (try = 0; try < 3; try++) {
552 status
= I915_READ_NOTRACE(ch_ctl
);
553 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
559 WARN(1, "dp_aux_ch not started status 0x%08x\n",
565 /* Only 5 data registers! */
566 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
571 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
572 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
577 /* Must try at least 3 times according to DP spec */
578 for (try = 0; try < 5; try++) {
579 /* Load the send data into the aux channel data registers */
580 for (i
= 0; i
< send_bytes
; i
+= 4)
581 I915_WRITE(ch_data
+ i
,
582 pack_aux(send
+ i
, send_bytes
- i
));
584 /* Send the command and wait for it to complete */
585 I915_WRITE(ch_ctl
, send_ctl
);
587 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
589 /* Clear done status and any errors */
593 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
594 DP_AUX_CH_CTL_RECEIVE_ERROR
);
596 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
597 DP_AUX_CH_CTL_RECEIVE_ERROR
))
599 if (status
& DP_AUX_CH_CTL_DONE
)
602 if (status
& DP_AUX_CH_CTL_DONE
)
606 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
607 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
612 /* Check for timeout or receive error.
613 * Timeouts occur when the sink is not connected
615 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
616 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
621 /* Timeouts occur when the device isn't connected, so they're
622 * "normal" -- don't fill the kernel log with these */
623 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
624 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
629 /* Unload any bytes sent back from the other side */
630 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
631 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
632 if (recv_bytes
> recv_size
)
633 recv_bytes
= recv_size
;
635 for (i
= 0; i
< recv_bytes
; i
+= 4)
636 unpack_aux(I915_READ(ch_data
+ i
),
637 recv
+ i
, recv_bytes
- i
);
641 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
642 intel_aux_display_runtime_put(dev_priv
);
645 edp_panel_vdd_off(intel_dp
, false);
650 #define BARE_ADDRESS_SIZE 3
651 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
653 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
655 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
656 uint8_t txbuf
[20], rxbuf
[20];
657 size_t txsize
, rxsize
;
660 txbuf
[0] = msg
->request
<< 4;
661 txbuf
[1] = msg
->address
>> 8;
662 txbuf
[2] = msg
->address
& 0xff;
663 txbuf
[3] = msg
->size
- 1;
665 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
666 case DP_AUX_NATIVE_WRITE
:
667 case DP_AUX_I2C_WRITE
:
668 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
671 if (WARN_ON(txsize
> 20))
674 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
676 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
678 msg
->reply
= rxbuf
[0] >> 4;
680 /* Return payload size. */
685 case DP_AUX_NATIVE_READ
:
686 case DP_AUX_I2C_READ
:
687 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
688 rxsize
= msg
->size
+ 1;
690 if (WARN_ON(rxsize
> 20))
693 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
695 msg
->reply
= rxbuf
[0] >> 4;
697 * Assume happy day, and copy the data. The caller is
698 * expected to check msg->reply before touching it.
700 * Return payload size.
703 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
716 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
718 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
719 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
720 enum port port
= intel_dig_port
->port
;
721 const char *name
= NULL
;
726 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
730 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
734 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
738 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
746 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
748 intel_dp
->aux
.name
= name
;
749 intel_dp
->aux
.dev
= dev
->dev
;
750 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
752 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
753 connector
->base
.kdev
->kobj
.name
);
755 ret
= drm_dp_aux_register(&intel_dp
->aux
);
757 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
762 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
763 &intel_dp
->aux
.ddc
.dev
.kobj
,
764 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
766 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
767 drm_dp_aux_unregister(&intel_dp
->aux
);
772 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
774 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
776 if (!intel_connector
->mst_port
)
777 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
778 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
779 intel_connector_unregister(intel_connector
);
783 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
786 case DP_LINK_BW_1_62
:
787 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
790 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
793 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
799 intel_dp_set_clock(struct intel_encoder
*encoder
,
800 struct intel_crtc_config
*pipe_config
, int link_bw
)
802 struct drm_device
*dev
= encoder
->base
.dev
;
803 const struct dp_link_dpll
*divisor
= NULL
;
808 count
= ARRAY_SIZE(gen4_dpll
);
809 } else if (HAS_PCH_SPLIT(dev
)) {
811 count
= ARRAY_SIZE(pch_dpll
);
812 } else if (IS_CHERRYVIEW(dev
)) {
814 count
= ARRAY_SIZE(chv_dpll
);
815 } else if (IS_VALLEYVIEW(dev
)) {
817 count
= ARRAY_SIZE(vlv_dpll
);
820 if (divisor
&& count
) {
821 for (i
= 0; i
< count
; i
++) {
822 if (link_bw
== divisor
[i
].link_bw
) {
823 pipe_config
->dpll
= divisor
[i
].dpll
;
824 pipe_config
->clock_set
= true;
832 intel_dp_set_m2_n2(struct intel_crtc
*crtc
, struct intel_link_m_n
*m_n
)
834 struct drm_device
*dev
= crtc
->base
.dev
;
835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
836 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
838 I915_WRITE(PIPE_DATA_M2(transcoder
),
839 TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
840 I915_WRITE(PIPE_DATA_N2(transcoder
), m_n
->gmch_n
);
841 I915_WRITE(PIPE_LINK_M2(transcoder
), m_n
->link_m
);
842 I915_WRITE(PIPE_LINK_N2(transcoder
), m_n
->link_n
);
846 intel_dp_compute_config(struct intel_encoder
*encoder
,
847 struct intel_crtc_config
*pipe_config
)
849 struct drm_device
*dev
= encoder
->base
.dev
;
850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
851 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
852 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
853 enum port port
= dp_to_dig_port(intel_dp
)->port
;
854 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
855 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
856 int lane_count
, clock
;
857 int min_lane_count
= 1;
858 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
859 /* Conveniently, the link BW constants become indices with a shift...*/
861 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
863 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
864 int link_avail
, link_clock
;
866 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
867 pipe_config
->has_pch_encoder
= true;
869 pipe_config
->has_dp_encoder
= true;
870 pipe_config
->has_audio
= intel_dp
->has_audio
;
872 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
873 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
875 if (!HAS_PCH_SPLIT(dev
))
876 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
877 intel_connector
->panel
.fitting_mode
);
879 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
880 intel_connector
->panel
.fitting_mode
);
883 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
886 DRM_DEBUG_KMS("DP link computation with max lane count %i "
887 "max bw %02x pixel clock %iKHz\n",
888 max_lane_count
, bws
[max_clock
],
889 adjusted_mode
->crtc_clock
);
891 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
893 bpp
= pipe_config
->pipe_bpp
;
894 if (is_edp(intel_dp
)) {
895 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
896 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
897 dev_priv
->vbt
.edp_bpp
);
898 bpp
= dev_priv
->vbt
.edp_bpp
;
901 if (IS_BROADWELL(dev
)) {
902 /* Yes, it's an ugly hack. */
903 min_lane_count
= max_lane_count
;
904 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
906 } else if (dev_priv
->vbt
.edp_lanes
) {
907 min_lane_count
= min(dev_priv
->vbt
.edp_lanes
,
909 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
913 if (dev_priv
->vbt
.edp_rate
) {
914 min_clock
= min(dev_priv
->vbt
.edp_rate
>> 3, max_clock
);
915 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
920 for (; bpp
>= 6*3; bpp
-= 2*3) {
921 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
924 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
925 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
926 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
927 link_avail
= intel_dp_max_data_rate(link_clock
,
930 if (mode_rate
<= link_avail
) {
940 if (intel_dp
->color_range_auto
) {
943 * CEA-861-E - 5.1 Default Encoding Parameters
944 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
946 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
947 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
949 intel_dp
->color_range
= 0;
952 if (intel_dp
->color_range
)
953 pipe_config
->limited_color_range
= true;
955 intel_dp
->link_bw
= bws
[clock
];
956 intel_dp
->lane_count
= lane_count
;
957 pipe_config
->pipe_bpp
= bpp
;
958 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
960 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
961 intel_dp
->link_bw
, intel_dp
->lane_count
,
962 pipe_config
->port_clock
, bpp
);
963 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
964 mode_rate
, link_avail
);
966 intel_link_compute_m_n(bpp
, lane_count
,
967 adjusted_mode
->crtc_clock
,
968 pipe_config
->port_clock
,
969 &pipe_config
->dp_m_n
);
971 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
972 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
973 intel_link_compute_m_n(bpp
, lane_count
,
974 intel_connector
->panel
.downclock_mode
->clock
,
975 pipe_config
->port_clock
,
976 &pipe_config
->dp_m2_n2
);
980 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
982 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
987 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
989 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
990 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
991 struct drm_device
*dev
= crtc
->base
.dev
;
992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
995 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
996 dpa_ctl
= I915_READ(DP_A
);
997 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
999 if (crtc
->config
.port_clock
== 162000) {
1000 /* For a long time we've carried around a ILK-DevA w/a for the
1001 * 160MHz clock. If we're really unlucky, it's still required.
1003 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1004 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1005 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1007 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1008 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1011 I915_WRITE(DP_A
, dpa_ctl
);
1017 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1019 struct drm_device
*dev
= encoder
->base
.dev
;
1020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1021 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1022 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1023 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1024 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1027 * There are four kinds of DP registers:
1034 * IBX PCH and CPU are the same for almost everything,
1035 * except that the CPU DP PLL is configured in this
1038 * CPT PCH is quite different, having many bits moved
1039 * to the TRANS_DP_CTL register instead. That
1040 * configuration happens (oddly) in ironlake_pch_enable
1043 /* Preserve the BIOS-computed detected bit. This is
1044 * supposed to be read-only.
1046 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1048 /* Handle DP bits in common between all three register formats */
1049 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1050 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1052 if (crtc
->config
.has_audio
) {
1053 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1054 pipe_name(crtc
->pipe
));
1055 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1056 intel_write_eld(&encoder
->base
, adjusted_mode
);
1059 /* Split out the IBX/CPU vs CPT settings */
1061 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1062 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1063 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1064 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1065 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1066 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1068 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1069 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1071 intel_dp
->DP
|= crtc
->pipe
<< 29;
1072 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1073 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1074 intel_dp
->DP
|= intel_dp
->color_range
;
1076 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1077 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1078 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1079 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1080 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1082 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1083 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1085 if (!IS_CHERRYVIEW(dev
)) {
1086 if (crtc
->pipe
== 1)
1087 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1089 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1092 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1096 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1097 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1099 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1100 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1102 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1103 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1105 static void wait_panel_status(struct intel_dp
*intel_dp
,
1109 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1111 u32 pp_stat_reg
, pp_ctrl_reg
;
1113 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1114 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1116 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1118 I915_READ(pp_stat_reg
),
1119 I915_READ(pp_ctrl_reg
));
1121 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1122 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1123 I915_READ(pp_stat_reg
),
1124 I915_READ(pp_ctrl_reg
));
1127 DRM_DEBUG_KMS("Wait complete\n");
1130 static void wait_panel_on(struct intel_dp
*intel_dp
)
1132 DRM_DEBUG_KMS("Wait for panel power on\n");
1133 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1136 static void wait_panel_off(struct intel_dp
*intel_dp
)
1138 DRM_DEBUG_KMS("Wait for panel power off time\n");
1139 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1142 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1144 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1146 /* When we disable the VDD override bit last we have to do the manual
1148 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1149 intel_dp
->panel_power_cycle_delay
);
1151 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1154 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1156 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1157 intel_dp
->backlight_on_delay
);
1160 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1162 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1163 intel_dp
->backlight_off_delay
);
1166 /* Read the current pp_control value, unlocking the register if it
1170 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1172 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1176 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1177 control
&= ~PANEL_UNLOCK_MASK
;
1178 control
|= PANEL_UNLOCK_REGS
;
1182 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1184 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1185 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1186 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1188 enum intel_display_power_domain power_domain
;
1190 u32 pp_stat_reg
, pp_ctrl_reg
;
1191 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1193 if (!is_edp(intel_dp
))
1196 intel_dp
->want_panel_vdd
= true;
1198 if (edp_have_panel_vdd(intel_dp
))
1199 return need_to_disable
;
1201 power_domain
= intel_display_port_power_domain(intel_encoder
);
1202 intel_display_power_get(dev_priv
, power_domain
);
1204 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1206 if (!edp_have_panel_power(intel_dp
))
1207 wait_panel_power_cycle(intel_dp
);
1209 pp
= ironlake_get_pp_control(intel_dp
);
1210 pp
|= EDP_FORCE_VDD
;
1212 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1213 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1215 I915_WRITE(pp_ctrl_reg
, pp
);
1216 POSTING_READ(pp_ctrl_reg
);
1217 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1218 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1220 * If the panel wasn't on, delay before accessing aux channel
1222 if (!edp_have_panel_power(intel_dp
)) {
1223 DRM_DEBUG_KMS("eDP was not running\n");
1224 msleep(intel_dp
->panel_power_up_delay
);
1227 return need_to_disable
;
1230 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1232 if (is_edp(intel_dp
)) {
1233 bool vdd
= _edp_panel_vdd_on(intel_dp
);
1235 WARN(!vdd
, "eDP VDD already requested on\n");
1239 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1241 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1244 u32 pp_stat_reg
, pp_ctrl_reg
;
1246 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
1248 if (!intel_dp
->want_panel_vdd
&& edp_have_panel_vdd(intel_dp
)) {
1249 struct intel_digital_port
*intel_dig_port
=
1250 dp_to_dig_port(intel_dp
);
1251 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1252 enum intel_display_power_domain power_domain
;
1254 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1256 pp
= ironlake_get_pp_control(intel_dp
);
1257 pp
&= ~EDP_FORCE_VDD
;
1259 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1260 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1262 I915_WRITE(pp_ctrl_reg
, pp
);
1263 POSTING_READ(pp_ctrl_reg
);
1265 /* Make sure sequencer is idle before allowing subsequent activity */
1266 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1267 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1269 if ((pp
& POWER_TARGET_ON
) == 0)
1270 intel_dp
->last_power_cycle
= jiffies
;
1272 power_domain
= intel_display_port_power_domain(intel_encoder
);
1273 intel_display_power_put(dev_priv
, power_domain
);
1277 static void edp_panel_vdd_work(struct work_struct
*__work
)
1279 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1280 struct intel_dp
, panel_vdd_work
);
1281 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1283 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
1284 edp_panel_vdd_off_sync(intel_dp
);
1285 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
1288 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1290 unsigned long delay
;
1293 * Queue the timer to fire a long time from now (relative to the power
1294 * down delay) to keep the panel power up across a sequence of
1297 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1298 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1301 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1303 if (!is_edp(intel_dp
))
1306 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1308 intel_dp
->want_panel_vdd
= false;
1311 edp_panel_vdd_off_sync(intel_dp
);
1313 edp_panel_vdd_schedule_off(intel_dp
);
1316 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1318 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1323 if (!is_edp(intel_dp
))
1326 DRM_DEBUG_KMS("Turn eDP power on\n");
1328 if (edp_have_panel_power(intel_dp
)) {
1329 DRM_DEBUG_KMS("eDP power already on\n");
1333 wait_panel_power_cycle(intel_dp
);
1335 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1336 pp
= ironlake_get_pp_control(intel_dp
);
1338 /* ILK workaround: disable reset around power sequence */
1339 pp
&= ~PANEL_POWER_RESET
;
1340 I915_WRITE(pp_ctrl_reg
, pp
);
1341 POSTING_READ(pp_ctrl_reg
);
1344 pp
|= POWER_TARGET_ON
;
1346 pp
|= PANEL_POWER_RESET
;
1348 I915_WRITE(pp_ctrl_reg
, pp
);
1349 POSTING_READ(pp_ctrl_reg
);
1351 wait_panel_on(intel_dp
);
1352 intel_dp
->last_power_on
= jiffies
;
1355 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1356 I915_WRITE(pp_ctrl_reg
, pp
);
1357 POSTING_READ(pp_ctrl_reg
);
1361 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1363 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1364 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1365 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1367 enum intel_display_power_domain power_domain
;
1371 if (!is_edp(intel_dp
))
1374 DRM_DEBUG_KMS("Turn eDP power off\n");
1376 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1378 pp
= ironlake_get_pp_control(intel_dp
);
1379 /* We need to switch off panel power _and_ force vdd, for otherwise some
1380 * panels get very unhappy and cease to work. */
1381 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1384 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1386 intel_dp
->want_panel_vdd
= false;
1388 I915_WRITE(pp_ctrl_reg
, pp
);
1389 POSTING_READ(pp_ctrl_reg
);
1391 intel_dp
->last_power_cycle
= jiffies
;
1392 wait_panel_off(intel_dp
);
1394 /* We got a reference when we enabled the VDD. */
1395 power_domain
= intel_display_port_power_domain(intel_encoder
);
1396 intel_display_power_put(dev_priv
, power_domain
);
1399 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1401 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1402 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1407 if (!is_edp(intel_dp
))
1410 DRM_DEBUG_KMS("\n");
1412 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1415 * If we enable the backlight right away following a panel power
1416 * on, we may see slight flicker as the panel syncs with the eDP
1417 * link. So delay a bit to make sure the image is solid before
1418 * allowing it to appear.
1420 wait_backlight_on(intel_dp
);
1421 pp
= ironlake_get_pp_control(intel_dp
);
1422 pp
|= EDP_BLC_ENABLE
;
1424 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1426 I915_WRITE(pp_ctrl_reg
, pp
);
1427 POSTING_READ(pp_ctrl_reg
);
1430 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1432 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1437 if (!is_edp(intel_dp
))
1440 DRM_DEBUG_KMS("\n");
1441 pp
= ironlake_get_pp_control(intel_dp
);
1442 pp
&= ~EDP_BLC_ENABLE
;
1444 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1446 I915_WRITE(pp_ctrl_reg
, pp
);
1447 POSTING_READ(pp_ctrl_reg
);
1448 intel_dp
->last_backlight_off
= jiffies
;
1450 edp_wait_backlight_off(intel_dp
);
1452 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1455 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1457 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1458 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1459 struct drm_device
*dev
= crtc
->dev
;
1460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1463 assert_pipe_disabled(dev_priv
,
1464 to_intel_crtc(crtc
)->pipe
);
1466 DRM_DEBUG_KMS("\n");
1467 dpa_ctl
= I915_READ(DP_A
);
1468 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1469 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1471 /* We don't adjust intel_dp->DP while tearing down the link, to
1472 * facilitate link retraining (e.g. after hotplug). Hence clear all
1473 * enable bits here to ensure that we don't enable too much. */
1474 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1475 intel_dp
->DP
|= DP_PLL_ENABLE
;
1476 I915_WRITE(DP_A
, intel_dp
->DP
);
1481 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1483 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1484 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1485 struct drm_device
*dev
= crtc
->dev
;
1486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1489 assert_pipe_disabled(dev_priv
,
1490 to_intel_crtc(crtc
)->pipe
);
1492 dpa_ctl
= I915_READ(DP_A
);
1493 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1494 "dp pll off, should be on\n");
1495 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1497 /* We can't rely on the value tracked for the DP register in
1498 * intel_dp->DP because link_down must not change that (otherwise link
1499 * re-training will fail. */
1500 dpa_ctl
&= ~DP_PLL_ENABLE
;
1501 I915_WRITE(DP_A
, dpa_ctl
);
1506 /* If the sink supports it, try to set the power state appropriately */
1507 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1511 /* Should have a valid DPCD by this point */
1512 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1515 if (mode
!= DRM_MODE_DPMS_ON
) {
1516 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1519 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1522 * When turning on, we need to retry for 1ms to give the sink
1525 for (i
= 0; i
< 3; i
++) {
1526 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1535 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1538 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1539 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1540 struct drm_device
*dev
= encoder
->base
.dev
;
1541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1542 enum intel_display_power_domain power_domain
;
1545 power_domain
= intel_display_port_power_domain(encoder
);
1546 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1549 tmp
= I915_READ(intel_dp
->output_reg
);
1551 if (!(tmp
& DP_PORT_EN
))
1554 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1555 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1556 } else if (IS_CHERRYVIEW(dev
)) {
1557 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1558 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1559 *pipe
= PORT_TO_PIPE(tmp
);
1565 switch (intel_dp
->output_reg
) {
1567 trans_sel
= TRANS_DP_PORT_SEL_B
;
1570 trans_sel
= TRANS_DP_PORT_SEL_C
;
1573 trans_sel
= TRANS_DP_PORT_SEL_D
;
1580 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1581 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1587 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1588 intel_dp
->output_reg
);
1594 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1595 struct intel_crtc_config
*pipe_config
)
1597 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1599 struct drm_device
*dev
= encoder
->base
.dev
;
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1601 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1602 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1605 tmp
= I915_READ(intel_dp
->output_reg
);
1606 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1607 pipe_config
->has_audio
= true;
1609 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1610 if (tmp
& DP_SYNC_HS_HIGH
)
1611 flags
|= DRM_MODE_FLAG_PHSYNC
;
1613 flags
|= DRM_MODE_FLAG_NHSYNC
;
1615 if (tmp
& DP_SYNC_VS_HIGH
)
1616 flags
|= DRM_MODE_FLAG_PVSYNC
;
1618 flags
|= DRM_MODE_FLAG_NVSYNC
;
1620 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1621 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1622 flags
|= DRM_MODE_FLAG_PHSYNC
;
1624 flags
|= DRM_MODE_FLAG_NHSYNC
;
1626 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1627 flags
|= DRM_MODE_FLAG_PVSYNC
;
1629 flags
|= DRM_MODE_FLAG_NVSYNC
;
1632 pipe_config
->adjusted_mode
.flags
|= flags
;
1634 pipe_config
->has_dp_encoder
= true;
1636 intel_dp_get_m_n(crtc
, pipe_config
);
1638 if (port
== PORT_A
) {
1639 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1640 pipe_config
->port_clock
= 162000;
1642 pipe_config
->port_clock
= 270000;
1645 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1646 &pipe_config
->dp_m_n
);
1648 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1649 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1651 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1653 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1654 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1656 * This is a big fat ugly hack.
1658 * Some machines in UEFI boot mode provide us a VBT that has 18
1659 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1660 * unknown we fail to light up. Yet the same BIOS boots up with
1661 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1662 * max, not what it tells us to use.
1664 * Note: This will still be broken if the eDP panel is not lit
1665 * up by the BIOS, and thus we can't get the mode at module
1668 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1669 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1670 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1674 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1676 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1679 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1686 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1689 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1690 struct edp_vsc_psr
*vsc_psr
)
1692 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1693 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1695 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1696 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1697 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1698 uint32_t *data
= (uint32_t *) vsc_psr
;
1701 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1702 the video DIP being updated before program video DIP data buffer
1703 registers for DIP being updated. */
1704 I915_WRITE(ctl_reg
, 0);
1705 POSTING_READ(ctl_reg
);
1707 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1708 if (i
< sizeof(struct edp_vsc_psr
))
1709 I915_WRITE(data_reg
+ i
, *data
++);
1711 I915_WRITE(data_reg
+ i
, 0);
1714 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1715 POSTING_READ(ctl_reg
);
1718 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1720 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1722 struct edp_vsc_psr psr_vsc
;
1724 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1725 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1726 psr_vsc
.sdp_header
.HB0
= 0;
1727 psr_vsc
.sdp_header
.HB1
= 0x7;
1728 psr_vsc
.sdp_header
.HB2
= 0x2;
1729 psr_vsc
.sdp_header
.HB3
= 0x8;
1730 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1732 /* Avoid continuous PSR exit by masking memup and hpd */
1733 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1734 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1737 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1739 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1740 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1742 uint32_t aux_clock_divider
;
1743 int precharge
= 0x3;
1744 int msg_size
= 5; /* Header(4) + Message(1) */
1745 bool only_standby
= false;
1747 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
1749 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
1750 only_standby
= true;
1752 /* Enable PSR in sink */
1753 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
1754 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1755 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
1757 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1758 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
1760 /* Setup AUX registers */
1761 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
1762 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
1763 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
1764 DP_AUX_CH_CTL_TIME_OUT_400us
|
1765 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1766 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1767 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1770 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1772 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1773 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1775 uint32_t max_sleep_time
= 0x1f;
1776 uint32_t idle_frames
= 1;
1778 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
1779 bool only_standby
= false;
1781 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
1782 only_standby
= true;
1784 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
1785 val
|= EDP_PSR_LINK_STANDBY
;
1786 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1787 val
|= EDP_PSR_TP1_TIME_0us
;
1788 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1789 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
1791 val
|= EDP_PSR_LINK_DISABLE
;
1793 I915_WRITE(EDP_PSR_CTL(dev
), val
|
1794 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
1795 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1796 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1800 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1802 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1803 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1805 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1806 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1808 lockdep_assert_held(&dev_priv
->psr
.lock
);
1809 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
1810 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
1812 dev_priv
->psr
.source_ok
= false;
1814 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
1815 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1819 if (!i915
.enable_psr
) {
1820 DRM_DEBUG_KMS("PSR disable by flag\n");
1824 /* Below limitations aren't valid for Broadwell */
1825 if (IS_BROADWELL(dev
))
1828 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1830 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1834 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1835 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1840 dev_priv
->psr
.source_ok
= true;
1844 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1846 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1847 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1850 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
1851 WARN_ON(dev_priv
->psr
.active
);
1852 lockdep_assert_held(&dev_priv
->psr
.lock
);
1854 /* Enable PSR on the panel */
1855 intel_edp_psr_enable_sink(intel_dp
);
1857 /* Enable PSR on the host */
1858 intel_edp_psr_enable_source(intel_dp
);
1860 dev_priv
->psr
.active
= true;
1863 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1865 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1868 if (!HAS_PSR(dev
)) {
1869 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1873 if (!is_edp_psr(intel_dp
)) {
1874 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1878 mutex_lock(&dev_priv
->psr
.lock
);
1879 if (dev_priv
->psr
.enabled
) {
1880 DRM_DEBUG_KMS("PSR already in use\n");
1881 mutex_unlock(&dev_priv
->psr
.lock
);
1885 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
1887 /* Setup PSR once */
1888 intel_edp_psr_setup(intel_dp
);
1890 if (intel_edp_psr_match_conditions(intel_dp
))
1891 dev_priv
->psr
.enabled
= intel_dp
;
1892 mutex_unlock(&dev_priv
->psr
.lock
);
1895 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1897 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1900 mutex_lock(&dev_priv
->psr
.lock
);
1901 if (!dev_priv
->psr
.enabled
) {
1902 mutex_unlock(&dev_priv
->psr
.lock
);
1906 if (dev_priv
->psr
.active
) {
1907 I915_WRITE(EDP_PSR_CTL(dev
),
1908 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
1910 /* Wait till PSR is idle */
1911 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
1912 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1913 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1915 dev_priv
->psr
.active
= false;
1917 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
1920 dev_priv
->psr
.enabled
= NULL
;
1921 mutex_unlock(&dev_priv
->psr
.lock
);
1923 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
1926 static void intel_edp_psr_work(struct work_struct
*work
)
1928 struct drm_i915_private
*dev_priv
=
1929 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
1930 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
1932 mutex_lock(&dev_priv
->psr
.lock
);
1933 intel_dp
= dev_priv
->psr
.enabled
;
1939 * The delayed work can race with an invalidate hence we need to
1940 * recheck. Since psr_flush first clears this and then reschedules we
1941 * won't ever miss a flush when bailing out here.
1943 if (dev_priv
->psr
.busy_frontbuffer_bits
)
1946 intel_edp_psr_do_enable(intel_dp
);
1948 mutex_unlock(&dev_priv
->psr
.lock
);
1951 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
1953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1955 if (dev_priv
->psr
.active
) {
1956 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
1958 WARN_ON(!(val
& EDP_PSR_ENABLE
));
1960 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
1962 dev_priv
->psr
.active
= false;
1967 void intel_edp_psr_invalidate(struct drm_device
*dev
,
1968 unsigned frontbuffer_bits
)
1970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1971 struct drm_crtc
*crtc
;
1974 mutex_lock(&dev_priv
->psr
.lock
);
1975 if (!dev_priv
->psr
.enabled
) {
1976 mutex_unlock(&dev_priv
->psr
.lock
);
1980 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
1981 pipe
= to_intel_crtc(crtc
)->pipe
;
1983 intel_edp_psr_do_exit(dev
);
1985 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
1987 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
1988 mutex_unlock(&dev_priv
->psr
.lock
);
1991 void intel_edp_psr_flush(struct drm_device
*dev
,
1992 unsigned frontbuffer_bits
)
1994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1995 struct drm_crtc
*crtc
;
1998 mutex_lock(&dev_priv
->psr
.lock
);
1999 if (!dev_priv
->psr
.enabled
) {
2000 mutex_unlock(&dev_priv
->psr
.lock
);
2004 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2005 pipe
= to_intel_crtc(crtc
)->pipe
;
2006 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2009 * On Haswell sprite plane updates don't result in a psr invalidating
2010 * signal in the hardware. Which means we need to manually fake this in
2011 * software for all flushes, not just when we've seen a preceding
2012 * invalidation through frontbuffer rendering.
2014 if (IS_HASWELL(dev
) &&
2015 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2016 intel_edp_psr_do_exit(dev
);
2018 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2019 schedule_delayed_work(&dev_priv
->psr
.work
,
2020 msecs_to_jiffies(100));
2021 mutex_unlock(&dev_priv
->psr
.lock
);
2024 void intel_edp_psr_init(struct drm_device
*dev
)
2026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2028 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2029 mutex_init(&dev_priv
->psr
.lock
);
2032 static void intel_disable_dp(struct intel_encoder
*encoder
)
2034 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2035 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2036 struct drm_device
*dev
= encoder
->base
.dev
;
2038 /* Make sure the panel is off before trying to change the mode. But also
2039 * ensure that we have vdd while we switch off the panel. */
2040 intel_edp_panel_vdd_on(intel_dp
);
2041 intel_edp_backlight_off(intel_dp
);
2042 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2043 intel_edp_panel_off(intel_dp
);
2045 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2046 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
2047 intel_dp_link_down(intel_dp
);
2050 static void g4x_post_disable_dp(struct intel_encoder
*encoder
)
2052 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2053 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2058 intel_dp_link_down(intel_dp
);
2059 ironlake_edp_pll_off(intel_dp
);
2062 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2064 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2066 intel_dp_link_down(intel_dp
);
2069 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2071 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2072 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2073 struct drm_device
*dev
= encoder
->base
.dev
;
2074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2075 struct intel_crtc
*intel_crtc
=
2076 to_intel_crtc(encoder
->base
.crtc
);
2077 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2078 enum pipe pipe
= intel_crtc
->pipe
;
2081 intel_dp_link_down(intel_dp
);
2083 mutex_lock(&dev_priv
->dpio_lock
);
2085 /* Propagate soft reset to data lane reset */
2086 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2087 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2088 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2090 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2091 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2092 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2094 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2095 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2096 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2098 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2099 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2100 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2102 mutex_unlock(&dev_priv
->dpio_lock
);
2105 static void intel_enable_dp(struct intel_encoder
*encoder
)
2107 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2108 struct drm_device
*dev
= encoder
->base
.dev
;
2109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2110 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2112 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2115 intel_edp_panel_vdd_on(intel_dp
);
2116 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2117 intel_dp_start_link_train(intel_dp
);
2118 intel_edp_panel_on(intel_dp
);
2119 edp_panel_vdd_off(intel_dp
, true);
2120 intel_dp_complete_link_train(intel_dp
);
2121 intel_dp_stop_link_train(intel_dp
);
2124 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2126 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2128 intel_enable_dp(encoder
);
2129 intel_edp_backlight_on(intel_dp
);
2132 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2134 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2136 intel_edp_backlight_on(intel_dp
);
2139 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2141 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2142 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2144 intel_dp_prepare(encoder
);
2146 /* Only ilk+ has port A */
2147 if (dport
->port
== PORT_A
) {
2148 ironlake_set_pll_cpu_edp(intel_dp
);
2149 ironlake_edp_pll_on(intel_dp
);
2153 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2155 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2156 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2157 struct drm_device
*dev
= encoder
->base
.dev
;
2158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2159 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2160 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2161 int pipe
= intel_crtc
->pipe
;
2162 struct edp_power_seq power_seq
;
2165 mutex_lock(&dev_priv
->dpio_lock
);
2167 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2174 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2175 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2176 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2178 mutex_unlock(&dev_priv
->dpio_lock
);
2180 if (is_edp(intel_dp
)) {
2181 /* init power sequencer on this pipe and port */
2182 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2183 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2187 intel_enable_dp(encoder
);
2189 vlv_wait_port_ready(dev_priv
, dport
);
2192 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2194 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2195 struct drm_device
*dev
= encoder
->base
.dev
;
2196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2197 struct intel_crtc
*intel_crtc
=
2198 to_intel_crtc(encoder
->base
.crtc
);
2199 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2200 int pipe
= intel_crtc
->pipe
;
2202 intel_dp_prepare(encoder
);
2204 /* Program Tx lane resets to default */
2205 mutex_lock(&dev_priv
->dpio_lock
);
2206 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2207 DPIO_PCS_TX_LANE2_RESET
|
2208 DPIO_PCS_TX_LANE1_RESET
);
2209 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2210 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2211 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2212 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2213 DPIO_PCS_CLK_SOFT_RESET
);
2215 /* Fix up inter-pair skew failure */
2216 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2217 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2218 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2219 mutex_unlock(&dev_priv
->dpio_lock
);
2222 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2224 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2225 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2226 struct drm_device
*dev
= encoder
->base
.dev
;
2227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2228 struct edp_power_seq power_seq
;
2229 struct intel_crtc
*intel_crtc
=
2230 to_intel_crtc(encoder
->base
.crtc
);
2231 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2232 int pipe
= intel_crtc
->pipe
;
2236 mutex_lock(&dev_priv
->dpio_lock
);
2238 /* Deassert soft data lane reset*/
2239 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2240 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2241 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2243 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2244 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2245 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2247 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2248 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2249 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2251 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2252 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2253 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2255 /* Program Tx lane latency optimal setting*/
2256 for (i
= 0; i
< 4; i
++) {
2257 /* Set the latency optimal bit */
2258 data
= (i
== 1) ? 0x0 : 0x6;
2259 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2260 data
<< DPIO_FRC_LATENCY_SHFIT
);
2262 /* Set the upar bit */
2263 data
= (i
== 1) ? 0x0 : 0x1;
2264 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2265 data
<< DPIO_UPAR_SHIFT
);
2268 /* Data lane stagger programming */
2269 /* FIXME: Fix up value only after power analysis */
2271 mutex_unlock(&dev_priv
->dpio_lock
);
2273 if (is_edp(intel_dp
)) {
2274 /* init power sequencer on this pipe and port */
2275 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2276 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2280 intel_enable_dp(encoder
);
2282 vlv_wait_port_ready(dev_priv
, dport
);
2285 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2287 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2288 struct drm_device
*dev
= encoder
->base
.dev
;
2289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2290 struct intel_crtc
*intel_crtc
=
2291 to_intel_crtc(encoder
->base
.crtc
);
2292 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2293 enum pipe pipe
= intel_crtc
->pipe
;
2296 mutex_lock(&dev_priv
->dpio_lock
);
2298 /* program left/right clock distribution */
2299 if (pipe
!= PIPE_B
) {
2300 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2301 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2303 val
|= CHV_BUFLEFTENA1_FORCE
;
2305 val
|= CHV_BUFRIGHTENA1_FORCE
;
2306 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2308 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2309 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2311 val
|= CHV_BUFLEFTENA2_FORCE
;
2313 val
|= CHV_BUFRIGHTENA2_FORCE
;
2314 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2317 /* program clock channel usage */
2318 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2319 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2321 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2323 val
|= CHV_PCS_USEDCLKCHANNEL
;
2324 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2326 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2327 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2329 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2331 val
|= CHV_PCS_USEDCLKCHANNEL
;
2332 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2335 * This a a bit weird since generally CL
2336 * matches the pipe, but here we need to
2337 * pick the CL based on the port.
2339 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2341 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2343 val
|= CHV_CMN_USEDCLKCHANNEL
;
2344 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2346 mutex_unlock(&dev_priv
->dpio_lock
);
2350 * Native read with retry for link status and receiver capability reads for
2351 * cases where the sink may still be asleep.
2353 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2354 * supposed to retry 3 times per the spec.
2357 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2358 void *buffer
, size_t size
)
2363 for (i
= 0; i
< 3; i
++) {
2364 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2374 * Fetch AUX CH registers 0x202 - 0x207 which contain
2375 * link status information
2378 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2380 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2383 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2386 /* These are source-specific values. */
2388 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2390 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2391 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2393 if (IS_VALLEYVIEW(dev
))
2394 return DP_TRAIN_VOLTAGE_SWING_1200
;
2395 else if (IS_GEN7(dev
) && port
== PORT_A
)
2396 return DP_TRAIN_VOLTAGE_SWING_800
;
2397 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2398 return DP_TRAIN_VOLTAGE_SWING_1200
;
2400 return DP_TRAIN_VOLTAGE_SWING_800
;
2404 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2406 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2407 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2409 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2410 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2411 case DP_TRAIN_VOLTAGE_SWING_400
:
2412 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2413 case DP_TRAIN_VOLTAGE_SWING_600
:
2414 return DP_TRAIN_PRE_EMPHASIS_6
;
2415 case DP_TRAIN_VOLTAGE_SWING_800
:
2416 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2417 case DP_TRAIN_VOLTAGE_SWING_1200
:
2419 return DP_TRAIN_PRE_EMPHASIS_0
;
2421 } else if (IS_VALLEYVIEW(dev
)) {
2422 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2423 case DP_TRAIN_VOLTAGE_SWING_400
:
2424 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2425 case DP_TRAIN_VOLTAGE_SWING_600
:
2426 return DP_TRAIN_PRE_EMPHASIS_6
;
2427 case DP_TRAIN_VOLTAGE_SWING_800
:
2428 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2429 case DP_TRAIN_VOLTAGE_SWING_1200
:
2431 return DP_TRAIN_PRE_EMPHASIS_0
;
2433 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2434 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2435 case DP_TRAIN_VOLTAGE_SWING_400
:
2436 return DP_TRAIN_PRE_EMPHASIS_6
;
2437 case DP_TRAIN_VOLTAGE_SWING_600
:
2438 case DP_TRAIN_VOLTAGE_SWING_800
:
2439 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2441 return DP_TRAIN_PRE_EMPHASIS_0
;
2444 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2445 case DP_TRAIN_VOLTAGE_SWING_400
:
2446 return DP_TRAIN_PRE_EMPHASIS_6
;
2447 case DP_TRAIN_VOLTAGE_SWING_600
:
2448 return DP_TRAIN_PRE_EMPHASIS_6
;
2449 case DP_TRAIN_VOLTAGE_SWING_800
:
2450 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2451 case DP_TRAIN_VOLTAGE_SWING_1200
:
2453 return DP_TRAIN_PRE_EMPHASIS_0
;
2458 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2460 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2462 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2463 struct intel_crtc
*intel_crtc
=
2464 to_intel_crtc(dport
->base
.base
.crtc
);
2465 unsigned long demph_reg_value
, preemph_reg_value
,
2466 uniqtranscale_reg_value
;
2467 uint8_t train_set
= intel_dp
->train_set
[0];
2468 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2469 int pipe
= intel_crtc
->pipe
;
2471 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2472 case DP_TRAIN_PRE_EMPHASIS_0
:
2473 preemph_reg_value
= 0x0004000;
2474 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2475 case DP_TRAIN_VOLTAGE_SWING_400
:
2476 demph_reg_value
= 0x2B405555;
2477 uniqtranscale_reg_value
= 0x552AB83A;
2479 case DP_TRAIN_VOLTAGE_SWING_600
:
2480 demph_reg_value
= 0x2B404040;
2481 uniqtranscale_reg_value
= 0x5548B83A;
2483 case DP_TRAIN_VOLTAGE_SWING_800
:
2484 demph_reg_value
= 0x2B245555;
2485 uniqtranscale_reg_value
= 0x5560B83A;
2487 case DP_TRAIN_VOLTAGE_SWING_1200
:
2488 demph_reg_value
= 0x2B405555;
2489 uniqtranscale_reg_value
= 0x5598DA3A;
2495 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2496 preemph_reg_value
= 0x0002000;
2497 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2498 case DP_TRAIN_VOLTAGE_SWING_400
:
2499 demph_reg_value
= 0x2B404040;
2500 uniqtranscale_reg_value
= 0x5552B83A;
2502 case DP_TRAIN_VOLTAGE_SWING_600
:
2503 demph_reg_value
= 0x2B404848;
2504 uniqtranscale_reg_value
= 0x5580B83A;
2506 case DP_TRAIN_VOLTAGE_SWING_800
:
2507 demph_reg_value
= 0x2B404040;
2508 uniqtranscale_reg_value
= 0x55ADDA3A;
2514 case DP_TRAIN_PRE_EMPHASIS_6
:
2515 preemph_reg_value
= 0x0000000;
2516 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2517 case DP_TRAIN_VOLTAGE_SWING_400
:
2518 demph_reg_value
= 0x2B305555;
2519 uniqtranscale_reg_value
= 0x5570B83A;
2521 case DP_TRAIN_VOLTAGE_SWING_600
:
2522 demph_reg_value
= 0x2B2B4040;
2523 uniqtranscale_reg_value
= 0x55ADDA3A;
2529 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2530 preemph_reg_value
= 0x0006000;
2531 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2532 case DP_TRAIN_VOLTAGE_SWING_400
:
2533 demph_reg_value
= 0x1B405555;
2534 uniqtranscale_reg_value
= 0x55ADDA3A;
2544 mutex_lock(&dev_priv
->dpio_lock
);
2545 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2546 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2547 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2548 uniqtranscale_reg_value
);
2549 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2550 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2551 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2552 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2553 mutex_unlock(&dev_priv
->dpio_lock
);
2558 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
2560 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2562 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2563 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
2564 u32 deemph_reg_value
, margin_reg_value
, val
;
2565 uint8_t train_set
= intel_dp
->train_set
[0];
2566 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2567 enum pipe pipe
= intel_crtc
->pipe
;
2570 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2571 case DP_TRAIN_PRE_EMPHASIS_0
:
2572 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2573 case DP_TRAIN_VOLTAGE_SWING_400
:
2574 deemph_reg_value
= 128;
2575 margin_reg_value
= 52;
2577 case DP_TRAIN_VOLTAGE_SWING_600
:
2578 deemph_reg_value
= 128;
2579 margin_reg_value
= 77;
2581 case DP_TRAIN_VOLTAGE_SWING_800
:
2582 deemph_reg_value
= 128;
2583 margin_reg_value
= 102;
2585 case DP_TRAIN_VOLTAGE_SWING_1200
:
2586 deemph_reg_value
= 128;
2587 margin_reg_value
= 154;
2588 /* FIXME extra to set for 1200 */
2594 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2595 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2596 case DP_TRAIN_VOLTAGE_SWING_400
:
2597 deemph_reg_value
= 85;
2598 margin_reg_value
= 78;
2600 case DP_TRAIN_VOLTAGE_SWING_600
:
2601 deemph_reg_value
= 85;
2602 margin_reg_value
= 116;
2604 case DP_TRAIN_VOLTAGE_SWING_800
:
2605 deemph_reg_value
= 85;
2606 margin_reg_value
= 154;
2612 case DP_TRAIN_PRE_EMPHASIS_6
:
2613 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2614 case DP_TRAIN_VOLTAGE_SWING_400
:
2615 deemph_reg_value
= 64;
2616 margin_reg_value
= 104;
2618 case DP_TRAIN_VOLTAGE_SWING_600
:
2619 deemph_reg_value
= 64;
2620 margin_reg_value
= 154;
2626 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2627 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2628 case DP_TRAIN_VOLTAGE_SWING_400
:
2629 deemph_reg_value
= 43;
2630 margin_reg_value
= 154;
2640 mutex_lock(&dev_priv
->dpio_lock
);
2642 /* Clear calc init */
2643 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2644 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2645 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2647 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2648 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2649 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2651 /* Program swing deemph */
2652 for (i
= 0; i
< 4; i
++) {
2653 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
2654 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
2655 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
2656 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
2659 /* Program swing margin */
2660 for (i
= 0; i
< 4; i
++) {
2661 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2662 val
&= ~DPIO_SWING_MARGIN_MASK
;
2663 val
|= margin_reg_value
<< DPIO_SWING_MARGIN_SHIFT
;
2664 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2667 /* Disable unique transition scale */
2668 for (i
= 0; i
< 4; i
++) {
2669 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2670 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2671 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2674 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
2675 == DP_TRAIN_PRE_EMPHASIS_0
) &&
2676 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
2677 == DP_TRAIN_VOLTAGE_SWING_1200
)) {
2680 * The document said it needs to set bit 27 for ch0 and bit 26
2681 * for ch1. Might be a typo in the doc.
2682 * For now, for this unique transition scale selection, set bit
2683 * 27 for ch0 and ch1.
2685 for (i
= 0; i
< 4; i
++) {
2686 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2687 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2688 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2691 for (i
= 0; i
< 4; i
++) {
2692 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2693 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2694 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2695 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2699 /* Start swing calculation */
2700 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2701 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2702 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2704 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2705 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2706 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2709 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
2710 val
|= DPIO_LRC_BYPASS
;
2711 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
2713 mutex_unlock(&dev_priv
->dpio_lock
);
2719 intel_get_adjust_train(struct intel_dp
*intel_dp
,
2720 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2725 uint8_t voltage_max
;
2726 uint8_t preemph_max
;
2728 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2729 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2730 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2738 voltage_max
= intel_dp_voltage_max(intel_dp
);
2739 if (v
>= voltage_max
)
2740 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2742 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2743 if (p
>= preemph_max
)
2744 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2746 for (lane
= 0; lane
< 4; lane
++)
2747 intel_dp
->train_set
[lane
] = v
| p
;
2751 intel_gen4_signal_levels(uint8_t train_set
)
2753 uint32_t signal_levels
= 0;
2755 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2756 case DP_TRAIN_VOLTAGE_SWING_400
:
2758 signal_levels
|= DP_VOLTAGE_0_4
;
2760 case DP_TRAIN_VOLTAGE_SWING_600
:
2761 signal_levels
|= DP_VOLTAGE_0_6
;
2763 case DP_TRAIN_VOLTAGE_SWING_800
:
2764 signal_levels
|= DP_VOLTAGE_0_8
;
2766 case DP_TRAIN_VOLTAGE_SWING_1200
:
2767 signal_levels
|= DP_VOLTAGE_1_2
;
2770 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2771 case DP_TRAIN_PRE_EMPHASIS_0
:
2773 signal_levels
|= DP_PRE_EMPHASIS_0
;
2775 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2776 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2778 case DP_TRAIN_PRE_EMPHASIS_6
:
2779 signal_levels
|= DP_PRE_EMPHASIS_6
;
2781 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2782 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2785 return signal_levels
;
2788 /* Gen6's DP voltage swing and pre-emphasis control */
2790 intel_gen6_edp_signal_levels(uint8_t train_set
)
2792 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2793 DP_TRAIN_PRE_EMPHASIS_MASK
);
2794 switch (signal_levels
) {
2795 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2796 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2797 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2798 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2799 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2800 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2801 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2802 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2803 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2804 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2805 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2806 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2807 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2808 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2810 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2811 "0x%x\n", signal_levels
);
2812 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2816 /* Gen7's DP voltage swing and pre-emphasis control */
2818 intel_gen7_edp_signal_levels(uint8_t train_set
)
2820 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2821 DP_TRAIN_PRE_EMPHASIS_MASK
);
2822 switch (signal_levels
) {
2823 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2824 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2825 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2826 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2827 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2828 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2830 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2831 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2832 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2833 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2835 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2836 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2837 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2838 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2841 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2842 "0x%x\n", signal_levels
);
2843 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2847 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2849 intel_hsw_signal_levels(uint8_t train_set
)
2851 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2852 DP_TRAIN_PRE_EMPHASIS_MASK
);
2853 switch (signal_levels
) {
2854 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2855 return DDI_BUF_EMP_400MV_0DB_HSW
;
2856 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2857 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2858 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2859 return DDI_BUF_EMP_400MV_6DB_HSW
;
2860 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2861 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2863 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2864 return DDI_BUF_EMP_600MV_0DB_HSW
;
2865 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2866 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2867 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2868 return DDI_BUF_EMP_600MV_6DB_HSW
;
2870 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2871 return DDI_BUF_EMP_800MV_0DB_HSW
;
2872 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2873 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2875 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2876 "0x%x\n", signal_levels
);
2877 return DDI_BUF_EMP_400MV_0DB_HSW
;
2881 /* Properly updates "DP" with the correct signal levels. */
2883 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2885 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2886 enum port port
= intel_dig_port
->port
;
2887 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2888 uint32_t signal_levels
, mask
;
2889 uint8_t train_set
= intel_dp
->train_set
[0];
2891 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2892 signal_levels
= intel_hsw_signal_levels(train_set
);
2893 mask
= DDI_BUF_EMP_MASK
;
2894 } else if (IS_CHERRYVIEW(dev
)) {
2895 signal_levels
= intel_chv_signal_levels(intel_dp
);
2897 } else if (IS_VALLEYVIEW(dev
)) {
2898 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2900 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2901 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2902 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2903 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2904 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2905 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2907 signal_levels
= intel_gen4_signal_levels(train_set
);
2908 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2911 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2913 *DP
= (*DP
& ~mask
) | signal_levels
;
2917 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2919 uint8_t dp_train_pat
)
2921 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2922 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2924 enum port port
= intel_dig_port
->port
;
2925 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
2929 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2931 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2932 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2934 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2936 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2937 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2938 case DP_TRAINING_PATTERN_DISABLE
:
2939 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2942 case DP_TRAINING_PATTERN_1
:
2943 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2945 case DP_TRAINING_PATTERN_2
:
2946 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2948 case DP_TRAINING_PATTERN_3
:
2949 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2952 I915_WRITE(DP_TP_CTL(port
), temp
);
2954 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2955 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2957 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2958 case DP_TRAINING_PATTERN_DISABLE
:
2959 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2961 case DP_TRAINING_PATTERN_1
:
2962 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2964 case DP_TRAINING_PATTERN_2
:
2965 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2967 case DP_TRAINING_PATTERN_3
:
2968 DRM_ERROR("DP training pattern 3 not supported\n");
2969 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2974 *DP
&= ~DP_LINK_TRAIN_MASK
;
2976 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2977 case DP_TRAINING_PATTERN_DISABLE
:
2978 *DP
|= DP_LINK_TRAIN_OFF
;
2980 case DP_TRAINING_PATTERN_1
:
2981 *DP
|= DP_LINK_TRAIN_PAT_1
;
2983 case DP_TRAINING_PATTERN_2
:
2984 *DP
|= DP_LINK_TRAIN_PAT_2
;
2986 case DP_TRAINING_PATTERN_3
:
2987 DRM_ERROR("DP training pattern 3 not supported\n");
2988 *DP
|= DP_LINK_TRAIN_PAT_2
;
2993 I915_WRITE(intel_dp
->output_reg
, *DP
);
2994 POSTING_READ(intel_dp
->output_reg
);
2996 buf
[0] = dp_train_pat
;
2997 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
2998 DP_TRAINING_PATTERN_DISABLE
) {
2999 /* don't write DP_TRAINING_LANEx_SET on disable */
3002 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3003 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3004 len
= intel_dp
->lane_count
+ 1;
3007 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3014 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3015 uint8_t dp_train_pat
)
3017 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3018 intel_dp_set_signal_levels(intel_dp
, DP
);
3019 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3023 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3024 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3026 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3027 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3031 intel_get_adjust_train(intel_dp
, link_status
);
3032 intel_dp_set_signal_levels(intel_dp
, DP
);
3034 I915_WRITE(intel_dp
->output_reg
, *DP
);
3035 POSTING_READ(intel_dp
->output_reg
);
3037 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3038 intel_dp
->train_set
, intel_dp
->lane_count
);
3040 return ret
== intel_dp
->lane_count
;
3043 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3045 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3046 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3048 enum port port
= intel_dig_port
->port
;
3054 val
= I915_READ(DP_TP_CTL(port
));
3055 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3056 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3057 I915_WRITE(DP_TP_CTL(port
), val
);
3060 * On PORT_A we can have only eDP in SST mode. There the only reason
3061 * we need to set idle transmission mode is to work around a HW issue
3062 * where we enable the pipe while not in idle link-training mode.
3063 * In this case there is requirement to wait for a minimum number of
3064 * idle patterns to be sent.
3069 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3071 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3074 /* Enable corresponding port and start training pattern 1 */
3076 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3078 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3079 struct drm_device
*dev
= encoder
->dev
;
3082 int voltage_tries
, loop_tries
;
3083 uint32_t DP
= intel_dp
->DP
;
3084 uint8_t link_config
[2];
3087 intel_ddi_prepare_link_retrain(encoder
);
3089 /* Write the link configuration data */
3090 link_config
[0] = intel_dp
->link_bw
;
3091 link_config
[1] = intel_dp
->lane_count
;
3092 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3093 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3094 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3097 link_config
[1] = DP_SET_ANSI_8B10B
;
3098 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3102 /* clock recovery */
3103 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3104 DP_TRAINING_PATTERN_1
|
3105 DP_LINK_SCRAMBLING_DISABLE
)) {
3106 DRM_ERROR("failed to enable link training\n");
3114 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3116 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3117 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3118 DRM_ERROR("failed to get link status\n");
3122 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3123 DRM_DEBUG_KMS("clock recovery OK\n");
3127 /* Check to see if we've tried the max voltage */
3128 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3129 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3131 if (i
== intel_dp
->lane_count
) {
3133 if (loop_tries
== 5) {
3134 DRM_ERROR("too many full retries, give up\n");
3137 intel_dp_reset_link_train(intel_dp
, &DP
,
3138 DP_TRAINING_PATTERN_1
|
3139 DP_LINK_SCRAMBLING_DISABLE
);
3144 /* Check to see if we've tried the same voltage 5 times */
3145 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3147 if (voltage_tries
== 5) {
3148 DRM_ERROR("too many voltage retries, give up\n");
3153 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3155 /* Update training set as requested by target */
3156 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3157 DRM_ERROR("failed to update link training\n");
3166 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3168 bool channel_eq
= false;
3169 int tries
, cr_tries
;
3170 uint32_t DP
= intel_dp
->DP
;
3171 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3173 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3174 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3175 training_pattern
= DP_TRAINING_PATTERN_3
;
3177 /* channel equalization */
3178 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3180 DP_LINK_SCRAMBLING_DISABLE
)) {
3181 DRM_ERROR("failed to start channel equalization\n");
3189 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3192 DRM_ERROR("failed to train DP, aborting\n");
3196 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3197 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3198 DRM_ERROR("failed to get link status\n");
3202 /* Make sure clock is still ok */
3203 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3204 intel_dp_start_link_train(intel_dp
);
3205 intel_dp_set_link_train(intel_dp
, &DP
,
3207 DP_LINK_SCRAMBLING_DISABLE
);
3212 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3217 /* Try 5 times, then try clock recovery if that fails */
3219 intel_dp_link_down(intel_dp
);
3220 intel_dp_start_link_train(intel_dp
);
3221 intel_dp_set_link_train(intel_dp
, &DP
,
3223 DP_LINK_SCRAMBLING_DISABLE
);
3229 /* Update training set as requested by target */
3230 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3231 DRM_ERROR("failed to update link training\n");
3237 intel_dp_set_idle_link_train(intel_dp
);
3242 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3246 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3248 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3249 DP_TRAINING_PATTERN_DISABLE
);
3253 intel_dp_link_down(struct intel_dp
*intel_dp
)
3255 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3256 enum port port
= intel_dig_port
->port
;
3257 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3259 struct intel_crtc
*intel_crtc
=
3260 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3261 uint32_t DP
= intel_dp
->DP
;
3263 if (WARN_ON(HAS_DDI(dev
)))
3266 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3269 DRM_DEBUG_KMS("\n");
3271 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3272 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3273 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3275 DP
&= ~DP_LINK_TRAIN_MASK
;
3276 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3278 POSTING_READ(intel_dp
->output_reg
);
3280 if (HAS_PCH_IBX(dev
) &&
3281 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3282 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3284 /* Hardware workaround: leaving our transcoder select
3285 * set to transcoder B while it's off will prevent the
3286 * corresponding HDMI output on transcoder A.
3288 * Combine this with another hardware workaround:
3289 * transcoder select bit can only be cleared while the
3292 DP
&= ~DP_PIPEB_SELECT
;
3293 I915_WRITE(intel_dp
->output_reg
, DP
);
3295 /* Changes to enable or select take place the vblank
3296 * after being written.
3298 if (WARN_ON(crtc
== NULL
)) {
3299 /* We should never try to disable a port without a crtc
3300 * attached. For paranoia keep the code around for a
3302 POSTING_READ(intel_dp
->output_reg
);
3305 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3308 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3309 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3310 POSTING_READ(intel_dp
->output_reg
);
3311 msleep(intel_dp
->panel_power_down_delay
);
3315 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3317 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3318 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3321 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
3323 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3324 sizeof(intel_dp
->dpcd
)) < 0)
3325 return false; /* aux transfer failed */
3327 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
3328 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
3329 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
3331 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3332 return false; /* DPCD not present */
3334 /* Check if the panel supports PSR */
3335 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3336 if (is_edp(intel_dp
)) {
3337 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3339 sizeof(intel_dp
->psr_dpcd
));
3340 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3341 dev_priv
->psr
.sink_support
= true;
3342 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3346 /* Training Pattern 3 support */
3347 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3348 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3349 intel_dp
->use_tps3
= true;
3350 DRM_DEBUG_KMS("Displayport TPS3 supported");
3352 intel_dp
->use_tps3
= false;
3354 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3355 DP_DWN_STRM_PORT_PRESENT
))
3356 return true; /* native DP sink */
3358 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3359 return true; /* no per-port downstream info */
3361 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3362 intel_dp
->downstream_ports
,
3363 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3364 return false; /* downstream port status fetch failed */
3370 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3374 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3377 intel_edp_panel_vdd_on(intel_dp
);
3379 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3380 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3381 buf
[0], buf
[1], buf
[2]);
3383 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3384 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3385 buf
[0], buf
[1], buf
[2]);
3387 edp_panel_vdd_off(intel_dp
, false);
3391 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3395 if (!intel_dp
->can_mst
)
3398 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3401 _edp_panel_vdd_on(intel_dp
);
3402 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3403 if (buf
[0] & DP_MST_CAP
) {
3404 DRM_DEBUG_KMS("Sink is MST capable\n");
3405 intel_dp
->is_mst
= true;
3407 DRM_DEBUG_KMS("Sink is not MST capable\n");
3408 intel_dp
->is_mst
= false;
3411 edp_panel_vdd_off(intel_dp
, false);
3413 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3414 return intel_dp
->is_mst
;
3417 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3419 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3420 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3421 struct intel_crtc
*intel_crtc
=
3422 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3425 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
3428 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
3431 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3432 DP_TEST_SINK_START
) < 0)
3435 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3436 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3437 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3439 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3442 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
3447 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3449 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3450 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3451 sink_irq_vector
, 1) == 1;
3455 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3459 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3461 sink_irq_vector
, 14);
3469 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3471 /* NAK by default */
3472 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3476 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3480 if (intel_dp
->is_mst
) {
3485 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3489 /* check link status - esi[10] = 0x200c */
3490 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3491 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3492 intel_dp_start_link_train(intel_dp
);
3493 intel_dp_complete_link_train(intel_dp
);
3494 intel_dp_stop_link_train(intel_dp
);
3497 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3498 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3501 for (retry
= 0; retry
< 3; retry
++) {
3503 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3504 DP_SINK_COUNT_ESI
+1,
3511 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3513 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3521 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3522 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3523 intel_dp
->is_mst
= false;
3524 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3525 /* send a hotplug event */
3526 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3533 * According to DP spec
3536 * 2. Configure link according to Receiver Capabilities
3537 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3538 * 4. Check link status on receipt of hot-plug interrupt
3541 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3543 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3544 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3546 u8 link_status
[DP_LINK_STATUS_SIZE
];
3548 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3550 if (!intel_encoder
->connectors_active
)
3553 if (WARN_ON(!intel_encoder
->base
.crtc
))
3556 /* Try to read receiver status if the link appears to be up */
3557 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3561 /* Now read the DPCD to see if it's actually running */
3562 if (!intel_dp_get_dpcd(intel_dp
)) {
3566 /* Try to read the source of the interrupt */
3567 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3568 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3569 /* Clear interrupt source */
3570 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3571 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3574 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3575 intel_dp_handle_test_request(intel_dp
);
3576 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3577 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3580 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3581 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3582 intel_encoder
->base
.name
);
3583 intel_dp_start_link_train(intel_dp
);
3584 intel_dp_complete_link_train(intel_dp
);
3585 intel_dp_stop_link_train(intel_dp
);
3589 /* XXX this is probably wrong for multiple downstream ports */
3590 static enum drm_connector_status
3591 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3593 uint8_t *dpcd
= intel_dp
->dpcd
;
3596 if (!intel_dp_get_dpcd(intel_dp
))
3597 return connector_status_disconnected
;
3599 /* if there's no downstream port, we're done */
3600 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3601 return connector_status_connected
;
3603 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3604 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3605 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3608 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3610 return connector_status_unknown
;
3612 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3613 : connector_status_disconnected
;
3616 /* If no HPD, poke DDC gently */
3617 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3618 return connector_status_connected
;
3620 /* Well we tried, say unknown for unreliable port types */
3621 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3622 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3623 if (type
== DP_DS_PORT_TYPE_VGA
||
3624 type
== DP_DS_PORT_TYPE_NON_EDID
)
3625 return connector_status_unknown
;
3627 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3628 DP_DWN_STRM_PORT_TYPE_MASK
;
3629 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3630 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3631 return connector_status_unknown
;
3634 /* Anything else is out of spec, warn and ignore */
3635 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3636 return connector_status_disconnected
;
3639 static enum drm_connector_status
3640 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3642 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3644 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3645 enum drm_connector_status status
;
3647 /* Can't disconnect eDP, but you can close the lid... */
3648 if (is_edp(intel_dp
)) {
3649 status
= intel_panel_detect(dev
);
3650 if (status
== connector_status_unknown
)
3651 status
= connector_status_connected
;
3655 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3656 return connector_status_disconnected
;
3658 return intel_dp_detect_dpcd(intel_dp
);
3661 static enum drm_connector_status
3662 g4x_dp_detect(struct intel_dp
*intel_dp
)
3664 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3666 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3669 /* Can't disconnect eDP, but you can close the lid... */
3670 if (is_edp(intel_dp
)) {
3671 enum drm_connector_status status
;
3673 status
= intel_panel_detect(dev
);
3674 if (status
== connector_status_unknown
)
3675 status
= connector_status_connected
;
3679 if (IS_VALLEYVIEW(dev
)) {
3680 switch (intel_dig_port
->port
) {
3682 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3685 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3688 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3691 return connector_status_unknown
;
3694 switch (intel_dig_port
->port
) {
3696 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3699 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3702 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3705 return connector_status_unknown
;
3709 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3710 return connector_status_disconnected
;
3712 return intel_dp_detect_dpcd(intel_dp
);
3715 static struct edid
*
3716 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3718 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3720 /* use cached edid if we have one */
3721 if (intel_connector
->edid
) {
3723 if (IS_ERR(intel_connector
->edid
))
3726 return drm_edid_duplicate(intel_connector
->edid
);
3729 return drm_get_edid(connector
, adapter
);
3733 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3735 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3737 /* use cached edid if we have one */
3738 if (intel_connector
->edid
) {
3740 if (IS_ERR(intel_connector
->edid
))
3743 return intel_connector_update_modes(connector
,
3744 intel_connector
->edid
);
3747 return intel_ddc_get_modes(connector
, adapter
);
3750 static enum drm_connector_status
3751 intel_dp_detect(struct drm_connector
*connector
, bool force
)
3753 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3754 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3755 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3756 struct drm_device
*dev
= connector
->dev
;
3757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3758 enum drm_connector_status status
;
3759 enum intel_display_power_domain power_domain
;
3760 struct edid
*edid
= NULL
;
3763 power_domain
= intel_display_port_power_domain(intel_encoder
);
3764 intel_display_power_get(dev_priv
, power_domain
);
3766 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3767 connector
->base
.id
, connector
->name
);
3769 if (intel_dp
->is_mst
) {
3770 /* MST devices are disconnected from a monitor POV */
3771 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3772 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3773 status
= connector_status_disconnected
;
3777 intel_dp
->has_audio
= false;
3779 if (HAS_PCH_SPLIT(dev
))
3780 status
= ironlake_dp_detect(intel_dp
);
3782 status
= g4x_dp_detect(intel_dp
);
3784 if (status
!= connector_status_connected
)
3787 intel_dp_probe_oui(intel_dp
);
3789 ret
= intel_dp_probe_mst(intel_dp
);
3791 /* if we are in MST mode then this connector
3792 won't appear connected or have anything with EDID on it */
3793 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3794 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3795 status
= connector_status_disconnected
;
3799 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
3800 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
3802 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3804 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
3809 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3810 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3811 status
= connector_status_connected
;
3814 intel_display_power_put(dev_priv
, power_domain
);
3818 static int intel_dp_get_modes(struct drm_connector
*connector
)
3820 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3821 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3822 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3823 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3824 struct drm_device
*dev
= connector
->dev
;
3825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3826 enum intel_display_power_domain power_domain
;
3829 /* We should parse the EDID data and find out if it has an audio sink
3832 power_domain
= intel_display_port_power_domain(intel_encoder
);
3833 intel_display_power_get(dev_priv
, power_domain
);
3835 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->aux
.ddc
);
3836 intel_display_power_put(dev_priv
, power_domain
);
3840 /* if eDP has no EDID, fall back to fixed mode */
3841 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3842 struct drm_display_mode
*mode
;
3843 mode
= drm_mode_duplicate(dev
,
3844 intel_connector
->panel
.fixed_mode
);
3846 drm_mode_probed_add(connector
, mode
);
3854 intel_dp_detect_audio(struct drm_connector
*connector
)
3856 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3857 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3858 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3859 struct drm_device
*dev
= connector
->dev
;
3860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3861 enum intel_display_power_domain power_domain
;
3863 bool has_audio
= false;
3865 power_domain
= intel_display_port_power_domain(intel_encoder
);
3866 intel_display_power_get(dev_priv
, power_domain
);
3868 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3870 has_audio
= drm_detect_monitor_audio(edid
);
3874 intel_display_power_put(dev_priv
, power_domain
);
3880 intel_dp_set_property(struct drm_connector
*connector
,
3881 struct drm_property
*property
,
3884 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3885 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3886 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3887 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3890 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3894 if (property
== dev_priv
->force_audio_property
) {
3898 if (i
== intel_dp
->force_audio
)
3901 intel_dp
->force_audio
= i
;
3903 if (i
== HDMI_AUDIO_AUTO
)
3904 has_audio
= intel_dp_detect_audio(connector
);
3906 has_audio
= (i
== HDMI_AUDIO_ON
);
3908 if (has_audio
== intel_dp
->has_audio
)
3911 intel_dp
->has_audio
= has_audio
;
3915 if (property
== dev_priv
->broadcast_rgb_property
) {
3916 bool old_auto
= intel_dp
->color_range_auto
;
3917 uint32_t old_range
= intel_dp
->color_range
;
3920 case INTEL_BROADCAST_RGB_AUTO
:
3921 intel_dp
->color_range_auto
= true;
3923 case INTEL_BROADCAST_RGB_FULL
:
3924 intel_dp
->color_range_auto
= false;
3925 intel_dp
->color_range
= 0;
3927 case INTEL_BROADCAST_RGB_LIMITED
:
3928 intel_dp
->color_range_auto
= false;
3929 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3935 if (old_auto
== intel_dp
->color_range_auto
&&
3936 old_range
== intel_dp
->color_range
)
3942 if (is_edp(intel_dp
) &&
3943 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3944 if (val
== DRM_MODE_SCALE_NONE
) {
3945 DRM_DEBUG_KMS("no scaling not supported\n");
3949 if (intel_connector
->panel
.fitting_mode
== val
) {
3950 /* the eDP scaling property is not changed */
3953 intel_connector
->panel
.fitting_mode
= val
;
3961 if (intel_encoder
->base
.crtc
)
3962 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
3968 intel_dp_connector_destroy(struct drm_connector
*connector
)
3970 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3972 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
3973 kfree(intel_connector
->edid
);
3975 /* Can't call is_edp() since the encoder may have been destroyed
3977 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3978 intel_panel_fini(&intel_connector
->panel
);
3980 drm_connector_cleanup(connector
);
3984 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
3986 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
3987 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3988 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3990 drm_dp_aux_unregister(&intel_dp
->aux
);
3991 intel_dp_mst_encoder_cleanup(intel_dig_port
);
3992 drm_encoder_cleanup(encoder
);
3993 if (is_edp(intel_dp
)) {
3994 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3995 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
3996 edp_panel_vdd_off_sync(intel_dp
);
3997 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
3998 if (intel_dp
->edp_notifier
.notifier_call
) {
3999 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4000 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4003 kfree(intel_dig_port
);
4006 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4008 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder
));
4011 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4012 .dpms
= intel_connector_dpms
,
4013 .detect
= intel_dp_detect
,
4014 .fill_modes
= drm_helper_probe_single_connector_modes
,
4015 .set_property
= intel_dp_set_property
,
4016 .destroy
= intel_dp_connector_destroy
,
4019 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4020 .get_modes
= intel_dp_get_modes
,
4021 .mode_valid
= intel_dp_mode_valid
,
4022 .best_encoder
= intel_best_encoder
,
4025 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4026 .reset
= intel_dp_encoder_reset
,
4027 .destroy
= intel_dp_encoder_destroy
,
4031 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4037 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4039 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4040 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4043 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4044 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4046 DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port
->port
,
4047 long_hpd
? "long" : "short");
4050 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4053 if (!intel_dp_get_dpcd(intel_dp
)) {
4057 intel_dp_probe_oui(intel_dp
);
4059 if (!intel_dp_probe_mst(intel_dp
))
4063 if (intel_dp
->is_mst
) {
4064 ret
= intel_dp_check_mst_status(intel_dp
);
4069 if (!intel_dp
->is_mst
) {
4071 * we'll check the link status via the normal hot plug path later -
4072 * but for short hpds we should check it now
4074 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4075 intel_dp_check_link_status(intel_dp
);
4076 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4081 /* if we were in MST mode, and device is not there get out of MST mode */
4082 if (intel_dp
->is_mst
) {
4083 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4084 intel_dp
->is_mst
= false;
4085 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4090 /* Return which DP Port should be selected for Transcoder DP control */
4092 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4094 struct drm_device
*dev
= crtc
->dev
;
4095 struct intel_encoder
*intel_encoder
;
4096 struct intel_dp
*intel_dp
;
4098 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4099 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4101 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4102 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4103 return intel_dp
->output_reg
;
4109 /* check the VBT to see whether the eDP is on DP-D port */
4110 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4113 union child_device_config
*p_child
;
4115 static const short port_mapping
[] = {
4116 [PORT_B
] = PORT_IDPB
,
4117 [PORT_C
] = PORT_IDPC
,
4118 [PORT_D
] = PORT_IDPD
,
4124 if (!dev_priv
->vbt
.child_dev_num
)
4127 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4128 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4130 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4131 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4132 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4139 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4141 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4143 intel_attach_force_audio_property(connector
);
4144 intel_attach_broadcast_rgb_property(connector
);
4145 intel_dp
->color_range_auto
= true;
4147 if (is_edp(intel_dp
)) {
4148 drm_mode_create_scaling_mode_property(connector
->dev
);
4149 drm_object_attach_property(
4151 connector
->dev
->mode_config
.scaling_mode_property
,
4152 DRM_MODE_SCALE_ASPECT
);
4153 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4157 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4159 intel_dp
->last_power_cycle
= jiffies
;
4160 intel_dp
->last_power_on
= jiffies
;
4161 intel_dp
->last_backlight_off
= jiffies
;
4165 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4166 struct intel_dp
*intel_dp
,
4167 struct edp_power_seq
*out
)
4169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4170 struct edp_power_seq cur
, vbt
, spec
, final
;
4171 u32 pp_on
, pp_off
, pp_div
, pp
;
4172 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4174 if (HAS_PCH_SPLIT(dev
)) {
4175 pp_ctrl_reg
= PCH_PP_CONTROL
;
4176 pp_on_reg
= PCH_PP_ON_DELAYS
;
4177 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4178 pp_div_reg
= PCH_PP_DIVISOR
;
4180 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4182 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4183 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4184 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4185 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4188 /* Workaround: Need to write PP_CONTROL with the unlock key as
4189 * the very first thing. */
4190 pp
= ironlake_get_pp_control(intel_dp
);
4191 I915_WRITE(pp_ctrl_reg
, pp
);
4193 pp_on
= I915_READ(pp_on_reg
);
4194 pp_off
= I915_READ(pp_off_reg
);
4195 pp_div
= I915_READ(pp_div_reg
);
4197 /* Pull timing values out of registers */
4198 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4199 PANEL_POWER_UP_DELAY_SHIFT
;
4201 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4202 PANEL_LIGHT_ON_DELAY_SHIFT
;
4204 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4205 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4207 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4208 PANEL_POWER_DOWN_DELAY_SHIFT
;
4210 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4211 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4213 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4214 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4216 vbt
= dev_priv
->vbt
.edp_pps
;
4218 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4219 * our hw here, which are all in 100usec. */
4220 spec
.t1_t3
= 210 * 10;
4221 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4222 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4223 spec
.t10
= 500 * 10;
4224 /* This one is special and actually in units of 100ms, but zero
4225 * based in the hw (so we need to add 100 ms). But the sw vbt
4226 * table multiplies it with 1000 to make it in units of 100usec,
4228 spec
.t11_t12
= (510 + 100) * 10;
4230 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4231 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4233 /* Use the max of the register settings and vbt. If both are
4234 * unset, fall back to the spec limits. */
4235 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4237 max(cur.field, vbt.field))
4238 assign_final(t1_t3
);
4242 assign_final(t11_t12
);
4245 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4246 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4247 intel_dp
->backlight_on_delay
= get_delay(t8
);
4248 intel_dp
->backlight_off_delay
= get_delay(t9
);
4249 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4250 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4253 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4254 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4255 intel_dp
->panel_power_cycle_delay
);
4257 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4258 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4265 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4266 struct intel_dp
*intel_dp
,
4267 struct edp_power_seq
*seq
)
4269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4270 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4271 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4272 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4274 if (HAS_PCH_SPLIT(dev
)) {
4275 pp_on_reg
= PCH_PP_ON_DELAYS
;
4276 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4277 pp_div_reg
= PCH_PP_DIVISOR
;
4279 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4281 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4282 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4283 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4287 * And finally store the new values in the power sequencer. The
4288 * backlight delays are set to 1 because we do manual waits on them. For
4289 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4290 * we'll end up waiting for the backlight off delay twice: once when we
4291 * do the manual sleep, and once when we disable the panel and wait for
4292 * the PP_STATUS bit to become zero.
4294 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4295 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4296 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4297 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4298 /* Compute the divisor for the pp clock, simply match the Bspec
4300 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4301 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4302 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4304 /* Haswell doesn't have any port selection bits for the panel
4305 * power sequencer any more. */
4306 if (IS_VALLEYVIEW(dev
)) {
4307 if (dp_to_dig_port(intel_dp
)->port
== PORT_B
)
4308 port_sel
= PANEL_PORT_SELECT_DPB_VLV
;
4310 port_sel
= PANEL_PORT_SELECT_DPC_VLV
;
4311 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4312 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
4313 port_sel
= PANEL_PORT_SELECT_DPA
;
4315 port_sel
= PANEL_PORT_SELECT_DPD
;
4320 I915_WRITE(pp_on_reg
, pp_on
);
4321 I915_WRITE(pp_off_reg
, pp_off
);
4322 I915_WRITE(pp_div_reg
, pp_div
);
4324 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4325 I915_READ(pp_on_reg
),
4326 I915_READ(pp_off_reg
),
4327 I915_READ(pp_div_reg
));
4330 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4333 struct intel_encoder
*encoder
;
4334 struct intel_dp
*intel_dp
= NULL
;
4335 struct intel_crtc_config
*config
= NULL
;
4336 struct intel_crtc
*intel_crtc
= NULL
;
4337 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4339 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4341 if (refresh_rate
<= 0) {
4342 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4346 if (intel_connector
== NULL
) {
4347 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4352 * FIXME: This needs proper synchronization with psr state. But really
4353 * hard to tell without seeing the user of this function of this code.
4354 * Check locking and ordering once that lands.
4356 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4357 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4361 encoder
= intel_attached_encoder(&intel_connector
->base
);
4362 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4363 intel_crtc
= encoder
->new_crtc
;
4366 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4370 config
= &intel_crtc
->config
;
4372 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4373 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4377 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4378 index
= DRRS_LOW_RR
;
4380 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4382 "DRRS requested for previously set RR...ignoring\n");
4386 if (!intel_crtc
->active
) {
4387 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4391 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4392 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4393 val
= I915_READ(reg
);
4394 if (index
> DRRS_HIGH_RR
) {
4395 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4396 intel_dp_set_m2_n2(intel_crtc
, &config
->dp_m2_n2
);
4398 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4400 I915_WRITE(reg
, val
);
4404 * mutex taken to ensure that there is no race between differnt
4405 * drrs calls trying to update refresh rate. This scenario may occur
4406 * in future when idleness detection based DRRS in kernel and
4407 * possible calls from user space to set differnt RR are made.
4410 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4412 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4414 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4416 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4419 static struct drm_display_mode
*
4420 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4421 struct intel_connector
*intel_connector
,
4422 struct drm_display_mode
*fixed_mode
)
4424 struct drm_connector
*connector
= &intel_connector
->base
;
4425 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4426 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4428 struct drm_display_mode
*downclock_mode
= NULL
;
4430 if (INTEL_INFO(dev
)->gen
<= 6) {
4431 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4435 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4436 DRM_INFO("VBT doesn't support DRRS\n");
4440 downclock_mode
= intel_find_panel_downclock
4441 (dev
, fixed_mode
, connector
);
4443 if (!downclock_mode
) {
4444 DRM_INFO("DRRS not supported\n");
4448 dev_priv
->drrs
.connector
= intel_connector
;
4450 mutex_init(&intel_dp
->drrs_state
.mutex
);
4452 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
4454 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
4455 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4456 return downclock_mode
;
4459 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
)
4461 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4463 struct intel_dp
*intel_dp
;
4464 enum intel_display_power_domain power_domain
;
4466 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4469 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4470 if (!edp_have_panel_vdd(intel_dp
))
4473 * The VDD bit needs a power domain reference, so if the bit is
4474 * already enabled when we boot or resume, grab this reference and
4475 * schedule a vdd off, so we don't hold on to the reference
4478 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4479 power_domain
= intel_display_port_power_domain(intel_encoder
);
4480 intel_display_power_get(dev_priv
, power_domain
);
4482 edp_panel_vdd_schedule_off(intel_dp
);
4485 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4486 struct intel_connector
*intel_connector
,
4487 struct edp_power_seq
*power_seq
)
4489 struct drm_connector
*connector
= &intel_connector
->base
;
4490 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4491 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4492 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4494 struct drm_display_mode
*fixed_mode
= NULL
;
4495 struct drm_display_mode
*downclock_mode
= NULL
;
4497 struct drm_display_mode
*scan
;
4500 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
4502 if (!is_edp(intel_dp
))
4505 intel_edp_panel_vdd_sanitize(intel_encoder
);
4507 /* Cache DPCD and EDID for edp. */
4508 intel_edp_panel_vdd_on(intel_dp
);
4509 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
4510 edp_panel_vdd_off(intel_dp
, false);
4513 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4514 dev_priv
->no_aux_handshake
=
4515 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4516 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4518 /* if this fails, presume the device is a ghost */
4519 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4523 /* We now know it's not a ghost, init power sequence regs. */
4524 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
4526 mutex_lock(&dev
->mode_config
.mutex
);
4527 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
4529 if (drm_add_edid_modes(connector
, edid
)) {
4530 drm_mode_connector_update_edid_property(connector
,
4532 drm_edid_to_eld(connector
, edid
);
4535 edid
= ERR_PTR(-EINVAL
);
4538 edid
= ERR_PTR(-ENOENT
);
4540 intel_connector
->edid
= edid
;
4542 /* prefer fixed mode from EDID if available */
4543 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
4544 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
4545 fixed_mode
= drm_mode_duplicate(dev
, scan
);
4546 downclock_mode
= intel_dp_drrs_init(
4548 intel_connector
, fixed_mode
);
4553 /* fallback to VBT if available for eDP */
4554 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
4555 fixed_mode
= drm_mode_duplicate(dev
,
4556 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
4558 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4560 mutex_unlock(&dev
->mode_config
.mutex
);
4562 if (IS_VALLEYVIEW(dev
)) {
4563 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
4564 register_reboot_notifier(&intel_dp
->edp_notifier
);
4567 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
4568 intel_panel_setup_backlight(connector
);
4574 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
4575 struct intel_connector
*intel_connector
)
4577 struct drm_connector
*connector
= &intel_connector
->base
;
4578 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4579 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4580 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4582 enum port port
= intel_dig_port
->port
;
4583 struct edp_power_seq power_seq
= { 0 };
4586 /* intel_dp vfuncs */
4587 if (IS_VALLEYVIEW(dev
))
4588 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
4589 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4590 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
4591 else if (HAS_PCH_SPLIT(dev
))
4592 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
4594 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
4596 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
4598 /* Preserve the current hw state. */
4599 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4600 intel_dp
->attached_connector
= intel_connector
;
4602 if (intel_dp_is_edp(dev
, port
))
4603 type
= DRM_MODE_CONNECTOR_eDP
;
4605 type
= DRM_MODE_CONNECTOR_DisplayPort
;
4608 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4609 * for DP the encoder type can be set by the caller to
4610 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4612 if (type
== DRM_MODE_CONNECTOR_eDP
)
4613 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
4615 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4616 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
4619 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
4620 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
4622 connector
->interlace_allowed
= true;
4623 connector
->doublescan_allowed
= 0;
4625 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
4626 edp_panel_vdd_work
);
4628 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
4629 drm_connector_register(connector
);
4632 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
4634 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
4635 intel_connector
->unregister
= intel_dp_connector_unregister
;
4637 /* Set up the hotplug pin. */
4640 intel_encoder
->hpd_pin
= HPD_PORT_A
;
4643 intel_encoder
->hpd_pin
= HPD_PORT_B
;
4646 intel_encoder
->hpd_pin
= HPD_PORT_C
;
4649 intel_encoder
->hpd_pin
= HPD_PORT_D
;
4655 if (is_edp(intel_dp
)) {
4656 intel_dp_init_panel_power_timestamps(intel_dp
);
4657 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
4660 intel_dp_aux_init(intel_dp
, intel_connector
);
4662 /* init MST on ports that can support it */
4663 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
4664 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
4665 intel_dp_mst_encoder_init(intel_dig_port
, intel_connector
->base
.base
.id
);
4669 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
4670 drm_dp_aux_unregister(&intel_dp
->aux
);
4671 if (is_edp(intel_dp
)) {
4672 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4673 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4674 edp_panel_vdd_off_sync(intel_dp
);
4675 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4677 drm_connector_unregister(connector
);
4678 drm_connector_cleanup(connector
);
4682 intel_dp_add_properties(intel_dp
, connector
);
4684 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4685 * 0xd. Failure to do so will result in spurious interrupts being
4686 * generated on the port when a cable is not attached.
4688 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
4689 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
4690 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
4697 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
4699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4700 struct intel_digital_port
*intel_dig_port
;
4701 struct intel_encoder
*intel_encoder
;
4702 struct drm_encoder
*encoder
;
4703 struct intel_connector
*intel_connector
;
4705 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
4706 if (!intel_dig_port
)
4709 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
4710 if (!intel_connector
) {
4711 kfree(intel_dig_port
);
4715 intel_encoder
= &intel_dig_port
->base
;
4716 encoder
= &intel_encoder
->base
;
4718 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
4719 DRM_MODE_ENCODER_TMDS
);
4721 intel_encoder
->compute_config
= intel_dp_compute_config
;
4722 intel_encoder
->disable
= intel_disable_dp
;
4723 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
4724 intel_encoder
->get_config
= intel_dp_get_config
;
4725 if (IS_CHERRYVIEW(dev
)) {
4726 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
4727 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
4728 intel_encoder
->enable
= vlv_enable_dp
;
4729 intel_encoder
->post_disable
= chv_post_disable_dp
;
4730 } else if (IS_VALLEYVIEW(dev
)) {
4731 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
4732 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
4733 intel_encoder
->enable
= vlv_enable_dp
;
4734 intel_encoder
->post_disable
= vlv_post_disable_dp
;
4736 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
4737 intel_encoder
->enable
= g4x_enable_dp
;
4738 intel_encoder
->post_disable
= g4x_post_disable_dp
;
4741 intel_dig_port
->port
= port
;
4742 intel_dig_port
->dp
.output_reg
= output_reg
;
4744 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4745 if (IS_CHERRYVIEW(dev
)) {
4747 intel_encoder
->crtc_mask
= 1 << 2;
4749 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
4751 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
4753 intel_encoder
->cloneable
= 0;
4754 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
4756 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
4757 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
4759 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
4760 drm_encoder_cleanup(encoder
);
4761 kfree(intel_dig_port
);
4762 kfree(intel_connector
);
4766 void intel_dp_mst_suspend(struct drm_device
*dev
)
4768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4772 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
4773 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
4774 if (!intel_dig_port
)
4777 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
4778 if (!intel_dig_port
->dp
.can_mst
)
4780 if (intel_dig_port
->dp
.is_mst
)
4781 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
4786 void intel_dp_mst_resume(struct drm_device
*dev
)
4788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4791 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
4792 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
4793 if (!intel_dig_port
)
4795 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
4798 if (!intel_dig_port
->dp
.can_mst
)
4801 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
4803 intel_dp_check_mst_status(&intel_dig_port
->dp
);