2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates
[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp
*intel_dp
)
109 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
111 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
114 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
118 return intel_dig_port
->base
.base
.dev
;
121 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
123 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
126 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
130 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
132 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
134 static unsigned int intel_dp_unused_lane_mask(int lane_count
)
136 return ~((1 << lane_count
) - 1) & 0xf;
140 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
142 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
144 switch (max_link_bw
) {
145 case DP_LINK_BW_1_62
:
150 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
152 max_link_bw
= DP_LINK_BW_1_62
;
158 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
160 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
161 u8 source_max
, sink_max
;
163 source_max
= intel_dig_port
->max_lanes
;
164 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
166 return min(source_max
, sink_max
);
170 * The units on the numbers in the next two are... bizarre. Examples will
171 * make it clearer; this one parallels an example in the eDP spec.
173 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
175 * 270000 * 1 * 8 / 10 == 216000
177 * The actual data capacity of that configuration is 2.16Gbit/s, so the
178 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
179 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
180 * 119000. At 18bpp that's 2142000 kilobits per second.
182 * Thus the strange-looking division by 10 in intel_dp_link_required, to
183 * get the result in decakilobits instead of kilobits.
187 intel_dp_link_required(int pixel_clock
, int bpp
)
189 return (pixel_clock
* bpp
+ 9) / 10;
193 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
195 return (max_link_clock
* max_lanes
* 8) / 10;
198 static enum drm_mode_status
199 intel_dp_mode_valid(struct drm_connector
*connector
,
200 struct drm_display_mode
*mode
)
202 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
203 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
204 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
205 int target_clock
= mode
->clock
;
206 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
207 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
209 if (is_edp(intel_dp
) && fixed_mode
) {
210 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
213 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
216 target_clock
= fixed_mode
->clock
;
219 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
220 max_lanes
= intel_dp_max_lane_count(intel_dp
);
222 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
223 mode_rate
= intel_dp_link_required(target_clock
, 18);
225 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
226 return MODE_CLOCK_HIGH
;
228 if (mode
->clock
< 10000)
229 return MODE_CLOCK_LOW
;
231 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
232 return MODE_H_ILLEGAL
;
237 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
244 for (i
= 0; i
< src_bytes
; i
++)
245 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
249 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
254 for (i
= 0; i
< dst_bytes
; i
++)
255 dst
[i
] = src
>> ((3-i
) * 8);
259 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
260 struct intel_dp
*intel_dp
);
262 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
263 struct intel_dp
*intel_dp
);
265 static void pps_lock(struct intel_dp
*intel_dp
)
267 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
268 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
269 struct drm_device
*dev
= encoder
->base
.dev
;
270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
271 enum intel_display_power_domain power_domain
;
274 * See vlv_power_sequencer_reset() why we need
275 * a power domain reference here.
277 power_domain
= intel_display_port_aux_power_domain(encoder
);
278 intel_display_power_get(dev_priv
, power_domain
);
280 mutex_lock(&dev_priv
->pps_mutex
);
283 static void pps_unlock(struct intel_dp
*intel_dp
)
285 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
286 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
287 struct drm_device
*dev
= encoder
->base
.dev
;
288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
289 enum intel_display_power_domain power_domain
;
291 mutex_unlock(&dev_priv
->pps_mutex
);
293 power_domain
= intel_display_port_aux_power_domain(encoder
);
294 intel_display_power_put(dev_priv
, power_domain
);
298 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
300 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
301 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
302 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
303 enum pipe pipe
= intel_dp
->pps_pipe
;
304 bool pll_enabled
, release_cl_override
= false;
305 enum dpio_phy phy
= DPIO_PHY(pipe
);
306 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
309 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
310 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
311 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
314 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
315 pipe_name(pipe
), port_name(intel_dig_port
->port
));
317 /* Preserve the BIOS-computed detected bit. This is
318 * supposed to be read-only.
320 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
321 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
322 DP
|= DP_PORT_WIDTH(1);
323 DP
|= DP_LINK_TRAIN_PAT_1
;
325 if (IS_CHERRYVIEW(dev
))
326 DP
|= DP_PIPE_SELECT_CHV(pipe
);
327 else if (pipe
== PIPE_B
)
328 DP
|= DP_PIPEB_SELECT
;
330 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
333 * The DPLL for the pipe must be enabled for this to work.
334 * So enable temporarily it if it's not already enabled.
337 release_cl_override
= IS_CHERRYVIEW(dev
) &&
338 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
340 if (vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
341 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
342 DRM_ERROR("Failed to force on pll for pipe %c!\n",
349 * Similar magic as in intel_dp_enable_port().
350 * We _must_ do this port enable + disable trick
351 * to make this power seqeuencer lock onto the port.
352 * Otherwise even VDD force bit won't work.
354 I915_WRITE(intel_dp
->output_reg
, DP
);
355 POSTING_READ(intel_dp
->output_reg
);
357 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
358 POSTING_READ(intel_dp
->output_reg
);
360 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
361 POSTING_READ(intel_dp
->output_reg
);
364 vlv_force_pll_off(dev
, pipe
);
366 if (release_cl_override
)
367 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
372 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
374 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
375 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
377 struct intel_encoder
*encoder
;
378 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
381 lockdep_assert_held(&dev_priv
->pps_mutex
);
383 /* We should never land here with regular DP ports */
384 WARN_ON(!is_edp(intel_dp
));
386 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
387 return intel_dp
->pps_pipe
;
390 * We don't have power sequencer currently.
391 * Pick one that's not used by other ports.
393 for_each_intel_encoder(dev
, encoder
) {
394 struct intel_dp
*tmp
;
396 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
399 tmp
= enc_to_intel_dp(&encoder
->base
);
401 if (tmp
->pps_pipe
!= INVALID_PIPE
)
402 pipes
&= ~(1 << tmp
->pps_pipe
);
406 * Didn't find one. This should not happen since there
407 * are two power sequencers and up to two eDP ports.
409 if (WARN_ON(pipes
== 0))
412 pipe
= ffs(pipes
) - 1;
414 vlv_steal_power_sequencer(dev
, pipe
);
415 intel_dp
->pps_pipe
= pipe
;
417 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
418 pipe_name(intel_dp
->pps_pipe
),
419 port_name(intel_dig_port
->port
));
421 /* init power sequencer on this pipe and port */
422 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
423 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
426 * Even vdd force doesn't work until we've made
427 * the power sequencer lock in on the port.
429 vlv_power_sequencer_kick(intel_dp
);
431 return intel_dp
->pps_pipe
;
434 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
437 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
440 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
443 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
446 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
449 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
456 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
458 vlv_pipe_check pipe_check
)
462 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
463 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
464 PANEL_PORT_SELECT_MASK
;
466 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
469 if (!pipe_check(dev_priv
, pipe
))
479 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
481 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
482 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
484 enum port port
= intel_dig_port
->port
;
486 lockdep_assert_held(&dev_priv
->pps_mutex
);
488 /* try to find a pipe with this port selected */
489 /* first pick one where the panel is on */
490 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
492 /* didn't find one? pick one where vdd is on */
493 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
494 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
495 vlv_pipe_has_vdd_on
);
496 /* didn't find one? pick one with just the correct port */
497 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
498 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
501 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
502 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
503 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
508 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
509 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
511 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
512 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
515 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
517 struct drm_device
*dev
= dev_priv
->dev
;
518 struct intel_encoder
*encoder
;
520 if (WARN_ON(!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)))
524 * We can't grab pps_mutex here due to deadlock with power_domain
525 * mutex when power_domain functions are called while holding pps_mutex.
526 * That also means that in order to use pps_pipe the code needs to
527 * hold both a power domain reference and pps_mutex, and the power domain
528 * reference get/put must be done while _not_ holding pps_mutex.
529 * pps_{lock,unlock}() do these steps in the correct order, so one
530 * should use them always.
533 for_each_intel_encoder(dev
, encoder
) {
534 struct intel_dp
*intel_dp
;
536 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
539 intel_dp
= enc_to_intel_dp(&encoder
->base
);
540 intel_dp
->pps_pipe
= INVALID_PIPE
;
545 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
547 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
550 return BXT_PP_CONTROL(0);
551 else if (HAS_PCH_SPLIT(dev
))
552 return PCH_PP_CONTROL
;
554 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
558 _pp_stat_reg(struct intel_dp
*intel_dp
)
560 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
563 return BXT_PP_STATUS(0);
564 else if (HAS_PCH_SPLIT(dev
))
565 return PCH_PP_STATUS
;
567 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
570 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
571 This function only applicable when panel PM state is not to be tracked */
572 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
575 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
577 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
580 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
585 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
586 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
587 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
590 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
591 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
592 pp_div
= I915_READ(pp_div_reg
);
593 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
595 /* 0x1F write to PP_DIV_REG sets max cycle delay */
596 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
597 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
598 msleep(intel_dp
->panel_power_cycle_delay
);
601 pps_unlock(intel_dp
);
606 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
608 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
611 lockdep_assert_held(&dev_priv
->pps_mutex
);
613 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
614 intel_dp
->pps_pipe
== INVALID_PIPE
)
617 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
620 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
622 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
625 lockdep_assert_held(&dev_priv
->pps_mutex
);
627 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
628 intel_dp
->pps_pipe
== INVALID_PIPE
)
631 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
635 intel_dp_check_edp(struct intel_dp
*intel_dp
)
637 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
640 if (!is_edp(intel_dp
))
643 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
644 WARN(1, "eDP powered off while attempting aux channel communication.\n");
645 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
646 I915_READ(_pp_stat_reg(intel_dp
)),
647 I915_READ(_pp_ctrl_reg(intel_dp
)));
652 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
654 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
655 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
657 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
661 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
663 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
664 msecs_to_jiffies_timeout(10));
666 done
= wait_for_atomic(C
, 10) == 0;
668 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
675 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
677 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
678 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
684 * The clock divider is based off the hrawclk, and would like to run at
685 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
687 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
690 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
692 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
693 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
699 * The clock divider is based off the cdclk or PCH rawclk, and would
700 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
701 * divide by 2000 and use that
703 if (intel_dig_port
->port
== PORT_A
)
704 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
706 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
709 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
711 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
712 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
714 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
715 /* Workaround for non-ULT HSW */
723 return ilk_get_aux_clock_divider(intel_dp
, index
);
726 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
729 * SKL doesn't need us to program the AUX clock divider (Hardware will
730 * derive the clock from CDCLK automatically). We still implement the
731 * get_aux_clock_divider vfunc to plug-in into the existing code.
733 return index
? 0 : 1;
736 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
739 uint32_t aux_clock_divider
)
741 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
742 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
743 uint32_t precharge
, timeout
;
750 if (IS_BROADWELL(dev
) && intel_dig_port
->port
== PORT_A
)
751 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
753 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
755 return DP_AUX_CH_CTL_SEND_BUSY
|
757 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
758 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
760 DP_AUX_CH_CTL_RECEIVE_ERROR
|
761 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
762 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
763 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
766 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
771 return DP_AUX_CH_CTL_SEND_BUSY
|
773 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
775 DP_AUX_CH_CTL_TIME_OUT_1600us
|
776 DP_AUX_CH_CTL_RECEIVE_ERROR
|
777 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
778 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
782 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
783 const uint8_t *send
, int send_bytes
,
784 uint8_t *recv
, int recv_size
)
786 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
787 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
789 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
790 uint32_t aux_clock_divider
;
791 int i
, ret
, recv_bytes
;
794 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
800 * We will be called with VDD already enabled for dpcd/edid/oui reads.
801 * In such cases we want to leave VDD enabled and it's up to upper layers
802 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
805 vdd
= edp_panel_vdd_on(intel_dp
);
807 /* dp aux is extremely sensitive to irq latency, hence request the
808 * lowest possible wakeup latency and so prevent the cpu from going into
811 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
813 intel_dp_check_edp(intel_dp
);
815 /* Try to wait for any previous AUX channel activity */
816 for (try = 0; try < 3; try++) {
817 status
= I915_READ_NOTRACE(ch_ctl
);
818 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
824 static u32 last_status
= -1;
825 const u32 status
= I915_READ(ch_ctl
);
827 if (status
!= last_status
) {
828 WARN(1, "dp_aux_ch not started status 0x%08x\n",
830 last_status
= status
;
837 /* Only 5 data registers! */
838 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
843 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
844 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
849 /* Must try at least 3 times according to DP spec */
850 for (try = 0; try < 5; try++) {
851 /* Load the send data into the aux channel data registers */
852 for (i
= 0; i
< send_bytes
; i
+= 4)
853 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
854 intel_dp_pack_aux(send
+ i
,
857 /* Send the command and wait for it to complete */
858 I915_WRITE(ch_ctl
, send_ctl
);
860 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
862 /* Clear done status and any errors */
866 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
867 DP_AUX_CH_CTL_RECEIVE_ERROR
);
869 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
872 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
873 * 400us delay required for errors and timeouts
874 * Timeout errors from the HW already meet this
875 * requirement so skip to next iteration
877 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
878 usleep_range(400, 500);
881 if (status
& DP_AUX_CH_CTL_DONE
)
886 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
887 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
893 /* Check for timeout or receive error.
894 * Timeouts occur when the sink is not connected
896 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
897 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
902 /* Timeouts occur when the device isn't connected, so they're
903 * "normal" -- don't fill the kernel log with these */
904 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
905 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
910 /* Unload any bytes sent back from the other side */
911 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
912 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
915 * By BSpec: "Message sizes of 0 or >20 are not allowed."
916 * We have no idea of what happened so we return -EBUSY so
917 * drm layer takes care for the necessary retries.
919 if (recv_bytes
== 0 || recv_bytes
> 20) {
920 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
923 * FIXME: This patch was created on top of a series that
924 * organize the retries at drm level. There EBUSY should
925 * also take care for 1ms wait before retrying.
926 * That aux retries re-org is still needed and after that is
927 * merged we remove this sleep from here.
929 usleep_range(1000, 1500);
934 if (recv_bytes
> recv_size
)
935 recv_bytes
= recv_size
;
937 for (i
= 0; i
< recv_bytes
; i
+= 4)
938 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
939 recv
+ i
, recv_bytes
- i
);
943 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
946 edp_panel_vdd_off(intel_dp
, false);
948 pps_unlock(intel_dp
);
953 #define BARE_ADDRESS_SIZE 3
954 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
956 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
958 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
959 uint8_t txbuf
[20], rxbuf
[20];
960 size_t txsize
, rxsize
;
963 txbuf
[0] = (msg
->request
<< 4) |
964 ((msg
->address
>> 16) & 0xf);
965 txbuf
[1] = (msg
->address
>> 8) & 0xff;
966 txbuf
[2] = msg
->address
& 0xff;
967 txbuf
[3] = msg
->size
- 1;
969 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
970 case DP_AUX_NATIVE_WRITE
:
971 case DP_AUX_I2C_WRITE
:
972 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
973 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
974 rxsize
= 2; /* 0 or 1 data bytes */
976 if (WARN_ON(txsize
> 20))
980 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
984 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
986 msg
->reply
= rxbuf
[0] >> 4;
989 /* Number of bytes written in a short write. */
990 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
992 /* Return payload size. */
998 case DP_AUX_NATIVE_READ
:
999 case DP_AUX_I2C_READ
:
1000 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1001 rxsize
= msg
->size
+ 1;
1003 if (WARN_ON(rxsize
> 20))
1006 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1008 msg
->reply
= rxbuf
[0] >> 4;
1010 * Assume happy day, and copy the data. The caller is
1011 * expected to check msg->reply before touching it.
1013 * Return payload size.
1016 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1028 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1035 return DP_AUX_CH_CTL(port
);
1038 return DP_AUX_CH_CTL(PORT_B
);
1042 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1043 enum port port
, int index
)
1049 return DP_AUX_CH_DATA(port
, index
);
1052 return DP_AUX_CH_DATA(PORT_B
, index
);
1056 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1061 return DP_AUX_CH_CTL(port
);
1065 return PCH_DP_AUX_CH_CTL(port
);
1068 return DP_AUX_CH_CTL(PORT_A
);
1072 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1073 enum port port
, int index
)
1077 return DP_AUX_CH_DATA(port
, index
);
1081 return PCH_DP_AUX_CH_DATA(port
, index
);
1084 return DP_AUX_CH_DATA(PORT_A
, index
);
1089 * On SKL we don't have Aux for port E so we rely
1090 * on VBT to set a proper alternate aux channel.
1092 static enum port
skl_porte_aux_port(struct drm_i915_private
*dev_priv
)
1094 const struct ddi_vbt_port_info
*info
=
1095 &dev_priv
->vbt
.ddi_port_info
[PORT_E
];
1097 switch (info
->alternate_aux_channel
) {
1107 MISSING_CASE(info
->alternate_aux_channel
);
1112 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1116 port
= skl_porte_aux_port(dev_priv
);
1123 return DP_AUX_CH_CTL(port
);
1126 return DP_AUX_CH_CTL(PORT_A
);
1130 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1131 enum port port
, int index
)
1134 port
= skl_porte_aux_port(dev_priv
);
1141 return DP_AUX_CH_DATA(port
, index
);
1144 return DP_AUX_CH_DATA(PORT_A
, index
);
1148 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1151 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1152 return skl_aux_ctl_reg(dev_priv
, port
);
1153 else if (HAS_PCH_SPLIT(dev_priv
))
1154 return ilk_aux_ctl_reg(dev_priv
, port
);
1156 return g4x_aux_ctl_reg(dev_priv
, port
);
1159 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1160 enum port port
, int index
)
1162 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1163 return skl_aux_data_reg(dev_priv
, port
, index
);
1164 else if (HAS_PCH_SPLIT(dev_priv
))
1165 return ilk_aux_data_reg(dev_priv
, port
, index
);
1167 return g4x_aux_data_reg(dev_priv
, port
, index
);
1170 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1172 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1173 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1176 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1177 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1178 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1182 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1184 drm_dp_aux_unregister(&intel_dp
->aux
);
1185 kfree(intel_dp
->aux
.name
);
1189 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1191 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1192 enum port port
= intel_dig_port
->port
;
1195 intel_aux_reg_init(intel_dp
);
1197 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1198 if (!intel_dp
->aux
.name
)
1201 intel_dp
->aux
.dev
= connector
->base
.kdev
;
1202 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1204 DRM_DEBUG_KMS("registering %s bus for %s\n",
1206 connector
->base
.kdev
->kobj
.name
);
1208 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1210 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1211 intel_dp
->aux
.name
, ret
);
1212 kfree(intel_dp
->aux
.name
);
1220 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1222 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1224 intel_dp_aux_fini(intel_dp
);
1225 intel_connector_unregister(intel_connector
);
1229 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1231 if (intel_dp
->num_sink_rates
) {
1232 *sink_rates
= intel_dp
->sink_rates
;
1233 return intel_dp
->num_sink_rates
;
1236 *sink_rates
= default_rates
;
1238 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1241 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1243 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1244 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1246 /* WaDisableHBR2:skl */
1247 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
))
1250 if ((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) || IS_BROADWELL(dev
) ||
1251 (INTEL_INFO(dev
)->gen
>= 9))
1258 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1260 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1261 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1264 if (IS_BROXTON(dev
)) {
1265 *source_rates
= bxt_rates
;
1266 size
= ARRAY_SIZE(bxt_rates
);
1267 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1268 *source_rates
= skl_rates
;
1269 size
= ARRAY_SIZE(skl_rates
);
1271 *source_rates
= default_rates
;
1272 size
= ARRAY_SIZE(default_rates
);
1275 /* This depends on the fact that 5.4 is last value in the array */
1276 if (!intel_dp_source_supports_hbr2(intel_dp
))
1283 intel_dp_set_clock(struct intel_encoder
*encoder
,
1284 struct intel_crtc_state
*pipe_config
)
1286 struct drm_device
*dev
= encoder
->base
.dev
;
1287 const struct dp_link_dpll
*divisor
= NULL
;
1291 divisor
= gen4_dpll
;
1292 count
= ARRAY_SIZE(gen4_dpll
);
1293 } else if (HAS_PCH_SPLIT(dev
)) {
1295 count
= ARRAY_SIZE(pch_dpll
);
1296 } else if (IS_CHERRYVIEW(dev
)) {
1298 count
= ARRAY_SIZE(chv_dpll
);
1299 } else if (IS_VALLEYVIEW(dev
)) {
1301 count
= ARRAY_SIZE(vlv_dpll
);
1304 if (divisor
&& count
) {
1305 for (i
= 0; i
< count
; i
++) {
1306 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1307 pipe_config
->dpll
= divisor
[i
].dpll
;
1308 pipe_config
->clock_set
= true;
1315 static int intersect_rates(const int *source_rates
, int source_len
,
1316 const int *sink_rates
, int sink_len
,
1319 int i
= 0, j
= 0, k
= 0;
1321 while (i
< source_len
&& j
< sink_len
) {
1322 if (source_rates
[i
] == sink_rates
[j
]) {
1323 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1325 common_rates
[k
] = source_rates
[i
];
1329 } else if (source_rates
[i
] < sink_rates
[j
]) {
1338 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1341 const int *source_rates
, *sink_rates
;
1342 int source_len
, sink_len
;
1344 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1345 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1347 return intersect_rates(source_rates
, source_len
,
1348 sink_rates
, sink_len
,
1352 static void snprintf_int_array(char *str
, size_t len
,
1353 const int *array
, int nelem
)
1359 for (i
= 0; i
< nelem
; i
++) {
1360 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1368 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1370 const int *source_rates
, *sink_rates
;
1371 int source_len
, sink_len
, common_len
;
1372 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1373 char str
[128]; /* FIXME: too big for stack? */
1375 if ((drm_debug
& DRM_UT_KMS
) == 0)
1378 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1379 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1380 DRM_DEBUG_KMS("source rates: %s\n", str
);
1382 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1383 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1384 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1386 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1387 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1388 DRM_DEBUG_KMS("common rates: %s\n", str
);
1391 static int rate_to_index(int find
, const int *rates
)
1395 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1396 if (find
== rates
[i
])
1403 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1405 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1408 len
= intel_dp_common_rates(intel_dp
, rates
);
1409 if (WARN_ON(len
<= 0))
1412 return rates
[rate_to_index(0, rates
) - 1];
1415 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1417 return rate_to_index(rate
, intel_dp
->sink_rates
);
1420 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1421 uint8_t *link_bw
, uint8_t *rate_select
)
1423 if (intel_dp
->num_sink_rates
) {
1426 intel_dp_rate_select(intel_dp
, port_clock
);
1428 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1434 intel_dp_compute_config(struct intel_encoder
*encoder
,
1435 struct intel_crtc_state
*pipe_config
)
1437 struct drm_device
*dev
= encoder
->base
.dev
;
1438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1439 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1440 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1441 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1442 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1443 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1444 int lane_count
, clock
;
1445 int min_lane_count
= 1;
1446 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1447 /* Conveniently, the link BW constants become indices with a shift...*/
1451 int link_avail
, link_clock
;
1452 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1454 uint8_t link_bw
, rate_select
;
1456 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1458 /* No common link rates between source and sink */
1459 WARN_ON(common_len
<= 0);
1461 max_clock
= common_len
- 1;
1463 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1464 pipe_config
->has_pch_encoder
= true;
1466 pipe_config
->has_dp_encoder
= true;
1467 pipe_config
->has_drrs
= false;
1468 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1470 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1471 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1474 if (INTEL_INFO(dev
)->gen
>= 9) {
1476 ret
= skl_update_scaler_crtc(pipe_config
);
1481 if (HAS_GMCH_DISPLAY(dev
))
1482 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1483 intel_connector
->panel
.fitting_mode
);
1485 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1486 intel_connector
->panel
.fitting_mode
);
1489 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1492 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1493 "max bw %d pixel clock %iKHz\n",
1494 max_lane_count
, common_rates
[max_clock
],
1495 adjusted_mode
->crtc_clock
);
1497 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1498 * bpc in between. */
1499 bpp
= pipe_config
->pipe_bpp
;
1500 if (is_edp(intel_dp
)) {
1502 /* Get bpp from vbt only for panels that dont have bpp in edid */
1503 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1504 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1505 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1506 dev_priv
->vbt
.edp
.bpp
);
1507 bpp
= dev_priv
->vbt
.edp
.bpp
;
1511 * Use the maximum clock and number of lanes the eDP panel
1512 * advertizes being capable of. The panels are generally
1513 * designed to support only a single clock and lane
1514 * configuration, and typically these values correspond to the
1515 * native resolution of the panel.
1517 min_lane_count
= max_lane_count
;
1518 min_clock
= max_clock
;
1521 for (; bpp
>= 6*3; bpp
-= 2*3) {
1522 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1525 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1526 for (lane_count
= min_lane_count
;
1527 lane_count
<= max_lane_count
;
1530 link_clock
= common_rates
[clock
];
1531 link_avail
= intel_dp_max_data_rate(link_clock
,
1534 if (mode_rate
<= link_avail
) {
1544 if (intel_dp
->color_range_auto
) {
1547 * CEA-861-E - 5.1 Default Encoding Parameters
1548 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1550 pipe_config
->limited_color_range
=
1551 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1553 pipe_config
->limited_color_range
=
1554 intel_dp
->limited_color_range
;
1557 pipe_config
->lane_count
= lane_count
;
1559 pipe_config
->pipe_bpp
= bpp
;
1560 pipe_config
->port_clock
= common_rates
[clock
];
1562 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1563 &link_bw
, &rate_select
);
1565 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1566 link_bw
, rate_select
, pipe_config
->lane_count
,
1567 pipe_config
->port_clock
, bpp
);
1568 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1569 mode_rate
, link_avail
);
1571 intel_link_compute_m_n(bpp
, lane_count
,
1572 adjusted_mode
->crtc_clock
,
1573 pipe_config
->port_clock
,
1574 &pipe_config
->dp_m_n
);
1576 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1577 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1578 pipe_config
->has_drrs
= true;
1579 intel_link_compute_m_n(bpp
, lane_count
,
1580 intel_connector
->panel
.downclock_mode
->clock
,
1581 pipe_config
->port_clock
,
1582 &pipe_config
->dp_m2_n2
);
1586 intel_dp_set_clock(encoder
, pipe_config
);
1591 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1592 const struct intel_crtc_state
*pipe_config
)
1594 intel_dp
->link_rate
= pipe_config
->port_clock
;
1595 intel_dp
->lane_count
= pipe_config
->lane_count
;
1598 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1600 struct drm_device
*dev
= encoder
->base
.dev
;
1601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1602 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1603 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1604 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1605 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1607 intel_dp_set_link_params(intel_dp
, crtc
->config
);
1610 * There are four kinds of DP registers:
1617 * IBX PCH and CPU are the same for almost everything,
1618 * except that the CPU DP PLL is configured in this
1621 * CPT PCH is quite different, having many bits moved
1622 * to the TRANS_DP_CTL register instead. That
1623 * configuration happens (oddly) in ironlake_pch_enable
1626 /* Preserve the BIOS-computed detected bit. This is
1627 * supposed to be read-only.
1629 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1631 /* Handle DP bits in common between all three register formats */
1632 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1633 intel_dp
->DP
|= DP_PORT_WIDTH(crtc
->config
->lane_count
);
1635 /* Split out the IBX/CPU vs CPT settings */
1637 if (IS_GEN7(dev
) && port
== PORT_A
) {
1638 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1639 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1640 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1641 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1642 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1644 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1645 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1647 intel_dp
->DP
|= crtc
->pipe
<< 29;
1648 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1651 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1653 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1654 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1655 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1657 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1658 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1660 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1661 !IS_CHERRYVIEW(dev
) && crtc
->config
->limited_color_range
)
1662 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1664 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1665 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1666 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1667 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1668 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1670 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1671 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1673 if (IS_CHERRYVIEW(dev
))
1674 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1675 else if (crtc
->pipe
== PIPE_B
)
1676 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1680 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1681 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1683 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1684 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1686 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1687 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1689 static void wait_panel_status(struct intel_dp
*intel_dp
,
1693 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1695 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1697 lockdep_assert_held(&dev_priv
->pps_mutex
);
1699 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1700 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1702 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1704 I915_READ(pp_stat_reg
),
1705 I915_READ(pp_ctrl_reg
));
1707 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
,
1708 5 * USEC_PER_SEC
, 10 * USEC_PER_MSEC
))
1709 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1710 I915_READ(pp_stat_reg
),
1711 I915_READ(pp_ctrl_reg
));
1713 DRM_DEBUG_KMS("Wait complete\n");
1716 static void wait_panel_on(struct intel_dp
*intel_dp
)
1718 DRM_DEBUG_KMS("Wait for panel power on\n");
1719 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1722 static void wait_panel_off(struct intel_dp
*intel_dp
)
1724 DRM_DEBUG_KMS("Wait for panel power off time\n");
1725 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1728 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1730 ktime_t panel_power_on_time
;
1731 s64 panel_power_off_duration
;
1733 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1735 /* take the difference of currrent time and panel power off time
1736 * and then make panel wait for t11_t12 if needed. */
1737 panel_power_on_time
= ktime_get_boottime();
1738 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1740 /* When we disable the VDD override bit last we have to do the manual
1742 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1743 wait_remaining_ms_from_jiffies(jiffies
,
1744 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1746 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1749 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1751 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1752 intel_dp
->backlight_on_delay
);
1755 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1757 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1758 intel_dp
->backlight_off_delay
);
1761 /* Read the current pp_control value, unlocking the register if it
1765 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1767 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1771 lockdep_assert_held(&dev_priv
->pps_mutex
);
1773 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1774 if (!IS_BROXTON(dev
)) {
1775 control
&= ~PANEL_UNLOCK_MASK
;
1776 control
|= PANEL_UNLOCK_REGS
;
1782 * Must be paired with edp_panel_vdd_off().
1783 * Must hold pps_mutex around the whole on/off sequence.
1784 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1786 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1788 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1789 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1790 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1792 enum intel_display_power_domain power_domain
;
1794 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1795 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1797 lockdep_assert_held(&dev_priv
->pps_mutex
);
1799 if (!is_edp(intel_dp
))
1802 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1803 intel_dp
->want_panel_vdd
= true;
1805 if (edp_have_panel_vdd(intel_dp
))
1806 return need_to_disable
;
1808 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1809 intel_display_power_get(dev_priv
, power_domain
);
1811 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1812 port_name(intel_dig_port
->port
));
1814 if (!edp_have_panel_power(intel_dp
))
1815 wait_panel_power_cycle(intel_dp
);
1817 pp
= ironlake_get_pp_control(intel_dp
);
1818 pp
|= EDP_FORCE_VDD
;
1820 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1821 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1823 I915_WRITE(pp_ctrl_reg
, pp
);
1824 POSTING_READ(pp_ctrl_reg
);
1825 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1826 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1828 * If the panel wasn't on, delay before accessing aux channel
1830 if (!edp_have_panel_power(intel_dp
)) {
1831 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1832 port_name(intel_dig_port
->port
));
1833 msleep(intel_dp
->panel_power_up_delay
);
1836 return need_to_disable
;
1840 * Must be paired with intel_edp_panel_vdd_off() or
1841 * intel_edp_panel_off().
1842 * Nested calls to these functions are not allowed since
1843 * we drop the lock. Caller must use some higher level
1844 * locking to prevent nested calls from other threads.
1846 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1850 if (!is_edp(intel_dp
))
1854 vdd
= edp_panel_vdd_on(intel_dp
);
1855 pps_unlock(intel_dp
);
1857 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1858 port_name(dp_to_dig_port(intel_dp
)->port
));
1861 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1863 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1865 struct intel_digital_port
*intel_dig_port
=
1866 dp_to_dig_port(intel_dp
);
1867 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1868 enum intel_display_power_domain power_domain
;
1870 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1872 lockdep_assert_held(&dev_priv
->pps_mutex
);
1874 WARN_ON(intel_dp
->want_panel_vdd
);
1876 if (!edp_have_panel_vdd(intel_dp
))
1879 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1880 port_name(intel_dig_port
->port
));
1882 pp
= ironlake_get_pp_control(intel_dp
);
1883 pp
&= ~EDP_FORCE_VDD
;
1885 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1886 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1888 I915_WRITE(pp_ctrl_reg
, pp
);
1889 POSTING_READ(pp_ctrl_reg
);
1891 /* Make sure sequencer is idle before allowing subsequent activity */
1892 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1893 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1895 if ((pp
& POWER_TARGET_ON
) == 0)
1896 intel_dp
->panel_power_off_time
= ktime_get_boottime();
1898 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1899 intel_display_power_put(dev_priv
, power_domain
);
1902 static void edp_panel_vdd_work(struct work_struct
*__work
)
1904 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1905 struct intel_dp
, panel_vdd_work
);
1908 if (!intel_dp
->want_panel_vdd
)
1909 edp_panel_vdd_off_sync(intel_dp
);
1910 pps_unlock(intel_dp
);
1913 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1915 unsigned long delay
;
1918 * Queue the timer to fire a long time from now (relative to the power
1919 * down delay) to keep the panel power up across a sequence of
1922 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1923 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1927 * Must be paired with edp_panel_vdd_on().
1928 * Must hold pps_mutex around the whole on/off sequence.
1929 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1931 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1933 struct drm_i915_private
*dev_priv
=
1934 intel_dp_to_dev(intel_dp
)->dev_private
;
1936 lockdep_assert_held(&dev_priv
->pps_mutex
);
1938 if (!is_edp(intel_dp
))
1941 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1942 port_name(dp_to_dig_port(intel_dp
)->port
));
1944 intel_dp
->want_panel_vdd
= false;
1947 edp_panel_vdd_off_sync(intel_dp
);
1949 edp_panel_vdd_schedule_off(intel_dp
);
1952 static void edp_panel_on(struct intel_dp
*intel_dp
)
1954 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1957 i915_reg_t pp_ctrl_reg
;
1959 lockdep_assert_held(&dev_priv
->pps_mutex
);
1961 if (!is_edp(intel_dp
))
1964 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1965 port_name(dp_to_dig_port(intel_dp
)->port
));
1967 if (WARN(edp_have_panel_power(intel_dp
),
1968 "eDP port %c panel power already on\n",
1969 port_name(dp_to_dig_port(intel_dp
)->port
)))
1972 wait_panel_power_cycle(intel_dp
);
1974 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1975 pp
= ironlake_get_pp_control(intel_dp
);
1977 /* ILK workaround: disable reset around power sequence */
1978 pp
&= ~PANEL_POWER_RESET
;
1979 I915_WRITE(pp_ctrl_reg
, pp
);
1980 POSTING_READ(pp_ctrl_reg
);
1983 pp
|= POWER_TARGET_ON
;
1985 pp
|= PANEL_POWER_RESET
;
1987 I915_WRITE(pp_ctrl_reg
, pp
);
1988 POSTING_READ(pp_ctrl_reg
);
1990 wait_panel_on(intel_dp
);
1991 intel_dp
->last_power_on
= jiffies
;
1994 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1995 I915_WRITE(pp_ctrl_reg
, pp
);
1996 POSTING_READ(pp_ctrl_reg
);
2000 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2002 if (!is_edp(intel_dp
))
2006 edp_panel_on(intel_dp
);
2007 pps_unlock(intel_dp
);
2011 static void edp_panel_off(struct intel_dp
*intel_dp
)
2013 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2014 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2015 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2017 enum intel_display_power_domain power_domain
;
2019 i915_reg_t pp_ctrl_reg
;
2021 lockdep_assert_held(&dev_priv
->pps_mutex
);
2023 if (!is_edp(intel_dp
))
2026 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2027 port_name(dp_to_dig_port(intel_dp
)->port
));
2029 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2030 port_name(dp_to_dig_port(intel_dp
)->port
));
2032 pp
= ironlake_get_pp_control(intel_dp
);
2033 /* We need to switch off panel power _and_ force vdd, for otherwise some
2034 * panels get very unhappy and cease to work. */
2035 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2038 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2040 intel_dp
->want_panel_vdd
= false;
2042 I915_WRITE(pp_ctrl_reg
, pp
);
2043 POSTING_READ(pp_ctrl_reg
);
2045 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2046 wait_panel_off(intel_dp
);
2048 /* We got a reference when we enabled the VDD. */
2049 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2050 intel_display_power_put(dev_priv
, power_domain
);
2053 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2055 if (!is_edp(intel_dp
))
2059 edp_panel_off(intel_dp
);
2060 pps_unlock(intel_dp
);
2063 /* Enable backlight in the panel power control. */
2064 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2066 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2067 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2070 i915_reg_t pp_ctrl_reg
;
2073 * If we enable the backlight right away following a panel power
2074 * on, we may see slight flicker as the panel syncs with the eDP
2075 * link. So delay a bit to make sure the image is solid before
2076 * allowing it to appear.
2078 wait_backlight_on(intel_dp
);
2082 pp
= ironlake_get_pp_control(intel_dp
);
2083 pp
|= EDP_BLC_ENABLE
;
2085 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2087 I915_WRITE(pp_ctrl_reg
, pp
);
2088 POSTING_READ(pp_ctrl_reg
);
2090 pps_unlock(intel_dp
);
2093 /* Enable backlight PWM and backlight PP control. */
2094 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2096 if (!is_edp(intel_dp
))
2099 DRM_DEBUG_KMS("\n");
2101 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2102 _intel_edp_backlight_on(intel_dp
);
2105 /* Disable backlight in the panel power control. */
2106 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2108 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2111 i915_reg_t pp_ctrl_reg
;
2113 if (!is_edp(intel_dp
))
2118 pp
= ironlake_get_pp_control(intel_dp
);
2119 pp
&= ~EDP_BLC_ENABLE
;
2121 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2123 I915_WRITE(pp_ctrl_reg
, pp
);
2124 POSTING_READ(pp_ctrl_reg
);
2126 pps_unlock(intel_dp
);
2128 intel_dp
->last_backlight_off
= jiffies
;
2129 edp_wait_backlight_off(intel_dp
);
2132 /* Disable backlight PP control and backlight PWM. */
2133 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2135 if (!is_edp(intel_dp
))
2138 DRM_DEBUG_KMS("\n");
2140 _intel_edp_backlight_off(intel_dp
);
2141 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2145 * Hook for controlling the panel power control backlight through the bl_power
2146 * sysfs attribute. Take care to handle multiple calls.
2148 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2151 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2155 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2156 pps_unlock(intel_dp
);
2158 if (is_enabled
== enable
)
2161 DRM_DEBUG_KMS("panel power control backlight %s\n",
2162 enable
? "enable" : "disable");
2165 _intel_edp_backlight_on(intel_dp
);
2167 _intel_edp_backlight_off(intel_dp
);
2170 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2172 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2173 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2174 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2176 I915_STATE_WARN(cur_state
!= state
,
2177 "DP port %c state assertion failure (expected %s, current %s)\n",
2178 port_name(dig_port
->port
),
2179 onoff(state
), onoff(cur_state
));
2181 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2183 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2185 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2187 I915_STATE_WARN(cur_state
!= state
,
2188 "eDP PLL state assertion failure (expected %s, current %s)\n",
2189 onoff(state
), onoff(cur_state
));
2191 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2192 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2194 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2196 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2197 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2198 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2200 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2201 assert_dp_port_disabled(intel_dp
);
2202 assert_edp_pll_disabled(dev_priv
);
2204 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2205 crtc
->config
->port_clock
);
2207 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2209 if (crtc
->config
->port_clock
== 162000)
2210 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2212 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2214 I915_WRITE(DP_A
, intel_dp
->DP
);
2218 intel_dp
->DP
|= DP_PLL_ENABLE
;
2220 I915_WRITE(DP_A
, intel_dp
->DP
);
2225 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2227 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2228 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2229 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2231 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2232 assert_dp_port_disabled(intel_dp
);
2233 assert_edp_pll_enabled(dev_priv
);
2235 DRM_DEBUG_KMS("disabling eDP PLL\n");
2237 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2239 I915_WRITE(DP_A
, intel_dp
->DP
);
2244 /* If the sink supports it, try to set the power state appropriately */
2245 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2249 /* Should have a valid DPCD by this point */
2250 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2253 if (mode
!= DRM_MODE_DPMS_ON
) {
2254 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2258 * When turning on, we need to retry for 1ms to give the sink
2261 for (i
= 0; i
< 3; i
++) {
2262 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2271 DRM_DEBUG_KMS("failed to %s sink power state\n",
2272 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2275 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2278 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2279 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2280 struct drm_device
*dev
= encoder
->base
.dev
;
2281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2282 enum intel_display_power_domain power_domain
;
2286 power_domain
= intel_display_port_power_domain(encoder
);
2287 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2292 tmp
= I915_READ(intel_dp
->output_reg
);
2294 if (!(tmp
& DP_PORT_EN
))
2297 if (IS_GEN7(dev
) && port
== PORT_A
) {
2298 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2299 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2302 for_each_pipe(dev_priv
, p
) {
2303 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2304 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2312 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2313 i915_mmio_reg_offset(intel_dp
->output_reg
));
2314 } else if (IS_CHERRYVIEW(dev
)) {
2315 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2317 *pipe
= PORT_TO_PIPE(tmp
);
2323 intel_display_power_put(dev_priv
, power_domain
);
2328 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2329 struct intel_crtc_state
*pipe_config
)
2331 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2333 struct drm_device
*dev
= encoder
->base
.dev
;
2334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2335 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2336 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2338 tmp
= I915_READ(intel_dp
->output_reg
);
2340 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2342 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2343 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2345 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2346 flags
|= DRM_MODE_FLAG_PHSYNC
;
2348 flags
|= DRM_MODE_FLAG_NHSYNC
;
2350 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2351 flags
|= DRM_MODE_FLAG_PVSYNC
;
2353 flags
|= DRM_MODE_FLAG_NVSYNC
;
2355 if (tmp
& DP_SYNC_HS_HIGH
)
2356 flags
|= DRM_MODE_FLAG_PHSYNC
;
2358 flags
|= DRM_MODE_FLAG_NHSYNC
;
2360 if (tmp
& DP_SYNC_VS_HIGH
)
2361 flags
|= DRM_MODE_FLAG_PVSYNC
;
2363 flags
|= DRM_MODE_FLAG_NVSYNC
;
2366 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2368 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2369 !IS_CHERRYVIEW(dev
) && tmp
& DP_COLOR_RANGE_16_235
)
2370 pipe_config
->limited_color_range
= true;
2372 pipe_config
->has_dp_encoder
= true;
2374 pipe_config
->lane_count
=
2375 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2377 intel_dp_get_m_n(crtc
, pipe_config
);
2379 if (port
== PORT_A
) {
2380 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2381 pipe_config
->port_clock
= 162000;
2383 pipe_config
->port_clock
= 270000;
2386 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2387 intel_dotclock_calculate(pipe_config
->port_clock
,
2388 &pipe_config
->dp_m_n
);
2390 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2391 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2393 * This is a big fat ugly hack.
2395 * Some machines in UEFI boot mode provide us a VBT that has 18
2396 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2397 * unknown we fail to light up. Yet the same BIOS boots up with
2398 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2399 * max, not what it tells us to use.
2401 * Note: This will still be broken if the eDP panel is not lit
2402 * up by the BIOS, and thus we can't get the mode at module
2405 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2406 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2407 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2411 static void intel_disable_dp(struct intel_encoder
*encoder
)
2413 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2414 struct drm_device
*dev
= encoder
->base
.dev
;
2415 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2417 if (crtc
->config
->has_audio
)
2418 intel_audio_codec_disable(encoder
);
2420 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2421 intel_psr_disable(intel_dp
);
2423 /* Make sure the panel is off before trying to change the mode. But also
2424 * ensure that we have vdd while we switch off the panel. */
2425 intel_edp_panel_vdd_on(intel_dp
);
2426 intel_edp_backlight_off(intel_dp
);
2427 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2428 intel_edp_panel_off(intel_dp
);
2430 /* disable the port before the pipe on g4x */
2431 if (INTEL_INFO(dev
)->gen
< 5)
2432 intel_dp_link_down(intel_dp
);
2435 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2437 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2438 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2440 intel_dp_link_down(intel_dp
);
2442 /* Only ilk+ has port A */
2444 ironlake_edp_pll_off(intel_dp
);
2447 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2449 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2451 intel_dp_link_down(intel_dp
);
2454 static void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
2457 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2458 enum dpio_channel ch
= vlv_dport_to_channel(enc_to_dig_port(&encoder
->base
));
2459 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2460 enum pipe pipe
= crtc
->pipe
;
2463 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2465 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2467 val
|= DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
;
2468 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2470 if (crtc
->config
->lane_count
> 2) {
2471 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2473 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2475 val
|= DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
;
2476 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2479 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2480 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2482 val
&= ~DPIO_PCS_CLK_SOFT_RESET
;
2484 val
|= DPIO_PCS_CLK_SOFT_RESET
;
2485 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2487 if (crtc
->config
->lane_count
> 2) {
2488 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2489 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2491 val
&= ~DPIO_PCS_CLK_SOFT_RESET
;
2493 val
|= DPIO_PCS_CLK_SOFT_RESET
;
2494 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2498 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2500 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2501 struct drm_device
*dev
= encoder
->base
.dev
;
2502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2504 intel_dp_link_down(intel_dp
);
2506 mutex_lock(&dev_priv
->sb_lock
);
2508 /* Assert data lane reset */
2509 chv_data_lane_soft_reset(encoder
, true);
2511 mutex_unlock(&dev_priv
->sb_lock
);
2515 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2517 uint8_t dp_train_pat
)
2519 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2520 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2522 enum port port
= intel_dig_port
->port
;
2525 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2527 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2528 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2530 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2532 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2533 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2534 case DP_TRAINING_PATTERN_DISABLE
:
2535 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2538 case DP_TRAINING_PATTERN_1
:
2539 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2541 case DP_TRAINING_PATTERN_2
:
2542 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2544 case DP_TRAINING_PATTERN_3
:
2545 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2548 I915_WRITE(DP_TP_CTL(port
), temp
);
2550 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2551 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2552 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2554 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2555 case DP_TRAINING_PATTERN_DISABLE
:
2556 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2558 case DP_TRAINING_PATTERN_1
:
2559 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2561 case DP_TRAINING_PATTERN_2
:
2562 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2564 case DP_TRAINING_PATTERN_3
:
2565 DRM_ERROR("DP training pattern 3 not supported\n");
2566 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2571 if (IS_CHERRYVIEW(dev
))
2572 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2574 *DP
&= ~DP_LINK_TRAIN_MASK
;
2576 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2577 case DP_TRAINING_PATTERN_DISABLE
:
2578 *DP
|= DP_LINK_TRAIN_OFF
;
2580 case DP_TRAINING_PATTERN_1
:
2581 *DP
|= DP_LINK_TRAIN_PAT_1
;
2583 case DP_TRAINING_PATTERN_2
:
2584 *DP
|= DP_LINK_TRAIN_PAT_2
;
2586 case DP_TRAINING_PATTERN_3
:
2587 if (IS_CHERRYVIEW(dev
)) {
2588 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2590 DRM_ERROR("DP training pattern 3 not supported\n");
2591 *DP
|= DP_LINK_TRAIN_PAT_2
;
2598 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2600 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2602 struct intel_crtc
*crtc
=
2603 to_intel_crtc(dp_to_dig_port(intel_dp
)->base
.base
.crtc
);
2605 /* enable with pattern 1 (as per spec) */
2606 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2607 DP_TRAINING_PATTERN_1
);
2609 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2610 POSTING_READ(intel_dp
->output_reg
);
2613 * Magic for VLV/CHV. We _must_ first set up the register
2614 * without actually enabling the port, and then do another
2615 * write to enable the port. Otherwise link training will
2616 * fail when the power sequencer is freshly used for this port.
2618 intel_dp
->DP
|= DP_PORT_EN
;
2619 if (crtc
->config
->has_audio
)
2620 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2622 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2623 POSTING_READ(intel_dp
->output_reg
);
2626 static void intel_enable_dp(struct intel_encoder
*encoder
)
2628 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2629 struct drm_device
*dev
= encoder
->base
.dev
;
2630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2631 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2632 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2633 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2634 enum pipe pipe
= crtc
->pipe
;
2636 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2641 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2642 vlv_init_panel_power_sequencer(intel_dp
);
2645 * We get an occasional spurious underrun between the port
2646 * enable and vdd enable, when enabling port A eDP.
2648 * FIXME: Not sure if this applies to (PCH) port D eDP as well
2651 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
2653 intel_dp_enable_port(intel_dp
);
2655 if (port
== PORT_A
&& IS_GEN5(dev_priv
)) {
2657 * Underrun reporting for the other pipe was disabled in
2658 * g4x_pre_enable_dp(). The eDP PLL and port have now been
2659 * enabled, so it's now safe to re-enable underrun reporting.
2661 intel_wait_for_vblank_if_active(dev_priv
->dev
, !pipe
);
2662 intel_set_cpu_fifo_underrun_reporting(dev_priv
, !pipe
, true);
2663 intel_set_pch_fifo_underrun_reporting(dev_priv
, !pipe
, true);
2666 edp_panel_vdd_on(intel_dp
);
2667 edp_panel_on(intel_dp
);
2668 edp_panel_vdd_off(intel_dp
, true);
2671 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
2673 pps_unlock(intel_dp
);
2675 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2676 unsigned int lane_mask
= 0x0;
2678 if (IS_CHERRYVIEW(dev
))
2679 lane_mask
= intel_dp_unused_lane_mask(crtc
->config
->lane_count
);
2681 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2685 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2686 intel_dp_start_link_train(intel_dp
);
2687 intel_dp_stop_link_train(intel_dp
);
2689 if (crtc
->config
->has_audio
) {
2690 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2692 intel_audio_codec_enable(encoder
);
2696 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2698 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2700 intel_enable_dp(encoder
);
2701 intel_edp_backlight_on(intel_dp
);
2704 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2706 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2708 intel_edp_backlight_on(intel_dp
);
2709 intel_psr_enable(intel_dp
);
2712 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2714 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2715 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2716 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2717 enum pipe pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
2719 intel_dp_prepare(encoder
);
2721 if (port
== PORT_A
&& IS_GEN5(dev_priv
)) {
2723 * We get FIFO underruns on the other pipe when
2724 * enabling the CPU eDP PLL, and when enabling CPU
2725 * eDP port. We could potentially avoid the PLL
2726 * underrun with a vblank wait just prior to enabling
2727 * the PLL, but that doesn't appear to help the port
2728 * enable case. Just sweep it all under the rug.
2730 intel_set_cpu_fifo_underrun_reporting(dev_priv
, !pipe
, false);
2731 intel_set_pch_fifo_underrun_reporting(dev_priv
, !pipe
, false);
2734 /* Only ilk+ has port A */
2736 ironlake_edp_pll_on(intel_dp
);
2739 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2741 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2742 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2743 enum pipe pipe
= intel_dp
->pps_pipe
;
2744 i915_reg_t pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2746 edp_panel_vdd_off_sync(intel_dp
);
2749 * VLV seems to get confused when multiple power seqeuencers
2750 * have the same port selected (even if only one has power/vdd
2751 * enabled). The failure manifests as vlv_wait_port_ready() failing
2752 * CHV on the other hand doesn't seem to mind having the same port
2753 * selected in multiple power seqeuencers, but let's clear the
2754 * port select always when logically disconnecting a power sequencer
2757 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2758 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2759 I915_WRITE(pp_on_reg
, 0);
2760 POSTING_READ(pp_on_reg
);
2762 intel_dp
->pps_pipe
= INVALID_PIPE
;
2765 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2769 struct intel_encoder
*encoder
;
2771 lockdep_assert_held(&dev_priv
->pps_mutex
);
2773 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2776 for_each_intel_encoder(dev
, encoder
) {
2777 struct intel_dp
*intel_dp
;
2780 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2783 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2784 port
= dp_to_dig_port(intel_dp
)->port
;
2786 if (intel_dp
->pps_pipe
!= pipe
)
2789 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2790 pipe_name(pipe
), port_name(port
));
2792 WARN(encoder
->base
.crtc
,
2793 "stealing pipe %c power sequencer from active eDP port %c\n",
2794 pipe_name(pipe
), port_name(port
));
2796 /* make sure vdd is off before we steal it */
2797 vlv_detach_power_sequencer(intel_dp
);
2801 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2803 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2804 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2805 struct drm_device
*dev
= encoder
->base
.dev
;
2806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2807 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2809 lockdep_assert_held(&dev_priv
->pps_mutex
);
2811 if (!is_edp(intel_dp
))
2814 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2818 * If another power sequencer was being used on this
2819 * port previously make sure to turn off vdd there while
2820 * we still have control of it.
2822 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2823 vlv_detach_power_sequencer(intel_dp
);
2826 * We may be stealing the power
2827 * sequencer from another port.
2829 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2831 /* now it's all ours */
2832 intel_dp
->pps_pipe
= crtc
->pipe
;
2834 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2835 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2837 /* init power sequencer on this pipe and port */
2838 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2839 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2842 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2844 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2845 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2846 struct drm_device
*dev
= encoder
->base
.dev
;
2847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2848 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2849 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2850 int pipe
= intel_crtc
->pipe
;
2853 mutex_lock(&dev_priv
->sb_lock
);
2855 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2862 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2863 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2864 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2866 mutex_unlock(&dev_priv
->sb_lock
);
2868 intel_enable_dp(encoder
);
2871 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2873 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2874 struct drm_device
*dev
= encoder
->base
.dev
;
2875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2876 struct intel_crtc
*intel_crtc
=
2877 to_intel_crtc(encoder
->base
.crtc
);
2878 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2879 int pipe
= intel_crtc
->pipe
;
2881 intel_dp_prepare(encoder
);
2883 /* Program Tx lane resets to default */
2884 mutex_lock(&dev_priv
->sb_lock
);
2885 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2886 DPIO_PCS_TX_LANE2_RESET
|
2887 DPIO_PCS_TX_LANE1_RESET
);
2888 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2889 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2890 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2891 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2892 DPIO_PCS_CLK_SOFT_RESET
);
2894 /* Fix up inter-pair skew failure */
2895 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2896 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2897 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2898 mutex_unlock(&dev_priv
->sb_lock
);
2901 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2903 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2904 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2905 struct drm_device
*dev
= encoder
->base
.dev
;
2906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2907 struct intel_crtc
*intel_crtc
=
2908 to_intel_crtc(encoder
->base
.crtc
);
2909 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2910 int pipe
= intel_crtc
->pipe
;
2911 int data
, i
, stagger
;
2914 mutex_lock(&dev_priv
->sb_lock
);
2916 /* allow hardware to manage TX FIFO reset source */
2917 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2918 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2919 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2921 if (intel_crtc
->config
->lane_count
> 2) {
2922 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2923 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2924 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2927 /* Program Tx lane latency optimal setting*/
2928 for (i
= 0; i
< intel_crtc
->config
->lane_count
; i
++) {
2929 /* Set the upar bit */
2930 if (intel_crtc
->config
->lane_count
== 1)
2933 data
= (i
== 1) ? 0x0 : 0x1;
2934 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2935 data
<< DPIO_UPAR_SHIFT
);
2938 /* Data lane stagger programming */
2939 if (intel_crtc
->config
->port_clock
> 270000)
2941 else if (intel_crtc
->config
->port_clock
> 135000)
2943 else if (intel_crtc
->config
->port_clock
> 67500)
2945 else if (intel_crtc
->config
->port_clock
> 33750)
2950 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2951 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2952 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2954 if (intel_crtc
->config
->lane_count
> 2) {
2955 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2956 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2957 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2960 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW12(ch
),
2961 DPIO_LANESTAGGER_STRAP(stagger
) |
2962 DPIO_LANESTAGGER_STRAP_OVRD
|
2963 DPIO_TX1_STAGGER_MASK(0x1f) |
2964 DPIO_TX1_STAGGER_MULT(6) |
2965 DPIO_TX2_STAGGER_MULT(0));
2967 if (intel_crtc
->config
->lane_count
> 2) {
2968 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW12(ch
),
2969 DPIO_LANESTAGGER_STRAP(stagger
) |
2970 DPIO_LANESTAGGER_STRAP_OVRD
|
2971 DPIO_TX1_STAGGER_MASK(0x1f) |
2972 DPIO_TX1_STAGGER_MULT(7) |
2973 DPIO_TX2_STAGGER_MULT(5));
2976 /* Deassert data lane reset */
2977 chv_data_lane_soft_reset(encoder
, false);
2979 mutex_unlock(&dev_priv
->sb_lock
);
2981 intel_enable_dp(encoder
);
2983 /* Second common lane will stay alive on its own now */
2984 if (dport
->release_cl2_override
) {
2985 chv_phy_powergate_ch(dev_priv
, DPIO_PHY0
, DPIO_CH1
, false);
2986 dport
->release_cl2_override
= false;
2990 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2992 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2993 struct drm_device
*dev
= encoder
->base
.dev
;
2994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2995 struct intel_crtc
*intel_crtc
=
2996 to_intel_crtc(encoder
->base
.crtc
);
2997 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2998 enum pipe pipe
= intel_crtc
->pipe
;
2999 unsigned int lane_mask
=
3000 intel_dp_unused_lane_mask(intel_crtc
->config
->lane_count
);
3003 intel_dp_prepare(encoder
);
3006 * Must trick the second common lane into life.
3007 * Otherwise we can't even access the PLL.
3009 if (ch
== DPIO_CH0
&& pipe
== PIPE_B
)
3010 dport
->release_cl2_override
=
3011 !chv_phy_powergate_ch(dev_priv
, DPIO_PHY0
, DPIO_CH1
, true);
3013 chv_phy_powergate_lanes(encoder
, true, lane_mask
);
3015 mutex_lock(&dev_priv
->sb_lock
);
3017 /* Assert data lane reset */
3018 chv_data_lane_soft_reset(encoder
, true);
3020 /* program left/right clock distribution */
3021 if (pipe
!= PIPE_B
) {
3022 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
3023 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
3025 val
|= CHV_BUFLEFTENA1_FORCE
;
3027 val
|= CHV_BUFRIGHTENA1_FORCE
;
3028 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
3030 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
3031 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
3033 val
|= CHV_BUFLEFTENA2_FORCE
;
3035 val
|= CHV_BUFRIGHTENA2_FORCE
;
3036 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
3039 /* program clock channel usage */
3040 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
3041 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
3043 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
3045 val
|= CHV_PCS_USEDCLKCHANNEL
;
3046 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
3048 if (intel_crtc
->config
->lane_count
> 2) {
3049 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
3050 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
3052 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
3054 val
|= CHV_PCS_USEDCLKCHANNEL
;
3055 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
3059 * This a a bit weird since generally CL
3060 * matches the pipe, but here we need to
3061 * pick the CL based on the port.
3063 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
3065 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
3067 val
|= CHV_CMN_USEDCLKCHANNEL
;
3068 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
3070 mutex_unlock(&dev_priv
->sb_lock
);
3073 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
)
3075 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3076 enum pipe pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
3079 mutex_lock(&dev_priv
->sb_lock
);
3081 /* disable left/right clock distribution */
3082 if (pipe
!= PIPE_B
) {
3083 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
3084 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
3085 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
3087 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
3088 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
3089 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
3092 mutex_unlock(&dev_priv
->sb_lock
);
3095 * Leave the power down bit cleared for at least one
3096 * lane so that chv_powergate_phy_ch() will power
3097 * on something when the channel is otherwise unused.
3098 * When the port is off and the override is removed
3099 * the lanes power down anyway, so otherwise it doesn't
3100 * really matter what the state of power down bits is
3103 chv_phy_powergate_lanes(encoder
, false, 0x0);
3107 * Native read with retry for link status and receiver capability reads for
3108 * cases where the sink may still be asleep.
3110 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3111 * supposed to retry 3 times per the spec.
3114 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
3115 void *buffer
, size_t size
)
3121 * Sometime we just get the same incorrect byte repeated
3122 * over the entire buffer. Doing just one throw away read
3123 * initially seems to "solve" it.
3125 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
3127 for (i
= 0; i
< 3; i
++) {
3128 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
3138 * Fetch AUX CH registers 0x202 - 0x207 which contain
3139 * link status information
3142 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3144 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3147 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3150 /* These are source-specific values. */
3152 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3154 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3156 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3158 if (IS_BROXTON(dev
))
3159 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3160 else if (INTEL_INFO(dev
)->gen
>= 9) {
3161 if (dev_priv
->vbt
.edp
.low_vswing
&& port
== PORT_A
)
3162 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3163 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3164 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3165 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3166 else if (IS_GEN7(dev
) && port
== PORT_A
)
3167 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3168 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
3169 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3171 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3175 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3177 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3178 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3180 if (INTEL_INFO(dev
)->gen
>= 9) {
3181 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3183 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3185 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3187 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3189 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3191 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3193 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3194 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3196 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3198 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3200 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3203 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3205 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
3206 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3208 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3210 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3212 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3215 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3217 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3218 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3220 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3223 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3225 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3228 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3230 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3232 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3234 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3237 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3242 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3244 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3246 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3247 struct intel_crtc
*intel_crtc
=
3248 to_intel_crtc(dport
->base
.base
.crtc
);
3249 unsigned long demph_reg_value
, preemph_reg_value
,
3250 uniqtranscale_reg_value
;
3251 uint8_t train_set
= intel_dp
->train_set
[0];
3252 enum dpio_channel port
= vlv_dport_to_channel(dport
);
3253 int pipe
= intel_crtc
->pipe
;
3255 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3256 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3257 preemph_reg_value
= 0x0004000;
3258 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3260 demph_reg_value
= 0x2B405555;
3261 uniqtranscale_reg_value
= 0x552AB83A;
3263 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3264 demph_reg_value
= 0x2B404040;
3265 uniqtranscale_reg_value
= 0x5548B83A;
3267 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3268 demph_reg_value
= 0x2B245555;
3269 uniqtranscale_reg_value
= 0x5560B83A;
3271 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3272 demph_reg_value
= 0x2B405555;
3273 uniqtranscale_reg_value
= 0x5598DA3A;
3279 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3280 preemph_reg_value
= 0x0002000;
3281 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3283 demph_reg_value
= 0x2B404040;
3284 uniqtranscale_reg_value
= 0x5552B83A;
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3287 demph_reg_value
= 0x2B404848;
3288 uniqtranscale_reg_value
= 0x5580B83A;
3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3291 demph_reg_value
= 0x2B404040;
3292 uniqtranscale_reg_value
= 0x55ADDA3A;
3298 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3299 preemph_reg_value
= 0x0000000;
3300 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3302 demph_reg_value
= 0x2B305555;
3303 uniqtranscale_reg_value
= 0x5570B83A;
3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3306 demph_reg_value
= 0x2B2B4040;
3307 uniqtranscale_reg_value
= 0x55ADDA3A;
3313 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3314 preemph_reg_value
= 0x0006000;
3315 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3317 demph_reg_value
= 0x1B405555;
3318 uniqtranscale_reg_value
= 0x55ADDA3A;
3328 mutex_lock(&dev_priv
->sb_lock
);
3329 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3330 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3331 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3332 uniqtranscale_reg_value
);
3333 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3334 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3335 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3336 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3337 mutex_unlock(&dev_priv
->sb_lock
);
3342 static bool chv_need_uniq_trans_scale(uint8_t train_set
)
3344 return (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) == DP_TRAIN_PRE_EMPH_LEVEL_0
&&
3345 (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3348 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3350 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3352 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3353 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3354 u32 deemph_reg_value
, margin_reg_value
, val
;
3355 uint8_t train_set
= intel_dp
->train_set
[0];
3356 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3357 enum pipe pipe
= intel_crtc
->pipe
;
3360 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3361 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3362 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3363 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3364 deemph_reg_value
= 128;
3365 margin_reg_value
= 52;
3367 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3368 deemph_reg_value
= 128;
3369 margin_reg_value
= 77;
3371 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3372 deemph_reg_value
= 128;
3373 margin_reg_value
= 102;
3375 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3376 deemph_reg_value
= 128;
3377 margin_reg_value
= 154;
3378 /* FIXME extra to set for 1200 */
3384 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3385 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3387 deemph_reg_value
= 85;
3388 margin_reg_value
= 78;
3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3391 deemph_reg_value
= 85;
3392 margin_reg_value
= 116;
3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3395 deemph_reg_value
= 85;
3396 margin_reg_value
= 154;
3402 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3403 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3404 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3405 deemph_reg_value
= 64;
3406 margin_reg_value
= 104;
3408 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3409 deemph_reg_value
= 64;
3410 margin_reg_value
= 154;
3416 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3417 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3418 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3419 deemph_reg_value
= 43;
3420 margin_reg_value
= 154;
3430 mutex_lock(&dev_priv
->sb_lock
);
3432 /* Clear calc init */
3433 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3434 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3435 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3436 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3437 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3439 if (intel_crtc
->config
->lane_count
> 2) {
3440 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3441 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3442 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3443 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3444 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3447 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3448 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3449 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3450 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3452 if (intel_crtc
->config
->lane_count
> 2) {
3453 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3454 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3455 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3456 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3459 /* Program swing deemph */
3460 for (i
= 0; i
< intel_crtc
->config
->lane_count
; i
++) {
3461 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3462 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3463 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3464 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3467 /* Program swing margin */
3468 for (i
= 0; i
< intel_crtc
->config
->lane_count
; i
++) {
3469 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3471 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3472 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3475 * Supposedly this value shouldn't matter when unique transition
3476 * scale is disabled, but in fact it does matter. Let's just
3477 * always program the same value and hope it's OK.
3479 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3480 val
|= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
;
3482 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3486 * The document said it needs to set bit 27 for ch0 and bit 26
3487 * for ch1. Might be a typo in the doc.
3488 * For now, for this unique transition scale selection, set bit
3489 * 27 for ch0 and ch1.
3491 for (i
= 0; i
< intel_crtc
->config
->lane_count
; i
++) {
3492 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3493 if (chv_need_uniq_trans_scale(train_set
))
3494 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3496 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3497 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3500 /* Start swing calculation */
3501 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3502 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3503 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3505 if (intel_crtc
->config
->lane_count
> 2) {
3506 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3507 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3508 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3511 mutex_unlock(&dev_priv
->sb_lock
);
3517 gen4_signal_levels(uint8_t train_set
)
3519 uint32_t signal_levels
= 0;
3521 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3522 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3524 signal_levels
|= DP_VOLTAGE_0_4
;
3526 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3527 signal_levels
|= DP_VOLTAGE_0_6
;
3529 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3530 signal_levels
|= DP_VOLTAGE_0_8
;
3532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3533 signal_levels
|= DP_VOLTAGE_1_2
;
3536 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3537 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3539 signal_levels
|= DP_PRE_EMPHASIS_0
;
3541 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3542 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3544 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3545 signal_levels
|= DP_PRE_EMPHASIS_6
;
3547 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3548 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3551 return signal_levels
;
3554 /* Gen6's DP voltage swing and pre-emphasis control */
3556 gen6_edp_signal_levels(uint8_t train_set
)
3558 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3559 DP_TRAIN_PRE_EMPHASIS_MASK
);
3560 switch (signal_levels
) {
3561 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3562 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3563 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3564 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3565 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3566 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3567 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3568 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3569 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3570 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3571 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3572 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3573 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3574 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3576 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3577 "0x%x\n", signal_levels
);
3578 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3582 /* Gen7's DP voltage swing and pre-emphasis control */
3584 gen7_edp_signal_levels(uint8_t train_set
)
3586 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3587 DP_TRAIN_PRE_EMPHASIS_MASK
);
3588 switch (signal_levels
) {
3589 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3590 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3591 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3592 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3593 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3594 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3596 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3597 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3598 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3599 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3601 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3602 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3603 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3604 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3607 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3608 "0x%x\n", signal_levels
);
3609 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3614 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3616 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3617 enum port port
= intel_dig_port
->port
;
3618 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3619 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3620 uint32_t signal_levels
, mask
= 0;
3621 uint8_t train_set
= intel_dp
->train_set
[0];
3624 signal_levels
= ddi_signal_levels(intel_dp
);
3626 if (IS_BROXTON(dev
))
3629 mask
= DDI_BUF_EMP_MASK
;
3630 } else if (IS_CHERRYVIEW(dev
)) {
3631 signal_levels
= chv_signal_levels(intel_dp
);
3632 } else if (IS_VALLEYVIEW(dev
)) {
3633 signal_levels
= vlv_signal_levels(intel_dp
);
3634 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3635 signal_levels
= gen7_edp_signal_levels(train_set
);
3636 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3637 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3638 signal_levels
= gen6_edp_signal_levels(train_set
);
3639 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3641 signal_levels
= gen4_signal_levels(train_set
);
3642 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3646 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3648 DRM_DEBUG_KMS("Using vswing level %d\n",
3649 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3650 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3651 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3652 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3654 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3656 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3657 POSTING_READ(intel_dp
->output_reg
);
3661 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3662 uint8_t dp_train_pat
)
3664 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3665 struct drm_i915_private
*dev_priv
=
3666 to_i915(intel_dig_port
->base
.base
.dev
);
3668 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3670 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3671 POSTING_READ(intel_dp
->output_reg
);
3674 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3676 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3677 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3679 enum port port
= intel_dig_port
->port
;
3685 val
= I915_READ(DP_TP_CTL(port
));
3686 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3687 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3688 I915_WRITE(DP_TP_CTL(port
), val
);
3691 * On PORT_A we can have only eDP in SST mode. There the only reason
3692 * we need to set idle transmission mode is to work around a HW issue
3693 * where we enable the pipe while not in idle link-training mode.
3694 * In this case there is requirement to wait for a minimum number of
3695 * idle patterns to be sent.
3700 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3702 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3706 intel_dp_link_down(struct intel_dp
*intel_dp
)
3708 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3709 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3710 enum port port
= intel_dig_port
->port
;
3711 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3713 uint32_t DP
= intel_dp
->DP
;
3715 if (WARN_ON(HAS_DDI(dev
)))
3718 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3721 DRM_DEBUG_KMS("\n");
3723 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3724 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3725 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3726 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3728 if (IS_CHERRYVIEW(dev
))
3729 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3731 DP
&= ~DP_LINK_TRAIN_MASK
;
3732 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3734 I915_WRITE(intel_dp
->output_reg
, DP
);
3735 POSTING_READ(intel_dp
->output_reg
);
3737 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3738 I915_WRITE(intel_dp
->output_reg
, DP
);
3739 POSTING_READ(intel_dp
->output_reg
);
3742 * HW workaround for IBX, we need to move the port
3743 * to transcoder A after disabling it to allow the
3744 * matching HDMI port to be enabled on transcoder A.
3746 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3748 * We get CPU/PCH FIFO underruns on the other pipe when
3749 * doing the workaround. Sweep them under the rug.
3751 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3752 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3754 /* always enable with pattern 1 (as per spec) */
3755 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3756 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3757 I915_WRITE(intel_dp
->output_reg
, DP
);
3758 POSTING_READ(intel_dp
->output_reg
);
3761 I915_WRITE(intel_dp
->output_reg
, DP
);
3762 POSTING_READ(intel_dp
->output_reg
);
3764 intel_wait_for_vblank_if_active(dev_priv
->dev
, PIPE_A
);
3765 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3766 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3769 msleep(intel_dp
->panel_power_down_delay
);
3775 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3777 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3778 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3782 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3783 sizeof(intel_dp
->dpcd
)) < 0)
3784 return false; /* aux transfer failed */
3786 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3788 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3789 return false; /* DPCD not present */
3791 /* Check if the panel supports PSR */
3792 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3793 if (is_edp(intel_dp
)) {
3794 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3796 sizeof(intel_dp
->psr_dpcd
));
3797 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3798 dev_priv
->psr
.sink_support
= true;
3799 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3802 if (INTEL_INFO(dev
)->gen
>= 9 &&
3803 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3804 uint8_t frame_sync_cap
;
3806 dev_priv
->psr
.sink_support
= true;
3807 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3808 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3809 &frame_sync_cap
, 1);
3810 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3811 /* PSR2 needs frame sync as well */
3812 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3813 DRM_DEBUG_KMS("PSR2 %s on sink",
3814 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3818 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3819 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
3820 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
3822 /* Intermediate frequency support */
3823 if (is_edp(intel_dp
) &&
3824 (intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3825 (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_EDP_DPCD_REV
, &rev
, 1) == 1) &&
3826 (rev
>= 0x03)) { /* eDp v1.4 or higher */
3827 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3830 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3831 DP_SUPPORTED_LINK_RATES
,
3833 sizeof(sink_rates
));
3835 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3836 int val
= le16_to_cpu(sink_rates
[i
]);
3841 /* Value read is in kHz while drm clock is saved in deca-kHz */
3842 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3844 intel_dp
->num_sink_rates
= i
;
3847 intel_dp_print_rates(intel_dp
);
3849 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3850 DP_DWN_STRM_PORT_PRESENT
))
3851 return true; /* native DP sink */
3853 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3854 return true; /* no per-port downstream info */
3856 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3857 intel_dp
->downstream_ports
,
3858 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3859 return false; /* downstream port status fetch failed */
3865 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3869 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3872 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3873 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3874 buf
[0], buf
[1], buf
[2]);
3876 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3877 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3878 buf
[0], buf
[1], buf
[2]);
3882 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3886 if (!i915
.enable_dp_mst
)
3889 if (!intel_dp
->can_mst
)
3892 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3895 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3896 if (buf
[0] & DP_MST_CAP
) {
3897 DRM_DEBUG_KMS("Sink is MST capable\n");
3898 intel_dp
->is_mst
= true;
3900 DRM_DEBUG_KMS("Sink is not MST capable\n");
3901 intel_dp
->is_mst
= false;
3905 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3906 return intel_dp
->is_mst
;
3909 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3911 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3912 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3913 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3919 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3920 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3925 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3926 buf
& ~DP_TEST_SINK_START
) < 0) {
3927 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3933 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3935 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3936 DP_TEST_SINK_MISC
, &buf
) < 0) {
3940 count
= buf
& DP_TEST_COUNT_MASK
;
3941 } while (--attempts
&& count
);
3943 if (attempts
== 0) {
3944 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3949 hsw_enable_ips(intel_crtc
);
3953 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3955 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3956 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3957 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3961 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3964 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3967 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3970 if (buf
& DP_TEST_SINK_START
) {
3971 ret
= intel_dp_sink_crc_stop(intel_dp
);
3976 hsw_disable_ips(intel_crtc
);
3978 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3979 buf
| DP_TEST_SINK_START
) < 0) {
3980 hsw_enable_ips(intel_crtc
);
3984 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3988 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3990 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3991 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3992 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3997 ret
= intel_dp_sink_crc_start(intel_dp
);
4002 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4004 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4005 DP_TEST_SINK_MISC
, &buf
) < 0) {
4009 count
= buf
& DP_TEST_COUNT_MASK
;
4011 } while (--attempts
&& count
== 0);
4013 if (attempts
== 0) {
4014 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4019 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
4025 intel_dp_sink_crc_stop(intel_dp
);
4030 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4032 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4033 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4034 sink_irq_vector
, 1) == 1;
4038 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4042 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4044 sink_irq_vector
, 14);
4051 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4053 uint8_t test_result
= DP_TEST_ACK
;
4057 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4059 uint8_t test_result
= DP_TEST_NAK
;
4063 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4065 uint8_t test_result
= DP_TEST_NAK
;
4066 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4067 struct drm_connector
*connector
= &intel_connector
->base
;
4069 if (intel_connector
->detect_edid
== NULL
||
4070 connector
->edid_corrupt
||
4071 intel_dp
->aux
.i2c_defer_count
> 6) {
4072 /* Check EDID read for NACKs, DEFERs and corruption
4073 * (DP CTS 1.2 Core r1.1)
4074 * 4.2.2.4 : Failed EDID read, I2C_NAK
4075 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4076 * 4.2.2.6 : EDID corruption detected
4077 * Use failsafe mode for all cases
4079 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4080 intel_dp
->aux
.i2c_defer_count
> 0)
4081 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4082 intel_dp
->aux
.i2c_nack_count
,
4083 intel_dp
->aux
.i2c_defer_count
);
4084 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
4086 struct edid
*block
= intel_connector
->detect_edid
;
4088 /* We have to write the checksum
4089 * of the last block read
4091 block
+= intel_connector
->detect_edid
->extensions
;
4093 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
4094 DP_TEST_EDID_CHECKSUM
,
4097 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4099 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4100 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
4103 /* Set test active flag here so userspace doesn't interrupt things */
4104 intel_dp
->compliance_test_active
= 1;
4109 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4111 uint8_t test_result
= DP_TEST_NAK
;
4115 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4117 uint8_t response
= DP_TEST_NAK
;
4121 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
4123 DRM_DEBUG_KMS("Could not read test request from sink\n");
4128 case DP_TEST_LINK_TRAINING
:
4129 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4130 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
4131 response
= intel_dp_autotest_link_training(intel_dp
);
4133 case DP_TEST_LINK_VIDEO_PATTERN
:
4134 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4135 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
4136 response
= intel_dp_autotest_video_pattern(intel_dp
);
4138 case DP_TEST_LINK_EDID_READ
:
4139 DRM_DEBUG_KMS("EDID test requested\n");
4140 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
4141 response
= intel_dp_autotest_edid(intel_dp
);
4143 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4144 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4145 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
4146 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4149 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
4154 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
4158 DRM_DEBUG_KMS("Could not write test response to sink\n");
4162 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4166 if (intel_dp
->is_mst
) {
4171 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4175 /* check link status - esi[10] = 0x200c */
4176 if (intel_dp
->active_mst_links
&&
4177 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4178 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4179 intel_dp_start_link_train(intel_dp
);
4180 intel_dp_stop_link_train(intel_dp
);
4183 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4184 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4187 for (retry
= 0; retry
< 3; retry
++) {
4189 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4190 DP_SINK_COUNT_ESI
+1,
4197 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4199 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4207 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4208 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4209 intel_dp
->is_mst
= false;
4210 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4211 /* send a hotplug event */
4212 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4219 * According to DP spec
4222 * 2. Configure link according to Receiver Capabilities
4223 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4224 * 4. Check link status on receipt of hot-plug interrupt
4227 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4229 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4230 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4232 u8 link_status
[DP_LINK_STATUS_SIZE
];
4234 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4237 * Clearing compliance test variables to allow capturing
4238 * of values for next automated test request.
4240 intel_dp
->compliance_test_active
= 0;
4241 intel_dp
->compliance_test_type
= 0;
4242 intel_dp
->compliance_test_data
= 0;
4244 if (!intel_encoder
->base
.crtc
)
4247 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4250 /* Try to read receiver status if the link appears to be up */
4251 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4255 /* Now read the DPCD to see if it's actually running */
4256 if (!intel_dp_get_dpcd(intel_dp
)) {
4260 /* Try to read the source of the interrupt */
4261 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4262 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4263 /* Clear interrupt source */
4264 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4265 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4268 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4269 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4270 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4271 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4274 /* if link training is requested we should perform it always */
4275 if ((intel_dp
->compliance_test_type
== DP_TEST_LINK_TRAINING
) ||
4276 (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
))) {
4277 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4278 intel_encoder
->base
.name
);
4279 intel_dp_start_link_train(intel_dp
);
4280 intel_dp_stop_link_train(intel_dp
);
4284 /* XXX this is probably wrong for multiple downstream ports */
4285 static enum drm_connector_status
4286 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4288 uint8_t *dpcd
= intel_dp
->dpcd
;
4291 if (!intel_dp_get_dpcd(intel_dp
))
4292 return connector_status_disconnected
;
4294 /* if there's no downstream port, we're done */
4295 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4296 return connector_status_connected
;
4298 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4299 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4300 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4303 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4305 return connector_status_unknown
;
4307 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4308 : connector_status_disconnected
;
4311 /* If no HPD, poke DDC gently */
4312 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4313 return connector_status_connected
;
4315 /* Well we tried, say unknown for unreliable port types */
4316 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4317 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4318 if (type
== DP_DS_PORT_TYPE_VGA
||
4319 type
== DP_DS_PORT_TYPE_NON_EDID
)
4320 return connector_status_unknown
;
4322 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4323 DP_DWN_STRM_PORT_TYPE_MASK
;
4324 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4325 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4326 return connector_status_unknown
;
4329 /* Anything else is out of spec, warn and ignore */
4330 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4331 return connector_status_disconnected
;
4334 static enum drm_connector_status
4335 edp_detect(struct intel_dp
*intel_dp
)
4337 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4338 enum drm_connector_status status
;
4340 status
= intel_panel_detect(dev
);
4341 if (status
== connector_status_unknown
)
4342 status
= connector_status_connected
;
4347 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4348 struct intel_digital_port
*port
)
4352 switch (port
->port
) {
4356 bit
= SDE_PORTB_HOTPLUG
;
4359 bit
= SDE_PORTC_HOTPLUG
;
4362 bit
= SDE_PORTD_HOTPLUG
;
4365 MISSING_CASE(port
->port
);
4369 return I915_READ(SDEISR
) & bit
;
4372 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4373 struct intel_digital_port
*port
)
4377 switch (port
->port
) {
4381 bit
= SDE_PORTB_HOTPLUG_CPT
;
4384 bit
= SDE_PORTC_HOTPLUG_CPT
;
4387 bit
= SDE_PORTD_HOTPLUG_CPT
;
4390 bit
= SDE_PORTE_HOTPLUG_SPT
;
4393 MISSING_CASE(port
->port
);
4397 return I915_READ(SDEISR
) & bit
;
4400 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4401 struct intel_digital_port
*port
)
4405 switch (port
->port
) {
4407 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4410 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4413 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4416 MISSING_CASE(port
->port
);
4420 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4423 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4424 struct intel_digital_port
*port
)
4428 switch (port
->port
) {
4430 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4433 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4436 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4439 MISSING_CASE(port
->port
);
4443 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4446 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4447 struct intel_digital_port
*intel_dig_port
)
4449 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4453 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4456 bit
= BXT_DE_PORT_HP_DDIA
;
4459 bit
= BXT_DE_PORT_HP_DDIB
;
4462 bit
= BXT_DE_PORT_HP_DDIC
;
4469 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4473 * intel_digital_port_connected - is the specified port connected?
4474 * @dev_priv: i915 private structure
4475 * @port: the port to test
4477 * Return %true if @port is connected, %false otherwise.
4479 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4480 struct intel_digital_port
*port
)
4482 if (HAS_PCH_IBX(dev_priv
))
4483 return ibx_digital_port_connected(dev_priv
, port
);
4484 else if (HAS_PCH_SPLIT(dev_priv
))
4485 return cpt_digital_port_connected(dev_priv
, port
);
4486 else if (IS_BROXTON(dev_priv
))
4487 return bxt_digital_port_connected(dev_priv
, port
);
4488 else if (IS_GM45(dev_priv
))
4489 return gm45_digital_port_connected(dev_priv
, port
);
4491 return g4x_digital_port_connected(dev_priv
, port
);
4494 static struct edid
*
4495 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4497 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4499 /* use cached edid if we have one */
4500 if (intel_connector
->edid
) {
4502 if (IS_ERR(intel_connector
->edid
))
4505 return drm_edid_duplicate(intel_connector
->edid
);
4507 return drm_get_edid(&intel_connector
->base
,
4508 &intel_dp
->aux
.ddc
);
4512 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4514 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4517 intel_dp_unset_edid(intel_dp
);
4518 edid
= intel_dp_get_edid(intel_dp
);
4519 intel_connector
->detect_edid
= edid
;
4521 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4522 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4524 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4528 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4530 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4532 kfree(intel_connector
->detect_edid
);
4533 intel_connector
->detect_edid
= NULL
;
4535 intel_dp
->has_audio
= false;
4539 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4541 struct drm_connector
*connector
= &intel_connector
->base
;
4542 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4543 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4544 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4545 struct drm_device
*dev
= connector
->dev
;
4546 enum drm_connector_status status
;
4547 enum intel_display_power_domain power_domain
;
4551 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4552 intel_display_power_get(to_i915(dev
), power_domain
);
4554 /* Can't disconnect eDP, but you can close the lid... */
4555 if (is_edp(intel_dp
))
4556 status
= edp_detect(intel_dp
);
4557 else if (intel_digital_port_connected(to_i915(dev
),
4558 dp_to_dig_port(intel_dp
)))
4559 status
= intel_dp_detect_dpcd(intel_dp
);
4561 status
= connector_status_disconnected
;
4563 if (status
!= connector_status_connected
) {
4564 intel_dp
->compliance_test_active
= 0;
4565 intel_dp
->compliance_test_type
= 0;
4566 intel_dp
->compliance_test_data
= 0;
4571 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4572 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4574 intel_dp_probe_oui(intel_dp
);
4576 ret
= intel_dp_probe_mst(intel_dp
);
4579 * If we are in MST mode then this connector
4580 * won't appear connected or have anything
4583 status
= connector_status_disconnected
;
4588 * Clearing NACK and defer counts to get their exact values
4589 * while reading EDID which are required by Compliance tests
4590 * 4.2.2.4 and 4.2.2.5
4592 intel_dp
->aux
.i2c_nack_count
= 0;
4593 intel_dp
->aux
.i2c_defer_count
= 0;
4595 intel_dp_set_edid(intel_dp
);
4597 status
= connector_status_connected
;
4599 /* Try to read the source of the interrupt */
4600 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4601 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4602 /* Clear interrupt source */
4603 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4604 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4607 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4608 intel_dp_handle_test_request(intel_dp
);
4609 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4610 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4614 if (status
!= connector_status_connected
)
4615 intel_dp_unset_edid(intel_dp
);
4616 intel_display_power_put(to_i915(dev
), power_domain
);
4620 static enum drm_connector_status
4621 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4623 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4624 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4625 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4626 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4628 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4629 connector
->base
.id
, connector
->name
);
4631 if (intel_dp
->is_mst
) {
4632 /* MST devices are disconnected from a monitor POV */
4633 intel_dp_unset_edid(intel_dp
);
4634 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4635 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4636 return connector_status_disconnected
;
4639 intel_dp_long_pulse(intel_dp
->attached_connector
);
4641 if (intel_connector
->detect_edid
)
4642 return connector_status_connected
;
4644 return connector_status_disconnected
;
4648 intel_dp_force(struct drm_connector
*connector
)
4650 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4651 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4652 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4653 enum intel_display_power_domain power_domain
;
4655 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4656 connector
->base
.id
, connector
->name
);
4657 intel_dp_unset_edid(intel_dp
);
4659 if (connector
->status
!= connector_status_connected
)
4662 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4663 intel_display_power_get(dev_priv
, power_domain
);
4665 intel_dp_set_edid(intel_dp
);
4667 intel_display_power_put(dev_priv
, power_domain
);
4669 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4670 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4673 static int intel_dp_get_modes(struct drm_connector
*connector
)
4675 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4678 edid
= intel_connector
->detect_edid
;
4680 int ret
= intel_connector_update_modes(connector
, edid
);
4685 /* if eDP has no EDID, fall back to fixed mode */
4686 if (is_edp(intel_attached_dp(connector
)) &&
4687 intel_connector
->panel
.fixed_mode
) {
4688 struct drm_display_mode
*mode
;
4690 mode
= drm_mode_duplicate(connector
->dev
,
4691 intel_connector
->panel
.fixed_mode
);
4693 drm_mode_probed_add(connector
, mode
);
4702 intel_dp_detect_audio(struct drm_connector
*connector
)
4704 bool has_audio
= false;
4707 edid
= to_intel_connector(connector
)->detect_edid
;
4709 has_audio
= drm_detect_monitor_audio(edid
);
4715 intel_dp_set_property(struct drm_connector
*connector
,
4716 struct drm_property
*property
,
4719 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4720 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4721 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4722 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4725 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4729 if (property
== dev_priv
->force_audio_property
) {
4733 if (i
== intel_dp
->force_audio
)
4736 intel_dp
->force_audio
= i
;
4738 if (i
== HDMI_AUDIO_AUTO
)
4739 has_audio
= intel_dp_detect_audio(connector
);
4741 has_audio
= (i
== HDMI_AUDIO_ON
);
4743 if (has_audio
== intel_dp
->has_audio
)
4746 intel_dp
->has_audio
= has_audio
;
4750 if (property
== dev_priv
->broadcast_rgb_property
) {
4751 bool old_auto
= intel_dp
->color_range_auto
;
4752 bool old_range
= intel_dp
->limited_color_range
;
4755 case INTEL_BROADCAST_RGB_AUTO
:
4756 intel_dp
->color_range_auto
= true;
4758 case INTEL_BROADCAST_RGB_FULL
:
4759 intel_dp
->color_range_auto
= false;
4760 intel_dp
->limited_color_range
= false;
4762 case INTEL_BROADCAST_RGB_LIMITED
:
4763 intel_dp
->color_range_auto
= false;
4764 intel_dp
->limited_color_range
= true;
4770 if (old_auto
== intel_dp
->color_range_auto
&&
4771 old_range
== intel_dp
->limited_color_range
)
4777 if (is_edp(intel_dp
) &&
4778 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4779 if (val
== DRM_MODE_SCALE_NONE
) {
4780 DRM_DEBUG_KMS("no scaling not supported\n");
4784 if (intel_connector
->panel
.fitting_mode
== val
) {
4785 /* the eDP scaling property is not changed */
4788 intel_connector
->panel
.fitting_mode
= val
;
4796 if (intel_encoder
->base
.crtc
)
4797 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4803 intel_dp_connector_destroy(struct drm_connector
*connector
)
4805 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4807 kfree(intel_connector
->detect_edid
);
4809 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4810 kfree(intel_connector
->edid
);
4812 /* Can't call is_edp() since the encoder may have been destroyed
4814 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4815 intel_panel_fini(&intel_connector
->panel
);
4817 drm_connector_cleanup(connector
);
4821 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4823 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4824 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4826 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4827 if (is_edp(intel_dp
)) {
4828 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4830 * vdd might still be enabled do to the delayed vdd off.
4831 * Make sure vdd is actually turned off here.
4834 edp_panel_vdd_off_sync(intel_dp
);
4835 pps_unlock(intel_dp
);
4837 if (intel_dp
->edp_notifier
.notifier_call
) {
4838 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4839 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4842 drm_encoder_cleanup(encoder
);
4843 kfree(intel_dig_port
);
4846 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4848 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4850 if (!is_edp(intel_dp
))
4854 * vdd might still be enabled do to the delayed vdd off.
4855 * Make sure vdd is actually turned off here.
4857 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4859 edp_panel_vdd_off_sync(intel_dp
);
4860 pps_unlock(intel_dp
);
4863 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4865 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4866 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4868 enum intel_display_power_domain power_domain
;
4870 lockdep_assert_held(&dev_priv
->pps_mutex
);
4872 if (!edp_have_panel_vdd(intel_dp
))
4876 * The VDD bit needs a power domain reference, so if the bit is
4877 * already enabled when we boot or resume, grab this reference and
4878 * schedule a vdd off, so we don't hold on to the reference
4881 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4882 power_domain
= intel_display_port_aux_power_domain(&intel_dig_port
->base
);
4883 intel_display_power_get(dev_priv
, power_domain
);
4885 edp_panel_vdd_schedule_off(intel_dp
);
4888 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4890 struct intel_dp
*intel_dp
;
4892 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4895 intel_dp
= enc_to_intel_dp(encoder
);
4900 * Read out the current power sequencer assignment,
4901 * in case the BIOS did something with it.
4903 if (IS_VALLEYVIEW(encoder
->dev
) || IS_CHERRYVIEW(encoder
->dev
))
4904 vlv_initial_power_sequencer_setup(intel_dp
);
4906 intel_edp_panel_vdd_sanitize(intel_dp
);
4908 pps_unlock(intel_dp
);
4911 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4912 .dpms
= drm_atomic_helper_connector_dpms
,
4913 .detect
= intel_dp_detect
,
4914 .force
= intel_dp_force
,
4915 .fill_modes
= drm_helper_probe_single_connector_modes
,
4916 .set_property
= intel_dp_set_property
,
4917 .atomic_get_property
= intel_connector_atomic_get_property
,
4918 .destroy
= intel_dp_connector_destroy
,
4919 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4920 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4923 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4924 .get_modes
= intel_dp_get_modes
,
4925 .mode_valid
= intel_dp_mode_valid
,
4926 .best_encoder
= intel_best_encoder
,
4929 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4930 .reset
= intel_dp_encoder_reset
,
4931 .destroy
= intel_dp_encoder_destroy
,
4935 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4937 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4938 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4939 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4941 enum intel_display_power_domain power_domain
;
4942 enum irqreturn ret
= IRQ_NONE
;
4944 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
4945 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
4946 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4948 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4950 * vdd off can generate a long pulse on eDP which
4951 * would require vdd on to handle it, and thus we
4952 * would end up in an endless cycle of
4953 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4955 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4956 port_name(intel_dig_port
->port
));
4960 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4961 port_name(intel_dig_port
->port
),
4962 long_hpd
? "long" : "short");
4964 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4965 intel_display_power_get(dev_priv
, power_domain
);
4968 /* indicate that we need to restart link training */
4969 intel_dp
->train_set_valid
= false;
4971 if (!intel_digital_port_connected(dev_priv
, intel_dig_port
))
4974 if (!intel_dp_get_dpcd(intel_dp
)) {
4978 intel_dp_probe_oui(intel_dp
);
4980 if (!intel_dp_probe_mst(intel_dp
)) {
4981 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4982 intel_dp_check_link_status(intel_dp
);
4983 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4987 if (intel_dp
->is_mst
) {
4988 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4992 if (!intel_dp
->is_mst
) {
4993 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4994 intel_dp_check_link_status(intel_dp
);
4995 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
5003 /* if we were in MST mode, and device is not there get out of MST mode */
5004 if (intel_dp
->is_mst
) {
5005 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5006 intel_dp
->is_mst
= false;
5007 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
5010 intel_display_power_put(dev_priv
, power_domain
);
5015 /* check the VBT to see whether the eDP is on another port */
5016 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
5018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5021 * eDP not supported on g4x. so bail out early just
5022 * for a bit extra safety in case the VBT is bonkers.
5024 if (INTEL_INFO(dev
)->gen
< 5)
5030 return intel_bios_is_port_edp(dev_priv
, port
);
5034 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5036 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5038 intel_attach_force_audio_property(connector
);
5039 intel_attach_broadcast_rgb_property(connector
);
5040 intel_dp
->color_range_auto
= true;
5042 if (is_edp(intel_dp
)) {
5043 drm_mode_create_scaling_mode_property(connector
->dev
);
5044 drm_object_attach_property(
5046 connector
->dev
->mode_config
.scaling_mode_property
,
5047 DRM_MODE_SCALE_ASPECT
);
5048 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
5052 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5054 intel_dp
->panel_power_off_time
= ktime_get_boottime();
5055 intel_dp
->last_power_on
= jiffies
;
5056 intel_dp
->last_backlight_off
= jiffies
;
5060 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5061 struct intel_dp
*intel_dp
)
5063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5064 struct edp_power_seq cur
, vbt
, spec
,
5065 *final
= &intel_dp
->pps_delays
;
5066 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5067 i915_reg_t pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
5069 lockdep_assert_held(&dev_priv
->pps_mutex
);
5071 /* already initialized? */
5072 if (final
->t11_t12
!= 0)
5075 if (IS_BROXTON(dev
)) {
5077 * TODO: BXT has 2 sets of PPS registers.
5078 * Correct Register for Broxton need to be identified
5079 * using VBT. hardcoding for now
5081 pp_ctrl_reg
= BXT_PP_CONTROL(0);
5082 pp_on_reg
= BXT_PP_ON_DELAYS(0);
5083 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
5084 } else if (HAS_PCH_SPLIT(dev
)) {
5085 pp_ctrl_reg
= PCH_PP_CONTROL
;
5086 pp_on_reg
= PCH_PP_ON_DELAYS
;
5087 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5088 pp_div_reg
= PCH_PP_DIVISOR
;
5090 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5092 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
5093 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5094 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5095 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5098 /* Workaround: Need to write PP_CONTROL with the unlock key as
5099 * the very first thing. */
5100 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5102 pp_on
= I915_READ(pp_on_reg
);
5103 pp_off
= I915_READ(pp_off_reg
);
5104 if (!IS_BROXTON(dev
)) {
5105 I915_WRITE(pp_ctrl_reg
, pp_ctl
);
5106 pp_div
= I915_READ(pp_div_reg
);
5109 /* Pull timing values out of registers */
5110 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5111 PANEL_POWER_UP_DELAY_SHIFT
;
5113 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5114 PANEL_LIGHT_ON_DELAY_SHIFT
;
5116 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5117 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5119 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5120 PANEL_POWER_DOWN_DELAY_SHIFT
;
5122 if (IS_BROXTON(dev
)) {
5123 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5124 BXT_POWER_CYCLE_DELAY_SHIFT
;
5126 cur
.t11_t12
= (tmp
- 1) * 1000;
5130 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5131 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5134 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5135 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
5137 vbt
= dev_priv
->vbt
.edp
.pps
;
5139 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5140 * our hw here, which are all in 100usec. */
5141 spec
.t1_t3
= 210 * 10;
5142 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5143 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5144 spec
.t10
= 500 * 10;
5145 /* This one is special and actually in units of 100ms, but zero
5146 * based in the hw (so we need to add 100 ms). But the sw vbt
5147 * table multiplies it with 1000 to make it in units of 100usec,
5149 spec
.t11_t12
= (510 + 100) * 10;
5151 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5152 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
5154 /* Use the max of the register settings and vbt. If both are
5155 * unset, fall back to the spec limits. */
5156 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5158 max(cur.field, vbt.field))
5159 assign_final(t1_t3
);
5163 assign_final(t11_t12
);
5166 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5167 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5168 intel_dp
->backlight_on_delay
= get_delay(t8
);
5169 intel_dp
->backlight_off_delay
= get_delay(t9
);
5170 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5171 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5174 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5175 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5176 intel_dp
->panel_power_cycle_delay
);
5178 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5179 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5183 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5184 struct intel_dp
*intel_dp
)
5186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5187 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5188 int div
= dev_priv
->rawclk_freq
/ 1000;
5189 i915_reg_t pp_on_reg
, pp_off_reg
, pp_div_reg
, pp_ctrl_reg
;
5190 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5191 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5193 lockdep_assert_held(&dev_priv
->pps_mutex
);
5195 if (IS_BROXTON(dev
)) {
5197 * TODO: BXT has 2 sets of PPS registers.
5198 * Correct Register for Broxton need to be identified
5199 * using VBT. hardcoding for now
5201 pp_ctrl_reg
= BXT_PP_CONTROL(0);
5202 pp_on_reg
= BXT_PP_ON_DELAYS(0);
5203 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
5205 } else if (HAS_PCH_SPLIT(dev
)) {
5206 pp_on_reg
= PCH_PP_ON_DELAYS
;
5207 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5208 pp_div_reg
= PCH_PP_DIVISOR
;
5210 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5212 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5213 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5214 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5218 * And finally store the new values in the power sequencer. The
5219 * backlight delays are set to 1 because we do manual waits on them. For
5220 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5221 * we'll end up waiting for the backlight off delay twice: once when we
5222 * do the manual sleep, and once when we disable the panel and wait for
5223 * the PP_STATUS bit to become zero.
5225 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5226 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
5227 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5228 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5229 /* Compute the divisor for the pp clock, simply match the Bspec
5231 if (IS_BROXTON(dev
)) {
5232 pp_div
= I915_READ(pp_ctrl_reg
);
5233 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5234 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5235 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5237 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5238 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5239 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5242 /* Haswell doesn't have any port selection bits for the panel
5243 * power sequencer any more. */
5244 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5245 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5246 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5248 port_sel
= PANEL_PORT_SELECT_DPA
;
5250 port_sel
= PANEL_PORT_SELECT_DPD
;
5255 I915_WRITE(pp_on_reg
, pp_on
);
5256 I915_WRITE(pp_off_reg
, pp_off
);
5257 if (IS_BROXTON(dev
))
5258 I915_WRITE(pp_ctrl_reg
, pp_div
);
5260 I915_WRITE(pp_div_reg
, pp_div
);
5262 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5263 I915_READ(pp_on_reg
),
5264 I915_READ(pp_off_reg
),
5266 (I915_READ(pp_ctrl_reg
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5267 I915_READ(pp_div_reg
));
5271 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5273 * @refresh_rate: RR to be programmed
5275 * This function gets called when refresh rate (RR) has to be changed from
5276 * one frequency to another. Switches can be between high and low RR
5277 * supported by the panel or to any other RR based on media playback (in
5278 * this case, RR value needs to be passed from user space).
5280 * The caller of this function needs to take a lock on dev_priv->drrs.
5282 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5285 struct intel_encoder
*encoder
;
5286 struct intel_digital_port
*dig_port
= NULL
;
5287 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5288 struct intel_crtc_state
*config
= NULL
;
5289 struct intel_crtc
*intel_crtc
= NULL
;
5290 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5292 if (refresh_rate
<= 0) {
5293 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5297 if (intel_dp
== NULL
) {
5298 DRM_DEBUG_KMS("DRRS not supported.\n");
5303 * FIXME: This needs proper synchronization with psr state for some
5304 * platforms that cannot have PSR and DRRS enabled at the same time.
5307 dig_port
= dp_to_dig_port(intel_dp
);
5308 encoder
= &dig_port
->base
;
5309 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5312 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5316 config
= intel_crtc
->config
;
5318 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5319 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5323 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5325 index
= DRRS_LOW_RR
;
5327 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5329 "DRRS requested for previously set RR...ignoring\n");
5333 if (!intel_crtc
->active
) {
5334 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5338 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5341 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5344 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5348 DRM_ERROR("Unsupported refreshrate type\n");
5350 } else if (INTEL_INFO(dev
)->gen
> 6) {
5351 i915_reg_t reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5354 val
= I915_READ(reg
);
5355 if (index
> DRRS_HIGH_RR
) {
5356 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5357 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5359 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5361 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5362 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5364 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5366 I915_WRITE(reg
, val
);
5369 dev_priv
->drrs
.refresh_rate_type
= index
;
5371 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5375 * intel_edp_drrs_enable - init drrs struct if supported
5376 * @intel_dp: DP struct
5378 * Initializes frontbuffer_bits and drrs.dp
5380 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5382 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5384 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5385 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5386 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5388 if (!intel_crtc
->config
->has_drrs
) {
5389 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5393 mutex_lock(&dev_priv
->drrs
.mutex
);
5394 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5395 DRM_ERROR("DRRS already enabled\n");
5399 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5401 dev_priv
->drrs
.dp
= intel_dp
;
5404 mutex_unlock(&dev_priv
->drrs
.mutex
);
5408 * intel_edp_drrs_disable - Disable DRRS
5409 * @intel_dp: DP struct
5412 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5414 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5416 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5417 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5418 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5420 if (!intel_crtc
->config
->has_drrs
)
5423 mutex_lock(&dev_priv
->drrs
.mutex
);
5424 if (!dev_priv
->drrs
.dp
) {
5425 mutex_unlock(&dev_priv
->drrs
.mutex
);
5429 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5430 intel_dp_set_drrs_state(dev_priv
->dev
,
5431 intel_dp
->attached_connector
->panel
.
5432 fixed_mode
->vrefresh
);
5434 dev_priv
->drrs
.dp
= NULL
;
5435 mutex_unlock(&dev_priv
->drrs
.mutex
);
5437 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5440 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5442 struct drm_i915_private
*dev_priv
=
5443 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5444 struct intel_dp
*intel_dp
;
5446 mutex_lock(&dev_priv
->drrs
.mutex
);
5448 intel_dp
= dev_priv
->drrs
.dp
;
5454 * The delayed work can race with an invalidate hence we need to
5458 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5461 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5462 intel_dp_set_drrs_state(dev_priv
->dev
,
5463 intel_dp
->attached_connector
->panel
.
5464 downclock_mode
->vrefresh
);
5467 mutex_unlock(&dev_priv
->drrs
.mutex
);
5471 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5473 * @frontbuffer_bits: frontbuffer plane tracking bits
5475 * This function gets called everytime rendering on the given planes start.
5476 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5478 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5480 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5481 unsigned frontbuffer_bits
)
5483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5484 struct drm_crtc
*crtc
;
5487 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5490 cancel_delayed_work(&dev_priv
->drrs
.work
);
5492 mutex_lock(&dev_priv
->drrs
.mutex
);
5493 if (!dev_priv
->drrs
.dp
) {
5494 mutex_unlock(&dev_priv
->drrs
.mutex
);
5498 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5499 pipe
= to_intel_crtc(crtc
)->pipe
;
5501 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5502 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5504 /* invalidate means busy screen hence upclock */
5505 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5506 intel_dp_set_drrs_state(dev_priv
->dev
,
5507 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5508 fixed_mode
->vrefresh
);
5510 mutex_unlock(&dev_priv
->drrs
.mutex
);
5514 * intel_edp_drrs_flush - Restart Idleness DRRS
5516 * @frontbuffer_bits: frontbuffer plane tracking bits
5518 * This function gets called every time rendering on the given planes has
5519 * completed or flip on a crtc is completed. So DRRS should be upclocked
5520 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5521 * if no other planes are dirty.
5523 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5525 void intel_edp_drrs_flush(struct drm_device
*dev
,
5526 unsigned frontbuffer_bits
)
5528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5529 struct drm_crtc
*crtc
;
5532 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5535 cancel_delayed_work(&dev_priv
->drrs
.work
);
5537 mutex_lock(&dev_priv
->drrs
.mutex
);
5538 if (!dev_priv
->drrs
.dp
) {
5539 mutex_unlock(&dev_priv
->drrs
.mutex
);
5543 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5544 pipe
= to_intel_crtc(crtc
)->pipe
;
5546 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5547 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5549 /* flush means busy screen hence upclock */
5550 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5551 intel_dp_set_drrs_state(dev_priv
->dev
,
5552 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5553 fixed_mode
->vrefresh
);
5556 * flush also means no more activity hence schedule downclock, if all
5557 * other fbs are quiescent too
5559 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5560 schedule_delayed_work(&dev_priv
->drrs
.work
,
5561 msecs_to_jiffies(1000));
5562 mutex_unlock(&dev_priv
->drrs
.mutex
);
5566 * DOC: Display Refresh Rate Switching (DRRS)
5568 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5569 * which enables swtching between low and high refresh rates,
5570 * dynamically, based on the usage scenario. This feature is applicable
5571 * for internal panels.
5573 * Indication that the panel supports DRRS is given by the panel EDID, which
5574 * would list multiple refresh rates for one resolution.
5576 * DRRS is of 2 types - static and seamless.
5577 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5578 * (may appear as a blink on screen) and is used in dock-undock scenario.
5579 * Seamless DRRS involves changing RR without any visual effect to the user
5580 * and can be used during normal system usage. This is done by programming
5581 * certain registers.
5583 * Support for static/seamless DRRS may be indicated in the VBT based on
5584 * inputs from the panel spec.
5586 * DRRS saves power by switching to low RR based on usage scenarios.
5589 * The implementation is based on frontbuffer tracking implementation.
5590 * When there is a disturbance on the screen triggered by user activity or a
5591 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5592 * When there is no movement on screen, after a timeout of 1 second, a switch
5593 * to low RR is made.
5594 * For integration with frontbuffer tracking code,
5595 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5597 * DRRS can be further extended to support other internal panels and also
5598 * the scenario of video playback wherein RR is set based on the rate
5599 * requested by userspace.
5603 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5604 * @intel_connector: eDP connector
5605 * @fixed_mode: preferred mode of panel
5607 * This function is called only once at driver load to initialize basic
5611 * Downclock mode if panel supports it, else return NULL.
5612 * DRRS support is determined by the presence of downclock mode (apart
5613 * from VBT setting).
5615 static struct drm_display_mode
*
5616 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5617 struct drm_display_mode
*fixed_mode
)
5619 struct drm_connector
*connector
= &intel_connector
->base
;
5620 struct drm_device
*dev
= connector
->dev
;
5621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5622 struct drm_display_mode
*downclock_mode
= NULL
;
5624 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5625 mutex_init(&dev_priv
->drrs
.mutex
);
5627 if (INTEL_INFO(dev
)->gen
<= 6) {
5628 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5632 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5633 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5637 downclock_mode
= intel_find_panel_downclock
5638 (dev
, fixed_mode
, connector
);
5640 if (!downclock_mode
) {
5641 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5645 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5647 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5648 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5649 return downclock_mode
;
5652 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5653 struct intel_connector
*intel_connector
)
5655 struct drm_connector
*connector
= &intel_connector
->base
;
5656 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5657 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5658 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5660 struct drm_display_mode
*fixed_mode
= NULL
;
5661 struct drm_display_mode
*downclock_mode
= NULL
;
5663 struct drm_display_mode
*scan
;
5665 enum pipe pipe
= INVALID_PIPE
;
5667 if (!is_edp(intel_dp
))
5671 intel_edp_panel_vdd_sanitize(intel_dp
);
5672 pps_unlock(intel_dp
);
5674 /* Cache DPCD and EDID for edp. */
5675 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5678 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5679 dev_priv
->no_aux_handshake
=
5680 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5681 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5683 /* if this fails, presume the device is a ghost */
5684 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5688 /* We now know it's not a ghost, init power sequence regs. */
5690 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5691 pps_unlock(intel_dp
);
5693 mutex_lock(&dev
->mode_config
.mutex
);
5694 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5696 if (drm_add_edid_modes(connector
, edid
)) {
5697 drm_mode_connector_update_edid_property(connector
,
5699 drm_edid_to_eld(connector
, edid
);
5702 edid
= ERR_PTR(-EINVAL
);
5705 edid
= ERR_PTR(-ENOENT
);
5707 intel_connector
->edid
= edid
;
5709 /* prefer fixed mode from EDID if available */
5710 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5711 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5712 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5713 downclock_mode
= intel_dp_drrs_init(
5714 intel_connector
, fixed_mode
);
5719 /* fallback to VBT if available for eDP */
5720 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5721 fixed_mode
= drm_mode_duplicate(dev
,
5722 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5724 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5726 mutex_unlock(&dev
->mode_config
.mutex
);
5728 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5729 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5730 register_reboot_notifier(&intel_dp
->edp_notifier
);
5733 * Figure out the current pipe for the initial backlight setup.
5734 * If the current pipe isn't valid, try the PPS pipe, and if that
5735 * fails just assume pipe A.
5737 if (IS_CHERRYVIEW(dev
))
5738 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5740 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5742 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5743 pipe
= intel_dp
->pps_pipe
;
5745 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5748 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5752 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5753 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5754 intel_panel_setup_backlight(connector
, pipe
);
5760 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5761 struct intel_connector
*intel_connector
)
5763 struct drm_connector
*connector
= &intel_connector
->base
;
5764 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5765 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5766 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5768 enum port port
= intel_dig_port
->port
;
5771 if (WARN(intel_dig_port
->max_lanes
< 1,
5772 "Not enough lanes (%d) for DP on port %c\n",
5773 intel_dig_port
->max_lanes
, port_name(port
)))
5776 intel_dp
->pps_pipe
= INVALID_PIPE
;
5778 /* intel_dp vfuncs */
5779 if (INTEL_INFO(dev
)->gen
>= 9)
5780 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5781 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5782 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5783 else if (HAS_PCH_SPLIT(dev
))
5784 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5786 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5788 if (INTEL_INFO(dev
)->gen
>= 9)
5789 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5791 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5794 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5796 /* Preserve the current hw state. */
5797 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5798 intel_dp
->attached_connector
= intel_connector
;
5800 if (intel_dp_is_edp(dev
, port
))
5801 type
= DRM_MODE_CONNECTOR_eDP
;
5803 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5806 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5807 * for DP the encoder type can be set by the caller to
5808 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5810 if (type
== DRM_MODE_CONNECTOR_eDP
)
5811 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5813 /* eDP only on port B and/or C on vlv/chv */
5814 if (WARN_ON((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
5815 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
5818 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5819 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5822 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5823 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5825 connector
->interlace_allowed
= true;
5826 connector
->doublescan_allowed
= 0;
5828 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5829 edp_panel_vdd_work
);
5831 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5832 drm_connector_register(connector
);
5835 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5837 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5838 intel_connector
->unregister
= intel_dp_connector_unregister
;
5840 /* Set up the hotplug pin. */
5843 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5846 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5847 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
5848 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5851 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5854 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5857 intel_encoder
->hpd_pin
= HPD_PORT_E
;
5863 if (is_edp(intel_dp
)) {
5865 intel_dp_init_panel_power_timestamps(intel_dp
);
5866 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5867 vlv_initial_power_sequencer_setup(intel_dp
);
5869 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5870 pps_unlock(intel_dp
);
5873 ret
= intel_dp_aux_init(intel_dp
, intel_connector
);
5877 /* init MST on ports that can support it */
5878 if (HAS_DP_MST(dev
) &&
5879 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5880 intel_dp_mst_encoder_init(intel_dig_port
,
5881 intel_connector
->base
.base
.id
);
5883 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5884 intel_dp_aux_fini(intel_dp
);
5885 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5889 intel_dp_add_properties(intel_dp
, connector
);
5891 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5892 * 0xd. Failure to do so will result in spurious interrupts being
5893 * generated on the port when a cable is not attached.
5895 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5896 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5897 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5900 i915_debugfs_connector_add(connector
);
5905 if (is_edp(intel_dp
)) {
5906 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5908 * vdd might still be enabled do to the delayed vdd off.
5909 * Make sure vdd is actually turned off here.
5912 edp_panel_vdd_off_sync(intel_dp
);
5913 pps_unlock(intel_dp
);
5915 drm_connector_unregister(connector
);
5916 drm_connector_cleanup(connector
);
5922 intel_dp_init(struct drm_device
*dev
,
5923 i915_reg_t output_reg
, enum port port
)
5925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5926 struct intel_digital_port
*intel_dig_port
;
5927 struct intel_encoder
*intel_encoder
;
5928 struct drm_encoder
*encoder
;
5929 struct intel_connector
*intel_connector
;
5931 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5932 if (!intel_dig_port
)
5935 intel_connector
= intel_connector_alloc();
5936 if (!intel_connector
)
5937 goto err_connector_alloc
;
5939 intel_encoder
= &intel_dig_port
->base
;
5940 encoder
= &intel_encoder
->base
;
5942 if (drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5943 DRM_MODE_ENCODER_TMDS
, NULL
))
5944 goto err_encoder_init
;
5946 intel_encoder
->compute_config
= intel_dp_compute_config
;
5947 intel_encoder
->disable
= intel_disable_dp
;
5948 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5949 intel_encoder
->get_config
= intel_dp_get_config
;
5950 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5951 if (IS_CHERRYVIEW(dev
)) {
5952 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5953 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5954 intel_encoder
->enable
= vlv_enable_dp
;
5955 intel_encoder
->post_disable
= chv_post_disable_dp
;
5956 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
5957 } else if (IS_VALLEYVIEW(dev
)) {
5958 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5959 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5960 intel_encoder
->enable
= vlv_enable_dp
;
5961 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5963 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5964 intel_encoder
->enable
= g4x_enable_dp
;
5965 if (INTEL_INFO(dev
)->gen
>= 5)
5966 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5969 intel_dig_port
->port
= port
;
5970 intel_dig_port
->dp
.output_reg
= output_reg
;
5971 intel_dig_port
->max_lanes
= 4;
5973 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5974 if (IS_CHERRYVIEW(dev
)) {
5976 intel_encoder
->crtc_mask
= 1 << 2;
5978 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5980 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5982 intel_encoder
->cloneable
= 0;
5984 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5985 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5987 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
5988 goto err_init_connector
;
5993 drm_encoder_cleanup(encoder
);
5995 kfree(intel_connector
);
5996 err_connector_alloc
:
5997 kfree(intel_dig_port
);
6002 void intel_dp_mst_suspend(struct drm_device
*dev
)
6004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6008 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6009 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6010 if (!intel_dig_port
)
6013 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
6014 if (!intel_dig_port
->dp
.can_mst
)
6016 if (intel_dig_port
->dp
.is_mst
)
6017 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
6022 void intel_dp_mst_resume(struct drm_device
*dev
)
6024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6027 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6028 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6029 if (!intel_dig_port
)
6031 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
6034 if (!intel_dig_port
->dp
.can_mst
)
6037 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6039 intel_dp_check_mst_status(&intel_dig_port
->dp
);