2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int chv_rates
[] = { 162000, 202500, 210000, 216000,
99 243000, 270000, 324000, 405000,
100 420000, 432000, 540000 };
101 static const int default_rates
[] = { 162000, 270000, 540000 };
104 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
105 * @intel_dp: DP struct
107 * If a CPU or PCH DP output is attached to an eDP panel, this function
108 * will return true, and false otherwise.
110 static bool is_edp(struct intel_dp
*intel_dp
)
112 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
114 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
117 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
119 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
121 return intel_dig_port
->base
.base
.dev
;
124 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
126 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
129 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
130 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
131 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
132 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
133 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
137 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
139 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
141 switch (max_link_bw
) {
142 case DP_LINK_BW_1_62
:
147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
149 max_link_bw
= DP_LINK_BW_1_62
;
155 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
157 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
158 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
159 u8 source_max
, sink_max
;
162 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
163 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
166 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
168 return min(source_max
, sink_max
);
172 * The units on the numbers in the next two are... bizarre. Examples will
173 * make it clearer; this one parallels an example in the eDP spec.
175 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
177 * 270000 * 1 * 8 / 10 == 216000
179 * The actual data capacity of that configuration is 2.16Gbit/s, so the
180 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
181 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
182 * 119000. At 18bpp that's 2142000 kilobits per second.
184 * Thus the strange-looking division by 10 in intel_dp_link_required, to
185 * get the result in decakilobits instead of kilobits.
189 intel_dp_link_required(int pixel_clock
, int bpp
)
191 return (pixel_clock
* bpp
+ 9) / 10;
195 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
197 return (max_link_clock
* max_lanes
* 8) / 10;
200 static enum drm_mode_status
201 intel_dp_mode_valid(struct drm_connector
*connector
,
202 struct drm_display_mode
*mode
)
204 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
205 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
206 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
207 int target_clock
= mode
->clock
;
208 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
210 if (is_edp(intel_dp
) && fixed_mode
) {
211 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
214 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
217 target_clock
= fixed_mode
->clock
;
220 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
221 max_lanes
= intel_dp_max_lane_count(intel_dp
);
223 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
224 mode_rate
= intel_dp_link_required(target_clock
, 18);
226 if (mode_rate
> max_rate
)
227 return MODE_CLOCK_HIGH
;
229 if (mode
->clock
< 10000)
230 return MODE_CLOCK_LOW
;
232 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
233 return MODE_H_ILLEGAL
;
238 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
245 for (i
= 0; i
< src_bytes
; i
++)
246 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
250 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
255 for (i
= 0; i
< dst_bytes
; i
++)
256 dst
[i
] = src
>> ((3-i
) * 8);
259 /* hrawclock is 1/4 the FSB frequency */
261 intel_hrawclk(struct drm_device
*dev
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev
))
270 clkcfg
= I915_READ(CLKCFG
);
271 switch (clkcfg
& CLKCFG_FSB_MASK
) {
280 case CLKCFG_FSB_1067
:
282 case CLKCFG_FSB_1333
:
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600
:
286 case CLKCFG_FSB_1600_ALT
:
294 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
295 struct intel_dp
*intel_dp
);
297 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
298 struct intel_dp
*intel_dp
);
300 static void pps_lock(struct intel_dp
*intel_dp
)
302 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
303 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
304 struct drm_device
*dev
= encoder
->base
.dev
;
305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 enum intel_display_power_domain power_domain
;
309 * See vlv_power_sequencer_reset() why we need
310 * a power domain reference here.
312 power_domain
= intel_display_port_power_domain(encoder
);
313 intel_display_power_get(dev_priv
, power_domain
);
315 mutex_lock(&dev_priv
->pps_mutex
);
318 static void pps_unlock(struct intel_dp
*intel_dp
)
320 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
321 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
322 struct drm_device
*dev
= encoder
->base
.dev
;
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 enum intel_display_power_domain power_domain
;
326 mutex_unlock(&dev_priv
->pps_mutex
);
328 power_domain
= intel_display_port_power_domain(encoder
);
329 intel_display_power_put(dev_priv
, power_domain
);
333 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
335 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
336 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
338 enum pipe pipe
= intel_dp
->pps_pipe
;
342 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
343 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
344 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
347 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
348 pipe_name(pipe
), port_name(intel_dig_port
->port
));
350 /* Preserve the BIOS-computed detected bit. This is
351 * supposed to be read-only.
353 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
354 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
355 DP
|= DP_PORT_WIDTH(1);
356 DP
|= DP_LINK_TRAIN_PAT_1
;
358 if (IS_CHERRYVIEW(dev
))
359 DP
|= DP_PIPE_SELECT_CHV(pipe
);
360 else if (pipe
== PIPE_B
)
361 DP
|= DP_PIPEB_SELECT
;
363 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
366 * The DPLL for the pipe must be enabled for this to work.
367 * So enable temporarily it if it's not already enabled.
370 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
371 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
374 * Similar magic as in intel_dp_enable_port().
375 * We _must_ do this port enable + disable trick
376 * to make this power seqeuencer lock onto the port.
377 * Otherwise even VDD force bit won't work.
379 I915_WRITE(intel_dp
->output_reg
, DP
);
380 POSTING_READ(intel_dp
->output_reg
);
382 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
383 POSTING_READ(intel_dp
->output_reg
);
385 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
386 POSTING_READ(intel_dp
->output_reg
);
389 vlv_force_pll_off(dev
, pipe
);
393 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
395 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
396 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
398 struct intel_encoder
*encoder
;
399 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
402 lockdep_assert_held(&dev_priv
->pps_mutex
);
404 /* We should never land here with regular DP ports */
405 WARN_ON(!is_edp(intel_dp
));
407 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
408 return intel_dp
->pps_pipe
;
411 * We don't have power sequencer currently.
412 * Pick one that's not used by other ports.
414 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
416 struct intel_dp
*tmp
;
418 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
421 tmp
= enc_to_intel_dp(&encoder
->base
);
423 if (tmp
->pps_pipe
!= INVALID_PIPE
)
424 pipes
&= ~(1 << tmp
->pps_pipe
);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes
== 0))
434 pipe
= ffs(pipes
) - 1;
436 vlv_steal_power_sequencer(dev
, pipe
);
437 intel_dp
->pps_pipe
= pipe
;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp
->pps_pipe
),
441 port_name(intel_dig_port
->port
));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
445 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp
);
453 return intel_dp
->pps_pipe
;
456 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
459 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
462 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
465 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
468 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
471 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
478 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
480 vlv_pipe_check pipe_check
)
484 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
485 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
486 PANEL_PORT_SELECT_MASK
;
488 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
491 if (!pipe_check(dev_priv
, pipe
))
501 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
503 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
504 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
506 enum port port
= intel_dig_port
->port
;
508 lockdep_assert_held(&dev_priv
->pps_mutex
);
510 /* try to find a pipe with this port selected */
511 /* first pick one where the panel is on */
512 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
514 /* didn't find one? pick one where vdd is on */
515 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
516 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
517 vlv_pipe_has_vdd_on
);
518 /* didn't find one? pick one with just the correct port */
519 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
520 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
523 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
524 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
525 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
530 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
531 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
533 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
534 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
537 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
539 struct drm_device
*dev
= dev_priv
->dev
;
540 struct intel_encoder
*encoder
;
542 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
546 * We can't grab pps_mutex here due to deadlock with power_domain
547 * mutex when power_domain functions are called while holding pps_mutex.
548 * That also means that in order to use pps_pipe the code needs to
549 * hold both a power domain reference and pps_mutex, and the power domain
550 * reference get/put must be done while _not_ holding pps_mutex.
551 * pps_{lock,unlock}() do these steps in the correct order, so one
552 * should use them always.
555 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
556 struct intel_dp
*intel_dp
;
558 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
561 intel_dp
= enc_to_intel_dp(&encoder
->base
);
562 intel_dp
->pps_pipe
= INVALID_PIPE
;
566 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
568 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
571 return BXT_PP_CONTROL(0);
572 else if (HAS_PCH_SPLIT(dev
))
573 return PCH_PP_CONTROL
;
575 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
578 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
580 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
583 return BXT_PP_STATUS(0);
584 else if (HAS_PCH_SPLIT(dev
))
585 return PCH_PP_STATUS
;
587 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
590 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
591 This function only applicable when panel PM state is not to be tracked */
592 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
595 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
597 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
600 u32 pp_ctrl_reg
, pp_div_reg
;
602 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
607 if (IS_VALLEYVIEW(dev
)) {
608 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
610 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
611 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
612 pp_div
= I915_READ(pp_div_reg
);
613 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
615 /* 0x1F write to PP_DIV_REG sets max cycle delay */
616 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
617 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
618 msleep(intel_dp
->panel_power_cycle_delay
);
621 pps_unlock(intel_dp
);
626 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
628 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
631 lockdep_assert_held(&dev_priv
->pps_mutex
);
633 if (IS_VALLEYVIEW(dev
) &&
634 intel_dp
->pps_pipe
== INVALID_PIPE
)
637 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
640 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
642 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
645 lockdep_assert_held(&dev_priv
->pps_mutex
);
647 if (IS_VALLEYVIEW(dev
) &&
648 intel_dp
->pps_pipe
== INVALID_PIPE
)
651 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
655 intel_dp_check_edp(struct intel_dp
*intel_dp
)
657 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
660 if (!is_edp(intel_dp
))
663 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
664 WARN(1, "eDP powered off while attempting aux channel communication.\n");
665 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
666 I915_READ(_pp_stat_reg(intel_dp
)),
667 I915_READ(_pp_ctrl_reg(intel_dp
)));
672 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
674 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
675 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
677 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
681 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
683 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
684 msecs_to_jiffies_timeout(10));
686 done
= wait_for_atomic(C
, 10) == 0;
688 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
695 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
697 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
698 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
701 * The clock divider is based off the hrawclk, and would like to run at
702 * 2MHz. So, take the hrawclk value and divide by 2 and use that
704 return index
? 0 : intel_hrawclk(dev
) / 2;
707 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
709 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
710 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
716 if (intel_dig_port
->port
== PORT_A
) {
717 return DIV_ROUND_UP(dev_priv
->cdclk_freq
, 2000);
720 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
724 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
726 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
727 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
730 if (intel_dig_port
->port
== PORT_A
) {
733 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
734 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
735 /* Workaround for non-ULT HSW */
742 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
746 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
748 return index
? 0 : 100;
751 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
754 * SKL doesn't need us to program the AUX clock divider (Hardware will
755 * derive the clock from CDCLK automatically). We still implement the
756 * get_aux_clock_divider vfunc to plug-in into the existing code.
758 return index
? 0 : 1;
761 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
764 uint32_t aux_clock_divider
)
766 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
767 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
768 uint32_t precharge
, timeout
;
775 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
776 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
778 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
780 return DP_AUX_CH_CTL_SEND_BUSY
|
782 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
783 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
785 DP_AUX_CH_CTL_RECEIVE_ERROR
|
786 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
787 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
788 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
791 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
796 return DP_AUX_CH_CTL_SEND_BUSY
|
798 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
799 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
800 DP_AUX_CH_CTL_TIME_OUT_1600us
|
801 DP_AUX_CH_CTL_RECEIVE_ERROR
|
802 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
803 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
807 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
808 const uint8_t *send
, int send_bytes
,
809 uint8_t *recv
, int recv_size
)
811 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
812 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
814 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
815 uint32_t ch_data
= ch_ctl
+ 4;
816 uint32_t aux_clock_divider
;
817 int i
, ret
, recv_bytes
;
820 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
826 * We will be called with VDD already enabled for dpcd/edid/oui reads.
827 * In such cases we want to leave VDD enabled and it's up to upper layers
828 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
831 vdd
= edp_panel_vdd_on(intel_dp
);
833 /* dp aux is extremely sensitive to irq latency, hence request the
834 * lowest possible wakeup latency and so prevent the cpu from going into
837 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
839 intel_dp_check_edp(intel_dp
);
841 intel_aux_display_runtime_get(dev_priv
);
843 /* Try to wait for any previous AUX channel activity */
844 for (try = 0; try < 3; try++) {
845 status
= I915_READ_NOTRACE(ch_ctl
);
846 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
852 WARN(1, "dp_aux_ch not started status 0x%08x\n",
858 /* Only 5 data registers! */
859 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
864 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
865 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
870 /* Must try at least 3 times according to DP spec */
871 for (try = 0; try < 5; try++) {
872 /* Load the send data into the aux channel data registers */
873 for (i
= 0; i
< send_bytes
; i
+= 4)
874 I915_WRITE(ch_data
+ i
,
875 intel_dp_pack_aux(send
+ i
,
878 /* Send the command and wait for it to complete */
879 I915_WRITE(ch_ctl
, send_ctl
);
881 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
883 /* Clear done status and any errors */
887 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
888 DP_AUX_CH_CTL_RECEIVE_ERROR
);
890 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
893 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
894 * 400us delay required for errors and timeouts
895 * Timeout errors from the HW already meet this
896 * requirement so skip to next iteration
898 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
899 usleep_range(400, 500);
902 if (status
& DP_AUX_CH_CTL_DONE
)
905 if (status
& DP_AUX_CH_CTL_DONE
)
909 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
910 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
915 /* Check for timeout or receive error.
916 * Timeouts occur when the sink is not connected
918 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
919 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
924 /* Timeouts occur when the device isn't connected, so they're
925 * "normal" -- don't fill the kernel log with these */
926 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
927 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
932 /* Unload any bytes sent back from the other side */
933 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
934 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
935 if (recv_bytes
> recv_size
)
936 recv_bytes
= recv_size
;
938 for (i
= 0; i
< recv_bytes
; i
+= 4)
939 intel_dp_unpack_aux(I915_READ(ch_data
+ i
),
940 recv
+ i
, recv_bytes
- i
);
944 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
945 intel_aux_display_runtime_put(dev_priv
);
948 edp_panel_vdd_off(intel_dp
, false);
950 pps_unlock(intel_dp
);
955 #define BARE_ADDRESS_SIZE 3
956 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
958 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
960 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
961 uint8_t txbuf
[20], rxbuf
[20];
962 size_t txsize
, rxsize
;
965 txbuf
[0] = (msg
->request
<< 4) |
966 ((msg
->address
>> 16) & 0xf);
967 txbuf
[1] = (msg
->address
>> 8) & 0xff;
968 txbuf
[2] = msg
->address
& 0xff;
969 txbuf
[3] = msg
->size
- 1;
971 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
972 case DP_AUX_NATIVE_WRITE
:
973 case DP_AUX_I2C_WRITE
:
974 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
975 rxsize
= 2; /* 0 or 1 data bytes */
977 if (WARN_ON(txsize
> 20))
980 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
982 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
984 msg
->reply
= rxbuf
[0] >> 4;
987 /* Number of bytes written in a short write. */
988 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
990 /* Return payload size. */
996 case DP_AUX_NATIVE_READ
:
997 case DP_AUX_I2C_READ
:
998 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
999 rxsize
= msg
->size
+ 1;
1001 if (WARN_ON(rxsize
> 20))
1004 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1006 msg
->reply
= rxbuf
[0] >> 4;
1008 * Assume happy day, and copy the data. The caller is
1009 * expected to check msg->reply before touching it.
1011 * Return payload size.
1014 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1027 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1029 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1030 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1031 enum port port
= intel_dig_port
->port
;
1032 const char *name
= NULL
;
1037 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1041 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1045 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1049 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1057 * The AUX_CTL register is usually DP_CTL + 0x10.
1059 * On Haswell and Broadwell though:
1060 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1061 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1063 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1065 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
1066 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1068 intel_dp
->aux
.name
= name
;
1069 intel_dp
->aux
.dev
= dev
->dev
;
1070 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1072 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1073 connector
->base
.kdev
->kobj
.name
);
1075 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1077 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1082 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1083 &intel_dp
->aux
.ddc
.dev
.kobj
,
1084 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1086 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1087 drm_dp_aux_unregister(&intel_dp
->aux
);
1092 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1094 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1096 if (!intel_connector
->mst_port
)
1097 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1098 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1099 intel_connector_unregister(intel_connector
);
1103 skl_edp_set_pll_config(struct intel_crtc_state
*pipe_config
, int link_clock
)
1107 memset(&pipe_config
->dpll_hw_state
, 0,
1108 sizeof(pipe_config
->dpll_hw_state
));
1110 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
1111 pipe_config
->dpll_hw_state
.cfgcr1
= 0;
1112 pipe_config
->dpll_hw_state
.cfgcr2
= 0;
1114 ctrl1
= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
1115 switch (link_clock
/ 2) {
1117 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
1121 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
,
1125 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
,
1129 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
,
1132 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1133 results in CDCLK change. Need to handle the change of CDCLK by
1134 disabling pipes and re-enabling them */
1136 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
1140 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
,
1145 pipe_config
->dpll_hw_state
.ctrl1
= ctrl1
;
1149 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state
*pipe_config
, int link_bw
)
1152 case DP_LINK_BW_1_62
:
1153 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1155 case DP_LINK_BW_2_7
:
1156 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1158 case DP_LINK_BW_5_4
:
1159 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1165 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1167 if (intel_dp
->num_sink_rates
) {
1168 *sink_rates
= intel_dp
->sink_rates
;
1169 return intel_dp
->num_sink_rates
;
1172 *sink_rates
= default_rates
;
1174 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1178 intel_dp_source_rates(struct drm_device
*dev
, const int **source_rates
)
1180 if (IS_BROXTON(dev
)) {
1181 *source_rates
= bxt_rates
;
1182 return ARRAY_SIZE(bxt_rates
);
1183 } else if (IS_SKYLAKE(dev
)) {
1184 *source_rates
= skl_rates
;
1185 return ARRAY_SIZE(skl_rates
);
1186 } else if (IS_CHERRYVIEW(dev
)) {
1187 *source_rates
= chv_rates
;
1188 return ARRAY_SIZE(chv_rates
);
1191 *source_rates
= default_rates
;
1193 if (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
)
1194 /* WaDisableHBR2:skl */
1195 return (DP_LINK_BW_2_7
>> 3) + 1;
1196 else if (INTEL_INFO(dev
)->gen
>= 8 ||
1197 (IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)))
1198 return (DP_LINK_BW_5_4
>> 3) + 1;
1200 return (DP_LINK_BW_2_7
>> 3) + 1;
1204 intel_dp_set_clock(struct intel_encoder
*encoder
,
1205 struct intel_crtc_state
*pipe_config
, int link_bw
)
1207 struct drm_device
*dev
= encoder
->base
.dev
;
1208 const struct dp_link_dpll
*divisor
= NULL
;
1212 divisor
= gen4_dpll
;
1213 count
= ARRAY_SIZE(gen4_dpll
);
1214 } else if (HAS_PCH_SPLIT(dev
)) {
1216 count
= ARRAY_SIZE(pch_dpll
);
1217 } else if (IS_CHERRYVIEW(dev
)) {
1219 count
= ARRAY_SIZE(chv_dpll
);
1220 } else if (IS_VALLEYVIEW(dev
)) {
1222 count
= ARRAY_SIZE(vlv_dpll
);
1225 if (divisor
&& count
) {
1226 for (i
= 0; i
< count
; i
++) {
1227 if (link_bw
== divisor
[i
].link_bw
) {
1228 pipe_config
->dpll
= divisor
[i
].dpll
;
1229 pipe_config
->clock_set
= true;
1236 static int intersect_rates(const int *source_rates
, int source_len
,
1237 const int *sink_rates
, int sink_len
,
1240 int i
= 0, j
= 0, k
= 0;
1242 while (i
< source_len
&& j
< sink_len
) {
1243 if (source_rates
[i
] == sink_rates
[j
]) {
1244 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1246 common_rates
[k
] = source_rates
[i
];
1250 } else if (source_rates
[i
] < sink_rates
[j
]) {
1259 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1262 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1263 const int *source_rates
, *sink_rates
;
1264 int source_len
, sink_len
;
1266 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1267 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1269 return intersect_rates(source_rates
, source_len
,
1270 sink_rates
, sink_len
,
1274 static void snprintf_int_array(char *str
, size_t len
,
1275 const int *array
, int nelem
)
1281 for (i
= 0; i
< nelem
; i
++) {
1282 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1290 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1292 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1293 const int *source_rates
, *sink_rates
;
1294 int source_len
, sink_len
, common_len
;
1295 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1296 char str
[128]; /* FIXME: too big for stack? */
1298 if ((drm_debug
& DRM_UT_KMS
) == 0)
1301 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1302 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1303 DRM_DEBUG_KMS("source rates: %s\n", str
);
1305 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1306 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1307 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1309 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1310 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1311 DRM_DEBUG_KMS("common rates: %s\n", str
);
1314 static int rate_to_index(int find
, const int *rates
)
1318 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1319 if (find
== rates
[i
])
1326 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1328 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1331 len
= intel_dp_common_rates(intel_dp
, rates
);
1332 if (WARN_ON(len
<= 0))
1335 return rates
[rate_to_index(0, rates
) - 1];
1338 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1340 return rate_to_index(rate
, intel_dp
->sink_rates
);
1344 intel_dp_compute_config(struct intel_encoder
*encoder
,
1345 struct intel_crtc_state
*pipe_config
)
1347 struct drm_device
*dev
= encoder
->base
.dev
;
1348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1349 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1350 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1351 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1352 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1353 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1354 int lane_count
, clock
;
1355 int min_lane_count
= 1;
1356 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1357 /* Conveniently, the link BW constants become indices with a shift...*/
1361 int link_avail
, link_clock
;
1362 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1365 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1367 /* No common link rates between source and sink */
1368 WARN_ON(common_len
<= 0);
1370 max_clock
= common_len
- 1;
1372 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1373 pipe_config
->has_pch_encoder
= true;
1375 pipe_config
->has_dp_encoder
= true;
1376 pipe_config
->has_drrs
= false;
1377 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1379 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1380 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1383 if (INTEL_INFO(dev
)->gen
>= 9) {
1385 ret
= skl_update_scaler_crtc(pipe_config
, 0);
1390 if (!HAS_PCH_SPLIT(dev
))
1391 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1392 intel_connector
->panel
.fitting_mode
);
1394 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1395 intel_connector
->panel
.fitting_mode
);
1398 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1401 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1402 "max bw %d pixel clock %iKHz\n",
1403 max_lane_count
, common_rates
[max_clock
],
1404 adjusted_mode
->crtc_clock
);
1406 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1407 * bpc in between. */
1408 bpp
= pipe_config
->pipe_bpp
;
1409 if (is_edp(intel_dp
)) {
1410 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1411 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1412 dev_priv
->vbt
.edp_bpp
);
1413 bpp
= dev_priv
->vbt
.edp_bpp
;
1417 * Use the maximum clock and number of lanes the eDP panel
1418 * advertizes being capable of. The panels are generally
1419 * designed to support only a single clock and lane
1420 * configuration, and typically these values correspond to the
1421 * native resolution of the panel.
1423 min_lane_count
= max_lane_count
;
1424 min_clock
= max_clock
;
1427 for (; bpp
>= 6*3; bpp
-= 2*3) {
1428 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1431 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1432 for (lane_count
= min_lane_count
;
1433 lane_count
<= max_lane_count
;
1436 link_clock
= common_rates
[clock
];
1437 link_avail
= intel_dp_max_data_rate(link_clock
,
1440 if (mode_rate
<= link_avail
) {
1450 if (intel_dp
->color_range_auto
) {
1453 * CEA-861-E - 5.1 Default Encoding Parameters
1454 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1456 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1457 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1459 intel_dp
->color_range
= 0;
1462 if (intel_dp
->color_range
)
1463 pipe_config
->limited_color_range
= true;
1465 intel_dp
->lane_count
= lane_count
;
1467 if (intel_dp
->num_sink_rates
) {
1468 intel_dp
->link_bw
= 0;
1469 intel_dp
->rate_select
=
1470 intel_dp_rate_select(intel_dp
, common_rates
[clock
]);
1473 drm_dp_link_rate_to_bw_code(common_rates
[clock
]);
1474 intel_dp
->rate_select
= 0;
1477 pipe_config
->pipe_bpp
= bpp
;
1478 pipe_config
->port_clock
= common_rates
[clock
];
1480 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1481 intel_dp
->link_bw
, intel_dp
->lane_count
,
1482 pipe_config
->port_clock
, bpp
);
1483 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1484 mode_rate
, link_avail
);
1486 intel_link_compute_m_n(bpp
, lane_count
,
1487 adjusted_mode
->crtc_clock
,
1488 pipe_config
->port_clock
,
1489 &pipe_config
->dp_m_n
);
1491 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1492 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1493 pipe_config
->has_drrs
= true;
1494 intel_link_compute_m_n(bpp
, lane_count
,
1495 intel_connector
->panel
.downclock_mode
->clock
,
1496 pipe_config
->port_clock
,
1497 &pipe_config
->dp_m2_n2
);
1500 if (IS_SKYLAKE(dev
) && is_edp(intel_dp
))
1501 skl_edp_set_pll_config(pipe_config
, common_rates
[clock
]);
1502 else if (IS_BROXTON(dev
))
1503 /* handled in ddi */;
1504 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1505 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1507 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1512 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1514 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1515 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1516 struct drm_device
*dev
= crtc
->base
.dev
;
1517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1520 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1521 crtc
->config
->port_clock
);
1522 dpa_ctl
= I915_READ(DP_A
);
1523 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1525 if (crtc
->config
->port_clock
== 162000) {
1526 /* For a long time we've carried around a ILK-DevA w/a for the
1527 * 160MHz clock. If we're really unlucky, it's still required.
1529 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1530 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1531 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1533 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1534 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1537 I915_WRITE(DP_A
, dpa_ctl
);
1543 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1545 struct drm_device
*dev
= encoder
->base
.dev
;
1546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1547 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1548 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1549 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1550 struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1553 * There are four kinds of DP registers:
1560 * IBX PCH and CPU are the same for almost everything,
1561 * except that the CPU DP PLL is configured in this
1564 * CPT PCH is quite different, having many bits moved
1565 * to the TRANS_DP_CTL register instead. That
1566 * configuration happens (oddly) in ironlake_pch_enable
1569 /* Preserve the BIOS-computed detected bit. This is
1570 * supposed to be read-only.
1572 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1574 /* Handle DP bits in common between all three register formats */
1575 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1576 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1578 if (crtc
->config
->has_audio
)
1579 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1581 /* Split out the IBX/CPU vs CPT settings */
1583 if (IS_GEN7(dev
) && port
== PORT_A
) {
1584 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1585 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1586 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1587 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1588 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1590 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1591 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1593 intel_dp
->DP
|= crtc
->pipe
<< 29;
1594 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1597 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1599 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1600 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1601 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1603 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1604 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1606 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1607 intel_dp
->DP
|= intel_dp
->color_range
;
1609 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1610 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1611 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1612 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1613 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1615 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1616 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1618 if (IS_CHERRYVIEW(dev
))
1619 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1620 else if (crtc
->pipe
== PIPE_B
)
1621 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1625 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1626 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1628 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1629 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1631 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1632 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1634 static void wait_panel_status(struct intel_dp
*intel_dp
,
1638 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1640 u32 pp_stat_reg
, pp_ctrl_reg
;
1642 lockdep_assert_held(&dev_priv
->pps_mutex
);
1644 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1645 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1647 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1649 I915_READ(pp_stat_reg
),
1650 I915_READ(pp_ctrl_reg
));
1652 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1653 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1654 I915_READ(pp_stat_reg
),
1655 I915_READ(pp_ctrl_reg
));
1658 DRM_DEBUG_KMS("Wait complete\n");
1661 static void wait_panel_on(struct intel_dp
*intel_dp
)
1663 DRM_DEBUG_KMS("Wait for panel power on\n");
1664 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1667 static void wait_panel_off(struct intel_dp
*intel_dp
)
1669 DRM_DEBUG_KMS("Wait for panel power off time\n");
1670 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1673 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1675 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1677 /* When we disable the VDD override bit last we have to do the manual
1679 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1680 intel_dp
->panel_power_cycle_delay
);
1682 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1685 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1687 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1688 intel_dp
->backlight_on_delay
);
1691 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1693 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1694 intel_dp
->backlight_off_delay
);
1697 /* Read the current pp_control value, unlocking the register if it
1701 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1703 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1707 lockdep_assert_held(&dev_priv
->pps_mutex
);
1709 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1710 if (!IS_BROXTON(dev
)) {
1711 control
&= ~PANEL_UNLOCK_MASK
;
1712 control
|= PANEL_UNLOCK_REGS
;
1718 * Must be paired with edp_panel_vdd_off().
1719 * Must hold pps_mutex around the whole on/off sequence.
1720 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1722 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1724 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1725 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1726 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1728 enum intel_display_power_domain power_domain
;
1730 u32 pp_stat_reg
, pp_ctrl_reg
;
1731 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1733 lockdep_assert_held(&dev_priv
->pps_mutex
);
1735 if (!is_edp(intel_dp
))
1738 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1739 intel_dp
->want_panel_vdd
= true;
1741 if (edp_have_panel_vdd(intel_dp
))
1742 return need_to_disable
;
1744 power_domain
= intel_display_port_power_domain(intel_encoder
);
1745 intel_display_power_get(dev_priv
, power_domain
);
1747 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1748 port_name(intel_dig_port
->port
));
1750 if (!edp_have_panel_power(intel_dp
))
1751 wait_panel_power_cycle(intel_dp
);
1753 pp
= ironlake_get_pp_control(intel_dp
);
1754 pp
|= EDP_FORCE_VDD
;
1756 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1757 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1759 I915_WRITE(pp_ctrl_reg
, pp
);
1760 POSTING_READ(pp_ctrl_reg
);
1761 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1762 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1764 * If the panel wasn't on, delay before accessing aux channel
1766 if (!edp_have_panel_power(intel_dp
)) {
1767 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1768 port_name(intel_dig_port
->port
));
1769 msleep(intel_dp
->panel_power_up_delay
);
1772 return need_to_disable
;
1776 * Must be paired with intel_edp_panel_vdd_off() or
1777 * intel_edp_panel_off().
1778 * Nested calls to these functions are not allowed since
1779 * we drop the lock. Caller must use some higher level
1780 * locking to prevent nested calls from other threads.
1782 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1786 if (!is_edp(intel_dp
))
1790 vdd
= edp_panel_vdd_on(intel_dp
);
1791 pps_unlock(intel_dp
);
1793 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1794 port_name(dp_to_dig_port(intel_dp
)->port
));
1797 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1799 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1801 struct intel_digital_port
*intel_dig_port
=
1802 dp_to_dig_port(intel_dp
);
1803 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1804 enum intel_display_power_domain power_domain
;
1806 u32 pp_stat_reg
, pp_ctrl_reg
;
1808 lockdep_assert_held(&dev_priv
->pps_mutex
);
1810 WARN_ON(intel_dp
->want_panel_vdd
);
1812 if (!edp_have_panel_vdd(intel_dp
))
1815 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1816 port_name(intel_dig_port
->port
));
1818 pp
= ironlake_get_pp_control(intel_dp
);
1819 pp
&= ~EDP_FORCE_VDD
;
1821 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1822 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1824 I915_WRITE(pp_ctrl_reg
, pp
);
1825 POSTING_READ(pp_ctrl_reg
);
1827 /* Make sure sequencer is idle before allowing subsequent activity */
1828 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1829 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1831 if ((pp
& POWER_TARGET_ON
) == 0)
1832 intel_dp
->last_power_cycle
= jiffies
;
1834 power_domain
= intel_display_port_power_domain(intel_encoder
);
1835 intel_display_power_put(dev_priv
, power_domain
);
1838 static void edp_panel_vdd_work(struct work_struct
*__work
)
1840 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1841 struct intel_dp
, panel_vdd_work
);
1844 if (!intel_dp
->want_panel_vdd
)
1845 edp_panel_vdd_off_sync(intel_dp
);
1846 pps_unlock(intel_dp
);
1849 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1851 unsigned long delay
;
1854 * Queue the timer to fire a long time from now (relative to the power
1855 * down delay) to keep the panel power up across a sequence of
1858 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1859 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1863 * Must be paired with edp_panel_vdd_on().
1864 * Must hold pps_mutex around the whole on/off sequence.
1865 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1867 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1869 struct drm_i915_private
*dev_priv
=
1870 intel_dp_to_dev(intel_dp
)->dev_private
;
1872 lockdep_assert_held(&dev_priv
->pps_mutex
);
1874 if (!is_edp(intel_dp
))
1877 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1878 port_name(dp_to_dig_port(intel_dp
)->port
));
1880 intel_dp
->want_panel_vdd
= false;
1883 edp_panel_vdd_off_sync(intel_dp
);
1885 edp_panel_vdd_schedule_off(intel_dp
);
1888 static void edp_panel_on(struct intel_dp
*intel_dp
)
1890 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1895 lockdep_assert_held(&dev_priv
->pps_mutex
);
1897 if (!is_edp(intel_dp
))
1900 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1901 port_name(dp_to_dig_port(intel_dp
)->port
));
1903 if (WARN(edp_have_panel_power(intel_dp
),
1904 "eDP port %c panel power already on\n",
1905 port_name(dp_to_dig_port(intel_dp
)->port
)))
1908 wait_panel_power_cycle(intel_dp
);
1910 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1911 pp
= ironlake_get_pp_control(intel_dp
);
1913 /* ILK workaround: disable reset around power sequence */
1914 pp
&= ~PANEL_POWER_RESET
;
1915 I915_WRITE(pp_ctrl_reg
, pp
);
1916 POSTING_READ(pp_ctrl_reg
);
1919 pp
|= POWER_TARGET_ON
;
1921 pp
|= PANEL_POWER_RESET
;
1923 I915_WRITE(pp_ctrl_reg
, pp
);
1924 POSTING_READ(pp_ctrl_reg
);
1926 wait_panel_on(intel_dp
);
1927 intel_dp
->last_power_on
= jiffies
;
1930 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1931 I915_WRITE(pp_ctrl_reg
, pp
);
1932 POSTING_READ(pp_ctrl_reg
);
1936 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1938 if (!is_edp(intel_dp
))
1942 edp_panel_on(intel_dp
);
1943 pps_unlock(intel_dp
);
1947 static void edp_panel_off(struct intel_dp
*intel_dp
)
1949 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1950 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1951 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1953 enum intel_display_power_domain power_domain
;
1957 lockdep_assert_held(&dev_priv
->pps_mutex
);
1959 if (!is_edp(intel_dp
))
1962 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1963 port_name(dp_to_dig_port(intel_dp
)->port
));
1965 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
1966 port_name(dp_to_dig_port(intel_dp
)->port
));
1968 pp
= ironlake_get_pp_control(intel_dp
);
1969 /* We need to switch off panel power _and_ force vdd, for otherwise some
1970 * panels get very unhappy and cease to work. */
1971 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1974 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1976 intel_dp
->want_panel_vdd
= false;
1978 I915_WRITE(pp_ctrl_reg
, pp
);
1979 POSTING_READ(pp_ctrl_reg
);
1981 intel_dp
->last_power_cycle
= jiffies
;
1982 wait_panel_off(intel_dp
);
1984 /* We got a reference when we enabled the VDD. */
1985 power_domain
= intel_display_port_power_domain(intel_encoder
);
1986 intel_display_power_put(dev_priv
, power_domain
);
1989 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1991 if (!is_edp(intel_dp
))
1995 edp_panel_off(intel_dp
);
1996 pps_unlock(intel_dp
);
1999 /* Enable backlight in the panel power control. */
2000 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2002 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2003 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2009 * If we enable the backlight right away following a panel power
2010 * on, we may see slight flicker as the panel syncs with the eDP
2011 * link. So delay a bit to make sure the image is solid before
2012 * allowing it to appear.
2014 wait_backlight_on(intel_dp
);
2018 pp
= ironlake_get_pp_control(intel_dp
);
2019 pp
|= EDP_BLC_ENABLE
;
2021 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2023 I915_WRITE(pp_ctrl_reg
, pp
);
2024 POSTING_READ(pp_ctrl_reg
);
2026 pps_unlock(intel_dp
);
2029 /* Enable backlight PWM and backlight PP control. */
2030 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2032 if (!is_edp(intel_dp
))
2035 DRM_DEBUG_KMS("\n");
2037 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2038 _intel_edp_backlight_on(intel_dp
);
2041 /* Disable backlight in the panel power control. */
2042 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2044 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2049 if (!is_edp(intel_dp
))
2054 pp
= ironlake_get_pp_control(intel_dp
);
2055 pp
&= ~EDP_BLC_ENABLE
;
2057 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2059 I915_WRITE(pp_ctrl_reg
, pp
);
2060 POSTING_READ(pp_ctrl_reg
);
2062 pps_unlock(intel_dp
);
2064 intel_dp
->last_backlight_off
= jiffies
;
2065 edp_wait_backlight_off(intel_dp
);
2068 /* Disable backlight PP control and backlight PWM. */
2069 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2071 if (!is_edp(intel_dp
))
2074 DRM_DEBUG_KMS("\n");
2076 _intel_edp_backlight_off(intel_dp
);
2077 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2081 * Hook for controlling the panel power control backlight through the bl_power
2082 * sysfs attribute. Take care to handle multiple calls.
2084 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2087 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2091 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2092 pps_unlock(intel_dp
);
2094 if (is_enabled
== enable
)
2097 DRM_DEBUG_KMS("panel power control backlight %s\n",
2098 enable
? "enable" : "disable");
2101 _intel_edp_backlight_on(intel_dp
);
2103 _intel_edp_backlight_off(intel_dp
);
2106 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2108 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2109 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2110 struct drm_device
*dev
= crtc
->dev
;
2111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2114 assert_pipe_disabled(dev_priv
,
2115 to_intel_crtc(crtc
)->pipe
);
2117 DRM_DEBUG_KMS("\n");
2118 dpa_ctl
= I915_READ(DP_A
);
2119 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
2120 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2122 /* We don't adjust intel_dp->DP while tearing down the link, to
2123 * facilitate link retraining (e.g. after hotplug). Hence clear all
2124 * enable bits here to ensure that we don't enable too much. */
2125 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
2126 intel_dp
->DP
|= DP_PLL_ENABLE
;
2127 I915_WRITE(DP_A
, intel_dp
->DP
);
2132 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2134 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2135 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2136 struct drm_device
*dev
= crtc
->dev
;
2137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2140 assert_pipe_disabled(dev_priv
,
2141 to_intel_crtc(crtc
)->pipe
);
2143 dpa_ctl
= I915_READ(DP_A
);
2144 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
2145 "dp pll off, should be on\n");
2146 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2148 /* We can't rely on the value tracked for the DP register in
2149 * intel_dp->DP because link_down must not change that (otherwise link
2150 * re-training will fail. */
2151 dpa_ctl
&= ~DP_PLL_ENABLE
;
2152 I915_WRITE(DP_A
, dpa_ctl
);
2157 /* If the sink supports it, try to set the power state appropriately */
2158 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2162 /* Should have a valid DPCD by this point */
2163 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2166 if (mode
!= DRM_MODE_DPMS_ON
) {
2167 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2171 * When turning on, we need to retry for 1ms to give the sink
2174 for (i
= 0; i
< 3; i
++) {
2175 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2184 DRM_DEBUG_KMS("failed to %s sink power state\n",
2185 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2188 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2191 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2192 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2193 struct drm_device
*dev
= encoder
->base
.dev
;
2194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2195 enum intel_display_power_domain power_domain
;
2198 power_domain
= intel_display_port_power_domain(encoder
);
2199 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2202 tmp
= I915_READ(intel_dp
->output_reg
);
2204 if (!(tmp
& DP_PORT_EN
))
2207 if (IS_GEN7(dev
) && port
== PORT_A
) {
2208 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2209 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2212 for_each_pipe(dev_priv
, p
) {
2213 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2214 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2220 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2221 intel_dp
->output_reg
);
2222 } else if (IS_CHERRYVIEW(dev
)) {
2223 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2225 *pipe
= PORT_TO_PIPE(tmp
);
2231 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2232 struct intel_crtc_state
*pipe_config
)
2234 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2236 struct drm_device
*dev
= encoder
->base
.dev
;
2237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2238 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2239 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2242 tmp
= I915_READ(intel_dp
->output_reg
);
2244 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2246 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2247 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2248 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2249 flags
|= DRM_MODE_FLAG_PHSYNC
;
2251 flags
|= DRM_MODE_FLAG_NHSYNC
;
2253 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2254 flags
|= DRM_MODE_FLAG_PVSYNC
;
2256 flags
|= DRM_MODE_FLAG_NVSYNC
;
2258 if (tmp
& DP_SYNC_HS_HIGH
)
2259 flags
|= DRM_MODE_FLAG_PHSYNC
;
2261 flags
|= DRM_MODE_FLAG_NHSYNC
;
2263 if (tmp
& DP_SYNC_VS_HIGH
)
2264 flags
|= DRM_MODE_FLAG_PVSYNC
;
2266 flags
|= DRM_MODE_FLAG_NVSYNC
;
2269 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2271 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2272 tmp
& DP_COLOR_RANGE_16_235
)
2273 pipe_config
->limited_color_range
= true;
2275 pipe_config
->has_dp_encoder
= true;
2277 intel_dp_get_m_n(crtc
, pipe_config
);
2279 if (port
== PORT_A
) {
2280 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2281 pipe_config
->port_clock
= 162000;
2283 pipe_config
->port_clock
= 270000;
2286 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2287 &pipe_config
->dp_m_n
);
2289 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2290 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2292 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
2294 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2295 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2297 * This is a big fat ugly hack.
2299 * Some machines in UEFI boot mode provide us a VBT that has 18
2300 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2301 * unknown we fail to light up. Yet the same BIOS boots up with
2302 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2303 * max, not what it tells us to use.
2305 * Note: This will still be broken if the eDP panel is not lit
2306 * up by the BIOS, and thus we can't get the mode at module
2309 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2310 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2311 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2315 static void intel_disable_dp(struct intel_encoder
*encoder
)
2317 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2318 struct drm_device
*dev
= encoder
->base
.dev
;
2319 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2321 if (crtc
->config
->has_audio
)
2322 intel_audio_codec_disable(encoder
);
2324 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2325 intel_psr_disable(intel_dp
);
2327 /* Make sure the panel is off before trying to change the mode. But also
2328 * ensure that we have vdd while we switch off the panel. */
2329 intel_edp_panel_vdd_on(intel_dp
);
2330 intel_edp_backlight_off(intel_dp
);
2331 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2332 intel_edp_panel_off(intel_dp
);
2334 /* disable the port before the pipe on g4x */
2335 if (INTEL_INFO(dev
)->gen
< 5)
2336 intel_dp_link_down(intel_dp
);
2339 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2341 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2342 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2344 intel_dp_link_down(intel_dp
);
2346 ironlake_edp_pll_off(intel_dp
);
2349 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2351 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2353 intel_dp_link_down(intel_dp
);
2356 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2358 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2359 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2360 struct drm_device
*dev
= encoder
->base
.dev
;
2361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2362 struct intel_crtc
*intel_crtc
=
2363 to_intel_crtc(encoder
->base
.crtc
);
2364 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2365 enum pipe pipe
= intel_crtc
->pipe
;
2368 intel_dp_link_down(intel_dp
);
2370 mutex_lock(&dev_priv
->sb_lock
);
2372 /* Propagate soft reset to data lane reset */
2373 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2374 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2375 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2377 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2378 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2379 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2381 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2382 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2383 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2385 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2386 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2387 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2389 mutex_unlock(&dev_priv
->sb_lock
);
2393 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2395 uint8_t dp_train_pat
)
2397 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2398 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2400 enum port port
= intel_dig_port
->port
;
2403 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2405 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2406 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2408 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2410 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2411 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2412 case DP_TRAINING_PATTERN_DISABLE
:
2413 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2416 case DP_TRAINING_PATTERN_1
:
2417 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2419 case DP_TRAINING_PATTERN_2
:
2420 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2422 case DP_TRAINING_PATTERN_3
:
2423 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2426 I915_WRITE(DP_TP_CTL(port
), temp
);
2428 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2429 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2430 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2432 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2433 case DP_TRAINING_PATTERN_DISABLE
:
2434 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2436 case DP_TRAINING_PATTERN_1
:
2437 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2439 case DP_TRAINING_PATTERN_2
:
2440 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2442 case DP_TRAINING_PATTERN_3
:
2443 DRM_ERROR("DP training pattern 3 not supported\n");
2444 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2449 if (IS_CHERRYVIEW(dev
))
2450 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2452 *DP
&= ~DP_LINK_TRAIN_MASK
;
2454 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2455 case DP_TRAINING_PATTERN_DISABLE
:
2456 *DP
|= DP_LINK_TRAIN_OFF
;
2458 case DP_TRAINING_PATTERN_1
:
2459 *DP
|= DP_LINK_TRAIN_PAT_1
;
2461 case DP_TRAINING_PATTERN_2
:
2462 *DP
|= DP_LINK_TRAIN_PAT_2
;
2464 case DP_TRAINING_PATTERN_3
:
2465 if (IS_CHERRYVIEW(dev
)) {
2466 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2468 DRM_ERROR("DP training pattern 3 not supported\n");
2469 *DP
|= DP_LINK_TRAIN_PAT_2
;
2476 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2478 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2481 /* enable with pattern 1 (as per spec) */
2482 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2483 DP_TRAINING_PATTERN_1
);
2485 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2486 POSTING_READ(intel_dp
->output_reg
);
2489 * Magic for VLV/CHV. We _must_ first set up the register
2490 * without actually enabling the port, and then do another
2491 * write to enable the port. Otherwise link training will
2492 * fail when the power sequencer is freshly used for this port.
2494 intel_dp
->DP
|= DP_PORT_EN
;
2496 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2497 POSTING_READ(intel_dp
->output_reg
);
2500 static void intel_enable_dp(struct intel_encoder
*encoder
)
2502 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2503 struct drm_device
*dev
= encoder
->base
.dev
;
2504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2505 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2506 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2507 unsigned int lane_mask
= 0x0;
2509 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2514 if (IS_VALLEYVIEW(dev
))
2515 vlv_init_panel_power_sequencer(intel_dp
);
2517 intel_dp_enable_port(intel_dp
);
2519 edp_panel_vdd_on(intel_dp
);
2520 edp_panel_on(intel_dp
);
2521 edp_panel_vdd_off(intel_dp
, true);
2523 pps_unlock(intel_dp
);
2525 if (IS_VALLEYVIEW(dev
))
2526 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2529 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2530 intel_dp_start_link_train(intel_dp
);
2531 intel_dp_complete_link_train(intel_dp
);
2532 intel_dp_stop_link_train(intel_dp
);
2534 if (crtc
->config
->has_audio
) {
2535 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2536 pipe_name(crtc
->pipe
));
2537 intel_audio_codec_enable(encoder
);
2541 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2543 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2545 intel_enable_dp(encoder
);
2546 intel_edp_backlight_on(intel_dp
);
2549 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2551 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2553 intel_edp_backlight_on(intel_dp
);
2554 intel_psr_enable(intel_dp
);
2557 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2559 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2560 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2562 intel_dp_prepare(encoder
);
2564 /* Only ilk+ has port A */
2565 if (dport
->port
== PORT_A
) {
2566 ironlake_set_pll_cpu_edp(intel_dp
);
2567 ironlake_edp_pll_on(intel_dp
);
2571 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2573 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2574 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2575 enum pipe pipe
= intel_dp
->pps_pipe
;
2576 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2578 edp_panel_vdd_off_sync(intel_dp
);
2581 * VLV seems to get confused when multiple power seqeuencers
2582 * have the same port selected (even if only one has power/vdd
2583 * enabled). The failure manifests as vlv_wait_port_ready() failing
2584 * CHV on the other hand doesn't seem to mind having the same port
2585 * selected in multiple power seqeuencers, but let's clear the
2586 * port select always when logically disconnecting a power sequencer
2589 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2590 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2591 I915_WRITE(pp_on_reg
, 0);
2592 POSTING_READ(pp_on_reg
);
2594 intel_dp
->pps_pipe
= INVALID_PIPE
;
2597 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2601 struct intel_encoder
*encoder
;
2603 lockdep_assert_held(&dev_priv
->pps_mutex
);
2605 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2608 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2610 struct intel_dp
*intel_dp
;
2613 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2616 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2617 port
= dp_to_dig_port(intel_dp
)->port
;
2619 if (intel_dp
->pps_pipe
!= pipe
)
2622 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2623 pipe_name(pipe
), port_name(port
));
2625 WARN(encoder
->connectors_active
,
2626 "stealing pipe %c power sequencer from active eDP port %c\n",
2627 pipe_name(pipe
), port_name(port
));
2629 /* make sure vdd is off before we steal it */
2630 vlv_detach_power_sequencer(intel_dp
);
2634 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2636 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2637 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2638 struct drm_device
*dev
= encoder
->base
.dev
;
2639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2640 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2642 lockdep_assert_held(&dev_priv
->pps_mutex
);
2644 if (!is_edp(intel_dp
))
2647 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2651 * If another power sequencer was being used on this
2652 * port previously make sure to turn off vdd there while
2653 * we still have control of it.
2655 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2656 vlv_detach_power_sequencer(intel_dp
);
2659 * We may be stealing the power
2660 * sequencer from another port.
2662 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2664 /* now it's all ours */
2665 intel_dp
->pps_pipe
= crtc
->pipe
;
2667 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2668 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2670 /* init power sequencer on this pipe and port */
2671 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2672 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2675 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2677 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2678 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2679 struct drm_device
*dev
= encoder
->base
.dev
;
2680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2681 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2682 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2683 int pipe
= intel_crtc
->pipe
;
2686 mutex_lock(&dev_priv
->sb_lock
);
2688 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2695 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2696 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2697 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2699 mutex_unlock(&dev_priv
->sb_lock
);
2701 intel_enable_dp(encoder
);
2704 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2706 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2707 struct drm_device
*dev
= encoder
->base
.dev
;
2708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2709 struct intel_crtc
*intel_crtc
=
2710 to_intel_crtc(encoder
->base
.crtc
);
2711 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2712 int pipe
= intel_crtc
->pipe
;
2714 intel_dp_prepare(encoder
);
2716 /* Program Tx lane resets to default */
2717 mutex_lock(&dev_priv
->sb_lock
);
2718 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2719 DPIO_PCS_TX_LANE2_RESET
|
2720 DPIO_PCS_TX_LANE1_RESET
);
2721 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2722 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2723 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2724 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2725 DPIO_PCS_CLK_SOFT_RESET
);
2727 /* Fix up inter-pair skew failure */
2728 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2729 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2730 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2731 mutex_unlock(&dev_priv
->sb_lock
);
2734 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2736 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2737 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2738 struct drm_device
*dev
= encoder
->base
.dev
;
2739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2740 struct intel_crtc
*intel_crtc
=
2741 to_intel_crtc(encoder
->base
.crtc
);
2742 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2743 int pipe
= intel_crtc
->pipe
;
2744 int data
, i
, stagger
;
2747 mutex_lock(&dev_priv
->sb_lock
);
2749 /* allow hardware to manage TX FIFO reset source */
2750 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2751 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2752 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2754 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2755 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2756 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2758 /* Deassert soft data lane reset*/
2759 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2760 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2761 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2763 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2764 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2765 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2767 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2768 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2769 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2771 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2772 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2773 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2775 /* Program Tx lane latency optimal setting*/
2776 for (i
= 0; i
< 4; i
++) {
2777 /* Set the upar bit */
2778 data
= (i
== 1) ? 0x0 : 0x1;
2779 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2780 data
<< DPIO_UPAR_SHIFT
);
2783 /* Data lane stagger programming */
2784 if (intel_crtc
->config
->port_clock
> 270000)
2786 else if (intel_crtc
->config
->port_clock
> 135000)
2788 else if (intel_crtc
->config
->port_clock
> 67500)
2790 else if (intel_crtc
->config
->port_clock
> 33750)
2795 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2796 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2797 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2799 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2800 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2801 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2803 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW12(ch
),
2804 DPIO_LANESTAGGER_STRAP(stagger
) |
2805 DPIO_LANESTAGGER_STRAP_OVRD
|
2806 DPIO_TX1_STAGGER_MASK(0x1f) |
2807 DPIO_TX1_STAGGER_MULT(6) |
2808 DPIO_TX2_STAGGER_MULT(0));
2810 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW12(ch
),
2811 DPIO_LANESTAGGER_STRAP(stagger
) |
2812 DPIO_LANESTAGGER_STRAP_OVRD
|
2813 DPIO_TX1_STAGGER_MASK(0x1f) |
2814 DPIO_TX1_STAGGER_MULT(7) |
2815 DPIO_TX2_STAGGER_MULT(5));
2817 mutex_unlock(&dev_priv
->sb_lock
);
2819 intel_enable_dp(encoder
);
2822 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2824 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2825 struct drm_device
*dev
= encoder
->base
.dev
;
2826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2827 struct intel_crtc
*intel_crtc
=
2828 to_intel_crtc(encoder
->base
.crtc
);
2829 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2830 enum pipe pipe
= intel_crtc
->pipe
;
2833 intel_dp_prepare(encoder
);
2835 mutex_lock(&dev_priv
->sb_lock
);
2837 /* program left/right clock distribution */
2838 if (pipe
!= PIPE_B
) {
2839 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2840 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2842 val
|= CHV_BUFLEFTENA1_FORCE
;
2844 val
|= CHV_BUFRIGHTENA1_FORCE
;
2845 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2847 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2848 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2850 val
|= CHV_BUFLEFTENA2_FORCE
;
2852 val
|= CHV_BUFRIGHTENA2_FORCE
;
2853 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2856 /* program clock channel usage */
2857 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2858 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2860 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2862 val
|= CHV_PCS_USEDCLKCHANNEL
;
2863 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2865 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2866 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2868 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2870 val
|= CHV_PCS_USEDCLKCHANNEL
;
2871 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2874 * This a a bit weird since generally CL
2875 * matches the pipe, but here we need to
2876 * pick the CL based on the port.
2878 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2880 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2882 val
|= CHV_CMN_USEDCLKCHANNEL
;
2883 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2885 mutex_unlock(&dev_priv
->sb_lock
);
2889 * Native read with retry for link status and receiver capability reads for
2890 * cases where the sink may still be asleep.
2892 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2893 * supposed to retry 3 times per the spec.
2896 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2897 void *buffer
, size_t size
)
2903 * Sometime we just get the same incorrect byte repeated
2904 * over the entire buffer. Doing just one throw away read
2905 * initially seems to "solve" it.
2907 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
2909 for (i
= 0; i
< 3; i
++) {
2910 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2920 * Fetch AUX CH registers 0x202 - 0x207 which contain
2921 * link status information
2924 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2926 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2929 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2932 /* These are source-specific values. */
2934 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2936 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2938 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2940 if (IS_BROXTON(dev
))
2941 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2942 else if (INTEL_INFO(dev
)->gen
>= 9) {
2943 if (dev_priv
->edp_low_vswing
&& port
== PORT_A
)
2944 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2945 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2946 } else if (IS_VALLEYVIEW(dev
))
2947 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2948 else if (IS_GEN7(dev
) && port
== PORT_A
)
2949 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2950 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2951 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2953 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2957 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2959 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2960 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2962 if (INTEL_INFO(dev
)->gen
>= 9) {
2963 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2964 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2965 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2966 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2967 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2968 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2969 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2971 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2973 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2975 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2976 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2977 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2978 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2979 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2980 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2981 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2982 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2983 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2985 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2987 } else if (IS_VALLEYVIEW(dev
)) {
2988 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2990 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2992 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2993 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2994 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2997 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2999 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3000 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3001 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3002 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3005 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3007 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3010 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3014 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3015 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3016 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3017 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3019 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3024 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3026 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3028 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3029 struct intel_crtc
*intel_crtc
=
3030 to_intel_crtc(dport
->base
.base
.crtc
);
3031 unsigned long demph_reg_value
, preemph_reg_value
,
3032 uniqtranscale_reg_value
;
3033 uint8_t train_set
= intel_dp
->train_set
[0];
3034 enum dpio_channel port
= vlv_dport_to_channel(dport
);
3035 int pipe
= intel_crtc
->pipe
;
3037 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3038 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3039 preemph_reg_value
= 0x0004000;
3040 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3042 demph_reg_value
= 0x2B405555;
3043 uniqtranscale_reg_value
= 0x552AB83A;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3046 demph_reg_value
= 0x2B404040;
3047 uniqtranscale_reg_value
= 0x5548B83A;
3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3050 demph_reg_value
= 0x2B245555;
3051 uniqtranscale_reg_value
= 0x5560B83A;
3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3054 demph_reg_value
= 0x2B405555;
3055 uniqtranscale_reg_value
= 0x5598DA3A;
3061 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3062 preemph_reg_value
= 0x0002000;
3063 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3065 demph_reg_value
= 0x2B404040;
3066 uniqtranscale_reg_value
= 0x5552B83A;
3068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3069 demph_reg_value
= 0x2B404848;
3070 uniqtranscale_reg_value
= 0x5580B83A;
3072 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3073 demph_reg_value
= 0x2B404040;
3074 uniqtranscale_reg_value
= 0x55ADDA3A;
3080 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3081 preemph_reg_value
= 0x0000000;
3082 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3084 demph_reg_value
= 0x2B305555;
3085 uniqtranscale_reg_value
= 0x5570B83A;
3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3088 demph_reg_value
= 0x2B2B4040;
3089 uniqtranscale_reg_value
= 0x55ADDA3A;
3095 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3096 preemph_reg_value
= 0x0006000;
3097 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3098 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3099 demph_reg_value
= 0x1B405555;
3100 uniqtranscale_reg_value
= 0x55ADDA3A;
3110 mutex_lock(&dev_priv
->sb_lock
);
3111 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3112 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3113 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3114 uniqtranscale_reg_value
);
3115 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3116 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3117 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3118 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3119 mutex_unlock(&dev_priv
->sb_lock
);
3124 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3126 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3128 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3129 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3130 u32 deemph_reg_value
, margin_reg_value
, val
;
3131 uint8_t train_set
= intel_dp
->train_set
[0];
3132 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3133 enum pipe pipe
= intel_crtc
->pipe
;
3136 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3137 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3138 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3140 deemph_reg_value
= 128;
3141 margin_reg_value
= 52;
3143 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3144 deemph_reg_value
= 128;
3145 margin_reg_value
= 77;
3147 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3148 deemph_reg_value
= 128;
3149 margin_reg_value
= 102;
3151 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3152 deemph_reg_value
= 128;
3153 margin_reg_value
= 154;
3154 /* FIXME extra to set for 1200 */
3160 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3161 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3163 deemph_reg_value
= 85;
3164 margin_reg_value
= 78;
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3167 deemph_reg_value
= 85;
3168 margin_reg_value
= 116;
3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3171 deemph_reg_value
= 85;
3172 margin_reg_value
= 154;
3178 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3179 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3181 deemph_reg_value
= 64;
3182 margin_reg_value
= 104;
3184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3185 deemph_reg_value
= 64;
3186 margin_reg_value
= 154;
3192 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3193 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3195 deemph_reg_value
= 43;
3196 margin_reg_value
= 154;
3206 mutex_lock(&dev_priv
->sb_lock
);
3208 /* Clear calc init */
3209 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3210 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3211 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3212 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3213 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3215 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3216 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3217 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3218 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3219 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3221 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3222 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3223 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3224 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3226 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3227 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3228 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3229 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3231 /* Program swing deemph */
3232 for (i
= 0; i
< 4; i
++) {
3233 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3234 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3235 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3236 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3239 /* Program swing margin */
3240 for (i
= 0; i
< 4; i
++) {
3241 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3242 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3243 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3244 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3247 /* Disable unique transition scale */
3248 for (i
= 0; i
< 4; i
++) {
3249 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3250 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3251 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3254 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3255 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3256 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3257 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3260 * The document said it needs to set bit 27 for ch0 and bit 26
3261 * for ch1. Might be a typo in the doc.
3262 * For now, for this unique transition scale selection, set bit
3263 * 27 for ch0 and ch1.
3265 for (i
= 0; i
< 4; i
++) {
3266 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3267 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3268 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3271 for (i
= 0; i
< 4; i
++) {
3272 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3273 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3274 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3275 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3279 /* Start swing calculation */
3280 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3281 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3282 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3284 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3285 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3286 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3289 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3290 val
|= DPIO_LRC_BYPASS
;
3291 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3293 mutex_unlock(&dev_priv
->sb_lock
);
3299 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3300 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3305 uint8_t voltage_max
;
3306 uint8_t preemph_max
;
3308 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3309 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3310 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3318 voltage_max
= intel_dp_voltage_max(intel_dp
);
3319 if (v
>= voltage_max
)
3320 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3322 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3323 if (p
>= preemph_max
)
3324 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3326 for (lane
= 0; lane
< 4; lane
++)
3327 intel_dp
->train_set
[lane
] = v
| p
;
3331 gen4_signal_levels(uint8_t train_set
)
3333 uint32_t signal_levels
= 0;
3335 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3338 signal_levels
|= DP_VOLTAGE_0_4
;
3340 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3341 signal_levels
|= DP_VOLTAGE_0_6
;
3343 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3344 signal_levels
|= DP_VOLTAGE_0_8
;
3346 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3347 signal_levels
|= DP_VOLTAGE_1_2
;
3350 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3351 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3353 signal_levels
|= DP_PRE_EMPHASIS_0
;
3355 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3356 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3358 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3359 signal_levels
|= DP_PRE_EMPHASIS_6
;
3361 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3362 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3365 return signal_levels
;
3368 /* Gen6's DP voltage swing and pre-emphasis control */
3370 gen6_edp_signal_levels(uint8_t train_set
)
3372 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3373 DP_TRAIN_PRE_EMPHASIS_MASK
);
3374 switch (signal_levels
) {
3375 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3376 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3377 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3378 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3379 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3381 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3382 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3383 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3384 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3385 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3387 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3388 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3390 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3391 "0x%x\n", signal_levels
);
3392 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3396 /* Gen7's DP voltage swing and pre-emphasis control */
3398 gen7_edp_signal_levels(uint8_t train_set
)
3400 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3401 DP_TRAIN_PRE_EMPHASIS_MASK
);
3402 switch (signal_levels
) {
3403 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3404 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3405 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3406 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3407 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3408 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3411 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3412 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3413 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3416 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3417 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3418 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3421 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3422 "0x%x\n", signal_levels
);
3423 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3427 /* Properly updates "DP" with the correct signal levels. */
3429 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3431 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3432 enum port port
= intel_dig_port
->port
;
3433 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3434 uint32_t signal_levels
, mask
= 0;
3435 uint8_t train_set
= intel_dp
->train_set
[0];
3438 signal_levels
= ddi_signal_levels(intel_dp
);
3440 if (IS_BROXTON(dev
))
3443 mask
= DDI_BUF_EMP_MASK
;
3444 } else if (IS_CHERRYVIEW(dev
)) {
3445 signal_levels
= chv_signal_levels(intel_dp
);
3446 } else if (IS_VALLEYVIEW(dev
)) {
3447 signal_levels
= vlv_signal_levels(intel_dp
);
3448 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3449 signal_levels
= gen7_edp_signal_levels(train_set
);
3450 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3451 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3452 signal_levels
= gen6_edp_signal_levels(train_set
);
3453 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3455 signal_levels
= gen4_signal_levels(train_set
);
3456 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3460 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3462 DRM_DEBUG_KMS("Using vswing level %d\n",
3463 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3464 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3465 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3466 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3468 *DP
= (*DP
& ~mask
) | signal_levels
;
3472 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3474 uint8_t dp_train_pat
)
3476 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3477 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3478 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3479 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3482 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3484 I915_WRITE(intel_dp
->output_reg
, *DP
);
3485 POSTING_READ(intel_dp
->output_reg
);
3487 buf
[0] = dp_train_pat
;
3488 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3489 DP_TRAINING_PATTERN_DISABLE
) {
3490 /* don't write DP_TRAINING_LANEx_SET on disable */
3493 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3494 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3495 len
= intel_dp
->lane_count
+ 1;
3498 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3505 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3506 uint8_t dp_train_pat
)
3508 if (!intel_dp
->train_set_valid
)
3509 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3510 intel_dp_set_signal_levels(intel_dp
, DP
);
3511 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3515 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3516 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3518 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3519 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3523 intel_get_adjust_train(intel_dp
, link_status
);
3524 intel_dp_set_signal_levels(intel_dp
, DP
);
3526 I915_WRITE(intel_dp
->output_reg
, *DP
);
3527 POSTING_READ(intel_dp
->output_reg
);
3529 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3530 intel_dp
->train_set
, intel_dp
->lane_count
);
3532 return ret
== intel_dp
->lane_count
;
3535 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3537 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3538 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3540 enum port port
= intel_dig_port
->port
;
3546 val
= I915_READ(DP_TP_CTL(port
));
3547 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3548 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3549 I915_WRITE(DP_TP_CTL(port
), val
);
3552 * On PORT_A we can have only eDP in SST mode. There the only reason
3553 * we need to set idle transmission mode is to work around a HW issue
3554 * where we enable the pipe while not in idle link-training mode.
3555 * In this case there is requirement to wait for a minimum number of
3556 * idle patterns to be sent.
3561 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3563 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3566 /* Enable corresponding port and start training pattern 1 */
3568 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3570 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3571 struct drm_device
*dev
= encoder
->dev
;
3574 int voltage_tries
, loop_tries
;
3575 uint32_t DP
= intel_dp
->DP
;
3576 uint8_t link_config
[2];
3579 intel_ddi_prepare_link_retrain(encoder
);
3581 /* Write the link configuration data */
3582 link_config
[0] = intel_dp
->link_bw
;
3583 link_config
[1] = intel_dp
->lane_count
;
3584 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3585 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3586 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3587 if (intel_dp
->num_sink_rates
)
3588 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_RATE_SET
,
3589 &intel_dp
->rate_select
, 1);
3592 link_config
[1] = DP_SET_ANSI_8B10B
;
3593 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3597 /* clock recovery */
3598 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3599 DP_TRAINING_PATTERN_1
|
3600 DP_LINK_SCRAMBLING_DISABLE
)) {
3601 DRM_ERROR("failed to enable link training\n");
3609 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3611 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3612 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3613 DRM_ERROR("failed to get link status\n");
3617 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3618 DRM_DEBUG_KMS("clock recovery OK\n");
3623 * if we used previously trained voltage and pre-emphasis values
3624 * and we don't get clock recovery, reset link training values
3626 if (intel_dp
->train_set_valid
) {
3627 DRM_DEBUG_KMS("clock recovery not ok, reset");
3628 /* clear the flag as we are not reusing train set */
3629 intel_dp
->train_set_valid
= false;
3630 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3631 DP_TRAINING_PATTERN_1
|
3632 DP_LINK_SCRAMBLING_DISABLE
)) {
3633 DRM_ERROR("failed to enable link training\n");
3639 /* Check to see if we've tried the max voltage */
3640 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3641 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3643 if (i
== intel_dp
->lane_count
) {
3645 if (loop_tries
== 5) {
3646 DRM_ERROR("too many full retries, give up\n");
3649 intel_dp_reset_link_train(intel_dp
, &DP
,
3650 DP_TRAINING_PATTERN_1
|
3651 DP_LINK_SCRAMBLING_DISABLE
);
3656 /* Check to see if we've tried the same voltage 5 times */
3657 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3659 if (voltage_tries
== 5) {
3660 DRM_ERROR("too many voltage retries, give up\n");
3665 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3667 /* Update training set as requested by target */
3668 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3669 DRM_ERROR("failed to update link training\n");
3678 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3680 bool channel_eq
= false;
3681 int tries
, cr_tries
;
3682 uint32_t DP
= intel_dp
->DP
;
3683 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3685 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3686 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3687 training_pattern
= DP_TRAINING_PATTERN_3
;
3689 /* channel equalization */
3690 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3692 DP_LINK_SCRAMBLING_DISABLE
)) {
3693 DRM_ERROR("failed to start channel equalization\n");
3701 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3704 DRM_ERROR("failed to train DP, aborting\n");
3708 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3709 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3710 DRM_ERROR("failed to get link status\n");
3714 /* Make sure clock is still ok */
3715 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3716 intel_dp
->train_set_valid
= false;
3717 intel_dp_start_link_train(intel_dp
);
3718 intel_dp_set_link_train(intel_dp
, &DP
,
3720 DP_LINK_SCRAMBLING_DISABLE
);
3725 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3730 /* Try 5 times, then try clock recovery if that fails */
3732 intel_dp
->train_set_valid
= false;
3733 intel_dp_start_link_train(intel_dp
);
3734 intel_dp_set_link_train(intel_dp
, &DP
,
3736 DP_LINK_SCRAMBLING_DISABLE
);
3742 /* Update training set as requested by target */
3743 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3744 DRM_ERROR("failed to update link training\n");
3750 intel_dp_set_idle_link_train(intel_dp
);
3755 intel_dp
->train_set_valid
= true;
3756 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3760 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3762 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3763 DP_TRAINING_PATTERN_DISABLE
);
3767 intel_dp_link_down(struct intel_dp
*intel_dp
)
3769 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3770 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3771 enum port port
= intel_dig_port
->port
;
3772 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3774 uint32_t DP
= intel_dp
->DP
;
3776 if (WARN_ON(HAS_DDI(dev
)))
3779 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3782 DRM_DEBUG_KMS("\n");
3784 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3785 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3786 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3787 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3789 if (IS_CHERRYVIEW(dev
))
3790 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3792 DP
&= ~DP_LINK_TRAIN_MASK
;
3793 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3795 I915_WRITE(intel_dp
->output_reg
, DP
);
3796 POSTING_READ(intel_dp
->output_reg
);
3798 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3799 I915_WRITE(intel_dp
->output_reg
, DP
);
3800 POSTING_READ(intel_dp
->output_reg
);
3803 * HW workaround for IBX, we need to move the port
3804 * to transcoder A after disabling it to allow the
3805 * matching HDMI port to be enabled on transcoder A.
3807 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3808 /* always enable with pattern 1 (as per spec) */
3809 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3810 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3811 I915_WRITE(intel_dp
->output_reg
, DP
);
3812 POSTING_READ(intel_dp
->output_reg
);
3815 I915_WRITE(intel_dp
->output_reg
, DP
);
3816 POSTING_READ(intel_dp
->output_reg
);
3819 msleep(intel_dp
->panel_power_down_delay
);
3823 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3825 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3826 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3830 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3831 sizeof(intel_dp
->dpcd
)) < 0)
3832 return false; /* aux transfer failed */
3834 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3836 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3837 return false; /* DPCD not present */
3839 /* Check if the panel supports PSR */
3840 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3841 if (is_edp(intel_dp
)) {
3842 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3844 sizeof(intel_dp
->psr_dpcd
));
3845 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3846 dev_priv
->psr
.sink_support
= true;
3847 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3850 if (INTEL_INFO(dev
)->gen
>= 9 &&
3851 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3852 uint8_t frame_sync_cap
;
3854 dev_priv
->psr
.sink_support
= true;
3855 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3856 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3857 &frame_sync_cap
, 1);
3858 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3859 /* PSR2 needs frame sync as well */
3860 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3861 DRM_DEBUG_KMS("PSR2 %s on sink",
3862 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3866 /* Training Pattern 3 support, both source and sink */
3867 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3868 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
&&
3869 (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)) {
3870 intel_dp
->use_tps3
= true;
3871 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3873 intel_dp
->use_tps3
= false;
3875 /* Intermediate frequency support */
3876 if (is_edp(intel_dp
) &&
3877 (intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3878 (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_EDP_DPCD_REV
, &rev
, 1) == 1) &&
3879 (rev
>= 0x03)) { /* eDp v1.4 or higher */
3880 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3883 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3884 DP_SUPPORTED_LINK_RATES
,
3886 sizeof(sink_rates
));
3888 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3889 int val
= le16_to_cpu(sink_rates
[i
]);
3894 /* Value read is in kHz while drm clock is saved in deca-kHz */
3895 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3897 intel_dp
->num_sink_rates
= i
;
3900 intel_dp_print_rates(intel_dp
);
3902 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3903 DP_DWN_STRM_PORT_PRESENT
))
3904 return true; /* native DP sink */
3906 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3907 return true; /* no per-port downstream info */
3909 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3910 intel_dp
->downstream_ports
,
3911 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3912 return false; /* downstream port status fetch failed */
3918 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3922 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3925 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3926 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3927 buf
[0], buf
[1], buf
[2]);
3929 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3930 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3931 buf
[0], buf
[1], buf
[2]);
3935 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3939 if (!intel_dp
->can_mst
)
3942 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3945 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3946 if (buf
[0] & DP_MST_CAP
) {
3947 DRM_DEBUG_KMS("Sink is MST capable\n");
3948 intel_dp
->is_mst
= true;
3950 DRM_DEBUG_KMS("Sink is not MST capable\n");
3951 intel_dp
->is_mst
= false;
3955 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3956 return intel_dp
->is_mst
;
3959 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3961 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3962 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3963 struct intel_crtc
*intel_crtc
=
3964 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3970 hsw_disable_ips(intel_crtc
);
3972 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0) {
3977 if (!(buf
& DP_TEST_CRC_SUPPORTED
)) {
3982 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3987 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3988 buf
| DP_TEST_SINK_START
) < 0) {
3993 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0) {
3998 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
4001 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4002 DP_TEST_SINK_MISC
, &buf
) < 0) {
4006 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4007 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
4009 if (attempts
== 0) {
4010 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4015 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
4020 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
4024 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4025 buf
& ~DP_TEST_SINK_START
) < 0) {
4030 hsw_enable_ips(intel_crtc
);
4035 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4037 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4038 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4039 sink_irq_vector
, 1) == 1;
4043 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4047 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4049 sink_irq_vector
, 14);
4056 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4058 uint8_t test_result
= DP_TEST_ACK
;
4062 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4064 uint8_t test_result
= DP_TEST_NAK
;
4068 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4070 uint8_t test_result
= DP_TEST_NAK
;
4071 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4072 struct drm_connector
*connector
= &intel_connector
->base
;
4074 if (intel_connector
->detect_edid
== NULL
||
4075 connector
->edid_corrupt
||
4076 intel_dp
->aux
.i2c_defer_count
> 6) {
4077 /* Check EDID read for NACKs, DEFERs and corruption
4078 * (DP CTS 1.2 Core r1.1)
4079 * 4.2.2.4 : Failed EDID read, I2C_NAK
4080 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4081 * 4.2.2.6 : EDID corruption detected
4082 * Use failsafe mode for all cases
4084 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4085 intel_dp
->aux
.i2c_defer_count
> 0)
4086 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4087 intel_dp
->aux
.i2c_nack_count
,
4088 intel_dp
->aux
.i2c_defer_count
);
4089 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
4091 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
4092 DP_TEST_EDID_CHECKSUM
,
4093 &intel_connector
->detect_edid
->checksum
,
4095 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4097 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4098 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
4101 /* Set test active flag here so userspace doesn't interrupt things */
4102 intel_dp
->compliance_test_active
= 1;
4107 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4109 uint8_t test_result
= DP_TEST_NAK
;
4113 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4115 uint8_t response
= DP_TEST_NAK
;
4119 intel_dp
->compliance_test_active
= 0;
4120 intel_dp
->compliance_test_type
= 0;
4121 intel_dp
->compliance_test_data
= 0;
4123 intel_dp
->aux
.i2c_nack_count
= 0;
4124 intel_dp
->aux
.i2c_defer_count
= 0;
4126 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
4128 DRM_DEBUG_KMS("Could not read test request from sink\n");
4133 case DP_TEST_LINK_TRAINING
:
4134 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4135 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
4136 response
= intel_dp_autotest_link_training(intel_dp
);
4138 case DP_TEST_LINK_VIDEO_PATTERN
:
4139 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4140 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
4141 response
= intel_dp_autotest_video_pattern(intel_dp
);
4143 case DP_TEST_LINK_EDID_READ
:
4144 DRM_DEBUG_KMS("EDID test requested\n");
4145 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
4146 response
= intel_dp_autotest_edid(intel_dp
);
4148 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4149 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4150 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
4151 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4154 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
4159 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
4163 DRM_DEBUG_KMS("Could not write test response to sink\n");
4167 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4171 if (intel_dp
->is_mst
) {
4176 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4180 /* check link status - esi[10] = 0x200c */
4181 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4182 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4183 intel_dp_start_link_train(intel_dp
);
4184 intel_dp_complete_link_train(intel_dp
);
4185 intel_dp_stop_link_train(intel_dp
);
4188 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4189 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4192 for (retry
= 0; retry
< 3; retry
++) {
4194 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4195 DP_SINK_COUNT_ESI
+1,
4202 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4204 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4212 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4213 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4214 intel_dp
->is_mst
= false;
4215 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4216 /* send a hotplug event */
4217 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4224 * According to DP spec
4227 * 2. Configure link according to Receiver Capabilities
4228 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4229 * 4. Check link status on receipt of hot-plug interrupt
4232 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4234 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4235 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4237 u8 link_status
[DP_LINK_STATUS_SIZE
];
4239 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4241 if (!intel_encoder
->connectors_active
)
4244 if (WARN_ON(!intel_encoder
->base
.crtc
))
4247 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4250 /* Try to read receiver status if the link appears to be up */
4251 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4255 /* Now read the DPCD to see if it's actually running */
4256 if (!intel_dp_get_dpcd(intel_dp
)) {
4260 /* Try to read the source of the interrupt */
4261 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4262 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4263 /* Clear interrupt source */
4264 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4265 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4268 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4269 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4270 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4271 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4274 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4275 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4276 intel_encoder
->base
.name
);
4277 intel_dp_start_link_train(intel_dp
);
4278 intel_dp_complete_link_train(intel_dp
);
4279 intel_dp_stop_link_train(intel_dp
);
4283 /* XXX this is probably wrong for multiple downstream ports */
4284 static enum drm_connector_status
4285 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4287 uint8_t *dpcd
= intel_dp
->dpcd
;
4290 if (!intel_dp_get_dpcd(intel_dp
))
4291 return connector_status_disconnected
;
4293 /* if there's no downstream port, we're done */
4294 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4295 return connector_status_connected
;
4297 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4298 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4299 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4302 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4304 return connector_status_unknown
;
4306 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4307 : connector_status_disconnected
;
4310 /* If no HPD, poke DDC gently */
4311 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4312 return connector_status_connected
;
4314 /* Well we tried, say unknown for unreliable port types */
4315 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4316 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4317 if (type
== DP_DS_PORT_TYPE_VGA
||
4318 type
== DP_DS_PORT_TYPE_NON_EDID
)
4319 return connector_status_unknown
;
4321 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4322 DP_DWN_STRM_PORT_TYPE_MASK
;
4323 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4324 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4325 return connector_status_unknown
;
4328 /* Anything else is out of spec, warn and ignore */
4329 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4330 return connector_status_disconnected
;
4333 static enum drm_connector_status
4334 edp_detect(struct intel_dp
*intel_dp
)
4336 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4337 enum drm_connector_status status
;
4339 status
= intel_panel_detect(dev
);
4340 if (status
== connector_status_unknown
)
4341 status
= connector_status_connected
;
4346 static enum drm_connector_status
4347 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4349 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4351 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4353 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4354 return connector_status_disconnected
;
4356 return intel_dp_detect_dpcd(intel_dp
);
4359 static int g4x_digital_port_connected(struct drm_device
*dev
,
4360 struct intel_digital_port
*intel_dig_port
)
4362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4365 if (IS_VALLEYVIEW(dev
)) {
4366 switch (intel_dig_port
->port
) {
4368 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4371 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4374 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4380 switch (intel_dig_port
->port
) {
4382 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4385 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4388 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4395 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4400 static enum drm_connector_status
4401 g4x_dp_detect(struct intel_dp
*intel_dp
)
4403 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4404 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4407 /* Can't disconnect eDP, but you can close the lid... */
4408 if (is_edp(intel_dp
)) {
4409 enum drm_connector_status status
;
4411 status
= intel_panel_detect(dev
);
4412 if (status
== connector_status_unknown
)
4413 status
= connector_status_connected
;
4417 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4419 return connector_status_unknown
;
4421 return connector_status_disconnected
;
4423 return intel_dp_detect_dpcd(intel_dp
);
4426 static struct edid
*
4427 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4429 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4431 /* use cached edid if we have one */
4432 if (intel_connector
->edid
) {
4434 if (IS_ERR(intel_connector
->edid
))
4437 return drm_edid_duplicate(intel_connector
->edid
);
4439 return drm_get_edid(&intel_connector
->base
,
4440 &intel_dp
->aux
.ddc
);
4444 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4446 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4449 edid
= intel_dp_get_edid(intel_dp
);
4450 intel_connector
->detect_edid
= edid
;
4452 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4453 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4455 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4459 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4461 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4463 kfree(intel_connector
->detect_edid
);
4464 intel_connector
->detect_edid
= NULL
;
4466 intel_dp
->has_audio
= false;
4469 static enum intel_display_power_domain
4470 intel_dp_power_get(struct intel_dp
*dp
)
4472 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4473 enum intel_display_power_domain power_domain
;
4475 power_domain
= intel_display_port_power_domain(encoder
);
4476 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4478 return power_domain
;
4482 intel_dp_power_put(struct intel_dp
*dp
,
4483 enum intel_display_power_domain power_domain
)
4485 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4486 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4489 static enum drm_connector_status
4490 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4492 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4493 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4494 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4495 struct drm_device
*dev
= connector
->dev
;
4496 enum drm_connector_status status
;
4497 enum intel_display_power_domain power_domain
;
4501 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4502 connector
->base
.id
, connector
->name
);
4503 intel_dp_unset_edid(intel_dp
);
4505 if (intel_dp
->is_mst
) {
4506 /* MST devices are disconnected from a monitor POV */
4507 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4508 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4509 return connector_status_disconnected
;
4512 power_domain
= intel_dp_power_get(intel_dp
);
4514 /* Can't disconnect eDP, but you can close the lid... */
4515 if (is_edp(intel_dp
))
4516 status
= edp_detect(intel_dp
);
4517 else if (HAS_PCH_SPLIT(dev
))
4518 status
= ironlake_dp_detect(intel_dp
);
4520 status
= g4x_dp_detect(intel_dp
);
4521 if (status
!= connector_status_connected
)
4524 intel_dp_probe_oui(intel_dp
);
4526 ret
= intel_dp_probe_mst(intel_dp
);
4528 /* if we are in MST mode then this connector
4529 won't appear connected or have anything with EDID on it */
4530 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4531 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4532 status
= connector_status_disconnected
;
4536 intel_dp_set_edid(intel_dp
);
4538 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4539 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4540 status
= connector_status_connected
;
4542 /* Try to read the source of the interrupt */
4543 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4544 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4545 /* Clear interrupt source */
4546 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4547 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4550 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4551 intel_dp_handle_test_request(intel_dp
);
4552 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4553 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4557 intel_dp_power_put(intel_dp
, power_domain
);
4562 intel_dp_force(struct drm_connector
*connector
)
4564 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4565 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4566 enum intel_display_power_domain power_domain
;
4568 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4569 connector
->base
.id
, connector
->name
);
4570 intel_dp_unset_edid(intel_dp
);
4572 if (connector
->status
!= connector_status_connected
)
4575 power_domain
= intel_dp_power_get(intel_dp
);
4577 intel_dp_set_edid(intel_dp
);
4579 intel_dp_power_put(intel_dp
, power_domain
);
4581 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4582 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4585 static int intel_dp_get_modes(struct drm_connector
*connector
)
4587 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4590 edid
= intel_connector
->detect_edid
;
4592 int ret
= intel_connector_update_modes(connector
, edid
);
4597 /* if eDP has no EDID, fall back to fixed mode */
4598 if (is_edp(intel_attached_dp(connector
)) &&
4599 intel_connector
->panel
.fixed_mode
) {
4600 struct drm_display_mode
*mode
;
4602 mode
= drm_mode_duplicate(connector
->dev
,
4603 intel_connector
->panel
.fixed_mode
);
4605 drm_mode_probed_add(connector
, mode
);
4614 intel_dp_detect_audio(struct drm_connector
*connector
)
4616 bool has_audio
= false;
4619 edid
= to_intel_connector(connector
)->detect_edid
;
4621 has_audio
= drm_detect_monitor_audio(edid
);
4627 intel_dp_set_property(struct drm_connector
*connector
,
4628 struct drm_property
*property
,
4631 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4632 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4633 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4634 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4637 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4641 if (property
== dev_priv
->force_audio_property
) {
4645 if (i
== intel_dp
->force_audio
)
4648 intel_dp
->force_audio
= i
;
4650 if (i
== HDMI_AUDIO_AUTO
)
4651 has_audio
= intel_dp_detect_audio(connector
);
4653 has_audio
= (i
== HDMI_AUDIO_ON
);
4655 if (has_audio
== intel_dp
->has_audio
)
4658 intel_dp
->has_audio
= has_audio
;
4662 if (property
== dev_priv
->broadcast_rgb_property
) {
4663 bool old_auto
= intel_dp
->color_range_auto
;
4664 uint32_t old_range
= intel_dp
->color_range
;
4667 case INTEL_BROADCAST_RGB_AUTO
:
4668 intel_dp
->color_range_auto
= true;
4670 case INTEL_BROADCAST_RGB_FULL
:
4671 intel_dp
->color_range_auto
= false;
4672 intel_dp
->color_range
= 0;
4674 case INTEL_BROADCAST_RGB_LIMITED
:
4675 intel_dp
->color_range_auto
= false;
4676 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4682 if (old_auto
== intel_dp
->color_range_auto
&&
4683 old_range
== intel_dp
->color_range
)
4689 if (is_edp(intel_dp
) &&
4690 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4691 if (val
== DRM_MODE_SCALE_NONE
) {
4692 DRM_DEBUG_KMS("no scaling not supported\n");
4696 if (intel_connector
->panel
.fitting_mode
== val
) {
4697 /* the eDP scaling property is not changed */
4700 intel_connector
->panel
.fitting_mode
= val
;
4708 if (intel_encoder
->base
.crtc
)
4709 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4715 intel_dp_connector_destroy(struct drm_connector
*connector
)
4717 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4719 kfree(intel_connector
->detect_edid
);
4721 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4722 kfree(intel_connector
->edid
);
4724 /* Can't call is_edp() since the encoder may have been destroyed
4726 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4727 intel_panel_fini(&intel_connector
->panel
);
4729 drm_connector_cleanup(connector
);
4733 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4735 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4736 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4738 drm_dp_aux_unregister(&intel_dp
->aux
);
4739 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4740 if (is_edp(intel_dp
)) {
4741 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4743 * vdd might still be enabled do to the delayed vdd off.
4744 * Make sure vdd is actually turned off here.
4747 edp_panel_vdd_off_sync(intel_dp
);
4748 pps_unlock(intel_dp
);
4750 if (intel_dp
->edp_notifier
.notifier_call
) {
4751 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4752 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4755 drm_encoder_cleanup(encoder
);
4756 kfree(intel_dig_port
);
4759 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4761 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4763 if (!is_edp(intel_dp
))
4767 * vdd might still be enabled do to the delayed vdd off.
4768 * Make sure vdd is actually turned off here.
4770 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4772 edp_panel_vdd_off_sync(intel_dp
);
4773 pps_unlock(intel_dp
);
4776 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4778 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4779 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4781 enum intel_display_power_domain power_domain
;
4783 lockdep_assert_held(&dev_priv
->pps_mutex
);
4785 if (!edp_have_panel_vdd(intel_dp
))
4789 * The VDD bit needs a power domain reference, so if the bit is
4790 * already enabled when we boot or resume, grab this reference and
4791 * schedule a vdd off, so we don't hold on to the reference
4794 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4795 power_domain
= intel_display_port_power_domain(&intel_dig_port
->base
);
4796 intel_display_power_get(dev_priv
, power_domain
);
4798 edp_panel_vdd_schedule_off(intel_dp
);
4801 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4803 struct intel_dp
*intel_dp
;
4805 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4808 intel_dp
= enc_to_intel_dp(encoder
);
4813 * Read out the current power sequencer assignment,
4814 * in case the BIOS did something with it.
4816 if (IS_VALLEYVIEW(encoder
->dev
))
4817 vlv_initial_power_sequencer_setup(intel_dp
);
4819 intel_edp_panel_vdd_sanitize(intel_dp
);
4821 pps_unlock(intel_dp
);
4824 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4825 .dpms
= intel_connector_dpms
,
4826 .detect
= intel_dp_detect
,
4827 .force
= intel_dp_force
,
4828 .fill_modes
= drm_helper_probe_single_connector_modes
,
4829 .set_property
= intel_dp_set_property
,
4830 .atomic_get_property
= intel_connector_atomic_get_property
,
4831 .destroy
= intel_dp_connector_destroy
,
4832 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4833 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4836 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4837 .get_modes
= intel_dp_get_modes
,
4838 .mode_valid
= intel_dp_mode_valid
,
4839 .best_encoder
= intel_best_encoder
,
4842 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4843 .reset
= intel_dp_encoder_reset
,
4844 .destroy
= intel_dp_encoder_destroy
,
4848 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4850 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4851 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4852 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4854 enum intel_display_power_domain power_domain
;
4855 enum irqreturn ret
= IRQ_NONE
;
4857 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4858 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4860 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4862 * vdd off can generate a long pulse on eDP which
4863 * would require vdd on to handle it, and thus we
4864 * would end up in an endless cycle of
4865 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4867 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4868 port_name(intel_dig_port
->port
));
4872 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4873 port_name(intel_dig_port
->port
),
4874 long_hpd
? "long" : "short");
4876 power_domain
= intel_display_port_power_domain(intel_encoder
);
4877 intel_display_power_get(dev_priv
, power_domain
);
4880 /* indicate that we need to restart link training */
4881 intel_dp
->train_set_valid
= false;
4883 if (HAS_PCH_SPLIT(dev
)) {
4884 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4887 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4891 if (!intel_dp_get_dpcd(intel_dp
)) {
4895 intel_dp_probe_oui(intel_dp
);
4897 if (!intel_dp_probe_mst(intel_dp
))
4901 if (intel_dp
->is_mst
) {
4902 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4906 if (!intel_dp
->is_mst
) {
4908 * we'll check the link status via the normal hot plug path later -
4909 * but for short hpds we should check it now
4911 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4912 intel_dp_check_link_status(intel_dp
);
4913 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4921 /* if we were in MST mode, and device is not there get out of MST mode */
4922 if (intel_dp
->is_mst
) {
4923 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4924 intel_dp
->is_mst
= false;
4925 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4928 intel_display_power_put(dev_priv
, power_domain
);
4933 /* Return which DP Port should be selected for Transcoder DP control */
4935 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4937 struct drm_device
*dev
= crtc
->dev
;
4938 struct intel_encoder
*intel_encoder
;
4939 struct intel_dp
*intel_dp
;
4941 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4942 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4944 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4945 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4946 return intel_dp
->output_reg
;
4952 /* check the VBT to see whether the eDP is on DP-D port */
4953 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4956 union child_device_config
*p_child
;
4958 static const short port_mapping
[] = {
4959 [PORT_B
] = PORT_IDPB
,
4960 [PORT_C
] = PORT_IDPC
,
4961 [PORT_D
] = PORT_IDPD
,
4967 if (!dev_priv
->vbt
.child_dev_num
)
4970 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4971 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4973 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4974 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4975 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4982 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4984 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4986 intel_attach_force_audio_property(connector
);
4987 intel_attach_broadcast_rgb_property(connector
);
4988 intel_dp
->color_range_auto
= true;
4990 if (is_edp(intel_dp
)) {
4991 drm_mode_create_scaling_mode_property(connector
->dev
);
4992 drm_object_attach_property(
4994 connector
->dev
->mode_config
.scaling_mode_property
,
4995 DRM_MODE_SCALE_ASPECT
);
4996 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
5000 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5002 intel_dp
->last_power_cycle
= jiffies
;
5003 intel_dp
->last_power_on
= jiffies
;
5004 intel_dp
->last_backlight_off
= jiffies
;
5008 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5009 struct intel_dp
*intel_dp
)
5011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5012 struct edp_power_seq cur
, vbt
, spec
,
5013 *final
= &intel_dp
->pps_delays
;
5014 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5015 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
= 0;
5017 lockdep_assert_held(&dev_priv
->pps_mutex
);
5019 /* already initialized? */
5020 if (final
->t11_t12
!= 0)
5023 if (IS_BROXTON(dev
)) {
5025 * TODO: BXT has 2 sets of PPS registers.
5026 * Correct Register for Broxton need to be identified
5027 * using VBT. hardcoding for now
5029 pp_ctrl_reg
= BXT_PP_CONTROL(0);
5030 pp_on_reg
= BXT_PP_ON_DELAYS(0);
5031 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
5032 } else if (HAS_PCH_SPLIT(dev
)) {
5033 pp_ctrl_reg
= PCH_PP_CONTROL
;
5034 pp_on_reg
= PCH_PP_ON_DELAYS
;
5035 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5036 pp_div_reg
= PCH_PP_DIVISOR
;
5038 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5040 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
5041 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5042 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5043 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5046 /* Workaround: Need to write PP_CONTROL with the unlock key as
5047 * the very first thing. */
5048 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5050 pp_on
= I915_READ(pp_on_reg
);
5051 pp_off
= I915_READ(pp_off_reg
);
5052 if (!IS_BROXTON(dev
)) {
5053 I915_WRITE(pp_ctrl_reg
, pp_ctl
);
5054 pp_div
= I915_READ(pp_div_reg
);
5057 /* Pull timing values out of registers */
5058 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5059 PANEL_POWER_UP_DELAY_SHIFT
;
5061 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5062 PANEL_LIGHT_ON_DELAY_SHIFT
;
5064 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5065 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5067 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5068 PANEL_POWER_DOWN_DELAY_SHIFT
;
5070 if (IS_BROXTON(dev
)) {
5071 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5072 BXT_POWER_CYCLE_DELAY_SHIFT
;
5074 cur
.t11_t12
= (tmp
- 1) * 1000;
5078 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5079 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5082 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5083 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
5085 vbt
= dev_priv
->vbt
.edp_pps
;
5087 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5088 * our hw here, which are all in 100usec. */
5089 spec
.t1_t3
= 210 * 10;
5090 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5091 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5092 spec
.t10
= 500 * 10;
5093 /* This one is special and actually in units of 100ms, but zero
5094 * based in the hw (so we need to add 100 ms). But the sw vbt
5095 * table multiplies it with 1000 to make it in units of 100usec,
5097 spec
.t11_t12
= (510 + 100) * 10;
5099 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5100 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
5102 /* Use the max of the register settings and vbt. If both are
5103 * unset, fall back to the spec limits. */
5104 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5106 max(cur.field, vbt.field))
5107 assign_final(t1_t3
);
5111 assign_final(t11_t12
);
5114 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5115 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5116 intel_dp
->backlight_on_delay
= get_delay(t8
);
5117 intel_dp
->backlight_off_delay
= get_delay(t9
);
5118 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5119 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5122 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5123 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5124 intel_dp
->panel_power_cycle_delay
);
5126 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5127 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5131 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5132 struct intel_dp
*intel_dp
)
5134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5135 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5136 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
5137 int pp_on_reg
, pp_off_reg
, pp_div_reg
= 0, pp_ctrl_reg
;
5138 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5139 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5141 lockdep_assert_held(&dev_priv
->pps_mutex
);
5143 if (IS_BROXTON(dev
)) {
5145 * TODO: BXT has 2 sets of PPS registers.
5146 * Correct Register for Broxton need to be identified
5147 * using VBT. hardcoding for now
5149 pp_ctrl_reg
= BXT_PP_CONTROL(0);
5150 pp_on_reg
= BXT_PP_ON_DELAYS(0);
5151 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
5153 } else if (HAS_PCH_SPLIT(dev
)) {
5154 pp_on_reg
= PCH_PP_ON_DELAYS
;
5155 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5156 pp_div_reg
= PCH_PP_DIVISOR
;
5158 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5160 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5161 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5162 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5166 * And finally store the new values in the power sequencer. The
5167 * backlight delays are set to 1 because we do manual waits on them. For
5168 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5169 * we'll end up waiting for the backlight off delay twice: once when we
5170 * do the manual sleep, and once when we disable the panel and wait for
5171 * the PP_STATUS bit to become zero.
5173 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5174 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
5175 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5176 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5177 /* Compute the divisor for the pp clock, simply match the Bspec
5179 if (IS_BROXTON(dev
)) {
5180 pp_div
= I915_READ(pp_ctrl_reg
);
5181 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5182 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5183 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5185 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5186 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5187 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5190 /* Haswell doesn't have any port selection bits for the panel
5191 * power sequencer any more. */
5192 if (IS_VALLEYVIEW(dev
)) {
5193 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5194 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5196 port_sel
= PANEL_PORT_SELECT_DPA
;
5198 port_sel
= PANEL_PORT_SELECT_DPD
;
5203 I915_WRITE(pp_on_reg
, pp_on
);
5204 I915_WRITE(pp_off_reg
, pp_off
);
5205 if (IS_BROXTON(dev
))
5206 I915_WRITE(pp_ctrl_reg
, pp_div
);
5208 I915_WRITE(pp_div_reg
, pp_div
);
5210 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5211 I915_READ(pp_on_reg
),
5212 I915_READ(pp_off_reg
),
5214 (I915_READ(pp_ctrl_reg
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5215 I915_READ(pp_div_reg
));
5219 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5221 * @refresh_rate: RR to be programmed
5223 * This function gets called when refresh rate (RR) has to be changed from
5224 * one frequency to another. Switches can be between high and low RR
5225 * supported by the panel or to any other RR based on media playback (in
5226 * this case, RR value needs to be passed from user space).
5228 * The caller of this function needs to take a lock on dev_priv->drrs.
5230 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5233 struct intel_encoder
*encoder
;
5234 struct intel_digital_port
*dig_port
= NULL
;
5235 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5236 struct intel_crtc_state
*config
= NULL
;
5237 struct intel_crtc
*intel_crtc
= NULL
;
5239 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5241 if (refresh_rate
<= 0) {
5242 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5246 if (intel_dp
== NULL
) {
5247 DRM_DEBUG_KMS("DRRS not supported.\n");
5252 * FIXME: This needs proper synchronization with psr state for some
5253 * platforms that cannot have PSR and DRRS enabled at the same time.
5256 dig_port
= dp_to_dig_port(intel_dp
);
5257 encoder
= &dig_port
->base
;
5258 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5261 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5265 config
= intel_crtc
->config
;
5267 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5268 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5272 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5274 index
= DRRS_LOW_RR
;
5276 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5278 "DRRS requested for previously set RR...ignoring\n");
5282 if (!intel_crtc
->active
) {
5283 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5287 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5290 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5293 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5297 DRM_ERROR("Unsupported refreshrate type\n");
5299 } else if (INTEL_INFO(dev
)->gen
> 6) {
5300 reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5301 val
= I915_READ(reg
);
5303 if (index
> DRRS_HIGH_RR
) {
5304 if (IS_VALLEYVIEW(dev
))
5305 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5307 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5309 if (IS_VALLEYVIEW(dev
))
5310 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5312 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5314 I915_WRITE(reg
, val
);
5317 dev_priv
->drrs
.refresh_rate_type
= index
;
5319 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5323 * intel_edp_drrs_enable - init drrs struct if supported
5324 * @intel_dp: DP struct
5326 * Initializes frontbuffer_bits and drrs.dp
5328 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5330 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5332 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5333 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5334 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5336 if (!intel_crtc
->config
->has_drrs
) {
5337 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5341 mutex_lock(&dev_priv
->drrs
.mutex
);
5342 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5343 DRM_ERROR("DRRS already enabled\n");
5347 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5349 dev_priv
->drrs
.dp
= intel_dp
;
5352 mutex_unlock(&dev_priv
->drrs
.mutex
);
5356 * intel_edp_drrs_disable - Disable DRRS
5357 * @intel_dp: DP struct
5360 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5362 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5364 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5365 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5366 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5368 if (!intel_crtc
->config
->has_drrs
)
5371 mutex_lock(&dev_priv
->drrs
.mutex
);
5372 if (!dev_priv
->drrs
.dp
) {
5373 mutex_unlock(&dev_priv
->drrs
.mutex
);
5377 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5378 intel_dp_set_drrs_state(dev_priv
->dev
,
5379 intel_dp
->attached_connector
->panel
.
5380 fixed_mode
->vrefresh
);
5382 dev_priv
->drrs
.dp
= NULL
;
5383 mutex_unlock(&dev_priv
->drrs
.mutex
);
5385 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5388 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5390 struct drm_i915_private
*dev_priv
=
5391 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5392 struct intel_dp
*intel_dp
;
5394 mutex_lock(&dev_priv
->drrs
.mutex
);
5396 intel_dp
= dev_priv
->drrs
.dp
;
5402 * The delayed work can race with an invalidate hence we need to
5406 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5409 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5410 intel_dp_set_drrs_state(dev_priv
->dev
,
5411 intel_dp
->attached_connector
->panel
.
5412 downclock_mode
->vrefresh
);
5415 mutex_unlock(&dev_priv
->drrs
.mutex
);
5419 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5421 * @frontbuffer_bits: frontbuffer plane tracking bits
5423 * This function gets called everytime rendering on the given planes start.
5424 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5426 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5428 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5429 unsigned frontbuffer_bits
)
5431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5432 struct drm_crtc
*crtc
;
5435 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5438 cancel_delayed_work(&dev_priv
->drrs
.work
);
5440 mutex_lock(&dev_priv
->drrs
.mutex
);
5441 if (!dev_priv
->drrs
.dp
) {
5442 mutex_unlock(&dev_priv
->drrs
.mutex
);
5446 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5447 pipe
= to_intel_crtc(crtc
)->pipe
;
5449 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5450 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5452 /* invalidate means busy screen hence upclock */
5453 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5454 intel_dp_set_drrs_state(dev_priv
->dev
,
5455 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5456 fixed_mode
->vrefresh
);
5458 mutex_unlock(&dev_priv
->drrs
.mutex
);
5462 * intel_edp_drrs_flush - Restart Idleness DRRS
5464 * @frontbuffer_bits: frontbuffer plane tracking bits
5466 * This function gets called every time rendering on the given planes has
5467 * completed or flip on a crtc is completed. So DRRS should be upclocked
5468 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5469 * if no other planes are dirty.
5471 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5473 void intel_edp_drrs_flush(struct drm_device
*dev
,
5474 unsigned frontbuffer_bits
)
5476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5477 struct drm_crtc
*crtc
;
5480 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5483 cancel_delayed_work(&dev_priv
->drrs
.work
);
5485 mutex_lock(&dev_priv
->drrs
.mutex
);
5486 if (!dev_priv
->drrs
.dp
) {
5487 mutex_unlock(&dev_priv
->drrs
.mutex
);
5491 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5492 pipe
= to_intel_crtc(crtc
)->pipe
;
5494 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5495 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5497 /* flush means busy screen hence upclock */
5498 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5499 intel_dp_set_drrs_state(dev_priv
->dev
,
5500 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5501 fixed_mode
->vrefresh
);
5504 * flush also means no more activity hence schedule downclock, if all
5505 * other fbs are quiescent too
5507 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5508 schedule_delayed_work(&dev_priv
->drrs
.work
,
5509 msecs_to_jiffies(1000));
5510 mutex_unlock(&dev_priv
->drrs
.mutex
);
5514 * DOC: Display Refresh Rate Switching (DRRS)
5516 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5517 * which enables swtching between low and high refresh rates,
5518 * dynamically, based on the usage scenario. This feature is applicable
5519 * for internal panels.
5521 * Indication that the panel supports DRRS is given by the panel EDID, which
5522 * would list multiple refresh rates for one resolution.
5524 * DRRS is of 2 types - static and seamless.
5525 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5526 * (may appear as a blink on screen) and is used in dock-undock scenario.
5527 * Seamless DRRS involves changing RR without any visual effect to the user
5528 * and can be used during normal system usage. This is done by programming
5529 * certain registers.
5531 * Support for static/seamless DRRS may be indicated in the VBT based on
5532 * inputs from the panel spec.
5534 * DRRS saves power by switching to low RR based on usage scenarios.
5537 * The implementation is based on frontbuffer tracking implementation.
5538 * When there is a disturbance on the screen triggered by user activity or a
5539 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5540 * When there is no movement on screen, after a timeout of 1 second, a switch
5541 * to low RR is made.
5542 * For integration with frontbuffer tracking code,
5543 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5545 * DRRS can be further extended to support other internal panels and also
5546 * the scenario of video playback wherein RR is set based on the rate
5547 * requested by userspace.
5551 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5552 * @intel_connector: eDP connector
5553 * @fixed_mode: preferred mode of panel
5555 * This function is called only once at driver load to initialize basic
5559 * Downclock mode if panel supports it, else return NULL.
5560 * DRRS support is determined by the presence of downclock mode (apart
5561 * from VBT setting).
5563 static struct drm_display_mode
*
5564 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5565 struct drm_display_mode
*fixed_mode
)
5567 struct drm_connector
*connector
= &intel_connector
->base
;
5568 struct drm_device
*dev
= connector
->dev
;
5569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5570 struct drm_display_mode
*downclock_mode
= NULL
;
5572 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5573 mutex_init(&dev_priv
->drrs
.mutex
);
5575 if (INTEL_INFO(dev
)->gen
<= 6) {
5576 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5580 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5581 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5585 downclock_mode
= intel_find_panel_downclock
5586 (dev
, fixed_mode
, connector
);
5588 if (!downclock_mode
) {
5589 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5593 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5595 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5596 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5597 return downclock_mode
;
5600 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5601 struct intel_connector
*intel_connector
)
5603 struct drm_connector
*connector
= &intel_connector
->base
;
5604 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5605 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5606 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5608 struct drm_display_mode
*fixed_mode
= NULL
;
5609 struct drm_display_mode
*downclock_mode
= NULL
;
5611 struct drm_display_mode
*scan
;
5613 enum pipe pipe
= INVALID_PIPE
;
5615 if (!is_edp(intel_dp
))
5619 intel_edp_panel_vdd_sanitize(intel_dp
);
5620 pps_unlock(intel_dp
);
5622 /* Cache DPCD and EDID for edp. */
5623 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5626 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5627 dev_priv
->no_aux_handshake
=
5628 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5629 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5631 /* if this fails, presume the device is a ghost */
5632 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5636 /* We now know it's not a ghost, init power sequence regs. */
5638 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5639 pps_unlock(intel_dp
);
5641 mutex_lock(&dev
->mode_config
.mutex
);
5642 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5644 if (drm_add_edid_modes(connector
, edid
)) {
5645 drm_mode_connector_update_edid_property(connector
,
5647 drm_edid_to_eld(connector
, edid
);
5650 edid
= ERR_PTR(-EINVAL
);
5653 edid
= ERR_PTR(-ENOENT
);
5655 intel_connector
->edid
= edid
;
5657 /* prefer fixed mode from EDID if available */
5658 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5659 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5660 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5661 downclock_mode
= intel_dp_drrs_init(
5662 intel_connector
, fixed_mode
);
5667 /* fallback to VBT if available for eDP */
5668 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5669 fixed_mode
= drm_mode_duplicate(dev
,
5670 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5672 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5674 mutex_unlock(&dev
->mode_config
.mutex
);
5676 if (IS_VALLEYVIEW(dev
)) {
5677 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5678 register_reboot_notifier(&intel_dp
->edp_notifier
);
5681 * Figure out the current pipe for the initial backlight setup.
5682 * If the current pipe isn't valid, try the PPS pipe, and if that
5683 * fails just assume pipe A.
5685 if (IS_CHERRYVIEW(dev
))
5686 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5688 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5690 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5691 pipe
= intel_dp
->pps_pipe
;
5693 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5696 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5700 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5701 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5702 intel_panel_setup_backlight(connector
, pipe
);
5708 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5709 struct intel_connector
*intel_connector
)
5711 struct drm_connector
*connector
= &intel_connector
->base
;
5712 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5713 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5714 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5716 enum port port
= intel_dig_port
->port
;
5719 intel_dp
->pps_pipe
= INVALID_PIPE
;
5721 /* intel_dp vfuncs */
5722 if (INTEL_INFO(dev
)->gen
>= 9)
5723 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5724 else if (IS_VALLEYVIEW(dev
))
5725 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5726 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5727 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5728 else if (HAS_PCH_SPLIT(dev
))
5729 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5731 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5733 if (INTEL_INFO(dev
)->gen
>= 9)
5734 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5736 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5738 /* Preserve the current hw state. */
5739 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5740 intel_dp
->attached_connector
= intel_connector
;
5742 if (intel_dp_is_edp(dev
, port
))
5743 type
= DRM_MODE_CONNECTOR_eDP
;
5745 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5748 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5749 * for DP the encoder type can be set by the caller to
5750 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5752 if (type
== DRM_MODE_CONNECTOR_eDP
)
5753 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5755 /* eDP only on port B and/or C on vlv/chv */
5756 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5757 port
!= PORT_B
&& port
!= PORT_C
))
5760 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5761 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5764 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5765 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5767 connector
->interlace_allowed
= true;
5768 connector
->doublescan_allowed
= 0;
5770 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5771 edp_panel_vdd_work
);
5773 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5774 drm_connector_register(connector
);
5777 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5779 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5780 intel_connector
->unregister
= intel_dp_connector_unregister
;
5782 /* Set up the hotplug pin. */
5785 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5788 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5791 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5794 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5800 if (is_edp(intel_dp
)) {
5802 intel_dp_init_panel_power_timestamps(intel_dp
);
5803 if (IS_VALLEYVIEW(dev
))
5804 vlv_initial_power_sequencer_setup(intel_dp
);
5806 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5807 pps_unlock(intel_dp
);
5810 intel_dp_aux_init(intel_dp
, intel_connector
);
5812 /* init MST on ports that can support it */
5813 if (HAS_DP_MST(dev
) &&
5814 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5815 intel_dp_mst_encoder_init(intel_dig_port
,
5816 intel_connector
->base
.base
.id
);
5818 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5819 drm_dp_aux_unregister(&intel_dp
->aux
);
5820 if (is_edp(intel_dp
)) {
5821 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5823 * vdd might still be enabled do to the delayed vdd off.
5824 * Make sure vdd is actually turned off here.
5827 edp_panel_vdd_off_sync(intel_dp
);
5828 pps_unlock(intel_dp
);
5830 drm_connector_unregister(connector
);
5831 drm_connector_cleanup(connector
);
5835 intel_dp_add_properties(intel_dp
, connector
);
5837 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5838 * 0xd. Failure to do so will result in spurious interrupts being
5839 * generated on the port when a cable is not attached.
5841 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5842 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5843 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5846 i915_debugfs_connector_add(connector
);
5852 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5855 struct intel_digital_port
*intel_dig_port
;
5856 struct intel_encoder
*intel_encoder
;
5857 struct drm_encoder
*encoder
;
5858 struct intel_connector
*intel_connector
;
5860 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5861 if (!intel_dig_port
)
5864 intel_connector
= intel_connector_alloc();
5865 if (!intel_connector
) {
5866 kfree(intel_dig_port
);
5870 intel_encoder
= &intel_dig_port
->base
;
5871 encoder
= &intel_encoder
->base
;
5873 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5874 DRM_MODE_ENCODER_TMDS
);
5876 intel_encoder
->compute_config
= intel_dp_compute_config
;
5877 intel_encoder
->disable
= intel_disable_dp
;
5878 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5879 intel_encoder
->get_config
= intel_dp_get_config
;
5880 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5881 if (IS_CHERRYVIEW(dev
)) {
5882 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5883 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5884 intel_encoder
->enable
= vlv_enable_dp
;
5885 intel_encoder
->post_disable
= chv_post_disable_dp
;
5886 } else if (IS_VALLEYVIEW(dev
)) {
5887 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5888 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5889 intel_encoder
->enable
= vlv_enable_dp
;
5890 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5892 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5893 intel_encoder
->enable
= g4x_enable_dp
;
5894 if (INTEL_INFO(dev
)->gen
>= 5)
5895 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5898 intel_dig_port
->port
= port
;
5899 intel_dig_port
->dp
.output_reg
= output_reg
;
5901 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5902 if (IS_CHERRYVIEW(dev
)) {
5904 intel_encoder
->crtc_mask
= 1 << 2;
5906 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5908 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5910 intel_encoder
->cloneable
= 0;
5912 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5913 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5915 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5916 drm_encoder_cleanup(encoder
);
5917 kfree(intel_dig_port
);
5918 kfree(intel_connector
);
5922 void intel_dp_mst_suspend(struct drm_device
*dev
)
5924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5928 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5929 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5930 if (!intel_dig_port
)
5933 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5934 if (!intel_dig_port
->dp
.can_mst
)
5936 if (intel_dig_port
->dp
.is_mst
)
5937 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5942 void intel_dp_mst_resume(struct drm_device
*dev
)
5944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5947 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5948 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5949 if (!intel_dig_port
)
5951 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5954 if (!intel_dig_port
->dp
.can_mst
)
5957 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5959 intel_dp_check_mst_status(&intel_dig_port
->dp
);