2 * Copyright © 2006-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
26 struct intel_shared_dpll
*
27 intel_get_shared_dpll_by_id(struct drm_i915_private
*dev_priv
,
28 enum intel_dpll_id id
)
30 return &dev_priv
->shared_dplls
[id
];
34 intel_get_shared_dpll_id(struct drm_i915_private
*dev_priv
,
35 struct intel_shared_dpll
*pll
)
37 if (WARN_ON(pll
< dev_priv
->shared_dplls
||
38 pll
> &dev_priv
->shared_dplls
[dev_priv
->num_shared_dpll
]))
41 return (enum intel_dpll_id
) (pll
- dev_priv
->shared_dplls
);
45 intel_shared_dpll_config_get(struct intel_shared_dpll_config
*config
,
46 struct intel_shared_dpll
*pll
,
47 struct intel_crtc
*crtc
)
49 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
50 enum intel_dpll_id id
= intel_get_shared_dpll_id(dev_priv
, pll
);
52 config
[id
].crtc_mask
|= 1 << crtc
->pipe
;
56 intel_shared_dpll_config_put(struct intel_shared_dpll_config
*config
,
57 struct intel_shared_dpll
*pll
,
58 struct intel_crtc
*crtc
)
60 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
61 enum intel_dpll_id id
= intel_get_shared_dpll_id(dev_priv
, pll
);
63 config
[id
].crtc_mask
&= ~(1 << crtc
->pipe
);
67 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
68 struct intel_shared_dpll
*pll
,
72 struct intel_dpll_hw_state hw_state
;
74 if (WARN(!pll
, "asserting DPLL %s with no DPLL\n", onoff(state
)))
77 cur_state
= pll
->funcs
.get_hw_state(dev_priv
, pll
, &hw_state
);
78 I915_STATE_WARN(cur_state
!= state
,
79 "%s assertion failure (expected %s, current %s)\n",
80 pll
->name
, onoff(state
), onoff(cur_state
));
83 void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
85 struct drm_device
*dev
= crtc
->base
.dev
;
86 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
87 struct intel_shared_dpll
*pll
= crtc
->config
->shared_dpll
;
89 if (WARN_ON(pll
== NULL
))
92 mutex_lock(&dev_priv
->dpll_lock
);
93 WARN_ON(!pll
->config
.crtc_mask
);
94 if (!pll
->active_mask
) {
95 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
97 assert_shared_dpll_disabled(dev_priv
, pll
);
99 pll
->funcs
.mode_set(dev_priv
, pll
);
101 mutex_unlock(&dev_priv
->dpll_lock
);
105 * intel_enable_shared_dpll - enable PCH PLL
106 * @dev_priv: i915 private structure
107 * @pipe: pipe PLL to enable
109 * The PCH PLL needs to be enabled before the PCH transcoder, since it
110 * drives the transcoder clock.
112 void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
114 struct drm_device
*dev
= crtc
->base
.dev
;
115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
116 struct intel_shared_dpll
*pll
= crtc
->config
->shared_dpll
;
117 unsigned crtc_mask
= 1 << drm_crtc_index(&crtc
->base
);
120 if (WARN_ON(pll
== NULL
))
123 mutex_lock(&dev_priv
->dpll_lock
);
124 old_mask
= pll
->active_mask
;
126 if (WARN_ON(!(pll
->config
.crtc_mask
& crtc_mask
)) ||
127 WARN_ON(pll
->active_mask
& crtc_mask
))
130 pll
->active_mask
|= crtc_mask
;
132 DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
133 pll
->name
, pll
->active_mask
, pll
->on
,
138 assert_shared_dpll_enabled(dev_priv
, pll
);
143 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
144 pll
->funcs
.enable(dev_priv
, pll
);
148 mutex_unlock(&dev_priv
->dpll_lock
);
151 void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
153 struct drm_device
*dev
= crtc
->base
.dev
;
154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
155 struct intel_shared_dpll
*pll
= crtc
->config
->shared_dpll
;
156 unsigned crtc_mask
= 1 << drm_crtc_index(&crtc
->base
);
158 /* PCH only available on ILK+ */
159 if (INTEL_INFO(dev
)->gen
< 5)
165 mutex_lock(&dev_priv
->dpll_lock
);
166 if (WARN_ON(!(pll
->active_mask
& crtc_mask
)))
169 DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
170 pll
->name
, pll
->active_mask
, pll
->on
,
173 assert_shared_dpll_enabled(dev_priv
, pll
);
176 pll
->active_mask
&= ~crtc_mask
;
177 if (pll
->active_mask
)
180 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
181 pll
->funcs
.disable(dev_priv
, pll
);
185 mutex_unlock(&dev_priv
->dpll_lock
);
188 static struct intel_shared_dpll
*
189 intel_find_shared_dpll(struct intel_crtc
*crtc
,
190 struct intel_crtc_state
*crtc_state
,
191 enum intel_dpll_id range_min
,
192 enum intel_dpll_id range_max
)
194 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
195 struct intel_shared_dpll
*pll
;
196 struct intel_shared_dpll_config
*shared_dpll
;
197 enum intel_dpll_id i
;
199 shared_dpll
= intel_atomic_get_shared_dpll_state(crtc_state
->base
.state
);
201 for (i
= range_min
; i
<= range_max
; i
++) {
202 pll
= &dev_priv
->shared_dplls
[i
];
204 /* Only want to check enabled timings first */
205 if (shared_dpll
[i
].crtc_mask
== 0)
208 if (memcmp(&crtc_state
->dpll_hw_state
,
209 &shared_dpll
[i
].hw_state
,
210 sizeof(crtc_state
->dpll_hw_state
)) == 0) {
211 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, active %x)\n",
212 crtc
->base
.base
.id
, pll
->name
,
213 shared_dpll
[i
].crtc_mask
,
219 /* Ok no matching timings, maybe there's a free one? */
220 for (i
= range_min
; i
<= range_max
; i
++) {
221 pll
= &dev_priv
->shared_dplls
[i
];
222 if (shared_dpll
[i
].crtc_mask
== 0) {
223 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
224 crtc
->base
.base
.id
, pll
->name
);
233 intel_reference_shared_dpll(struct intel_shared_dpll
*pll
,
234 struct intel_crtc_state
*crtc_state
)
236 struct intel_shared_dpll_config
*shared_dpll
;
237 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
238 enum intel_dpll_id i
= pll
->id
;
240 shared_dpll
= intel_atomic_get_shared_dpll_state(crtc_state
->base
.state
);
242 if (shared_dpll
[i
].crtc_mask
== 0)
243 shared_dpll
[i
].hw_state
=
244 crtc_state
->dpll_hw_state
;
246 crtc_state
->shared_dpll
= pll
;
247 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
248 pipe_name(crtc
->pipe
));
250 intel_shared_dpll_config_get(shared_dpll
, pll
, crtc
);
253 void intel_shared_dpll_commit(struct drm_atomic_state
*state
)
255 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
256 struct intel_shared_dpll_config
*shared_dpll
;
257 struct intel_shared_dpll
*pll
;
258 enum intel_dpll_id i
;
260 if (!to_intel_atomic_state(state
)->dpll_set
)
263 shared_dpll
= to_intel_atomic_state(state
)->shared_dpll
;
264 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
265 pll
= &dev_priv
->shared_dplls
[i
];
266 pll
->config
= shared_dpll
[i
];
270 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
271 struct intel_shared_dpll
*pll
,
272 struct intel_dpll_hw_state
*hw_state
)
276 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
279 val
= I915_READ(PCH_DPLL(pll
->id
));
280 hw_state
->dpll
= val
;
281 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
282 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
284 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
286 return val
& DPLL_VCO_ENABLE
;
289 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
290 struct intel_shared_dpll
*pll
)
292 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
293 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
296 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
301 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
303 val
= I915_READ(PCH_DREF_CONTROL
);
304 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
305 DREF_SUPERSPREAD_SOURCE_MASK
));
306 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
309 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
310 struct intel_shared_dpll
*pll
)
312 /* PCH refclock must be enabled first */
313 ibx_assert_pch_refclk_enabled(dev_priv
);
315 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
317 /* Wait for the clocks to stabilize. */
318 POSTING_READ(PCH_DPLL(pll
->id
));
321 /* The pixel multiplier can only be updated once the
322 * DPLL is enabled and the clocks are stable.
326 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
327 POSTING_READ(PCH_DPLL(pll
->id
));
331 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
332 struct intel_shared_dpll
*pll
)
334 struct drm_device
*dev
= dev_priv
->dev
;
335 struct intel_crtc
*crtc
;
337 /* Make sure no transcoder isn't still depending on us. */
338 for_each_intel_crtc(dev
, crtc
) {
339 if (crtc
->config
->shared_dpll
== pll
)
340 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
343 I915_WRITE(PCH_DPLL(pll
->id
), 0);
344 POSTING_READ(PCH_DPLL(pll
->id
));
348 static struct intel_shared_dpll
*
349 ibx_get_dpll(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
,
350 struct intel_encoder
*encoder
)
352 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
353 struct intel_shared_dpll
*pll
;
354 enum intel_dpll_id i
;
356 if (HAS_PCH_IBX(dev_priv
)) {
357 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
358 i
= (enum intel_dpll_id
) crtc
->pipe
;
359 pll
= &dev_priv
->shared_dplls
[i
];
361 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
362 crtc
->base
.base
.id
, pll
->name
);
364 pll
= intel_find_shared_dpll(crtc
, crtc_state
,
369 /* reference the pll */
370 intel_reference_shared_dpll(pll
, crtc_state
);
375 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs
= {
376 .mode_set
= ibx_pch_dpll_mode_set
,
377 .enable
= ibx_pch_dpll_enable
,
378 .disable
= ibx_pch_dpll_disable
,
379 .get_hw_state
= ibx_pch_dpll_get_hw_state
,
382 static void hsw_ddi_wrpll_enable(struct drm_i915_private
*dev_priv
,
383 struct intel_shared_dpll
*pll
)
385 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->config
.hw_state
.wrpll
);
386 POSTING_READ(WRPLL_CTL(pll
->id
));
390 static void hsw_ddi_spll_enable(struct drm_i915_private
*dev_priv
,
391 struct intel_shared_dpll
*pll
)
393 I915_WRITE(SPLL_CTL
, pll
->config
.hw_state
.spll
);
394 POSTING_READ(SPLL_CTL
);
398 static void hsw_ddi_wrpll_disable(struct drm_i915_private
*dev_priv
,
399 struct intel_shared_dpll
*pll
)
403 val
= I915_READ(WRPLL_CTL(pll
->id
));
404 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
405 POSTING_READ(WRPLL_CTL(pll
->id
));
408 static void hsw_ddi_spll_disable(struct drm_i915_private
*dev_priv
,
409 struct intel_shared_dpll
*pll
)
413 val
= I915_READ(SPLL_CTL
);
414 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
415 POSTING_READ(SPLL_CTL
);
418 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private
*dev_priv
,
419 struct intel_shared_dpll
*pll
,
420 struct intel_dpll_hw_state
*hw_state
)
424 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
427 val
= I915_READ(WRPLL_CTL(pll
->id
));
428 hw_state
->wrpll
= val
;
430 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
432 return val
& WRPLL_PLL_ENABLE
;
435 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private
*dev_priv
,
436 struct intel_shared_dpll
*pll
,
437 struct intel_dpll_hw_state
*hw_state
)
441 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
444 val
= I915_READ(SPLL_CTL
);
445 hw_state
->spll
= val
;
447 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
449 return val
& SPLL_PLL_ENABLE
;
452 static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll
*pll
)
456 return PORT_CLK_SEL_WRPLL1
;
458 return PORT_CLK_SEL_WRPLL2
;
460 return PORT_CLK_SEL_SPLL
;
461 case DPLL_ID_LCPLL_810
:
462 return PORT_CLK_SEL_LCPLL_810
;
463 case DPLL_ID_LCPLL_1350
:
464 return PORT_CLK_SEL_LCPLL_1350
;
465 case DPLL_ID_LCPLL_2700
:
466 return PORT_CLK_SEL_LCPLL_2700
;
468 return PORT_CLK_SEL_NONE
;
473 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
479 /* Constraints for PLL good behavior */
485 struct hsw_wrpll_rnp
{
489 static unsigned hsw_wrpll_get_budget_for_freq(int clock
)
563 static void hsw_wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
564 unsigned r2
, unsigned n2
, unsigned p
,
565 struct hsw_wrpll_rnp
*best
)
567 uint64_t a
, b
, c
, d
, diff
, diff_best
;
569 /* No best (r,n,p) yet */
578 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
582 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
585 * and we would like delta <= budget.
587 * If the discrepancy is above the PPM-based budget, always prefer to
588 * improve upon the previous solution. However, if you're within the
589 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
591 a
= freq2k
* budget
* p
* r2
;
592 b
= freq2k
* budget
* best
->p
* best
->r2
;
593 diff
= abs_diff(freq2k
* p
* r2
, LC_FREQ_2K
* n2
);
594 diff_best
= abs_diff(freq2k
* best
->p
* best
->r2
,
595 LC_FREQ_2K
* best
->n2
);
597 d
= 1000000 * diff_best
;
599 if (a
< c
&& b
< d
) {
600 /* If both are above the budget, pick the closer */
601 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
606 } else if (a
>= c
&& b
< d
) {
607 /* If A is below the threshold but B is above it? Update. */
611 } else if (a
>= c
&& b
>= d
) {
612 /* Both are below the limit, so pick the higher n2/(r2*r2) */
613 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
619 /* Otherwise a < c && b >= d, do nothing */
623 hsw_ddi_calculate_wrpll(int clock
/* in Hz */,
624 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
628 struct hsw_wrpll_rnp best
= { 0, 0, 0 };
631 freq2k
= clock
/ 100;
633 budget
= hsw_wrpll_get_budget_for_freq(clock
);
635 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
636 * and directly pass the LC PLL to it. */
637 if (freq2k
== 5400000) {
645 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
648 * We want R so that REF_MIN <= Ref <= REF_MAX.
649 * Injecting R2 = 2 * R gives:
650 * REF_MAX * r2 > LC_FREQ * 2 and
651 * REF_MIN * r2 < LC_FREQ * 2
653 * Which means the desired boundaries for r2 are:
654 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
657 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
658 r2
<= LC_FREQ
* 2 / REF_MIN
;
662 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
664 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
665 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
666 * VCO_MAX * r2 > n2 * LC_FREQ and
667 * VCO_MIN * r2 < n2 * LC_FREQ)
669 * Which means the desired boundaries for n2 are:
670 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
672 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
673 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
676 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
677 hsw_wrpll_update_rnp(freq2k
, budget
,
687 static struct intel_shared_dpll
*
688 hsw_get_dpll(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
,
689 struct intel_encoder
*encoder
)
691 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
692 struct intel_shared_dpll
*pll
;
693 int clock
= crtc_state
->port_clock
;
695 memset(&crtc_state
->dpll_hw_state
, 0,
696 sizeof(crtc_state
->dpll_hw_state
));
698 if (encoder
->type
== INTEL_OUTPUT_HDMI
) {
702 hsw_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
704 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_LCPLL
|
705 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
706 WRPLL_DIVIDER_POST(p
);
708 crtc_state
->dpll_hw_state
.wrpll
= val
;
710 pll
= intel_find_shared_dpll(crtc
, crtc_state
,
711 DPLL_ID_WRPLL1
, DPLL_ID_WRPLL2
);
713 } else if (encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
714 encoder
->type
== INTEL_OUTPUT_DP_MST
||
715 encoder
->type
== INTEL_OUTPUT_EDP
) {
716 enum intel_dpll_id pll_id
;
720 pll_id
= DPLL_ID_LCPLL_810
;
723 pll_id
= DPLL_ID_LCPLL_1350
;
726 pll_id
= DPLL_ID_LCPLL_2700
;
729 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock
);
733 pll
= intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
735 } else if (encoder
->type
== INTEL_OUTPUT_ANALOG
) {
736 if (WARN_ON(crtc_state
->port_clock
/ 2 != 135000))
739 crtc_state
->dpll_hw_state
.spll
=
740 SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
;
742 pll
= intel_find_shared_dpll(crtc
, crtc_state
,
743 DPLL_ID_SPLL
, DPLL_ID_SPLL
);
751 crtc_state
->ddi_pll_sel
= hsw_pll_to_ddi_pll_sel(pll
);
753 intel_reference_shared_dpll(pll
, crtc_state
);
759 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs
= {
760 .enable
= hsw_ddi_wrpll_enable
,
761 .disable
= hsw_ddi_wrpll_disable
,
762 .get_hw_state
= hsw_ddi_wrpll_get_hw_state
,
765 static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs
= {
766 .enable
= hsw_ddi_spll_enable
,
767 .disable
= hsw_ddi_spll_disable
,
768 .get_hw_state
= hsw_ddi_spll_get_hw_state
,
771 static void hsw_ddi_lcpll_enable(struct drm_i915_private
*dev_priv
,
772 struct intel_shared_dpll
*pll
)
776 static void hsw_ddi_lcpll_disable(struct drm_i915_private
*dev_priv
,
777 struct intel_shared_dpll
*pll
)
781 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private
*dev_priv
,
782 struct intel_shared_dpll
*pll
,
783 struct intel_dpll_hw_state
*hw_state
)
788 static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs
= {
789 .enable
= hsw_ddi_lcpll_enable
,
790 .disable
= hsw_ddi_lcpll_disable
,
791 .get_hw_state
= hsw_ddi_lcpll_get_hw_state
,
794 struct skl_dpll_regs
{
795 i915_reg_t ctl
, cfgcr1
, cfgcr2
;
798 /* this array is indexed by the *shared* pll id */
799 static const struct skl_dpll_regs skl_dpll_regs
[4] = {
803 /* DPLL 0 doesn't support HDMI mode */
808 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL1
),
809 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL1
),
814 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL2
),
815 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL2
),
820 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL3
),
821 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL3
),
825 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private
*dev_priv
,
826 struct intel_shared_dpll
*pll
)
830 val
= I915_READ(DPLL_CTRL1
);
832 val
&= ~(DPLL_CTRL1_HDMI_MODE(pll
->id
) | DPLL_CTRL1_SSC(pll
->id
) |
833 DPLL_CTRL1_LINK_RATE_MASK(pll
->id
));
834 val
|= pll
->config
.hw_state
.ctrl1
<< (pll
->id
* 6);
836 I915_WRITE(DPLL_CTRL1
, val
);
837 POSTING_READ(DPLL_CTRL1
);
840 static void skl_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
841 struct intel_shared_dpll
*pll
)
843 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
845 skl_ddi_pll_write_ctrl1(dev_priv
, pll
);
847 I915_WRITE(regs
[pll
->id
].cfgcr1
, pll
->config
.hw_state
.cfgcr1
);
848 I915_WRITE(regs
[pll
->id
].cfgcr2
, pll
->config
.hw_state
.cfgcr2
);
849 POSTING_READ(regs
[pll
->id
].cfgcr1
);
850 POSTING_READ(regs
[pll
->id
].cfgcr2
);
852 /* the enable bit is always bit 31 */
853 I915_WRITE(regs
[pll
->id
].ctl
,
854 I915_READ(regs
[pll
->id
].ctl
) | LCPLL_PLL_ENABLE
);
856 if (wait_for(I915_READ(DPLL_STATUS
) & DPLL_LOCK(pll
->id
), 5))
857 DRM_ERROR("DPLL %d not locked\n", pll
->id
);
860 static void skl_ddi_dpll0_enable(struct drm_i915_private
*dev_priv
,
861 struct intel_shared_dpll
*pll
)
863 skl_ddi_pll_write_ctrl1(dev_priv
, pll
);
866 static void skl_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
867 struct intel_shared_dpll
*pll
)
869 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
871 /* the enable bit is always bit 31 */
872 I915_WRITE(regs
[pll
->id
].ctl
,
873 I915_READ(regs
[pll
->id
].ctl
) & ~LCPLL_PLL_ENABLE
);
874 POSTING_READ(regs
[pll
->id
].ctl
);
877 static void skl_ddi_dpll0_disable(struct drm_i915_private
*dev_priv
,
878 struct intel_shared_dpll
*pll
)
882 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
883 struct intel_shared_dpll
*pll
,
884 struct intel_dpll_hw_state
*hw_state
)
887 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
890 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
895 val
= I915_READ(regs
[pll
->id
].ctl
);
896 if (!(val
& LCPLL_PLL_ENABLE
))
899 val
= I915_READ(DPLL_CTRL1
);
900 hw_state
->ctrl1
= (val
>> (pll
->id
* 6)) & 0x3f;
902 /* avoid reading back stale values if HDMI mode is not enabled */
903 if (val
& DPLL_CTRL1_HDMI_MODE(pll
->id
)) {
904 hw_state
->cfgcr1
= I915_READ(regs
[pll
->id
].cfgcr1
);
905 hw_state
->cfgcr2
= I915_READ(regs
[pll
->id
].cfgcr2
);
910 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
915 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private
*dev_priv
,
916 struct intel_shared_dpll
*pll
,
917 struct intel_dpll_hw_state
*hw_state
)
920 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
923 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
928 /* DPLL0 is always enabled since it drives CDCLK */
929 val
= I915_READ(regs
[pll
->id
].ctl
);
930 if (WARN_ON(!(val
& LCPLL_PLL_ENABLE
)))
933 val
= I915_READ(DPLL_CTRL1
);
934 hw_state
->ctrl1
= (val
>> (pll
->id
* 6)) & 0x3f;
939 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
944 struct skl_wrpll_context
{
945 uint64_t min_deviation
; /* current minimal deviation */
946 uint64_t central_freq
; /* chosen central freq */
947 uint64_t dco_freq
; /* chosen dco freq */
948 unsigned int p
; /* chosen divider */
951 static void skl_wrpll_context_init(struct skl_wrpll_context
*ctx
)
953 memset(ctx
, 0, sizeof(*ctx
));
955 ctx
->min_deviation
= U64_MAX
;
958 /* DCO freq must be within +1%/-6% of the DCO central freq */
959 #define SKL_DCO_MAX_PDEVIATION 100
960 #define SKL_DCO_MAX_NDEVIATION 600
962 static void skl_wrpll_try_divider(struct skl_wrpll_context
*ctx
,
963 uint64_t central_freq
,
965 unsigned int divider
)
969 deviation
= div64_u64(10000 * abs_diff(dco_freq
, central_freq
),
972 /* positive deviation */
973 if (dco_freq
>= central_freq
) {
974 if (deviation
< SKL_DCO_MAX_PDEVIATION
&&
975 deviation
< ctx
->min_deviation
) {
976 ctx
->min_deviation
= deviation
;
977 ctx
->central_freq
= central_freq
;
978 ctx
->dco_freq
= dco_freq
;
981 /* negative deviation */
982 } else if (deviation
< SKL_DCO_MAX_NDEVIATION
&&
983 deviation
< ctx
->min_deviation
) {
984 ctx
->min_deviation
= deviation
;
985 ctx
->central_freq
= central_freq
;
986 ctx
->dco_freq
= dco_freq
;
991 static void skl_wrpll_get_multipliers(unsigned int p
,
992 unsigned int *p0
/* out */,
993 unsigned int *p1
/* out */,
994 unsigned int *p2
/* out */)
998 unsigned int half
= p
/ 2;
1000 if (half
== 1 || half
== 2 || half
== 3 || half
== 5) {
1004 } else if (half
% 2 == 0) {
1008 } else if (half
% 3 == 0) {
1012 } else if (half
% 7 == 0) {
1017 } else if (p
== 3 || p
== 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1021 } else if (p
== 5 || p
== 7) {
1025 } else if (p
== 15) {
1029 } else if (p
== 21) {
1033 } else if (p
== 35) {
1040 struct skl_wrpll_params
{
1041 uint32_t dco_fraction
;
1042 uint32_t dco_integer
;
1043 uint32_t qdiv_ratio
;
1047 uint32_t central_freq
;
1050 static void skl_wrpll_params_populate(struct skl_wrpll_params
*params
,
1052 uint64_t central_freq
,
1053 uint32_t p0
, uint32_t p1
, uint32_t p2
)
1057 switch (central_freq
) {
1059 params
->central_freq
= 0;
1062 params
->central_freq
= 1;
1065 params
->central_freq
= 3;
1082 WARN(1, "Incorrect PDiv\n");
1099 WARN(1, "Incorrect KDiv\n");
1102 params
->qdiv_ratio
= p1
;
1103 params
->qdiv_mode
= (params
->qdiv_ratio
== 1) ? 0 : 1;
1105 dco_freq
= p0
* p1
* p2
* afe_clock
;
1108 * Intermediate values are in Hz.
1109 * Divide by MHz to match bsepc
1111 params
->dco_integer
= div_u64(dco_freq
, 24 * MHz(1));
1112 params
->dco_fraction
=
1113 div_u64((div_u64(dco_freq
, 24) -
1114 params
->dco_integer
* MHz(1)) * 0x8000, MHz(1));
1118 skl_ddi_calculate_wrpll(int clock
/* in Hz */,
1119 struct skl_wrpll_params
*wrpll_params
)
1121 uint64_t afe_clock
= clock
* 5; /* AFE Clock is 5x Pixel clock */
1122 uint64_t dco_central_freq
[3] = {8400000000ULL,
1125 static const int even_dividers
[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1126 24, 28, 30, 32, 36, 40, 42, 44,
1127 48, 52, 54, 56, 60, 64, 66, 68,
1128 70, 72, 76, 78, 80, 84, 88, 90,
1130 static const int odd_dividers
[] = { 3, 5, 7, 9, 15, 21, 35 };
1131 static const struct {
1135 { even_dividers
, ARRAY_SIZE(even_dividers
) },
1136 { odd_dividers
, ARRAY_SIZE(odd_dividers
) },
1138 struct skl_wrpll_context ctx
;
1139 unsigned int dco
, d
, i
;
1140 unsigned int p0
, p1
, p2
;
1142 skl_wrpll_context_init(&ctx
);
1144 for (d
= 0; d
< ARRAY_SIZE(dividers
); d
++) {
1145 for (dco
= 0; dco
< ARRAY_SIZE(dco_central_freq
); dco
++) {
1146 for (i
= 0; i
< dividers
[d
].n_dividers
; i
++) {
1147 unsigned int p
= dividers
[d
].list
[i
];
1148 uint64_t dco_freq
= p
* afe_clock
;
1150 skl_wrpll_try_divider(&ctx
,
1151 dco_central_freq
[dco
],
1155 * Skip the remaining dividers if we're sure to
1156 * have found the definitive divider, we can't
1157 * improve a 0 deviation.
1159 if (ctx
.min_deviation
== 0)
1160 goto skip_remaining_dividers
;
1164 skip_remaining_dividers
:
1166 * If a solution is found with an even divider, prefer
1169 if (d
== 0 && ctx
.p
)
1174 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock
);
1179 * gcc incorrectly analyses that these can be used without being
1180 * initialized. To be fair, it's hard to guess.
1183 skl_wrpll_get_multipliers(ctx
.p
, &p0
, &p1
, &p2
);
1184 skl_wrpll_params_populate(wrpll_params
, afe_clock
, ctx
.central_freq
,
1190 static struct intel_shared_dpll
*
1191 skl_get_dpll(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
,
1192 struct intel_encoder
*encoder
)
1194 struct intel_shared_dpll
*pll
;
1195 uint32_t ctrl1
, cfgcr1
, cfgcr2
;
1196 int clock
= crtc_state
->port_clock
;
1199 * See comment in intel_dpll_hw_state to understand why we always use 0
1200 * as the DPLL id in this function.
1203 ctrl1
= DPLL_CTRL1_OVERRIDE(0);
1205 if (encoder
->type
== INTEL_OUTPUT_HDMI
) {
1206 struct skl_wrpll_params wrpll_params
= { 0, };
1208 ctrl1
|= DPLL_CTRL1_HDMI_MODE(0);
1210 if (!skl_ddi_calculate_wrpll(clock
* 1000, &wrpll_params
))
1213 cfgcr1
= DPLL_CFGCR1_FREQ_ENABLE
|
1214 DPLL_CFGCR1_DCO_FRACTION(wrpll_params
.dco_fraction
) |
1215 wrpll_params
.dco_integer
;
1217 cfgcr2
= DPLL_CFGCR2_QDIV_RATIO(wrpll_params
.qdiv_ratio
) |
1218 DPLL_CFGCR2_QDIV_MODE(wrpll_params
.qdiv_mode
) |
1219 DPLL_CFGCR2_KDIV(wrpll_params
.kdiv
) |
1220 DPLL_CFGCR2_PDIV(wrpll_params
.pdiv
) |
1221 wrpll_params
.central_freq
;
1222 } else if (encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
1223 encoder
->type
== INTEL_OUTPUT_DP_MST
||
1224 encoder
->type
== INTEL_OUTPUT_EDP
) {
1225 switch (crtc_state
->port_clock
/ 2) {
1227 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, 0);
1230 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, 0);
1233 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, 0);
1237 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
, 0);
1239 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1240 results in CDCLK change. Need to handle the change of CDCLK by
1241 disabling pipes and re-enabling them */
1243 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
, 0);
1246 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
, 0);
1250 cfgcr1
= cfgcr2
= 0;
1255 memset(&crtc_state
->dpll_hw_state
, 0,
1256 sizeof(crtc_state
->dpll_hw_state
));
1258 crtc_state
->dpll_hw_state
.ctrl1
= ctrl1
;
1259 crtc_state
->dpll_hw_state
.cfgcr1
= cfgcr1
;
1260 crtc_state
->dpll_hw_state
.cfgcr2
= cfgcr2
;
1262 if (encoder
->type
== INTEL_OUTPUT_EDP
)
1263 pll
= intel_find_shared_dpll(crtc
, crtc_state
,
1267 pll
= intel_find_shared_dpll(crtc
, crtc_state
,
1273 crtc_state
->ddi_pll_sel
= pll
->id
;
1275 intel_reference_shared_dpll(pll
, crtc_state
);
1280 static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs
= {
1281 .enable
= skl_ddi_pll_enable
,
1282 .disable
= skl_ddi_pll_disable
,
1283 .get_hw_state
= skl_ddi_pll_get_hw_state
,
1286 static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs
= {
1287 .enable
= skl_ddi_dpll0_enable
,
1288 .disable
= skl_ddi_dpll0_disable
,
1289 .get_hw_state
= skl_ddi_dpll0_get_hw_state
,
1292 static void bxt_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
1293 struct intel_shared_dpll
*pll
)
1296 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
1298 /* Non-SSC reference */
1299 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
1300 temp
|= PORT_PLL_REF_SEL
;
1301 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
1303 /* Disable 10 bit clock */
1304 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
1305 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
1306 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
1309 temp
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
1310 temp
&= ~(PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
);
1311 temp
|= pll
->config
.hw_state
.ebb0
;
1312 I915_WRITE(BXT_PORT_PLL_EBB_0(port
), temp
);
1314 /* Write M2 integer */
1315 temp
= I915_READ(BXT_PORT_PLL(port
, 0));
1316 temp
&= ~PORT_PLL_M2_MASK
;
1317 temp
|= pll
->config
.hw_state
.pll0
;
1318 I915_WRITE(BXT_PORT_PLL(port
, 0), temp
);
1321 temp
= I915_READ(BXT_PORT_PLL(port
, 1));
1322 temp
&= ~PORT_PLL_N_MASK
;
1323 temp
|= pll
->config
.hw_state
.pll1
;
1324 I915_WRITE(BXT_PORT_PLL(port
, 1), temp
);
1326 /* Write M2 fraction */
1327 temp
= I915_READ(BXT_PORT_PLL(port
, 2));
1328 temp
&= ~PORT_PLL_M2_FRAC_MASK
;
1329 temp
|= pll
->config
.hw_state
.pll2
;
1330 I915_WRITE(BXT_PORT_PLL(port
, 2), temp
);
1332 /* Write M2 fraction enable */
1333 temp
= I915_READ(BXT_PORT_PLL(port
, 3));
1334 temp
&= ~PORT_PLL_M2_FRAC_ENABLE
;
1335 temp
|= pll
->config
.hw_state
.pll3
;
1336 I915_WRITE(BXT_PORT_PLL(port
, 3), temp
);
1339 temp
= I915_READ(BXT_PORT_PLL(port
, 6));
1340 temp
&= ~PORT_PLL_PROP_COEFF_MASK
;
1341 temp
&= ~PORT_PLL_INT_COEFF_MASK
;
1342 temp
&= ~PORT_PLL_GAIN_CTL_MASK
;
1343 temp
|= pll
->config
.hw_state
.pll6
;
1344 I915_WRITE(BXT_PORT_PLL(port
, 6), temp
);
1346 /* Write calibration val */
1347 temp
= I915_READ(BXT_PORT_PLL(port
, 8));
1348 temp
&= ~PORT_PLL_TARGET_CNT_MASK
;
1349 temp
|= pll
->config
.hw_state
.pll8
;
1350 I915_WRITE(BXT_PORT_PLL(port
, 8), temp
);
1352 temp
= I915_READ(BXT_PORT_PLL(port
, 9));
1353 temp
&= ~PORT_PLL_LOCK_THRESHOLD_MASK
;
1354 temp
|= pll
->config
.hw_state
.pll9
;
1355 I915_WRITE(BXT_PORT_PLL(port
, 9), temp
);
1357 temp
= I915_READ(BXT_PORT_PLL(port
, 10));
1358 temp
&= ~PORT_PLL_DCO_AMP_OVR_EN_H
;
1359 temp
&= ~PORT_PLL_DCO_AMP_MASK
;
1360 temp
|= pll
->config
.hw_state
.pll10
;
1361 I915_WRITE(BXT_PORT_PLL(port
, 10), temp
);
1363 /* Recalibrate with new settings */
1364 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
1365 temp
|= PORT_PLL_RECALIBRATE
;
1366 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
1367 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
1368 temp
|= pll
->config
.hw_state
.ebb4
;
1369 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
1372 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
1373 temp
|= PORT_PLL_ENABLE
;
1374 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
1375 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
1377 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port
)) &
1378 PORT_PLL_LOCK
), 200))
1379 DRM_ERROR("PLL %d not locked\n", port
);
1382 * While we write to the group register to program all lanes at once we
1383 * can read only lane registers and we pick lanes 0/1 for that.
1385 temp
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
1386 temp
&= ~LANE_STAGGER_MASK
;
1387 temp
&= ~LANESTAGGER_STRAP_OVRD
;
1388 temp
|= pll
->config
.hw_state
.pcsdw12
;
1389 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port
), temp
);
1392 static void bxt_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
1393 struct intel_shared_dpll
*pll
)
1395 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
1398 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
1399 temp
&= ~PORT_PLL_ENABLE
;
1400 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
1401 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
1404 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
1405 struct intel_shared_dpll
*pll
,
1406 struct intel_dpll_hw_state
*hw_state
)
1408 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
1412 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
1417 val
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
1418 if (!(val
& PORT_PLL_ENABLE
))
1421 hw_state
->ebb0
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
1422 hw_state
->ebb0
&= PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
;
1424 hw_state
->ebb4
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
1425 hw_state
->ebb4
&= PORT_PLL_10BIT_CLK_ENABLE
;
1427 hw_state
->pll0
= I915_READ(BXT_PORT_PLL(port
, 0));
1428 hw_state
->pll0
&= PORT_PLL_M2_MASK
;
1430 hw_state
->pll1
= I915_READ(BXT_PORT_PLL(port
, 1));
1431 hw_state
->pll1
&= PORT_PLL_N_MASK
;
1433 hw_state
->pll2
= I915_READ(BXT_PORT_PLL(port
, 2));
1434 hw_state
->pll2
&= PORT_PLL_M2_FRAC_MASK
;
1436 hw_state
->pll3
= I915_READ(BXT_PORT_PLL(port
, 3));
1437 hw_state
->pll3
&= PORT_PLL_M2_FRAC_ENABLE
;
1439 hw_state
->pll6
= I915_READ(BXT_PORT_PLL(port
, 6));
1440 hw_state
->pll6
&= PORT_PLL_PROP_COEFF_MASK
|
1441 PORT_PLL_INT_COEFF_MASK
|
1442 PORT_PLL_GAIN_CTL_MASK
;
1444 hw_state
->pll8
= I915_READ(BXT_PORT_PLL(port
, 8));
1445 hw_state
->pll8
&= PORT_PLL_TARGET_CNT_MASK
;
1447 hw_state
->pll9
= I915_READ(BXT_PORT_PLL(port
, 9));
1448 hw_state
->pll9
&= PORT_PLL_LOCK_THRESHOLD_MASK
;
1450 hw_state
->pll10
= I915_READ(BXT_PORT_PLL(port
, 10));
1451 hw_state
->pll10
&= PORT_PLL_DCO_AMP_OVR_EN_H
|
1452 PORT_PLL_DCO_AMP_MASK
;
1455 * While we write to the group register to program all lanes at once we
1456 * can read only lane registers. We configure all lanes the same way, so
1457 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
1459 hw_state
->pcsdw12
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
1460 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port
)) != hw_state
->pcsdw12
)
1461 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
1463 I915_READ(BXT_PORT_PCS_DW12_LN23(port
)));
1464 hw_state
->pcsdw12
&= LANE_STAGGER_MASK
| LANESTAGGER_STRAP_OVRD
;
1469 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1474 /* bxt clock parameters */
1475 struct bxt_clk_div
{
1485 /* pre-calculated values for DP linkrates */
1486 static const struct bxt_clk_div bxt_dp_clk_val
[] = {
1487 {162000, 4, 2, 32, 1677722, 1, 1},
1488 {270000, 4, 1, 27, 0, 0, 1},
1489 {540000, 2, 1, 27, 0, 0, 1},
1490 {216000, 3, 2, 32, 1677722, 1, 1},
1491 {243000, 4, 1, 24, 1258291, 1, 1},
1492 {324000, 4, 1, 32, 1677722, 1, 1},
1493 {432000, 3, 1, 32, 1677722, 1, 1}
1496 static struct intel_shared_dpll
*
1497 bxt_get_dpll(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
,
1498 struct intel_encoder
*encoder
)
1500 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1501 struct intel_shared_dpll
*pll
;
1502 enum intel_dpll_id i
;
1503 struct intel_digital_port
*intel_dig_port
;
1504 struct bxt_clk_div clk_div
= {0};
1506 uint32_t prop_coef
, int_coef
, gain_ctl
, targ_cnt
;
1507 uint32_t lanestagger
;
1508 int clock
= crtc_state
->port_clock
;
1510 if (encoder
->type
== INTEL_OUTPUT_HDMI
) {
1511 intel_clock_t best_clock
;
1513 /* Calculate HDMI div */
1515 * FIXME: tie the following calculation into
1516 * i9xx_crtc_compute_clock
1518 if (!bxt_find_best_dpll(crtc_state
, clock
, &best_clock
)) {
1519 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1520 clock
, pipe_name(crtc
->pipe
));
1524 clk_div
.p1
= best_clock
.p1
;
1525 clk_div
.p2
= best_clock
.p2
;
1526 WARN_ON(best_clock
.m1
!= 2);
1527 clk_div
.n
= best_clock
.n
;
1528 clk_div
.m2_int
= best_clock
.m2
>> 22;
1529 clk_div
.m2_frac
= best_clock
.m2
& ((1 << 22) - 1);
1530 clk_div
.m2_frac_en
= clk_div
.m2_frac
!= 0;
1532 vco
= best_clock
.vco
;
1533 } else if (encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
1534 encoder
->type
== INTEL_OUTPUT_EDP
) {
1537 clk_div
= bxt_dp_clk_val
[0];
1538 for (i
= 0; i
< ARRAY_SIZE(bxt_dp_clk_val
); ++i
) {
1539 if (bxt_dp_clk_val
[i
].clock
== clock
) {
1540 clk_div
= bxt_dp_clk_val
[i
];
1544 vco
= clock
* 10 / 2 * clk_div
.p1
* clk_div
.p2
;
1547 if (vco
>= 6200000 && vco
<= 6700000) {
1552 } else if ((vco
> 5400000 && vco
< 6200000) ||
1553 (vco
>= 4800000 && vco
< 5400000)) {
1558 } else if (vco
== 5400000) {
1564 DRM_ERROR("Invalid VCO\n");
1568 memset(&crtc_state
->dpll_hw_state
, 0,
1569 sizeof(crtc_state
->dpll_hw_state
));
1573 else if (clock
> 135000)
1575 else if (clock
> 67000)
1577 else if (clock
> 33000)
1582 crtc_state
->dpll_hw_state
.ebb0
=
1583 PORT_PLL_P1(clk_div
.p1
) | PORT_PLL_P2(clk_div
.p2
);
1584 crtc_state
->dpll_hw_state
.pll0
= clk_div
.m2_int
;
1585 crtc_state
->dpll_hw_state
.pll1
= PORT_PLL_N(clk_div
.n
);
1586 crtc_state
->dpll_hw_state
.pll2
= clk_div
.m2_frac
;
1588 if (clk_div
.m2_frac_en
)
1589 crtc_state
->dpll_hw_state
.pll3
=
1590 PORT_PLL_M2_FRAC_ENABLE
;
1592 crtc_state
->dpll_hw_state
.pll6
=
1593 prop_coef
| PORT_PLL_INT_COEFF(int_coef
);
1594 crtc_state
->dpll_hw_state
.pll6
|=
1595 PORT_PLL_GAIN_CTL(gain_ctl
);
1597 crtc_state
->dpll_hw_state
.pll8
= targ_cnt
;
1599 crtc_state
->dpll_hw_state
.pll9
= 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT
;
1601 crtc_state
->dpll_hw_state
.pll10
=
1602 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT
)
1603 | PORT_PLL_DCO_AMP_OVR_EN_H
;
1605 crtc_state
->dpll_hw_state
.ebb4
= PORT_PLL_10BIT_CLK_ENABLE
;
1607 crtc_state
->dpll_hw_state
.pcsdw12
=
1608 LANESTAGGER_STRAP_OVRD
| lanestagger
;
1610 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
1612 /* 1:1 mapping between ports and PLLs */
1613 i
= (enum intel_dpll_id
) intel_dig_port
->port
;
1614 pll
= intel_get_shared_dpll_by_id(dev_priv
, i
);
1616 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
1617 crtc
->base
.base
.id
, pll
->name
);
1619 intel_reference_shared_dpll(pll
, crtc_state
);
1621 /* shared DPLL id 0 is DPLL A */
1622 crtc_state
->ddi_pll_sel
= pll
->id
;
1627 static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs
= {
1628 .enable
= bxt_ddi_pll_enable
,
1629 .disable
= bxt_ddi_pll_disable
,
1630 .get_hw_state
= bxt_ddi_pll_get_hw_state
,
1633 static void intel_ddi_pll_init(struct drm_device
*dev
)
1635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1636 uint32_t val
= I915_READ(LCPLL_CTL
);
1638 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1641 cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
1642 dev_priv
->skl_boot_cdclk
= cdclk_freq
;
1643 if (skl_sanitize_cdclk(dev_priv
))
1644 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
1645 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
))
1646 DRM_ERROR("LCPLL1 is disabled\n");
1647 } else if (!IS_BROXTON(dev_priv
)) {
1649 * The LCPLL register should be turned on by the BIOS. For now
1650 * let's just check its state and print errors in case
1651 * something is wrong. Don't even try to turn it on.
1654 if (val
& LCPLL_CD_SOURCE_FCLK
)
1655 DRM_ERROR("CDCLK source is not LCPLL\n");
1657 if (val
& LCPLL_PLL_DISABLE
)
1658 DRM_ERROR("LCPLL is disabled\n");
1665 const struct intel_shared_dpll_funcs
*funcs
;
1669 struct intel_dpll_mgr
{
1670 const struct dpll_info
*dpll_info
;
1672 struct intel_shared_dpll
*(*get_dpll
)(struct intel_crtc
*crtc
,
1673 struct intel_crtc_state
*crtc_state
,
1674 struct intel_encoder
*encoder
);
1677 static const struct dpll_info pch_plls
[] = {
1678 { "PCH DPLL A", DPLL_ID_PCH_PLL_A
, &ibx_pch_dpll_funcs
, 0 },
1679 { "PCH DPLL B", DPLL_ID_PCH_PLL_B
, &ibx_pch_dpll_funcs
, 0 },
1680 { NULL
, -1, NULL
, 0 },
1683 static const struct intel_dpll_mgr pch_pll_mgr
= {
1684 .dpll_info
= pch_plls
,
1685 .get_dpll
= ibx_get_dpll
,
1688 static const struct dpll_info hsw_plls
[] = {
1689 { "WRPLL 1", DPLL_ID_WRPLL1
, &hsw_ddi_wrpll_funcs
, 0 },
1690 { "WRPLL 2", DPLL_ID_WRPLL2
, &hsw_ddi_wrpll_funcs
, 0 },
1691 { "SPLL", DPLL_ID_SPLL
, &hsw_ddi_spll_funcs
, 0 },
1692 { "LCPLL 810", DPLL_ID_LCPLL_810
, &hsw_ddi_lcpll_funcs
, INTEL_DPLL_ALWAYS_ON
},
1693 { "LCPLL 1350", DPLL_ID_LCPLL_1350
, &hsw_ddi_lcpll_funcs
, INTEL_DPLL_ALWAYS_ON
},
1694 { "LCPLL 2700", DPLL_ID_LCPLL_2700
, &hsw_ddi_lcpll_funcs
, INTEL_DPLL_ALWAYS_ON
},
1695 { NULL
, -1, NULL
, },
1698 static const struct intel_dpll_mgr hsw_pll_mgr
= {
1699 .dpll_info
= hsw_plls
,
1700 .get_dpll
= hsw_get_dpll
,
1703 static const struct dpll_info skl_plls
[] = {
1704 { "DPLL 0", DPLL_ID_SKL_DPLL0
, &skl_ddi_dpll0_funcs
, INTEL_DPLL_ALWAYS_ON
},
1705 { "DPLL 1", DPLL_ID_SKL_DPLL1
, &skl_ddi_pll_funcs
, 0 },
1706 { "DPLL 2", DPLL_ID_SKL_DPLL2
, &skl_ddi_pll_funcs
, 0 },
1707 { "DPLL 3", DPLL_ID_SKL_DPLL3
, &skl_ddi_pll_funcs
, 0 },
1708 { NULL
, -1, NULL
, },
1711 static const struct intel_dpll_mgr skl_pll_mgr
= {
1712 .dpll_info
= skl_plls
,
1713 .get_dpll
= skl_get_dpll
,
1716 static const struct dpll_info bxt_plls
[] = {
1717 { "PORT PLL A", DPLL_ID_SKL_DPLL0
, &bxt_ddi_pll_funcs
, 0 },
1718 { "PORT PLL B", DPLL_ID_SKL_DPLL1
, &bxt_ddi_pll_funcs
, 0 },
1719 { "PORT PLL C", DPLL_ID_SKL_DPLL2
, &bxt_ddi_pll_funcs
, 0 },
1720 { NULL
, -1, NULL
, },
1723 static const struct intel_dpll_mgr bxt_pll_mgr
= {
1724 .dpll_info
= bxt_plls
,
1725 .get_dpll
= bxt_get_dpll
,
1728 void intel_shared_dpll_init(struct drm_device
*dev
)
1730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1731 const struct intel_dpll_mgr
*dpll_mgr
= NULL
;
1732 const struct dpll_info
*dpll_info
;
1735 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
1736 dpll_mgr
= &skl_pll_mgr
;
1737 else if (IS_BROXTON(dev
))
1738 dpll_mgr
= &bxt_pll_mgr
;
1739 else if (HAS_DDI(dev
))
1740 dpll_mgr
= &hsw_pll_mgr
;
1741 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
1742 dpll_mgr
= &pch_pll_mgr
;
1745 dev_priv
->num_shared_dpll
= 0;
1749 dpll_info
= dpll_mgr
->dpll_info
;
1751 for (i
= 0; dpll_info
[i
].id
>= 0; i
++) {
1752 WARN_ON(i
!= dpll_info
[i
].id
);
1754 dev_priv
->shared_dplls
[i
].id
= dpll_info
[i
].id
;
1755 dev_priv
->shared_dplls
[i
].name
= dpll_info
[i
].name
;
1756 dev_priv
->shared_dplls
[i
].funcs
= *dpll_info
[i
].funcs
;
1757 dev_priv
->shared_dplls
[i
].flags
= dpll_info
[i
].flags
;
1760 dev_priv
->dpll_mgr
= dpll_mgr
;
1761 dev_priv
->num_shared_dpll
= i
;
1762 mutex_init(&dev_priv
->dpll_lock
);
1764 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
1766 /* FIXME: Move this to a more suitable place */
1768 intel_ddi_pll_init(dev
);
1771 struct intel_shared_dpll
*
1772 intel_get_shared_dpll(struct intel_crtc
*crtc
,
1773 struct intel_crtc_state
*crtc_state
,
1774 struct intel_encoder
*encoder
)
1776 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1777 const struct intel_dpll_mgr
*dpll_mgr
= dev_priv
->dpll_mgr
;
1779 if (WARN_ON(!dpll_mgr
))
1782 return dpll_mgr
->get_dpll(crtc
, crtc_state
, encoder
);