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286127001c43cafd45802710bf1bad1cef1c644f
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
32 #include "i915_drv.h"
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
39
40 /**
41 * _wait_for - magic (register) wait macro
42 *
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
47 */
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
50 int ret__ = 0; \
51 while (!(COND)) { \
52 if (time_after(jiffies, timeout__)) { \
53 if (!(COND)) \
54 ret__ = -ETIMEDOUT; \
55 break; \
56 } \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
59 } else { \
60 cpu_relax(); \
61 } \
62 } \
63 ret__; \
64 })
65
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
70
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
73
74 /*
75 * Display related stuff
76 */
77
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
81 #define MAX_OUTPUTS 6
82 /* maximum connectors per crtcs in the mode set */
83
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
89
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
92
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type {
96 INTEL_OUTPUT_UNUSED = 0,
97 INTEL_OUTPUT_ANALOG = 1,
98 INTEL_OUTPUT_DVO = 2,
99 INTEL_OUTPUT_SDVO = 3,
100 INTEL_OUTPUT_LVDS = 4,
101 INTEL_OUTPUT_TVOUT = 5,
102 INTEL_OUTPUT_HDMI = 6,
103 INTEL_OUTPUT_DISPLAYPORT = 7,
104 INTEL_OUTPUT_EDP = 8,
105 INTEL_OUTPUT_DSI = 9,
106 INTEL_OUTPUT_UNKNOWN = 10,
107 INTEL_OUTPUT_DP_MST = 11,
108 };
109
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
114
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
117
118 struct intel_framebuffer {
119 struct drm_framebuffer base;
120 struct drm_i915_gem_object *obj;
121 };
122
123 struct intel_fbdev {
124 struct drm_fb_helper helper;
125 struct intel_framebuffer *fb;
126 struct list_head fbdev_list;
127 struct drm_display_mode *our_mode;
128 int preferred_bpp;
129 };
130
131 struct intel_encoder {
132 struct drm_encoder base;
133 /*
134 * The new crtc this encoder will be driven from. Only differs from
135 * base->crtc while a modeset is in progress.
136 */
137 struct intel_crtc *new_crtc;
138
139 enum intel_output_type type;
140 unsigned int cloneable;
141 bool connectors_active;
142 void (*hot_plug)(struct intel_encoder *);
143 bool (*compute_config)(struct intel_encoder *,
144 struct intel_crtc_state *);
145 void (*pre_pll_enable)(struct intel_encoder *);
146 void (*pre_enable)(struct intel_encoder *);
147 void (*enable)(struct intel_encoder *);
148 void (*mode_set)(struct intel_encoder *intel_encoder);
149 void (*disable)(struct intel_encoder *);
150 void (*post_disable)(struct intel_encoder *);
151 /* Read out the current hw state of this connector, returning true if
152 * the encoder is active. If the encoder is enabled it also set the pipe
153 * it is connected to in the pipe parameter. */
154 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
155 /* Reconstructs the equivalent mode flags for the current hardware
156 * state. This must be called _after_ display->get_pipe_config has
157 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
158 * be set correctly before calling this function. */
159 void (*get_config)(struct intel_encoder *,
160 struct intel_crtc_state *pipe_config);
161 /*
162 * Called during system suspend after all pending requests for the
163 * encoder are flushed (for example for DP AUX transactions) and
164 * device interrupts are disabled.
165 */
166 void (*suspend)(struct intel_encoder *);
167 int crtc_mask;
168 enum hpd_pin hpd_pin;
169 };
170
171 struct intel_panel {
172 struct drm_display_mode *fixed_mode;
173 struct drm_display_mode *downclock_mode;
174 int fitting_mode;
175
176 /* backlight */
177 struct {
178 bool present;
179 u32 level;
180 u32 min;
181 u32 max;
182 bool enabled;
183 bool combination_mode; /* gen 2/4 only */
184 bool active_low_pwm;
185
186 /* PWM chip */
187 struct pwm_device *pwm;
188
189 struct backlight_device *device;
190 } backlight;
191
192 void (*backlight_power)(struct intel_connector *, bool enable);
193 };
194
195 struct intel_connector {
196 struct drm_connector base;
197 /*
198 * The fixed encoder this connector is connected to.
199 */
200 struct intel_encoder *encoder;
201
202 /*
203 * The new encoder this connector will be driven. Only differs from
204 * encoder while a modeset is in progress.
205 */
206 struct intel_encoder *new_encoder;
207
208 /* Reads out the current hw, returning true if the connector is enabled
209 * and active (i.e. dpms ON state). */
210 bool (*get_hw_state)(struct intel_connector *);
211
212 /*
213 * Removes all interfaces through which the connector is accessible
214 * - like sysfs, debugfs entries -, so that no new operations can be
215 * started on the connector. Also makes sure all currently pending
216 * operations finish before returing.
217 */
218 void (*unregister)(struct intel_connector *);
219
220 /* Panel info for eDP and LVDS */
221 struct intel_panel panel;
222
223 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
224 struct edid *edid;
225 struct edid *detect_edid;
226
227 /* since POLL and HPD connectors may use the same HPD line keep the native
228 state of connector->polled in case hotplug storm detection changes it */
229 u8 polled;
230
231 void *port; /* store this opaque as its illegal to dereference it */
232
233 struct intel_dp *mst_port;
234 };
235
236 typedef struct dpll {
237 /* given values */
238 int n;
239 int m1, m2;
240 int p1, p2;
241 /* derived values */
242 int dot;
243 int vco;
244 int m;
245 int p;
246 } intel_clock_t;
247
248 struct intel_plane_state {
249 struct drm_plane_state base;
250 struct drm_rect src;
251 struct drm_rect dst;
252 struct drm_rect clip;
253 bool visible;
254
255 /*
256 * scaler_id
257 * = -1 : not using a scaler
258 * >= 0 : using a scalers
259 *
260 * plane requiring a scaler:
261 * - During check_plane, its bit is set in
262 * crtc_state->scaler_state.scaler_users by calling helper function
263 * update_scaler_users.
264 * - scaler_id indicates the scaler it got assigned.
265 *
266 * plane doesn't require a scaler:
267 * - this can happen when scaling is no more required or plane simply
268 * got disabled.
269 * - During check_plane, corresponding bit is reset in
270 * crtc_state->scaler_state.scaler_users by calling helper function
271 * update_scaler_users.
272 */
273 int scaler_id;
274 };
275
276 struct intel_initial_plane_config {
277 struct intel_framebuffer *fb;
278 unsigned int tiling;
279 int size;
280 u32 base;
281 };
282
283 #define SKL_MIN_SRC_W 8
284 #define SKL_MAX_SRC_W 4096
285 #define SKL_MIN_SRC_H 8
286 #define SKL_MAX_SRC_H 4096
287 #define SKL_MIN_DST_W 8
288 #define SKL_MAX_DST_W 4096
289 #define SKL_MIN_DST_H 8
290 #define SKL_MAX_DST_H 4096
291
292 struct intel_scaler {
293 int id;
294 int in_use;
295 uint32_t mode;
296 };
297
298 struct intel_crtc_scaler_state {
299 #define SKL_NUM_SCALERS 2
300 struct intel_scaler scalers[SKL_NUM_SCALERS];
301
302 /*
303 * scaler_users: keeps track of users requesting scalers on this crtc.
304 *
305 * If a bit is set, a user is using a scaler.
306 * Here user can be a plane or crtc as defined below:
307 * bits 0-30 - plane (bit position is index from drm_plane_index)
308 * bit 31 - crtc
309 *
310 * Instead of creating a new index to cover planes and crtc, using
311 * existing drm_plane_index for planes which is well less than 31
312 * planes and bit 31 for crtc. This should be fine to cover all
313 * our platforms.
314 *
315 * intel_atomic_setup_scalers will setup available scalers to users
316 * requesting scalers. It will gracefully fail if request exceeds
317 * avilability.
318 */
319 #define SKL_CRTC_INDEX 31
320 unsigned scaler_users;
321
322 /* scaler used by crtc for panel fitting purpose */
323 int scaler_id;
324 };
325
326 struct intel_crtc_state {
327 struct drm_crtc_state base;
328
329 /**
330 * quirks - bitfield with hw state readout quirks
331 *
332 * For various reasons the hw state readout code might not be able to
333 * completely faithfully read out the current state. These cases are
334 * tracked with quirk flags so that fastboot and state checker can act
335 * accordingly.
336 */
337 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
338 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
339 unsigned long quirks;
340
341 /* Pipe source size (ie. panel fitter input size)
342 * All planes will be positioned inside this space,
343 * and get clipped at the edges. */
344 int pipe_src_w, pipe_src_h;
345
346 /* Whether to set up the PCH/FDI. Note that we never allow sharing
347 * between pch encoders and cpu encoders. */
348 bool has_pch_encoder;
349
350 /* Are we sending infoframes on the attached port */
351 bool has_infoframe;
352
353 /* CPU Transcoder for the pipe. Currently this can only differ from the
354 * pipe on Haswell (where we have a special eDP transcoder). */
355 enum transcoder cpu_transcoder;
356
357 /*
358 * Use reduced/limited/broadcast rbg range, compressing from the full
359 * range fed into the crtcs.
360 */
361 bool limited_color_range;
362
363 /* DP has a bunch of special case unfortunately, so mark the pipe
364 * accordingly. */
365 bool has_dp_encoder;
366
367 /* Whether we should send NULL infoframes. Required for audio. */
368 bool has_hdmi_sink;
369
370 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
371 * has_dp_encoder is set. */
372 bool has_audio;
373
374 /*
375 * Enable dithering, used when the selected pipe bpp doesn't match the
376 * plane bpp.
377 */
378 bool dither;
379
380 /* Controls for the clock computation, to override various stages. */
381 bool clock_set;
382
383 /* SDVO TV has a bunch of special case. To make multifunction encoders
384 * work correctly, we need to track this at runtime.*/
385 bool sdvo_tv_clock;
386
387 /*
388 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
389 * required. This is set in the 2nd loop of calling encoder's
390 * ->compute_config if the first pick doesn't work out.
391 */
392 bool bw_constrained;
393
394 /* Settings for the intel dpll used on pretty much everything but
395 * haswell. */
396 struct dpll dpll;
397
398 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
399 enum intel_dpll_id shared_dpll;
400
401 /*
402 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
403 * - enum skl_dpll on SKL
404 */
405 uint32_t ddi_pll_sel;
406
407 /* Actual register state of the dpll, for shared dpll cross-checking. */
408 struct intel_dpll_hw_state dpll_hw_state;
409
410 int pipe_bpp;
411 struct intel_link_m_n dp_m_n;
412
413 /* m2_n2 for eDP downclock */
414 struct intel_link_m_n dp_m2_n2;
415 bool has_drrs;
416
417 /*
418 * Frequence the dpll for the port should run at. Differs from the
419 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
420 * already multiplied by pixel_multiplier.
421 */
422 int port_clock;
423
424 /* Used by SDVO (and if we ever fix it, HDMI). */
425 unsigned pixel_multiplier;
426
427 /* Panel fitter controls for gen2-gen4 + VLV */
428 struct {
429 u32 control;
430 u32 pgm_ratios;
431 u32 lvds_border_bits;
432 } gmch_pfit;
433
434 /* Panel fitter placement and size for Ironlake+ */
435 struct {
436 u32 pos;
437 u32 size;
438 bool enabled;
439 bool force_thru;
440 } pch_pfit;
441
442 /* FDI configuration, only valid if has_pch_encoder is set. */
443 int fdi_lanes;
444 struct intel_link_m_n fdi_m_n;
445
446 bool ips_enabled;
447
448 bool double_wide;
449
450 bool dp_encoder_is_mst;
451 int pbn;
452
453 struct intel_crtc_scaler_state scaler_state;
454 };
455
456 struct intel_pipe_wm {
457 struct intel_wm_level wm[5];
458 uint32_t linetime;
459 bool fbc_wm_enabled;
460 bool pipe_enabled;
461 bool sprites_enabled;
462 bool sprites_scaled;
463 };
464
465 struct intel_mmio_flip {
466 struct work_struct work;
467 struct drm_i915_private *i915;
468 struct drm_i915_gem_request *req;
469 struct intel_crtc *crtc;
470 };
471
472 struct skl_pipe_wm {
473 struct skl_wm_level wm[8];
474 struct skl_wm_level trans_wm;
475 uint32_t linetime;
476 };
477
478 /*
479 * Tracking of operations that need to be performed at the beginning/end of an
480 * atomic commit, outside the atomic section where interrupts are disabled.
481 * These are generally operations that grab mutexes or might otherwise sleep
482 * and thus can't be run with interrupts disabled.
483 */
484 struct intel_crtc_atomic_commit {
485 /* vblank evasion */
486 bool evade;
487 unsigned start_vbl_count;
488
489 /* Sleepable operations to perform before commit */
490 bool wait_for_flips;
491 bool disable_fbc;
492 bool disable_ips;
493 bool pre_disable_primary;
494 bool update_wm;
495 unsigned disabled_planes;
496
497 /* Sleepable operations to perform after commit */
498 unsigned fb_bits;
499 bool wait_vblank;
500 bool update_fbc;
501 bool post_enable_primary;
502 unsigned update_sprite_watermarks;
503 };
504
505 struct intel_crtc {
506 struct drm_crtc base;
507 enum pipe pipe;
508 enum plane plane;
509 u8 lut_r[256], lut_g[256], lut_b[256];
510 /*
511 * Whether the crtc and the connected output pipeline is active. Implies
512 * that crtc->enabled is set, i.e. the current mode configuration has
513 * some outputs connected to this crtc.
514 */
515 bool active;
516 unsigned long enabled_power_domains;
517 bool lowfreq_avail;
518 struct intel_overlay *overlay;
519 struct intel_unpin_work *unpin_work;
520
521 atomic_t unpin_work_count;
522
523 /* Display surface base address adjustement for pageflips. Note that on
524 * gen4+ this only adjusts up to a tile, offsets within a tile are
525 * handled in the hw itself (with the TILEOFF register). */
526 unsigned long dspaddr_offset;
527
528 struct drm_i915_gem_object *cursor_bo;
529 uint32_t cursor_addr;
530 uint32_t cursor_cntl;
531 uint32_t cursor_size;
532 uint32_t cursor_base;
533
534 struct intel_initial_plane_config plane_config;
535 struct intel_crtc_state *config;
536 bool new_enabled;
537
538 /* reset counter value when the last flip was submitted */
539 unsigned int reset_counter;
540
541 /* Access to these should be protected by dev_priv->irq_lock. */
542 bool cpu_fifo_underrun_disabled;
543 bool pch_fifo_underrun_disabled;
544
545 /* per-pipe watermark state */
546 struct {
547 /* watermarks currently being used */
548 struct intel_pipe_wm active;
549 /* SKL wm values currently in use */
550 struct skl_pipe_wm skl_active;
551 } wm;
552
553 int scanline_offset;
554
555 struct intel_crtc_atomic_commit atomic;
556
557 /* scalers available on this crtc */
558 int num_scalers;
559 };
560
561 struct intel_plane_wm_parameters {
562 uint32_t horiz_pixels;
563 uint32_t vert_pixels;
564 /*
565 * For packed pixel formats:
566 * bytes_per_pixel - holds bytes per pixel
567 * For planar pixel formats:
568 * bytes_per_pixel - holds bytes per pixel for uv-plane
569 * y_bytes_per_pixel - holds bytes per pixel for y-plane
570 */
571 uint8_t bytes_per_pixel;
572 uint8_t y_bytes_per_pixel;
573 bool enabled;
574 bool scaled;
575 u64 tiling;
576 unsigned int rotation;
577 };
578
579 struct intel_plane {
580 struct drm_plane base;
581 int plane;
582 enum pipe pipe;
583 bool can_scale;
584 int max_downscale;
585
586 /* FIXME convert to properties */
587 struct drm_intel_sprite_colorkey ckey;
588
589 /* Since we need to change the watermarks before/after
590 * enabling/disabling the planes, we need to store the parameters here
591 * as the other pieces of the struct may not reflect the values we want
592 * for the watermark calculations. Currently only Haswell uses this.
593 */
594 struct intel_plane_wm_parameters wm;
595
596 /*
597 * NOTE: Do not place new plane state fields here (e.g., when adding
598 * new plane properties). New runtime state should now be placed in
599 * the intel_plane_state structure and accessed via drm_plane->state.
600 */
601
602 void (*update_plane)(struct drm_plane *plane,
603 struct drm_crtc *crtc,
604 struct drm_framebuffer *fb,
605 int crtc_x, int crtc_y,
606 unsigned int crtc_w, unsigned int crtc_h,
607 uint32_t x, uint32_t y,
608 uint32_t src_w, uint32_t src_h);
609 void (*disable_plane)(struct drm_plane *plane,
610 struct drm_crtc *crtc, bool force);
611 int (*check_plane)(struct drm_plane *plane,
612 struct intel_plane_state *state);
613 void (*commit_plane)(struct drm_plane *plane,
614 struct intel_plane_state *state);
615 };
616
617 struct intel_watermark_params {
618 unsigned long fifo_size;
619 unsigned long max_wm;
620 unsigned long default_wm;
621 unsigned long guard_size;
622 unsigned long cacheline_size;
623 };
624
625 struct cxsr_latency {
626 int is_desktop;
627 int is_ddr3;
628 unsigned long fsb_freq;
629 unsigned long mem_freq;
630 unsigned long display_sr;
631 unsigned long display_hpll_disable;
632 unsigned long cursor_sr;
633 unsigned long cursor_hpll_disable;
634 };
635
636 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
637 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
638 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
639 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
640 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
641 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
642 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
643 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
644
645 struct intel_hdmi {
646 u32 hdmi_reg;
647 int ddc_bus;
648 uint32_t color_range;
649 bool color_range_auto;
650 bool has_hdmi_sink;
651 bool has_audio;
652 enum hdmi_force_audio force_audio;
653 bool rgb_quant_range_selectable;
654 enum hdmi_picture_aspect aspect_ratio;
655 void (*write_infoframe)(struct drm_encoder *encoder,
656 enum hdmi_infoframe_type type,
657 const void *frame, ssize_t len);
658 void (*set_infoframes)(struct drm_encoder *encoder,
659 bool enable,
660 struct drm_display_mode *adjusted_mode);
661 bool (*infoframe_enabled)(struct drm_encoder *encoder);
662 };
663
664 struct intel_dp_mst_encoder;
665 #define DP_MAX_DOWNSTREAM_PORTS 0x10
666
667 /*
668 * enum link_m_n_set:
669 * When platform provides two set of M_N registers for dp, we can
670 * program them and switch between them incase of DRRS.
671 * But When only one such register is provided, we have to program the
672 * required divider value on that registers itself based on the DRRS state.
673 *
674 * M1_N1 : Program dp_m_n on M1_N1 registers
675 * dp_m2_n2 on M2_N2 registers (If supported)
676 *
677 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
678 * M2_N2 registers are not supported
679 */
680
681 enum link_m_n_set {
682 /* Sets the m1_n1 and m2_n2 */
683 M1_N1 = 0,
684 M2_N2
685 };
686
687 struct intel_dp {
688 uint32_t output_reg;
689 uint32_t aux_ch_ctl_reg;
690 uint32_t DP;
691 bool has_audio;
692 enum hdmi_force_audio force_audio;
693 uint32_t color_range;
694 bool color_range_auto;
695 uint8_t link_bw;
696 uint8_t rate_select;
697 uint8_t lane_count;
698 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
699 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
700 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
701 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
702 uint8_t num_sink_rates;
703 int sink_rates[DP_MAX_SUPPORTED_RATES];
704 struct drm_dp_aux aux;
705 uint8_t train_set[4];
706 int panel_power_up_delay;
707 int panel_power_down_delay;
708 int panel_power_cycle_delay;
709 int backlight_on_delay;
710 int backlight_off_delay;
711 struct delayed_work panel_vdd_work;
712 bool want_panel_vdd;
713 unsigned long last_power_cycle;
714 unsigned long last_power_on;
715 unsigned long last_backlight_off;
716
717 struct notifier_block edp_notifier;
718
719 /*
720 * Pipe whose power sequencer is currently locked into
721 * this port. Only relevant on VLV/CHV.
722 */
723 enum pipe pps_pipe;
724 struct edp_power_seq pps_delays;
725
726 bool use_tps3;
727 bool can_mst; /* this port supports mst */
728 bool is_mst;
729 int active_mst_links;
730 /* connector directly attached - won't be use for modeset in mst world */
731 struct intel_connector *attached_connector;
732
733 /* mst connector list */
734 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
735 struct drm_dp_mst_topology_mgr mst_mgr;
736
737 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
738 /*
739 * This function returns the value we have to program the AUX_CTL
740 * register with to kick off an AUX transaction.
741 */
742 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
743 bool has_aux_irq,
744 int send_bytes,
745 uint32_t aux_clock_divider);
746 bool train_set_valid;
747
748 /* Displayport compliance testing */
749 unsigned long compliance_test_type;
750 unsigned long compliance_test_data;
751 bool compliance_test_active;
752 };
753
754 struct intel_digital_port {
755 struct intel_encoder base;
756 enum port port;
757 u32 saved_port_bits;
758 struct intel_dp dp;
759 struct intel_hdmi hdmi;
760 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
761 };
762
763 struct intel_dp_mst_encoder {
764 struct intel_encoder base;
765 enum pipe pipe;
766 struct intel_digital_port *primary;
767 void *port; /* store this opaque as its illegal to dereference it */
768 };
769
770 static inline int
771 vlv_dport_to_channel(struct intel_digital_port *dport)
772 {
773 switch (dport->port) {
774 case PORT_B:
775 case PORT_D:
776 return DPIO_CH0;
777 case PORT_C:
778 return DPIO_CH1;
779 default:
780 BUG();
781 }
782 }
783
784 static inline int
785 vlv_pipe_to_channel(enum pipe pipe)
786 {
787 switch (pipe) {
788 case PIPE_A:
789 case PIPE_C:
790 return DPIO_CH0;
791 case PIPE_B:
792 return DPIO_CH1;
793 default:
794 BUG();
795 }
796 }
797
798 static inline struct drm_crtc *
799 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
800 {
801 struct drm_i915_private *dev_priv = dev->dev_private;
802 return dev_priv->pipe_to_crtc_mapping[pipe];
803 }
804
805 static inline struct drm_crtc *
806 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
807 {
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 return dev_priv->plane_to_crtc_mapping[plane];
810 }
811
812 struct intel_unpin_work {
813 struct work_struct work;
814 struct drm_crtc *crtc;
815 struct drm_framebuffer *old_fb;
816 struct drm_i915_gem_object *pending_flip_obj;
817 struct drm_pending_vblank_event *event;
818 atomic_t pending;
819 #define INTEL_FLIP_INACTIVE 0
820 #define INTEL_FLIP_PENDING 1
821 #define INTEL_FLIP_COMPLETE 2
822 u32 flip_count;
823 u32 gtt_offset;
824 struct drm_i915_gem_request *flip_queued_req;
825 int flip_queued_vblank;
826 int flip_ready_vblank;
827 bool enable_stall_check;
828 };
829
830 struct intel_load_detect_pipe {
831 struct drm_framebuffer *release_fb;
832 bool load_detect_temp;
833 int dpms_mode;
834 };
835
836 static inline struct intel_encoder *
837 intel_attached_encoder(struct drm_connector *connector)
838 {
839 return to_intel_connector(connector)->encoder;
840 }
841
842 static inline struct intel_digital_port *
843 enc_to_dig_port(struct drm_encoder *encoder)
844 {
845 return container_of(encoder, struct intel_digital_port, base.base);
846 }
847
848 static inline struct intel_dp_mst_encoder *
849 enc_to_mst(struct drm_encoder *encoder)
850 {
851 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
852 }
853
854 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
855 {
856 return &enc_to_dig_port(encoder)->dp;
857 }
858
859 static inline struct intel_digital_port *
860 dp_to_dig_port(struct intel_dp *intel_dp)
861 {
862 return container_of(intel_dp, struct intel_digital_port, dp);
863 }
864
865 static inline struct intel_digital_port *
866 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
867 {
868 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
869 }
870
871 /*
872 * Returns the number of planes for this pipe, ie the number of sprites + 1
873 * (primary plane). This doesn't count the cursor plane then.
874 */
875 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
876 {
877 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
878 }
879
880 /* intel_fifo_underrun.c */
881 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
882 enum pipe pipe, bool enable);
883 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
884 enum transcoder pch_transcoder,
885 bool enable);
886 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
887 enum pipe pipe);
888 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
889 enum transcoder pch_transcoder);
890 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
891
892 /* i915_irq.c */
893 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
894 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
895 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
896 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
897 void gen6_reset_rps_interrupts(struct drm_device *dev);
898 void gen6_enable_rps_interrupts(struct drm_device *dev);
899 void gen6_disable_rps_interrupts(struct drm_device *dev);
900 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
901 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
902 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
903 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
904 {
905 /*
906 * We only use drm_irq_uninstall() at unload and VT switch, so
907 * this is the only thing we need to check.
908 */
909 return dev_priv->pm.irqs_enabled;
910 }
911
912 int intel_get_crtc_scanline(struct intel_crtc *crtc);
913 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
914 unsigned int pipe_mask);
915
916 /* intel_crt.c */
917 void intel_crt_init(struct drm_device *dev);
918
919
920 /* intel_ddi.c */
921 void intel_prepare_ddi(struct drm_device *dev);
922 void hsw_fdi_link_train(struct drm_crtc *crtc);
923 void intel_ddi_init(struct drm_device *dev, enum port port);
924 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
925 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
926 void intel_ddi_pll_init(struct drm_device *dev);
927 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
928 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
929 enum transcoder cpu_transcoder);
930 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
931 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
932 bool intel_ddi_pll_select(struct intel_crtc *crtc,
933 struct intel_crtc_state *crtc_state);
934 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
935 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
936 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
937 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
938 void intel_ddi_get_config(struct intel_encoder *encoder,
939 struct intel_crtc_state *pipe_config);
940 struct intel_encoder *
941 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
942
943 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
944 void intel_ddi_clock_get(struct intel_encoder *encoder,
945 struct intel_crtc_state *pipe_config);
946 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
947 void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
948 enum port port, int type);
949
950 /* intel_frontbuffer.c */
951 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
952 struct intel_engine_cs *ring,
953 enum fb_op_origin origin);
954 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
955 unsigned frontbuffer_bits);
956 void intel_frontbuffer_flip_complete(struct drm_device *dev,
957 unsigned frontbuffer_bits);
958 void intel_frontbuffer_flush(struct drm_device *dev,
959 unsigned frontbuffer_bits);
960 /**
961 * intel_frontbuffer_flip - synchronous frontbuffer flip
962 * @dev: DRM device
963 * @frontbuffer_bits: frontbuffer plane tracking bits
964 *
965 * This function gets called after scheduling a flip on @obj. This is for
966 * synchronous plane updates which will happen on the next vblank and which will
967 * not get delayed by pending gpu rendering.
968 *
969 * Can be called without any locks held.
970 */
971 static inline
972 void intel_frontbuffer_flip(struct drm_device *dev,
973 unsigned frontbuffer_bits)
974 {
975 intel_frontbuffer_flush(dev, frontbuffer_bits);
976 }
977
978 unsigned int intel_fb_align_height(struct drm_device *dev,
979 unsigned int height,
980 uint32_t pixel_format,
981 uint64_t fb_format_modifier);
982 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
983
984 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
985 uint32_t pixel_format);
986
987 /* intel_audio.c */
988 void intel_init_audio(struct drm_device *dev);
989 void intel_audio_codec_enable(struct intel_encoder *encoder);
990 void intel_audio_codec_disable(struct intel_encoder *encoder);
991 void i915_audio_component_init(struct drm_i915_private *dev_priv);
992 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
993
994 /* intel_display.c */
995 extern const struct drm_plane_funcs intel_plane_funcs;
996 bool intel_has_pending_fb_unpin(struct drm_device *dev);
997 int intel_pch_rawclk(struct drm_device *dev);
998 void intel_mark_busy(struct drm_device *dev);
999 void intel_mark_idle(struct drm_device *dev);
1000 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1001 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
1002 void intel_crtc_reset(struct intel_crtc *crtc);
1003 void intel_crtc_update_dpms(struct drm_crtc *crtc);
1004 void intel_encoder_destroy(struct drm_encoder *encoder);
1005 int intel_connector_init(struct intel_connector *);
1006 struct intel_connector *intel_connector_alloc(void);
1007 void intel_connector_dpms(struct drm_connector *, int mode);
1008 bool intel_connector_get_hw_state(struct intel_connector *connector);
1009 void intel_modeset_check_state(struct drm_device *dev);
1010 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1011 struct intel_digital_port *port);
1012 void intel_connector_attach_encoder(struct intel_connector *connector,
1013 struct intel_encoder *encoder);
1014 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1015 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1016 struct drm_crtc *crtc);
1017 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1018 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1019 struct drm_file *file_priv);
1020 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1021 enum pipe pipe);
1022 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1023 static inline void
1024 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1025 {
1026 drm_wait_one_vblank(dev, pipe);
1027 }
1028 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1029 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1030 struct intel_digital_port *dport,
1031 unsigned int expected_mask);
1032 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1033 struct drm_display_mode *mode,
1034 struct intel_load_detect_pipe *old,
1035 struct drm_modeset_acquire_ctx *ctx);
1036 void intel_release_load_detect_pipe(struct drm_connector *connector,
1037 struct intel_load_detect_pipe *old,
1038 struct drm_modeset_acquire_ctx *ctx);
1039 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1040 struct drm_framebuffer *fb,
1041 const struct drm_plane_state *plane_state,
1042 struct intel_engine_cs *pipelined);
1043 struct drm_framebuffer *
1044 __intel_framebuffer_create(struct drm_device *dev,
1045 struct drm_mode_fb_cmd2 *mode_cmd,
1046 struct drm_i915_gem_object *obj);
1047 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1048 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1049 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1050 void intel_check_page_flip(struct drm_device *dev, int pipe);
1051 int intel_prepare_plane_fb(struct drm_plane *plane,
1052 struct drm_framebuffer *fb,
1053 const struct drm_plane_state *new_state);
1054 void intel_cleanup_plane_fb(struct drm_plane *plane,
1055 struct drm_framebuffer *fb,
1056 const struct drm_plane_state *old_state);
1057 int intel_plane_atomic_get_property(struct drm_plane *plane,
1058 const struct drm_plane_state *state,
1059 struct drm_property *property,
1060 uint64_t *val);
1061 int intel_plane_atomic_set_property(struct drm_plane *plane,
1062 struct drm_plane_state *state,
1063 struct drm_property *property,
1064 uint64_t val);
1065
1066 unsigned int
1067 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1068 uint64_t fb_format_modifier);
1069
1070 static inline bool
1071 intel_rotation_90_or_270(unsigned int rotation)
1072 {
1073 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1074 }
1075
1076 void intel_create_rotation_property(struct drm_device *dev,
1077 struct intel_plane *plane);
1078
1079 bool intel_wm_need_update(struct drm_plane *plane,
1080 struct drm_plane_state *state);
1081
1082 /* shared dpll functions */
1083 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1084 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1085 struct intel_shared_dpll *pll,
1086 bool state);
1087 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1088 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1089 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1090 struct intel_crtc_state *state);
1091 void intel_put_shared_dpll(struct intel_crtc *crtc);
1092
1093 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1094 const struct dpll *dpll);
1095 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1096
1097 /* modesetting asserts */
1098 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1099 enum pipe pipe);
1100 void assert_pll(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state);
1102 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1103 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1104 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1105 enum pipe pipe, bool state);
1106 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1107 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1108 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1109 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1110 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1111 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1112 unsigned int tiling_mode,
1113 unsigned int bpp,
1114 unsigned int pitch);
1115 void intel_prepare_reset(struct drm_device *dev);
1116 void intel_finish_reset(struct drm_device *dev);
1117 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1118 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1119 void broxton_init_cdclk(struct drm_device *dev);
1120 void broxton_uninit_cdclk(struct drm_device *dev);
1121 void broxton_set_cdclk(struct drm_device *dev, int frequency);
1122 void broxton_ddi_phy_init(struct drm_device *dev);
1123 void broxton_ddi_phy_uninit(struct drm_device *dev);
1124 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1125 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1126 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1127 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1128 void intel_dp_get_m_n(struct intel_crtc *crtc,
1129 struct intel_crtc_state *pipe_config);
1130 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1131 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1132 void
1133 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1134 int dotclock);
1135 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1136 intel_clock_t *best_clock);
1137 bool intel_crtc_active(struct drm_crtc *crtc);
1138 void hsw_enable_ips(struct intel_crtc *crtc);
1139 void hsw_disable_ips(struct intel_crtc *crtc);
1140 enum intel_display_power_domain
1141 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1142 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1143 struct intel_crtc_state *pipe_config);
1144 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1145 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1146 void skl_detach_scalers(struct intel_crtc *intel_crtc);
1147 int skl_update_scaler_users(struct intel_crtc *intel_crtc,
1148 struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane,
1149 struct intel_plane_state *plane_state, int force_detach);
1150 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1151
1152 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1153 struct drm_i915_gem_object *obj);
1154 u32 skl_plane_ctl_format(uint32_t pixel_format);
1155 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1156 u32 skl_plane_ctl_rotation(unsigned int rotation);
1157
1158 /* intel_csr.c */
1159 void intel_csr_ucode_init(struct drm_device *dev);
1160 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1161 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1162 enum csr_state state);
1163 void intel_csr_load_program(struct drm_device *dev);
1164 void intel_csr_ucode_fini(struct drm_device *dev);
1165 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1166
1167 /* intel_dp.c */
1168 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1169 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1170 struct intel_connector *intel_connector);
1171 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1172 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1173 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1174 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1175 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1176 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1177 bool intel_dp_compute_config(struct intel_encoder *encoder,
1178 struct intel_crtc_state *pipe_config);
1179 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1180 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1181 bool long_hpd);
1182 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1183 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1184 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1185 void intel_edp_panel_on(struct intel_dp *intel_dp);
1186 void intel_edp_panel_off(struct intel_dp *intel_dp);
1187 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1188 void intel_dp_mst_suspend(struct drm_device *dev);
1189 void intel_dp_mst_resume(struct drm_device *dev);
1190 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1191 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1192 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1193 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1194 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1195 void intel_plane_destroy(struct drm_plane *plane);
1196 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1197 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1198 void intel_edp_drrs_invalidate(struct drm_device *dev,
1199 unsigned frontbuffer_bits);
1200 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1201
1202 /* intel_dp_mst.c */
1203 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1204 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1205 /* intel_dsi.c */
1206 void intel_dsi_init(struct drm_device *dev);
1207
1208
1209 /* intel_dvo.c */
1210 void intel_dvo_init(struct drm_device *dev);
1211
1212
1213 /* legacy fbdev emulation in intel_fbdev.c */
1214 #ifdef CONFIG_DRM_I915_FBDEV
1215 extern int intel_fbdev_init(struct drm_device *dev);
1216 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1217 extern void intel_fbdev_fini(struct drm_device *dev);
1218 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1219 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1220 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1221 #else
1222 static inline int intel_fbdev_init(struct drm_device *dev)
1223 {
1224 return 0;
1225 }
1226
1227 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1228 {
1229 }
1230
1231 static inline void intel_fbdev_fini(struct drm_device *dev)
1232 {
1233 }
1234
1235 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1236 {
1237 }
1238
1239 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1240 {
1241 }
1242 #endif
1243
1244 /* intel_fbc.c */
1245 bool intel_fbc_enabled(struct drm_device *dev);
1246 void intel_fbc_update(struct drm_device *dev);
1247 void intel_fbc_init(struct drm_i915_private *dev_priv);
1248 void intel_fbc_disable(struct drm_device *dev);
1249 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1250 unsigned int frontbuffer_bits,
1251 enum fb_op_origin origin);
1252 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1253 unsigned int frontbuffer_bits);
1254
1255 /* intel_hdmi.c */
1256 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1257 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1258 struct intel_connector *intel_connector);
1259 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1260 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1261 struct intel_crtc_state *pipe_config);
1262
1263
1264 /* intel_lvds.c */
1265 void intel_lvds_init(struct drm_device *dev);
1266 bool intel_is_dual_link_lvds(struct drm_device *dev);
1267
1268
1269 /* intel_modes.c */
1270 int intel_connector_update_modes(struct drm_connector *connector,
1271 struct edid *edid);
1272 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1273 void intel_attach_force_audio_property(struct drm_connector *connector);
1274 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1275
1276
1277 /* intel_overlay.c */
1278 void intel_setup_overlay(struct drm_device *dev);
1279 void intel_cleanup_overlay(struct drm_device *dev);
1280 int intel_overlay_switch_off(struct intel_overlay *overlay);
1281 int intel_overlay_put_image(struct drm_device *dev, void *data,
1282 struct drm_file *file_priv);
1283 int intel_overlay_attrs(struct drm_device *dev, void *data,
1284 struct drm_file *file_priv);
1285 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1286
1287
1288 /* intel_panel.c */
1289 int intel_panel_init(struct intel_panel *panel,
1290 struct drm_display_mode *fixed_mode,
1291 struct drm_display_mode *downclock_mode);
1292 void intel_panel_fini(struct intel_panel *panel);
1293 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1294 struct drm_display_mode *adjusted_mode);
1295 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1296 struct intel_crtc_state *pipe_config,
1297 int fitting_mode);
1298 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1299 struct intel_crtc_state *pipe_config,
1300 int fitting_mode);
1301 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1302 u32 level, u32 max);
1303 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1304 void intel_panel_enable_backlight(struct intel_connector *connector);
1305 void intel_panel_disable_backlight(struct intel_connector *connector);
1306 void intel_panel_destroy_backlight(struct drm_connector *connector);
1307 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1308 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1309 extern struct drm_display_mode *intel_find_panel_downclock(
1310 struct drm_device *dev,
1311 struct drm_display_mode *fixed_mode,
1312 struct drm_connector *connector);
1313 void intel_backlight_register(struct drm_device *dev);
1314 void intel_backlight_unregister(struct drm_device *dev);
1315
1316
1317 /* intel_psr.c */
1318 void intel_psr_enable(struct intel_dp *intel_dp);
1319 void intel_psr_disable(struct intel_dp *intel_dp);
1320 void intel_psr_invalidate(struct drm_device *dev,
1321 unsigned frontbuffer_bits);
1322 void intel_psr_flush(struct drm_device *dev,
1323 unsigned frontbuffer_bits);
1324 void intel_psr_init(struct drm_device *dev);
1325 void intel_psr_single_frame_update(struct drm_device *dev);
1326
1327 /* intel_runtime_pm.c */
1328 int intel_power_domains_init(struct drm_i915_private *);
1329 void intel_power_domains_fini(struct drm_i915_private *);
1330 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1331 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1332
1333 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1334 enum intel_display_power_domain domain);
1335 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1336 enum intel_display_power_domain domain);
1337 void intel_display_power_get(struct drm_i915_private *dev_priv,
1338 enum intel_display_power_domain domain);
1339 void intel_display_power_put(struct drm_i915_private *dev_priv,
1340 enum intel_display_power_domain domain);
1341 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1342 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1343 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1344 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1345 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1346
1347 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1348
1349 /* intel_pm.c */
1350 void intel_init_clock_gating(struct drm_device *dev);
1351 void intel_suspend_hw(struct drm_device *dev);
1352 int ilk_wm_max_level(const struct drm_device *dev);
1353 void intel_update_watermarks(struct drm_crtc *crtc);
1354 void intel_update_sprite_watermarks(struct drm_plane *plane,
1355 struct drm_crtc *crtc,
1356 uint32_t sprite_width,
1357 uint32_t sprite_height,
1358 int pixel_size,
1359 bool enabled, bool scaled);
1360 void intel_init_pm(struct drm_device *dev);
1361 void intel_pm_setup(struct drm_device *dev);
1362 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1363 void intel_gpu_ips_teardown(void);
1364 void intel_init_gt_powersave(struct drm_device *dev);
1365 void intel_cleanup_gt_powersave(struct drm_device *dev);
1366 void intel_enable_gt_powersave(struct drm_device *dev);
1367 void intel_disable_gt_powersave(struct drm_device *dev);
1368 void intel_suspend_gt_powersave(struct drm_device *dev);
1369 void intel_reset_gt_powersave(struct drm_device *dev);
1370 void gen6_update_ring_freq(struct drm_device *dev);
1371 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1372 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1373 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1374 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1375 struct intel_rps_client *rps,
1376 unsigned long submitted);
1377 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1378 struct drm_i915_gem_request *req);
1379 void ilk_wm_get_hw_state(struct drm_device *dev);
1380 void skl_wm_get_hw_state(struct drm_device *dev);
1381 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1382 struct skl_ddb_allocation *ddb /* out */);
1383
1384
1385 /* intel_sdvo.c */
1386 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1387
1388
1389 /* intel_sprite.c */
1390 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1391 int intel_plane_restore(struct drm_plane *plane);
1392 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1393 struct drm_file *file_priv);
1394 bool intel_pipe_update_start(struct intel_crtc *crtc,
1395 uint32_t *start_vbl_count);
1396 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1397
1398 /* intel_tv.c */
1399 void intel_tv_init(struct drm_device *dev);
1400
1401 /* intel_atomic.c */
1402 int intel_atomic_check(struct drm_device *dev,
1403 struct drm_atomic_state *state);
1404 int intel_atomic_commit(struct drm_device *dev,
1405 struct drm_atomic_state *state,
1406 bool async);
1407 int intel_connector_atomic_get_property(struct drm_connector *connector,
1408 const struct drm_connector_state *state,
1409 struct drm_property *property,
1410 uint64_t *val);
1411 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1412 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1413 struct drm_crtc_state *state);
1414 static inline struct intel_crtc_state *
1415 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1416 struct intel_crtc *crtc)
1417 {
1418 struct drm_crtc_state *crtc_state;
1419 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1420 if (IS_ERR(crtc_state))
1421 return ERR_CAST(crtc_state);
1422
1423 return to_intel_crtc_state(crtc_state);
1424 }
1425 int intel_atomic_setup_scalers(struct drm_device *dev,
1426 struct intel_crtc *intel_crtc,
1427 struct intel_crtc_state *crtc_state);
1428
1429 /* intel_atomic_plane.c */
1430 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1431 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1432 void intel_plane_destroy_state(struct drm_plane *plane,
1433 struct drm_plane_state *state);
1434 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1435
1436 #endif /* __INTEL_DRV_H__ */
Linux kernel - Deliverables
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