drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         struct list_head fbdev_list;
 127         struct drm_display_mode *our_mode;
 128         int preferred_bpp;
 129 };
 130
 131 struct intel_encoder {
 132         struct drm_encoder base;
 133
 134         enum intel_output_type type;
 135         unsigned int cloneable;
 136         void (*hot_plug)(struct intel_encoder *);
 137         bool (*compute_config)(struct intel_encoder *,
 138                                struct intel_crtc_state *);
 139         void (*pre_pll_enable)(struct intel_encoder *);
 140         void (*pre_enable)(struct intel_encoder *);
 141         void (*enable)(struct intel_encoder *);
 142         void (*mode_set)(struct intel_encoder *intel_encoder);
 143         void (*disable)(struct intel_encoder *);
 144         void (*post_disable)(struct intel_encoder *);
 145         /* Read out the current hw state of this connector, returning true if
 146          * the encoder is active. If the encoder is enabled it also set the pipe
 147          * it is connected to in the pipe parameter. */
 148         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 149         /* Reconstructs the equivalent mode flags for the current hardware
 150          * state. This must be called _after_ display->get_pipe_config has
 151          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 152          * be set correctly before calling this function. */
 153         void (*get_config)(struct intel_encoder *,
 154                            struct intel_crtc_state *pipe_config);
 155         /*
 156          * Called during system suspend after all pending requests for the
 157          * encoder are flushed (for example for DP AUX transactions) and
 158          * device interrupts are disabled.
 159          */
 160         void (*suspend)(struct intel_encoder *);
 161         int crtc_mask;
 162         enum hpd_pin hpd_pin;
 163 };
 164
 165 struct intel_panel {
 166         struct drm_display_mode *fixed_mode;
 167         struct drm_display_mode *downclock_mode;
 168         int fitting_mode;
 169
 170         /* backlight */
 171         struct {
 172                 bool present;
 173                 u32 level;
 174                 u32 min;
 175                 u32 max;
 176                 bool enabled;
 177                 bool combination_mode;  /* gen 2/4 only */
 178                 bool active_low_pwm;
 179
 180                 /* PWM chip */
 181                 struct pwm_device *pwm;
 182
 183                 struct backlight_device *device;
 184         } backlight;
 185
 186         void (*backlight_power)(struct intel_connector *, bool enable);
 187 };
 188
 189 struct intel_connector {
 190         struct drm_connector base;
 191         /*
 192          * The fixed encoder this connector is connected to.
 193          */
 194         struct intel_encoder *encoder;
 195
 196         /* Reads out the current hw, returning true if the connector is enabled
 197          * and active (i.e. dpms ON state). */
 198         bool (*get_hw_state)(struct intel_connector *);
 199
 200         /*
 201          * Removes all interfaces through which the connector is accessible
 202          * - like sysfs, debugfs entries -, so that no new operations can be
 203          * started on the connector. Also makes sure all currently pending
 204          * operations finish before returing.
 205          */
 206         void (*unregister)(struct intel_connector *);
 207
 208         /* Panel info for eDP and LVDS */
 209         struct intel_panel panel;
 210
 211         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 212         struct edid *edid;
 213         struct edid *detect_edid;
 214
 215         /* since POLL and HPD connectors may use the same HPD line keep the native
 216            state of connector->polled in case hotplug storm detection changes it */
 217         u8 polled;
 218
 219         void *port; /* store this opaque as its illegal to dereference it */
 220
 221         struct intel_dp *mst_port;
 222 };
 223
 224 typedef struct dpll {
 225         /* given values */
 226         int n;
 227         int m1, m2;
 228         int p1, p2;
 229         /* derived values */
 230         int     dot;
 231         int     vco;
 232         int     m;
 233         int     p;
 234 } intel_clock_t;
 235
 236 struct intel_atomic_state {
 237         struct drm_atomic_state base;
 238
 239         unsigned int cdclk;
 240         bool dpll_set;
 241         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 242 };
 243
 244 struct intel_plane_state {
 245         struct drm_plane_state base;
 246         struct drm_rect src;
 247         struct drm_rect dst;
 248         struct drm_rect clip;
 249         bool visible;
 250
 251         /*
 252          * scaler_id
 253          *    = -1 : not using a scaler
 254          *    >=  0 : using a scalers
 255          *
 256          * plane requiring a scaler:
 257          *   - During check_plane, its bit is set in
 258          *     crtc_state->scaler_state.scaler_users by calling helper function
 259          *     update_scaler_plane.
 260          *   - scaler_id indicates the scaler it got assigned.
 261          *
 262          * plane doesn't require a scaler:
 263          *   - this can happen when scaling is no more required or plane simply
 264          *     got disabled.
 265          *   - During check_plane, corresponding bit is reset in
 266          *     crtc_state->scaler_state.scaler_users by calling helper function
 267          *     update_scaler_plane.
 268          */
 269         int scaler_id;
 270
 271         struct drm_intel_sprite_colorkey ckey;
 272 };
 273
 274 struct intel_initial_plane_config {
 275         struct intel_framebuffer *fb;
 276         unsigned int tiling;
 277         int size;
 278         u32 base;
 279 };
 280
 281 #define SKL_MIN_SRC_W 8
 282 #define SKL_MAX_SRC_W 4096
 283 #define SKL_MIN_SRC_H 8
 284 #define SKL_MAX_SRC_H 4096
 285 #define SKL_MIN_DST_W 8
 286 #define SKL_MAX_DST_W 4096
 287 #define SKL_MIN_DST_H 8
 288 #define SKL_MAX_DST_H 4096
 289
 290 struct intel_scaler {
 291         int in_use;
 292         uint32_t mode;
 293 };
 294
 295 struct intel_crtc_scaler_state {
 296 #define SKL_NUM_SCALERS 2
 297         struct intel_scaler scalers[SKL_NUM_SCALERS];
 298
 299         /*
 300          * scaler_users: keeps track of users requesting scalers on this crtc.
 301          *
 302          *     If a bit is set, a user is using a scaler.
 303          *     Here user can be a plane or crtc as defined below:
 304          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 305          *       bit 31    - crtc
 306          *
 307          * Instead of creating a new index to cover planes and crtc, using
 308          * existing drm_plane_index for planes which is well less than 31
 309          * planes and bit 31 for crtc. This should be fine to cover all
 310          * our platforms.
 311          *
 312          * intel_atomic_setup_scalers will setup available scalers to users
 313          * requesting scalers. It will gracefully fail if request exceeds
 314          * avilability.
 315          */
 316 #define SKL_CRTC_INDEX 31
 317         unsigned scaler_users;
 318
 319         /* scaler used by crtc for panel fitting purpose */
 320         int scaler_id;
 321 };
 322
 323 /* drm_mode->private_flags */
 324 #define I915_MODE_FLAG_INHERITED 1
 325
 326 struct intel_crtc_state {
 327         struct drm_crtc_state base;
 328
 329         /**
 330          * quirks - bitfield with hw state readout quirks
 331          *
 332          * For various reasons the hw state readout code might not be able to
 333          * completely faithfully read out the current state. These cases are
 334          * tracked with quirk flags so that fastboot and state checker can act
 335          * accordingly.
 336          */
 337 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 338         unsigned long quirks;
 339
 340         /* Pipe source size (ie. panel fitter input size)
 341          * All planes will be positioned inside this space,
 342          * and get clipped at the edges. */
 343         int pipe_src_w, pipe_src_h;
 344
 345         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 346          * between pch encoders and cpu encoders. */
 347         bool has_pch_encoder;
 348
 349         /* Are we sending infoframes on the attached port */
 350         bool has_infoframe;
 351
 352         /* CPU Transcoder for the pipe. Currently this can only differ from the
 353          * pipe on Haswell (where we have a special eDP transcoder). */
 354         enum transcoder cpu_transcoder;
 355
 356         /*
 357          * Use reduced/limited/broadcast rbg range, compressing from the full
 358          * range fed into the crtcs.
 359          */
 360         bool limited_color_range;
 361
 362         /* DP has a bunch of special case unfortunately, so mark the pipe
 363          * accordingly. */
 364         bool has_dp_encoder;
 365
 366         /* Whether we should send NULL infoframes. Required for audio. */
 367         bool has_hdmi_sink;
 368
 369         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 370          * has_dp_encoder is set. */
 371         bool has_audio;
 372
 373         /*
 374          * Enable dithering, used when the selected pipe bpp doesn't match the
 375          * plane bpp.
 376          */
 377         bool dither;
 378
 379         /* Controls for the clock computation, to override various stages. */
 380         bool clock_set;
 381
 382         /* SDVO TV has a bunch of special case. To make multifunction encoders
 383          * work correctly, we need to track this at runtime.*/
 384         bool sdvo_tv_clock;
 385
 386         /*
 387          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 388          * required. This is set in the 2nd loop of calling encoder's
 389          * ->compute_config if the first pick doesn't work out.
 390          */
 391         bool bw_constrained;
 392
 393         /* Settings for the intel dpll used on pretty much everything but
 394          * haswell. */
 395         struct dpll dpll;
 396
 397         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 398         enum intel_dpll_id shared_dpll;
 399
 400         /*
 401          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 402          * - enum skl_dpll on SKL
 403          */
 404         uint32_t ddi_pll_sel;
 405
 406         /* Actual register state of the dpll, for shared dpll cross-checking. */
 407         struct intel_dpll_hw_state dpll_hw_state;
 408
 409         int pipe_bpp;
 410         struct intel_link_m_n dp_m_n;
 411
 412         /* m2_n2 for eDP downclock */
 413         struct intel_link_m_n dp_m2_n2;
 414         bool has_drrs;
 415
 416         /*
 417          * Frequence the dpll for the port should run at. Differs from the
 418          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 419          * already multiplied by pixel_multiplier.
 420          */
 421         int port_clock;
 422
 423         /* Used by SDVO (and if we ever fix it, HDMI). */
 424         unsigned pixel_multiplier;
 425
 426         /* Panel fitter controls for gen2-gen4 + VLV */
 427         struct {
 428                 u32 control;
 429                 u32 pgm_ratios;
 430                 u32 lvds_border_bits;
 431         } gmch_pfit;
 432
 433         /* Panel fitter placement and size for Ironlake+ */
 434         struct {
 435                 u32 pos;
 436                 u32 size;
 437                 bool enabled;
 438                 bool force_thru;
 439         } pch_pfit;
 440
 441         /* FDI configuration, only valid if has_pch_encoder is set. */
 442         int fdi_lanes;
 443         struct intel_link_m_n fdi_m_n;
 444
 445         bool ips_enabled;
 446
 447         bool double_wide;
 448
 449         bool dp_encoder_is_mst;
 450         int pbn;
 451
 452         struct intel_crtc_scaler_state scaler_state;
 453
 454         /* w/a for waiting 2 vblanks during crtc enable */
 455         enum pipe hsw_workaround_pipe;
 456 };
 457
 458 struct vlv_wm_state {
 459         struct vlv_pipe_wm wm[3];
 460         struct vlv_sr_wm sr[3];
 461         uint8_t num_active_planes;
 462         uint8_t num_levels;
 463         uint8_t level;
 464         bool cxsr;
 465 };
 466
 467 struct intel_pipe_wm {
 468         struct intel_wm_level wm[5];
 469         uint32_t linetime;
 470         bool fbc_wm_enabled;
 471         bool pipe_enabled;
 472         bool sprites_enabled;
 473         bool sprites_scaled;
 474 };
 475
 476 struct intel_mmio_flip {
 477         struct work_struct work;
 478         struct drm_i915_private *i915;
 479         struct drm_i915_gem_request *req;
 480         struct intel_crtc *crtc;
 481 };
 482
 483 struct skl_pipe_wm {
 484         struct skl_wm_level wm[8];
 485         struct skl_wm_level trans_wm;
 486         uint32_t linetime;
 487 };
 488
 489 /*
 490  * Tracking of operations that need to be performed at the beginning/end of an
 491  * atomic commit, outside the atomic section where interrupts are disabled.
 492  * These are generally operations that grab mutexes or might otherwise sleep
 493  * and thus can't be run with interrupts disabled.
 494  */
 495 struct intel_crtc_atomic_commit {
 496         /* Sleepable operations to perform before commit */
 497         bool wait_for_flips;
 498         bool disable_fbc;
 499         bool disable_ips;
 500         bool disable_cxsr;
 501         bool pre_disable_primary;
 502         bool update_wm_pre, update_wm_post;
 503         unsigned disabled_planes;
 504
 505         /* Sleepable operations to perform after commit */
 506         unsigned fb_bits;
 507         bool wait_vblank;
 508         bool update_fbc;
 509         bool post_enable_primary;
 510         unsigned update_sprite_watermarks;
 511 };
 512
 513 struct intel_crtc {
 514         struct drm_crtc base;
 515         enum pipe pipe;
 516         enum plane plane;
 517         u8 lut_r[256], lut_g[256], lut_b[256];
 518         /*
 519          * Whether the crtc and the connected output pipeline is active. Implies
 520          * that crtc->enabled is set, i.e. the current mode configuration has
 521          * some outputs connected to this crtc.
 522          */
 523         bool active;
 524         unsigned long enabled_power_domains;
 525         bool lowfreq_avail;
 526         struct intel_overlay *overlay;
 527         struct intel_unpin_work *unpin_work;
 528
 529         atomic_t unpin_work_count;
 530
 531         /* Display surface base address adjustement for pageflips. Note that on
 532          * gen4+ this only adjusts up to a tile, offsets within a tile are
 533          * handled in the hw itself (with the TILEOFF register). */
 534         unsigned long dspaddr_offset;
 535
 536         struct drm_i915_gem_object *cursor_bo;
 537         uint32_t cursor_addr;
 538         uint32_t cursor_cntl;
 539         uint32_t cursor_size;
 540         uint32_t cursor_base;
 541
 542         struct intel_crtc_state *config;
 543
 544         /* reset counter value when the last flip was submitted */
 545         unsigned int reset_counter;
 546
 547         /* Access to these should be protected by dev_priv->irq_lock. */
 548         bool cpu_fifo_underrun_disabled;
 549         bool pch_fifo_underrun_disabled;
 550
 551         /* per-pipe watermark state */
 552         struct {
 553                 /* watermarks currently being used  */
 554                 struct intel_pipe_wm active;
 555                 /* SKL wm values currently in use */
 556                 struct skl_pipe_wm skl_active;
 557                 /* allow CxSR on this pipe */
 558                 bool cxsr_allowed;
 559         } wm;
 560
 561         int scanline_offset;
 562
 563         unsigned start_vbl_count;
 564         struct intel_crtc_atomic_commit atomic;
 565
 566         /* scalers available on this crtc */
 567         int num_scalers;
 568
 569         struct vlv_wm_state wm_state;
 570 };
 571
 572 struct intel_plane_wm_parameters {
 573         uint32_t horiz_pixels;
 574         uint32_t vert_pixels;
 575         /*
 576          *   For packed pixel formats:
 577          *     bytes_per_pixel - holds bytes per pixel
 578          *   For planar pixel formats:
 579          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 580          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 581          */
 582         uint8_t bytes_per_pixel;
 583         uint8_t y_bytes_per_pixel;
 584         bool enabled;
 585         bool scaled;
 586         u64 tiling;
 587         unsigned int rotation;
 588         uint16_t fifo_size;
 589 };
 590
 591 struct intel_plane {
 592         struct drm_plane base;
 593         int plane;
 594         enum pipe pipe;
 595         bool can_scale;
 596         int max_downscale;
 597         uint32_t frontbuffer_bit;
 598
 599         /* Since we need to change the watermarks before/after
 600          * enabling/disabling the planes, we need to store the parameters here
 601          * as the other pieces of the struct may not reflect the values we want
 602          * for the watermark calculations. Currently only Haswell uses this.
 603          */
 604         struct intel_plane_wm_parameters wm;
 605
 606         /*
 607          * NOTE: Do not place new plane state fields here (e.g., when adding
 608          * new plane properties).  New runtime state should now be placed in
 609          * the intel_plane_state structure and accessed via drm_plane->state.
 610          */
 611
 612         void (*update_plane)(struct drm_plane *plane,
 613                              struct drm_crtc *crtc,
 614                              struct drm_framebuffer *fb,
 615                              int crtc_x, int crtc_y,
 616                              unsigned int crtc_w, unsigned int crtc_h,
 617                              uint32_t x, uint32_t y,
 618                              uint32_t src_w, uint32_t src_h);
 619         void (*disable_plane)(struct drm_plane *plane,
 620                               struct drm_crtc *crtc);
 621         int (*check_plane)(struct drm_plane *plane,
 622                            struct intel_crtc_state *crtc_state,
 623                            struct intel_plane_state *state);
 624         void (*commit_plane)(struct drm_plane *plane,
 625                              struct intel_plane_state *state);
 626 };
 627
 628 struct intel_watermark_params {
 629         unsigned long fifo_size;
 630         unsigned long max_wm;
 631         unsigned long default_wm;
 632         unsigned long guard_size;
 633         unsigned long cacheline_size;
 634 };
 635
 636 struct cxsr_latency {
 637         int is_desktop;
 638         int is_ddr3;
 639         unsigned long fsb_freq;
 640         unsigned long mem_freq;
 641         unsigned long display_sr;
 642         unsigned long display_hpll_disable;
 643         unsigned long cursor_sr;
 644         unsigned long cursor_hpll_disable;
 645 };
 646
 647 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 648 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 649 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 650 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 651 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 652 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 653 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 654 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 655 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 656
 657 struct intel_hdmi {
 658         u32 hdmi_reg;
 659         int ddc_bus;
 660         uint32_t color_range;
 661         bool color_range_auto;
 662         bool has_hdmi_sink;
 663         bool has_audio;
 664         enum hdmi_force_audio force_audio;
 665         bool rgb_quant_range_selectable;
 666         enum hdmi_picture_aspect aspect_ratio;
 667         void (*write_infoframe)(struct drm_encoder *encoder,
 668                                 enum hdmi_infoframe_type type,
 669                                 const void *frame, ssize_t len);
 670         void (*set_infoframes)(struct drm_encoder *encoder,
 671                                bool enable,
 672                                struct drm_display_mode *adjusted_mode);
 673         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 674 };
 675
 676 struct intel_dp_mst_encoder;
 677 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 678
 679 /*
 680  * enum link_m_n_set:
 681  *      When platform provides two set of M_N registers for dp, we can
 682  *      program them and switch between them incase of DRRS.
 683  *      But When only one such register is provided, we have to program the
 684  *      required divider value on that registers itself based on the DRRS state.
 685  *
 686  * M1_N1        : Program dp_m_n on M1_N1 registers
 687  *                        dp_m2_n2 on M2_N2 registers (If supported)
 688  *
 689  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 690  *                        M2_N2 registers are not supported
 691  */
 692
 693 enum link_m_n_set {
 694         /* Sets the m1_n1 and m2_n2 */
 695         M1_N1 = 0,
 696         M2_N2
 697 };
 698
 699 struct intel_dp {
 700         uint32_t output_reg;
 701         uint32_t aux_ch_ctl_reg;
 702         uint32_t DP;
 703         bool has_audio;
 704         enum hdmi_force_audio force_audio;
 705         uint32_t color_range;
 706         bool color_range_auto;
 707         uint8_t link_bw;
 708         uint8_t rate_select;
 709         uint8_t lane_count;
 710         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 711         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 712         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 713         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 714         uint8_t num_sink_rates;
 715         int sink_rates[DP_MAX_SUPPORTED_RATES];
 716         struct drm_dp_aux aux;
 717         uint8_t train_set[4];
 718         int panel_power_up_delay;
 719         int panel_power_down_delay;
 720         int panel_power_cycle_delay;
 721         int backlight_on_delay;
 722         int backlight_off_delay;
 723         struct delayed_work panel_vdd_work;
 724         bool want_panel_vdd;
 725         unsigned long last_power_cycle;
 726         unsigned long last_power_on;
 727         unsigned long last_backlight_off;
 728
 729         struct notifier_block edp_notifier;
 730
 731         /*
 732          * Pipe whose power sequencer is currently locked into
 733          * this port. Only relevant on VLV/CHV.
 734          */
 735         enum pipe pps_pipe;
 736         struct edp_power_seq pps_delays;
 737
 738         bool use_tps3;
 739         bool can_mst; /* this port supports mst */
 740         bool is_mst;
 741         int active_mst_links;
 742         /* connector directly attached - won't be use for modeset in mst world */
 743         struct intel_connector *attached_connector;
 744
 745         /* mst connector list */
 746         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 747         struct drm_dp_mst_topology_mgr mst_mgr;
 748
 749         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 750         /*
 751          * This function returns the value we have to program the AUX_CTL
 752          * register with to kick off an AUX transaction.
 753          */
 754         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 755                                      bool has_aux_irq,
 756                                      int send_bytes,
 757                                      uint32_t aux_clock_divider);
 758         bool train_set_valid;
 759
 760         /* Displayport compliance testing */
 761         unsigned long compliance_test_type;
 762         unsigned long compliance_test_data;
 763         bool compliance_test_active;
 764 };
 765
 766 struct intel_digital_port {
 767         struct intel_encoder base;
 768         enum port port;
 769         u32 saved_port_bits;
 770         struct intel_dp dp;
 771         struct intel_hdmi hdmi;
 772         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 773 };
 774
 775 struct intel_dp_mst_encoder {
 776         struct intel_encoder base;
 777         enum pipe pipe;
 778         struct intel_digital_port *primary;
 779         void *port; /* store this opaque as its illegal to dereference it */
 780 };
 781
 782 static inline int
 783 vlv_dport_to_channel(struct intel_digital_port *dport)
 784 {
 785         switch (dport->port) {
 786         case PORT_B:
 787         case PORT_D:
 788                 return DPIO_CH0;
 789         case PORT_C:
 790                 return DPIO_CH1;
 791         default:
 792                 BUG();
 793         }
 794 }
 795
 796 static inline int
 797 vlv_pipe_to_channel(enum pipe pipe)
 798 {
 799         switch (pipe) {
 800         case PIPE_A:
 801         case PIPE_C:
 802                 return DPIO_CH0;
 803         case PIPE_B:
 804                 return DPIO_CH1;
 805         default:
 806                 BUG();
 807         }
 808 }
 809
 810 static inline struct drm_crtc *
 811 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 812 {
 813         struct drm_i915_private *dev_priv = dev->dev_private;
 814         return dev_priv->pipe_to_crtc_mapping[pipe];
 815 }
 816
 817 static inline struct drm_crtc *
 818 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 819 {
 820         struct drm_i915_private *dev_priv = dev->dev_private;
 821         return dev_priv->plane_to_crtc_mapping[plane];
 822 }
 823
 824 struct intel_unpin_work {
 825         struct work_struct work;
 826         struct drm_crtc *crtc;
 827         struct drm_framebuffer *old_fb;
 828         struct drm_i915_gem_object *pending_flip_obj;
 829         struct drm_pending_vblank_event *event;
 830         atomic_t pending;
 831 #define INTEL_FLIP_INACTIVE     0
 832 #define INTEL_FLIP_PENDING      1
 833 #define INTEL_FLIP_COMPLETE     2
 834         u32 flip_count;
 835         u32 gtt_offset;
 836         struct drm_i915_gem_request *flip_queued_req;
 837         int flip_queued_vblank;
 838         int flip_ready_vblank;
 839         bool enable_stall_check;
 840 };
 841
 842 struct intel_load_detect_pipe {
 843         struct drm_framebuffer *release_fb;
 844         bool load_detect_temp;
 845         int dpms_mode;
 846 };
 847
 848 static inline struct intel_encoder *
 849 intel_attached_encoder(struct drm_connector *connector)
 850 {
 851         return to_intel_connector(connector)->encoder;
 852 }
 853
 854 static inline struct intel_digital_port *
 855 enc_to_dig_port(struct drm_encoder *encoder)
 856 {
 857         return container_of(encoder, struct intel_digital_port, base.base);
 858 }
 859
 860 static inline struct intel_dp_mst_encoder *
 861 enc_to_mst(struct drm_encoder *encoder)
 862 {
 863         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 864 }
 865
 866 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 867 {
 868         return &enc_to_dig_port(encoder)->dp;
 869 }
 870
 871 static inline struct intel_digital_port *
 872 dp_to_dig_port(struct intel_dp *intel_dp)
 873 {
 874         return container_of(intel_dp, struct intel_digital_port, dp);
 875 }
 876
 877 static inline struct intel_digital_port *
 878 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 879 {
 880         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 881 }
 882
 883 /*
 884  * Returns the number of planes for this pipe, ie the number of sprites + 1
 885  * (primary plane). This doesn't count the cursor plane then.
 886  */
 887 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 888 {
 889         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 890 }
 891
 892 /* intel_fifo_underrun.c */
 893 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 894                                            enum pipe pipe, bool enable);
 895 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 896                                            enum transcoder pch_transcoder,
 897                                            bool enable);
 898 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 899                                          enum pipe pipe);
 900 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 901                                          enum transcoder pch_transcoder);
 902 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 903
 904 /* i915_irq.c */
 905 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 906 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 907 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 908 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 909 void gen6_reset_rps_interrupts(struct drm_device *dev);
 910 void gen6_enable_rps_interrupts(struct drm_device *dev);
 911 void gen6_disable_rps_interrupts(struct drm_device *dev);
 912 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 913 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 914 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 915 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 916 {
 917         /*
 918          * We only use drm_irq_uninstall() at unload and VT switch, so
 919          * this is the only thing we need to check.
 920          */
 921         return dev_priv->pm.irqs_enabled;
 922 }
 923
 924 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 925 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 926                                      unsigned int pipe_mask);
 927
 928 /* intel_crt.c */
 929 void intel_crt_init(struct drm_device *dev);
 930
 931
 932 /* intel_ddi.c */
 933 void intel_prepare_ddi(struct drm_device *dev);
 934 void hsw_fdi_link_train(struct drm_crtc *crtc);
 935 void intel_ddi_init(struct drm_device *dev, enum port port);
 936 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 937 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 938 void intel_ddi_pll_init(struct drm_device *dev);
 939 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 940 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 941                                        enum transcoder cpu_transcoder);
 942 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 943 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 944 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 945                           struct intel_crtc_state *crtc_state);
 946 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 947 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 948 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 949 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 950 void intel_ddi_get_config(struct intel_encoder *encoder,
 951                           struct intel_crtc_state *pipe_config);
 952 struct intel_encoder *
 953 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
 954
 955 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 956 void intel_ddi_clock_get(struct intel_encoder *encoder,
 957                          struct intel_crtc_state *pipe_config);
 958 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 959 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 960
 961 /* intel_frontbuffer.c */
 962 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 963                              enum fb_op_origin origin);
 964 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 965                                     unsigned frontbuffer_bits);
 966 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 967                                      unsigned frontbuffer_bits);
 968 void intel_frontbuffer_flip(struct drm_device *dev,
 969                             unsigned frontbuffer_bits);
 970 unsigned int intel_fb_align_height(struct drm_device *dev,
 971                                    unsigned int height,
 972                                    uint32_t pixel_format,
 973                                    uint64_t fb_format_modifier);
 974 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
 975                         enum fb_op_origin origin);
 976 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
 977                               uint32_t pixel_format);
 978
 979 /* intel_audio.c */
 980 void intel_init_audio(struct drm_device *dev);
 981 void intel_audio_codec_enable(struct intel_encoder *encoder);
 982 void intel_audio_codec_disable(struct intel_encoder *encoder);
 983 void i915_audio_component_init(struct drm_i915_private *dev_priv);
 984 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
 985
 986 /* intel_display.c */
 987 extern const struct drm_plane_funcs intel_plane_funcs;
 988 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 989 int intel_pch_rawclk(struct drm_device *dev);
 990 void intel_mark_busy(struct drm_device *dev);
 991 void intel_mark_idle(struct drm_device *dev);
 992 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 993 int intel_display_suspend(struct drm_device *dev);
 994 void intel_encoder_destroy(struct drm_encoder *encoder);
 995 int intel_connector_init(struct intel_connector *);
 996 struct intel_connector *intel_connector_alloc(void);
 997 bool intel_connector_get_hw_state(struct intel_connector *connector);
 998 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 999                                 struct intel_digital_port *port);
1000 void intel_connector_attach_encoder(struct intel_connector *connector,
1001                                     struct intel_encoder *encoder);
1002 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1003 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1004                                              struct drm_crtc *crtc);
1005 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1006 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1007                                 struct drm_file *file_priv);
1008 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1009                                              enum pipe pipe);
1010 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1011 static inline void
1012 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1013 {
1014         drm_wait_one_vblank(dev, pipe);
1015 }
1016 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1017 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1018                          struct intel_digital_port *dport,
1019                          unsigned int expected_mask);
1020 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1021                                 struct drm_display_mode *mode,
1022                                 struct intel_load_detect_pipe *old,
1023                                 struct drm_modeset_acquire_ctx *ctx);
1024 void intel_release_load_detect_pipe(struct drm_connector *connector,
1025                                     struct intel_load_detect_pipe *old,
1026                                     struct drm_modeset_acquire_ctx *ctx);
1027 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1028                                struct drm_framebuffer *fb,
1029                                const struct drm_plane_state *plane_state,
1030                                struct intel_engine_cs *pipelined,
1031                                struct drm_i915_gem_request **pipelined_request);
1032 struct drm_framebuffer *
1033 __intel_framebuffer_create(struct drm_device *dev,
1034                            struct drm_mode_fb_cmd2 *mode_cmd,
1035                            struct drm_i915_gem_object *obj);
1036 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1037 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1038 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1039 void intel_check_page_flip(struct drm_device *dev, int pipe);
1040 int intel_prepare_plane_fb(struct drm_plane *plane,
1041                            struct drm_framebuffer *fb,
1042                            const struct drm_plane_state *new_state);
1043 void intel_cleanup_plane_fb(struct drm_plane *plane,
1044                             struct drm_framebuffer *fb,
1045                             const struct drm_plane_state *old_state);
1046 int intel_plane_atomic_get_property(struct drm_plane *plane,
1047                                     const struct drm_plane_state *state,
1048                                     struct drm_property *property,
1049                                     uint64_t *val);
1050 int intel_plane_atomic_set_property(struct drm_plane *plane,
1051                                     struct drm_plane_state *state,
1052                                     struct drm_property *property,
1053                                     uint64_t val);
1054 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1055                                     struct drm_plane_state *plane_state);
1056
1057 unsigned int
1058 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1059                   uint64_t fb_format_modifier);
1060
1061 static inline bool
1062 intel_rotation_90_or_270(unsigned int rotation)
1063 {
1064         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1065 }
1066
1067 void intel_create_rotation_property(struct drm_device *dev,
1068                                         struct intel_plane *plane);
1069
1070 /* shared dpll functions */
1071 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1072 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1073                         struct intel_shared_dpll *pll,
1074                         bool state);
1075 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1076 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1077 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1078                                                 struct intel_crtc_state *state);
1079
1080 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1081                       const struct dpll *dpll);
1082 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1083
1084 /* modesetting asserts */
1085 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1086                            enum pipe pipe);
1087 void assert_pll(struct drm_i915_private *dev_priv,
1088                 enum pipe pipe, bool state);
1089 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1090 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1091 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1092                        enum pipe pipe, bool state);
1093 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1094 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1095 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1096 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1097 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1098 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1099                                              int *x, int *y,
1100                                              unsigned int tiling_mode,
1101                                              unsigned int bpp,
1102                                              unsigned int pitch);
1103 void intel_prepare_reset(struct drm_device *dev);
1104 void intel_finish_reset(struct drm_device *dev);
1105 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1106 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1107 void broxton_init_cdclk(struct drm_device *dev);
1108 void broxton_uninit_cdclk(struct drm_device *dev);
1109 void broxton_ddi_phy_init(struct drm_device *dev);
1110 void broxton_ddi_phy_uninit(struct drm_device *dev);
1111 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1112 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1113 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1114 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1115 void intel_dp_get_m_n(struct intel_crtc *crtc,
1116                       struct intel_crtc_state *pipe_config);
1117 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1118 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1119 void
1120 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1121                                 int dotclock);
1122 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1123                         intel_clock_t *best_clock);
1124 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1125
1126 bool intel_crtc_active(struct drm_crtc *crtc);
1127 void hsw_enable_ips(struct intel_crtc *crtc);
1128 void hsw_disable_ips(struct intel_crtc *crtc);
1129 enum intel_display_power_domain
1130 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1131 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1132                                  struct intel_crtc_state *pipe_config);
1133 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1134 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1135
1136 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1137 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1138
1139 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1140                                      struct drm_i915_gem_object *obj);
1141 u32 skl_plane_ctl_format(uint32_t pixel_format);
1142 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1143 u32 skl_plane_ctl_rotation(unsigned int rotation);
1144
1145 /* intel_csr.c */
1146 void intel_csr_ucode_init(struct drm_device *dev);
1147 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1148 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1149                                         enum csr_state state);
1150 void intel_csr_load_program(struct drm_device *dev);
1151 void intel_csr_ucode_fini(struct drm_device *dev);
1152 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1153
1154 /* intel_dp.c */
1155 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1156 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1157                              struct intel_connector *intel_connector);
1158 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1159 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1160 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1161 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1162 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1163 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1164 bool intel_dp_compute_config(struct intel_encoder *encoder,
1165                              struct intel_crtc_state *pipe_config);
1166 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1167 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1168                                   bool long_hpd);
1169 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1170 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1171 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1172 void intel_edp_panel_on(struct intel_dp *intel_dp);
1173 void intel_edp_panel_off(struct intel_dp *intel_dp);
1174 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1175 void intel_dp_mst_suspend(struct drm_device *dev);
1176 void intel_dp_mst_resume(struct drm_device *dev);
1177 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1178 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1179 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1180 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1181 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1182 void intel_plane_destroy(struct drm_plane *plane);
1183 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1184 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1185 void intel_edp_drrs_invalidate(struct drm_device *dev,
1186                 unsigned frontbuffer_bits);
1187 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1188 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1189
1190 /* intel_dp_mst.c */
1191 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1192 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1193 /* intel_dsi.c */
1194 void intel_dsi_init(struct drm_device *dev);
1195
1196
1197 /* intel_dvo.c */
1198 void intel_dvo_init(struct drm_device *dev);
1199
1200
1201 /* legacy fbdev emulation in intel_fbdev.c */
1202 #ifdef CONFIG_DRM_FBDEV_EMULATION
1203 extern int intel_fbdev_init(struct drm_device *dev);
1204 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1205 extern void intel_fbdev_fini(struct drm_device *dev);
1206 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1207 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1208 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1209 #else
1210 static inline int intel_fbdev_init(struct drm_device *dev)
1211 {
1212         return 0;
1213 }
1214
1215 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1216 {
1217 }
1218
1219 static inline void intel_fbdev_fini(struct drm_device *dev)
1220 {
1221 }
1222
1223 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1224 {
1225 }
1226
1227 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1228 {
1229 }
1230 #endif
1231
1232 /* intel_fbc.c */
1233 bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
1234 void intel_fbc_update(struct drm_i915_private *dev_priv);
1235 void intel_fbc_init(struct drm_i915_private *dev_priv);
1236 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1237 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1238 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1239                           unsigned int frontbuffer_bits,
1240                           enum fb_op_origin origin);
1241 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1242                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1243 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1244 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1245
1246 /* intel_hdmi.c */
1247 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1248 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1249                                struct intel_connector *intel_connector);
1250 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1251 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1252                                struct intel_crtc_state *pipe_config);
1253
1254
1255 /* intel_lvds.c */
1256 void intel_lvds_init(struct drm_device *dev);
1257 bool intel_is_dual_link_lvds(struct drm_device *dev);
1258
1259
1260 /* intel_modes.c */
1261 int intel_connector_update_modes(struct drm_connector *connector,
1262                                  struct edid *edid);
1263 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1264 void intel_attach_force_audio_property(struct drm_connector *connector);
1265 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1266
1267
1268 /* intel_overlay.c */
1269 void intel_setup_overlay(struct drm_device *dev);
1270 void intel_cleanup_overlay(struct drm_device *dev);
1271 int intel_overlay_switch_off(struct intel_overlay *overlay);
1272 int intel_overlay_put_image(struct drm_device *dev, void *data,
1273                             struct drm_file *file_priv);
1274 int intel_overlay_attrs(struct drm_device *dev, void *data,
1275                         struct drm_file *file_priv);
1276 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1277
1278
1279 /* intel_panel.c */
1280 int intel_panel_init(struct intel_panel *panel,
1281                      struct drm_display_mode *fixed_mode,
1282                      struct drm_display_mode *downclock_mode);
1283 void intel_panel_fini(struct intel_panel *panel);
1284 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1285                             struct drm_display_mode *adjusted_mode);
1286 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1287                              struct intel_crtc_state *pipe_config,
1288                              int fitting_mode);
1289 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1290                               struct intel_crtc_state *pipe_config,
1291                               int fitting_mode);
1292 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1293                                     u32 level, u32 max);
1294 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1295 void intel_panel_enable_backlight(struct intel_connector *connector);
1296 void intel_panel_disable_backlight(struct intel_connector *connector);
1297 void intel_panel_destroy_backlight(struct drm_connector *connector);
1298 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1299 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1300 extern struct drm_display_mode *intel_find_panel_downclock(
1301                                 struct drm_device *dev,
1302                                 struct drm_display_mode *fixed_mode,
1303                                 struct drm_connector *connector);
1304 void intel_backlight_register(struct drm_device *dev);
1305 void intel_backlight_unregister(struct drm_device *dev);
1306
1307
1308 /* intel_psr.c */
1309 void intel_psr_enable(struct intel_dp *intel_dp);
1310 void intel_psr_disable(struct intel_dp *intel_dp);
1311 void intel_psr_invalidate(struct drm_device *dev,
1312                           unsigned frontbuffer_bits);
1313 void intel_psr_flush(struct drm_device *dev,
1314                      unsigned frontbuffer_bits,
1315                      enum fb_op_origin origin);
1316 void intel_psr_init(struct drm_device *dev);
1317 void intel_psr_single_frame_update(struct drm_device *dev,
1318                                    unsigned frontbuffer_bits);
1319
1320 /* intel_runtime_pm.c */
1321 int intel_power_domains_init(struct drm_i915_private *);
1322 void intel_power_domains_fini(struct drm_i915_private *);
1323 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1324 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1325
1326 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1327                                     enum intel_display_power_domain domain);
1328 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1329                                       enum intel_display_power_domain domain);
1330 void intel_display_power_get(struct drm_i915_private *dev_priv,
1331                              enum intel_display_power_domain domain);
1332 void intel_display_power_put(struct drm_i915_private *dev_priv,
1333                              enum intel_display_power_domain domain);
1334 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1335 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1336 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1337 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1338 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1339
1340 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1341
1342 /* intel_pm.c */
1343 void intel_init_clock_gating(struct drm_device *dev);
1344 void intel_suspend_hw(struct drm_device *dev);
1345 int ilk_wm_max_level(const struct drm_device *dev);
1346 void intel_update_watermarks(struct drm_crtc *crtc);
1347 void intel_update_sprite_watermarks(struct drm_plane *plane,
1348                                     struct drm_crtc *crtc,
1349                                     uint32_t sprite_width,
1350                                     uint32_t sprite_height,
1351                                     int pixel_size,
1352                                     bool enabled, bool scaled);
1353 void intel_init_pm(struct drm_device *dev);
1354 void intel_pm_setup(struct drm_device *dev);
1355 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1356 void intel_gpu_ips_teardown(void);
1357 void intel_init_gt_powersave(struct drm_device *dev);
1358 void intel_cleanup_gt_powersave(struct drm_device *dev);
1359 void intel_enable_gt_powersave(struct drm_device *dev);
1360 void intel_disable_gt_powersave(struct drm_device *dev);
1361 void intel_suspend_gt_powersave(struct drm_device *dev);
1362 void intel_reset_gt_powersave(struct drm_device *dev);
1363 void gen6_update_ring_freq(struct drm_device *dev);
1364 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1365 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1366 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1367 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1368                     struct intel_rps_client *rps,
1369                     unsigned long submitted);
1370 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1371                                        struct drm_i915_gem_request *req);
1372 void vlv_wm_get_hw_state(struct drm_device *dev);
1373 void ilk_wm_get_hw_state(struct drm_device *dev);
1374 void skl_wm_get_hw_state(struct drm_device *dev);
1375 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1376                           struct skl_ddb_allocation *ddb /* out */);
1377 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1378
1379 /* intel_sdvo.c */
1380 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1381
1382
1383 /* intel_sprite.c */
1384 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1385 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1386                               struct drm_file *file_priv);
1387 void intel_pipe_update_start(struct intel_crtc *crtc,
1388                              uint32_t *start_vbl_count);
1389 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1390
1391 /* intel_tv.c */
1392 void intel_tv_init(struct drm_device *dev);
1393
1394 /* intel_atomic.c */
1395 int intel_connector_atomic_get_property(struct drm_connector *connector,
1396                                         const struct drm_connector_state *state,
1397                                         struct drm_property *property,
1398                                         uint64_t *val);
1399 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1400 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1401                                struct drm_crtc_state *state);
1402 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1403 void intel_atomic_state_clear(struct drm_atomic_state *);
1404 struct intel_shared_dpll_config *
1405 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1406
1407 static inline struct intel_crtc_state *
1408 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1409                             struct intel_crtc *crtc)
1410 {
1411         struct drm_crtc_state *crtc_state;
1412         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1413         if (IS_ERR(crtc_state))
1414                 return ERR_CAST(crtc_state);
1415
1416         return to_intel_crtc_state(crtc_state);
1417 }
1418 int intel_atomic_setup_scalers(struct drm_device *dev,
1419         struct intel_crtc *intel_crtc,
1420         struct intel_crtc_state *crtc_state);
1421
1422 /* intel_atomic_plane.c */
1423 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1424 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1425 void intel_plane_destroy_state(struct drm_plane *plane,
1426                                struct drm_plane_state *state);
1427 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1428
1429 #endif /* __INTEL_DRV_H__ */