drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000*x)
  69 #define MHz(x) KHz(1000*x)
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80 #define INTELFB_CONN_LIMIT 4
  81
  82 #define INTEL_I2C_BUS_DVO 1
  83 #define INTEL_I2C_BUS_SDVO 2
  84
  85 /* these are outputs from the chip - integrated only
  86    external chips are via DVO or SDVO output */
  87 #define INTEL_OUTPUT_UNUSED 0
  88 #define INTEL_OUTPUT_ANALOG 1
  89 #define INTEL_OUTPUT_DVO 2
  90 #define INTEL_OUTPUT_SDVO 3
  91 #define INTEL_OUTPUT_LVDS 4
  92 #define INTEL_OUTPUT_TVOUT 5
  93 #define INTEL_OUTPUT_HDMI 6
  94 #define INTEL_OUTPUT_DISPLAYPORT 7
  95 #define INTEL_OUTPUT_EDP 8
  96 #define INTEL_OUTPUT_DSI 9
  97 #define INTEL_OUTPUT_UNKNOWN 10
  98
  99 #define INTEL_DVO_CHIP_NONE 0
 100 #define INTEL_DVO_CHIP_LVDS 1
 101 #define INTEL_DVO_CHIP_TMDS 2
 102 #define INTEL_DVO_CHIP_TVOUT 4
 103
 104 #define INTEL_DSI_COMMAND_MODE  0
 105 #define INTEL_DSI_VIDEO_MODE    1
 106
 107 struct intel_framebuffer {
 108         struct drm_framebuffer base;
 109         struct drm_i915_gem_object *obj;
 110 };
 111
 112 struct intel_fbdev {
 113         struct drm_fb_helper helper;
 114         struct intel_framebuffer ifb;
 115         struct list_head fbdev_list;
 116         struct drm_display_mode *our_mode;
 117 };
 118
 119 struct intel_encoder {
 120         struct drm_encoder base;
 121         /*
 122          * The new crtc this encoder will be driven from. Only differs from
 123          * base->crtc while a modeset is in progress.
 124          */
 125         struct intel_crtc *new_crtc;
 126
 127         int type;
 128         /*
 129          * Intel hw has only one MUX where encoders could be clone, hence a
 130          * simple flag is enough to compute the possible_clones mask.
 131          */
 132         bool cloneable;
 133         bool connectors_active;
 134         void (*hot_plug)(struct intel_encoder *);
 135         bool (*compute_config)(struct intel_encoder *,
 136                                struct intel_crtc_config *);
 137         void (*pre_pll_enable)(struct intel_encoder *);
 138         void (*pre_enable)(struct intel_encoder *);
 139         void (*enable)(struct intel_encoder *);
 140         void (*mode_set)(struct intel_encoder *intel_encoder);
 141         void (*disable)(struct intel_encoder *);
 142         void (*post_disable)(struct intel_encoder *);
 143         /* Read out the current hw state of this connector, returning true if
 144          * the encoder is active. If the encoder is enabled it also set the pipe
 145          * it is connected to in the pipe parameter. */
 146         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 147         /* Reconstructs the equivalent mode flags for the current hardware
 148          * state. This must be called _after_ display->get_pipe_config has
 149          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 150          * be set correctly before calling this function. */
 151         void (*get_config)(struct intel_encoder *,
 152                            struct intel_crtc_config *pipe_config);
 153         int crtc_mask;
 154         enum hpd_pin hpd_pin;
 155 };
 156
 157 struct intel_panel {
 158         struct drm_display_mode *fixed_mode;
 159         int fitting_mode;
 160 };
 161
 162 struct intel_connector {
 163         struct drm_connector base;
 164         /*
 165          * The fixed encoder this connector is connected to.
 166          */
 167         struct intel_encoder *encoder;
 168
 169         /*
 170          * The new encoder this connector will be driven. Only differs from
 171          * encoder while a modeset is in progress.
 172          */
 173         struct intel_encoder *new_encoder;
 174
 175         /* Reads out the current hw, returning true if the connector is enabled
 176          * and active (i.e. dpms ON state). */
 177         bool (*get_hw_state)(struct intel_connector *);
 178
 179         /* Panel info for eDP and LVDS */
 180         struct intel_panel panel;
 181
 182         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 183         struct edid *edid;
 184
 185         /* since POLL and HPD connectors may use the same HPD line keep the native
 186            state of connector->polled in case hotplug storm detection changes it */
 187         u8 polled;
 188 };
 189
 190 typedef struct dpll {
 191         /* given values */
 192         int n;
 193         int m1, m2;
 194         int p1, p2;
 195         /* derived values */
 196         int     dot;
 197         int     vco;
 198         int     m;
 199         int     p;
 200 } intel_clock_t;
 201
 202 struct intel_crtc_config {
 203         /**
 204          * quirks - bitfield with hw state readout quirks
 205          *
 206          * For various reasons the hw state readout code might not be able to
 207          * completely faithfully read out the current state. These cases are
 208          * tracked with quirk flags so that fastboot and state checker can act
 209          * accordingly.
 210          */
 211 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
 212         unsigned long quirks;
 213
 214         struct drm_display_mode requested_mode;
 215         /* Actual pipe timings ie. what we program into the pipe timing
 216          * registers. adjusted_mode.clock is the pipe pixel clock. */
 217         struct drm_display_mode adjusted_mode;
 218
 219         /* Pipe source size (ie. panel fitter input size)
 220          * All planes will be positioned inside this space,
 221          * and get clipped at the edges. */
 222         int pipe_src_w, pipe_src_h;
 223
 224         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 225          * between pch encoders and cpu encoders. */
 226         bool has_pch_encoder;
 227
 228         /* CPU Transcoder for the pipe. Currently this can only differ from the
 229          * pipe on Haswell (where we have a special eDP transcoder). */
 230         enum transcoder cpu_transcoder;
 231
 232         /*
 233          * Use reduced/limited/broadcast rbg range, compressing from the full
 234          * range fed into the crtcs.
 235          */
 236         bool limited_color_range;
 237
 238         /* DP has a bunch of special case unfortunately, so mark the pipe
 239          * accordingly. */
 240         bool has_dp_encoder;
 241
 242         /*
 243          * Enable dithering, used when the selected pipe bpp doesn't match the
 244          * plane bpp.
 245          */
 246         bool dither;
 247
 248         /* Controls for the clock computation, to override various stages. */
 249         bool clock_set;
 250
 251         /* SDVO TV has a bunch of special case. To make multifunction encoders
 252          * work correctly, we need to track this at runtime.*/
 253         bool sdvo_tv_clock;
 254
 255         /*
 256          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 257          * required. This is set in the 2nd loop of calling encoder's
 258          * ->compute_config if the first pick doesn't work out.
 259          */
 260         bool bw_constrained;
 261
 262         /* Settings for the intel dpll used on pretty much everything but
 263          * haswell. */
 264         struct dpll dpll;
 265
 266         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 267         enum intel_dpll_id shared_dpll;
 268
 269         /* Actual register state of the dpll, for shared dpll cross-checking. */
 270         struct intel_dpll_hw_state dpll_hw_state;
 271
 272         int pipe_bpp;
 273         struct intel_link_m_n dp_m_n;
 274
 275         /*
 276          * Frequence the dpll for the port should run at. Differs from the
 277          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 278          * already multiplied by pixel_multiplier.
 279          */
 280         int port_clock;
 281
 282         /* Used by SDVO (and if we ever fix it, HDMI). */
 283         unsigned pixel_multiplier;
 284
 285         /* Panel fitter controls for gen2-gen4 + VLV */
 286         struct {
 287                 u32 control;
 288                 u32 pgm_ratios;
 289                 u32 lvds_border_bits;
 290         } gmch_pfit;
 291
 292         /* Panel fitter placement and size for Ironlake+ */
 293         struct {
 294                 u32 pos;
 295                 u32 size;
 296         } pch_pfit;
 297
 298         /* FDI configuration, only valid if has_pch_encoder is set. */
 299         int fdi_lanes;
 300         struct intel_link_m_n fdi_m_n;
 301
 302         bool ips_enabled;
 303 };
 304
 305 struct intel_crtc {
 306         struct drm_crtc base;
 307         enum pipe pipe;
 308         enum plane plane;
 309         u8 lut_r[256], lut_g[256], lut_b[256];
 310         /*
 311          * Whether the crtc and the connected output pipeline is active. Implies
 312          * that crtc->enabled is set, i.e. the current mode configuration has
 313          * some outputs connected to this crtc.
 314          */
 315         bool active;
 316         bool eld_vld;
 317         bool primary_disabled; /* is the crtc obscured by a plane? */
 318         bool lowfreq_avail;
 319         struct intel_overlay *overlay;
 320         struct intel_unpin_work *unpin_work;
 321
 322         atomic_t unpin_work_count;
 323
 324         /* Display surface base address adjustement for pageflips. Note that on
 325          * gen4+ this only adjusts up to a tile, offsets within a tile are
 326          * handled in the hw itself (with the TILEOFF register). */
 327         unsigned long dspaddr_offset;
 328
 329         struct drm_i915_gem_object *cursor_bo;
 330         uint32_t cursor_addr;
 331         int16_t cursor_x, cursor_y;
 332         int16_t cursor_width, cursor_height;
 333         bool cursor_visible;
 334
 335         struct intel_crtc_config config;
 336
 337         uint32_t ddi_pll_sel;
 338
 339         /* reset counter value when the last flip was submitted */
 340         unsigned int reset_counter;
 341
 342         /* Access to these should be protected by dev_priv->irq_lock. */
 343         bool cpu_fifo_underrun_disabled;
 344         bool pch_fifo_underrun_disabled;
 345 };
 346
 347 struct intel_plane_wm_parameters {
 348         uint32_t horiz_pixels;
 349         uint8_t bytes_per_pixel;
 350         bool enabled;
 351         bool scaled;
 352 };
 353
 354 struct intel_plane {
 355         struct drm_plane base;
 356         int plane;
 357         enum pipe pipe;
 358         struct drm_i915_gem_object *obj;
 359         bool can_scale;
 360         int max_downscale;
 361         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 362         int crtc_x, crtc_y;
 363         unsigned int crtc_w, crtc_h;
 364         uint32_t src_x, src_y;
 365         uint32_t src_w, src_h;
 366
 367         /* Since we need to change the watermarks before/after
 368          * enabling/disabling the planes, we need to store the parameters here
 369          * as the other pieces of the struct may not reflect the values we want
 370          * for the watermark calculations. Currently only Haswell uses this.
 371          */
 372         struct intel_plane_wm_parameters wm;
 373
 374         void (*update_plane)(struct drm_plane *plane,
 375                              struct drm_crtc *crtc,
 376                              struct drm_framebuffer *fb,
 377                              struct drm_i915_gem_object *obj,
 378                              int crtc_x, int crtc_y,
 379                              unsigned int crtc_w, unsigned int crtc_h,
 380                              uint32_t x, uint32_t y,
 381                              uint32_t src_w, uint32_t src_h);
 382         void (*disable_plane)(struct drm_plane *plane,
 383                               struct drm_crtc *crtc);
 384         int (*update_colorkey)(struct drm_plane *plane,
 385                                struct drm_intel_sprite_colorkey *key);
 386         void (*get_colorkey)(struct drm_plane *plane,
 387                              struct drm_intel_sprite_colorkey *key);
 388 };
 389
 390 struct intel_watermark_params {
 391         unsigned long fifo_size;
 392         unsigned long max_wm;
 393         unsigned long default_wm;
 394         unsigned long guard_size;
 395         unsigned long cacheline_size;
 396 };
 397
 398 struct cxsr_latency {
 399         int is_desktop;
 400         int is_ddr3;
 401         unsigned long fsb_freq;
 402         unsigned long mem_freq;
 403         unsigned long display_sr;
 404         unsigned long display_hpll_disable;
 405         unsigned long cursor_sr;
 406         unsigned long cursor_hpll_disable;
 407 };
 408
 409 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 410 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 411 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 412 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 413 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 414
 415 struct intel_hdmi {
 416         u32 hdmi_reg;
 417         int ddc_bus;
 418         uint32_t color_range;
 419         bool color_range_auto;
 420         bool has_hdmi_sink;
 421         bool has_audio;
 422         enum hdmi_force_audio force_audio;
 423         bool rgb_quant_range_selectable;
 424         void (*write_infoframe)(struct drm_encoder *encoder,
 425                                 enum hdmi_infoframe_type type,
 426                                 const uint8_t *frame, ssize_t len);
 427         void (*set_infoframes)(struct drm_encoder *encoder,
 428                                struct drm_display_mode *adjusted_mode);
 429 };
 430
 431 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 432 #define DP_LINK_CONFIGURATION_SIZE      9
 433
 434 struct intel_dp {
 435         uint32_t output_reg;
 436         uint32_t aux_ch_ctl_reg;
 437         uint32_t DP;
 438         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
 439         bool has_audio;
 440         enum hdmi_force_audio force_audio;
 441         uint32_t color_range;
 442         bool color_range_auto;
 443         uint8_t link_bw;
 444         uint8_t lane_count;
 445         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 446         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 447         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 448         struct i2c_adapter adapter;
 449         struct i2c_algo_dp_aux_data algo;
 450         uint8_t train_set[4];
 451         int panel_power_up_delay;
 452         int panel_power_down_delay;
 453         int panel_power_cycle_delay;
 454         int backlight_on_delay;
 455         int backlight_off_delay;
 456         struct delayed_work panel_vdd_work;
 457         bool want_panel_vdd;
 458         bool psr_setup_done;
 459         struct intel_connector *attached_connector;
 460 };
 461
 462 struct intel_digital_port {
 463         struct intel_encoder base;
 464         enum port port;
 465         u32 saved_port_bits;
 466         struct intel_dp dp;
 467         struct intel_hdmi hdmi;
 468 };
 469
 470 static inline int
 471 vlv_dport_to_channel(struct intel_digital_port *dport)
 472 {
 473         switch (dport->port) {
 474         case PORT_B:
 475                 return 0;
 476         case PORT_C:
 477                 return 1;
 478         default:
 479                 BUG();
 480         }
 481 }
 482
 483 static inline struct drm_crtc *
 484 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 485 {
 486         struct drm_i915_private *dev_priv = dev->dev_private;
 487         return dev_priv->pipe_to_crtc_mapping[pipe];
 488 }
 489
 490 static inline struct drm_crtc *
 491 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 492 {
 493         struct drm_i915_private *dev_priv = dev->dev_private;
 494         return dev_priv->plane_to_crtc_mapping[plane];
 495 }
 496
 497 struct intel_unpin_work {
 498         struct work_struct work;
 499         struct drm_crtc *crtc;
 500         struct drm_i915_gem_object *old_fb_obj;
 501         struct drm_i915_gem_object *pending_flip_obj;
 502         struct drm_pending_vblank_event *event;
 503         atomic_t pending;
 504 #define INTEL_FLIP_INACTIVE     0
 505 #define INTEL_FLIP_PENDING      1
 506 #define INTEL_FLIP_COMPLETE     2
 507         bool enable_stall_check;
 508 };
 509
 510 int intel_pch_rawclk(struct drm_device *dev);
 511
 512 int intel_connector_update_modes(struct drm_connector *connector,
 513                                 struct edid *edid);
 514 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 515
 516 extern void intel_attach_force_audio_property(struct drm_connector *connector);
 517 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 518
 519 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
 520 extern void intel_crt_init(struct drm_device *dev);
 521 extern void intel_hdmi_init(struct drm_device *dev,
 522                             int hdmi_reg, enum port port);
 523 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 524                                       struct intel_connector *intel_connector);
 525 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 526 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 527                                       struct intel_crtc_config *pipe_config);
 528 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
 529                             bool is_sdvob);
 530 extern void intel_dvo_init(struct drm_device *dev);
 531 extern void intel_tv_init(struct drm_device *dev);
 532 extern void intel_mark_busy(struct drm_device *dev);
 533 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 534                                struct intel_ring_buffer *ring);
 535 extern void intel_mark_idle(struct drm_device *dev);
 536 extern void intel_lvds_init(struct drm_device *dev);
 537 extern bool intel_dsi_init(struct drm_device *dev);
 538 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
 539 extern void intel_dp_init(struct drm_device *dev, int output_reg,
 540                           enum port port);
 541 extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 542                                     struct intel_connector *intel_connector);
 543 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
 544 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
 545 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 546 extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 547 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 548 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 549 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
 550 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
 551                                     struct intel_crtc_config *pipe_config);
 552 extern bool intel_dpd_is_edp(struct drm_device *dev);
 553 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
 554 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
 555 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
 556 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
 557 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 558 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 559 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 560 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
 561                                       enum plane plane);
 562
 563 /* intel_panel.c */
 564 extern int intel_panel_init(struct intel_panel *panel,
 565                             struct drm_display_mode *fixed_mode);
 566 extern void intel_panel_fini(struct intel_panel *panel);
 567
 568 extern void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
 569                                    struct drm_display_mode *adjusted_mode);
 570 extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
 571                                     struct intel_crtc_config *pipe_config,
 572                                     int fitting_mode);
 573 extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 574                                      struct intel_crtc_config *pipe_config,
 575                                      int fitting_mode);
 576 extern void intel_panel_set_backlight(struct drm_device *dev,
 577                                       u32 level, u32 max);
 578 extern int intel_panel_setup_backlight(struct drm_connector *connector);
 579 extern void intel_panel_enable_backlight(struct drm_device *dev,
 580                                          enum pipe pipe);
 581 extern void intel_panel_disable_backlight(struct drm_device *dev);
 582 extern void intel_panel_destroy_backlight(struct drm_device *dev);
 583 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 584
 585 struct intel_set_config {
 586         struct drm_encoder **save_connector_encoders;
 587         struct drm_crtc **save_encoder_crtcs;
 588
 589         bool fb_changed;
 590         bool mode_changed;
 591 };
 592
 593 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
 594 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
 595 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
 596 extern void intel_encoder_destroy(struct drm_encoder *encoder);
 597 extern void intel_connector_dpms(struct drm_connector *, int mode);
 598 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
 599 extern void intel_modeset_check_state(struct drm_device *dev);
 600 extern void intel_plane_restore(struct drm_plane *plane);
 601 extern void intel_plane_disable(struct drm_plane *plane);
 602
 603
 604 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
 605 {
 606         return to_intel_connector(connector)->encoder;
 607 }
 608
 609 static inline struct intel_digital_port *
 610 enc_to_dig_port(struct drm_encoder *encoder)
 611 {
 612         return container_of(encoder, struct intel_digital_port, base.base);
 613 }
 614
 615 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 616 {
 617         return &enc_to_dig_port(encoder)->dp;
 618 }
 619
 620 static inline struct intel_digital_port *
 621 dp_to_dig_port(struct intel_dp *intel_dp)
 622 {
 623         return container_of(intel_dp, struct intel_digital_port, dp);
 624 }
 625
 626 static inline struct intel_digital_port *
 627 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 628 {
 629         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 630 }
 631
 632 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 633                                 struct intel_digital_port *port);
 634
 635 extern void intel_connector_attach_encoder(struct intel_connector *connector,
 636                                            struct intel_encoder *encoder);
 637 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 638
 639 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 640                                                     struct drm_crtc *crtc);
 641 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 642                                 struct drm_file *file_priv);
 643 extern enum transcoder
 644 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 645                              enum pipe pipe);
 646 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 647 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 648 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 649 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
 650
 651 struct intel_load_detect_pipe {
 652         struct drm_framebuffer *release_fb;
 653         bool load_detect_temp;
 654         int dpms_mode;
 655 };
 656 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
 657                                        struct drm_display_mode *mode,
 658                                        struct intel_load_detect_pipe *old);
 659 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
 660                                            struct intel_load_detect_pipe *old);
 661
 662 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 663                                     u16 blue, int regno);
 664 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 665                                     u16 *blue, int regno);
 666
 667 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 668                                       struct drm_i915_gem_object *obj,
 669                                       struct intel_ring_buffer *pipelined);
 670 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 671
 672 extern int intel_framebuffer_init(struct drm_device *dev,
 673                                   struct intel_framebuffer *ifb,
 674                                   struct drm_mode_fb_cmd2 *mode_cmd,
 675                                   struct drm_i915_gem_object *obj);
 676 extern void intel_framebuffer_fini(struct intel_framebuffer *fb);
 677 extern int intel_fbdev_init(struct drm_device *dev);
 678 extern void intel_fbdev_initial_config(struct drm_device *dev);
 679 extern void intel_fbdev_fini(struct drm_device *dev);
 680 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 681 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
 682 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
 683 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 684
 685 extern void intel_setup_overlay(struct drm_device *dev);
 686 extern void intel_cleanup_overlay(struct drm_device *dev);
 687 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
 688 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
 689                                    struct drm_file *file_priv);
 690 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
 691                                struct drm_file *file_priv);
 692
 693 extern void intel_fb_output_poll_changed(struct drm_device *dev);
 694 extern void intel_fb_restore_mode(struct drm_device *dev);
 695
 696 struct intel_shared_dpll *
 697 intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 698
 699 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 700                         struct intel_shared_dpll *pll,
 701                         bool state);
 702 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 703 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 704 void assert_pll(struct drm_i915_private *dev_priv,
 705                 enum pipe pipe, bool state);
 706 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 707 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 708 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 709                        enum pipe pipe, bool state);
 710 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 711 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 712 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 713                         bool state);
 714 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 715 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 716
 717 extern void intel_init_clock_gating(struct drm_device *dev);
 718 extern void intel_suspend_hw(struct drm_device *dev);
 719 extern void intel_write_eld(struct drm_encoder *encoder,
 720                             struct drm_display_mode *mode);
 721 extern void intel_prepare_ddi(struct drm_device *dev);
 722 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
 723 extern void intel_ddi_init(struct drm_device *dev, enum port port);
 724 extern enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 725
 726 /* For use by IVB LP watermark workaround in intel_sprite.c */
 727 extern void intel_update_watermarks(struct drm_crtc *crtc);
 728 extern void intel_update_sprite_watermarks(struct drm_plane *plane,
 729                                            struct drm_crtc *crtc,
 730                                            uint32_t sprite_width, int pixel_size,
 731                                            bool enabled, bool scaled);
 732
 733 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 734                                                     unsigned int tiling_mode,
 735                                                     unsigned int bpp,
 736                                                     unsigned int pitch);
 737
 738 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 739                                      struct drm_file *file_priv);
 740 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 741                                      struct drm_file *file_priv);
 742
 743 /* Power-related functions, located in intel_pm.c */
 744 extern void intel_init_pm(struct drm_device *dev);
 745 /* FBC */
 746 extern bool intel_fbc_enabled(struct drm_device *dev);
 747 extern void intel_update_fbc(struct drm_device *dev);
 748 /* IPS */
 749 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 750 extern void intel_gpu_ips_teardown(void);
 751
 752 /* Power well */
 753 extern int i915_init_power_well(struct drm_device *dev);
 754 extern void i915_remove_power_well(struct drm_device *dev);
 755
 756 extern bool intel_display_power_enabled(struct drm_device *dev,
 757                                         enum intel_display_power_domain domain);
 758 extern void intel_init_power_well(struct drm_device *dev);
 759 extern void intel_set_power_well(struct drm_device *dev, bool enable);
 760 extern void intel_enable_gt_powersave(struct drm_device *dev);
 761 extern void intel_disable_gt_powersave(struct drm_device *dev);
 762 extern void ironlake_teardown_rc6(struct drm_device *dev);
 763 void gen6_update_ring_freq(struct drm_device *dev);
 764
 765 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 766                                    enum pipe *pipe);
 767 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 768 extern void intel_ddi_pll_init(struct drm_device *dev);
 769 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 770 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 771                                               enum transcoder cpu_transcoder);
 772 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 773 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 774 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 775 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
 776 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 777 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 778 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 779 extern bool
 780 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 781 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 782
 783 extern void intel_display_handle_reset(struct drm_device *dev);
 784 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 785                                                   enum pipe pipe,
 786                                                   bool enable);
 787 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 788                                                  enum transcoder pch_transcoder,
 789                                                  bool enable);
 790
 791 extern void intel_edp_psr_enable(struct intel_dp *intel_dp);
 792 extern void intel_edp_psr_disable(struct intel_dp *intel_dp);
 793 extern void intel_edp_psr_update(struct drm_device *dev);
 794 extern void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
 795                               bool switch_to_fclk, bool allow_power_down);
 796 extern void hsw_restore_lcpll(struct drm_i915_private *dev_priv);
 797 extern void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 798 extern void ilk_disable_gt_irq(struct drm_i915_private *dev_priv,
 799                                uint32_t mask);
 800 extern void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 801 extern void snb_disable_pm_irq(struct drm_i915_private *dev_priv,
 802                                uint32_t mask);
 803 extern void hsw_enable_pc8_work(struct work_struct *__work);
 804 extern void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
 805 extern void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
 806 extern void hsw_pc8_disable_interrupts(struct drm_device *dev);
 807 extern void hsw_pc8_restore_interrupts(struct drm_device *dev);
 808 extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
 809 extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 810 extern void intel_dp_get_m_n(struct intel_crtc *crtc,
 811                              struct intel_crtc_config *pipe_config);
 812 extern int intel_dotclock_calculate(int link_freq,
 813                                     const struct intel_link_m_n *m_n);
 814 extern void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 815                                             int dotclock);
 816
 817 extern bool intel_crtc_active(struct drm_crtc *crtc);
 818
 819 #endif /* __INTEL_DRV_H__ */