drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000 * (x))
  69 #define MHz(x) KHz(1000 * (x))
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80
  81 #define INTEL_I2C_BUS_DVO 1
  82 #define INTEL_I2C_BUS_SDVO 2
  83
  84 /* these are outputs from the chip - integrated only
  85    external chips are via DVO or SDVO output */
  86 #define INTEL_OUTPUT_UNUSED 0
  87 #define INTEL_OUTPUT_ANALOG 1
  88 #define INTEL_OUTPUT_DVO 2
  89 #define INTEL_OUTPUT_SDVO 3
  90 #define INTEL_OUTPUT_LVDS 4
  91 #define INTEL_OUTPUT_TVOUT 5
  92 #define INTEL_OUTPUT_HDMI 6
  93 #define INTEL_OUTPUT_DISPLAYPORT 7
  94 #define INTEL_OUTPUT_EDP 8
  95 #define INTEL_OUTPUT_DSI 9
  96 #define INTEL_OUTPUT_UNKNOWN 10
  97
  98 #define INTEL_DVO_CHIP_NONE 0
  99 #define INTEL_DVO_CHIP_LVDS 1
 100 #define INTEL_DVO_CHIP_TMDS 2
 101 #define INTEL_DVO_CHIP_TVOUT 4
 102
 103 #define INTEL_DSI_COMMAND_MODE  0
 104 #define INTEL_DSI_VIDEO_MODE    1
 105
 106 struct intel_framebuffer {
 107         struct drm_framebuffer base;
 108         struct drm_i915_gem_object *obj;
 109 };
 110
 111 struct intel_fbdev {
 112         struct drm_fb_helper helper;
 113         struct intel_framebuffer *fb;
 114         struct list_head fbdev_list;
 115         struct drm_display_mode *our_mode;
 116         int preferred_bpp;
 117 };
 118
 119 struct intel_encoder {
 120         struct drm_encoder base;
 121         /*
 122          * The new crtc this encoder will be driven from. Only differs from
 123          * base->crtc while a modeset is in progress.
 124          */
 125         struct intel_crtc *new_crtc;
 126
 127         int type;
 128         unsigned int cloneable;
 129         bool connectors_active;
 130         void (*hot_plug)(struct intel_encoder *);
 131         bool (*compute_config)(struct intel_encoder *,
 132                                struct intel_crtc_config *);
 133         void (*pre_pll_enable)(struct intel_encoder *);
 134         void (*pre_enable)(struct intel_encoder *);
 135         void (*enable)(struct intel_encoder *);
 136         void (*mode_set)(struct intel_encoder *intel_encoder);
 137         void (*disable)(struct intel_encoder *);
 138         void (*post_disable)(struct intel_encoder *);
 139         /* Read out the current hw state of this connector, returning true if
 140          * the encoder is active. If the encoder is enabled it also set the pipe
 141          * it is connected to in the pipe parameter. */
 142         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 143         /* Reconstructs the equivalent mode flags for the current hardware
 144          * state. This must be called _after_ display->get_pipe_config has
 145          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 146          * be set correctly before calling this function. */
 147         void (*get_config)(struct intel_encoder *,
 148                            struct intel_crtc_config *pipe_config);
 149         int crtc_mask;
 150         enum hpd_pin hpd_pin;
 151 };
 152
 153 struct intel_panel {
 154         struct drm_display_mode *fixed_mode;
 155         struct drm_display_mode *downclock_mode;
 156         int fitting_mode;
 157
 158         /* backlight */
 159         struct {
 160                 bool present;
 161                 u32 level;
 162                 u32 max;
 163                 bool enabled;
 164                 bool combination_mode;  /* gen 2/4 only */
 165                 bool active_low_pwm;
 166                 struct backlight_device *device;
 167         } backlight;
 168 };
 169
 170 struct intel_connector {
 171         struct drm_connector base;
 172         /*
 173          * The fixed encoder this connector is connected to.
 174          */
 175         struct intel_encoder *encoder;
 176
 177         /*
 178          * The new encoder this connector will be driven. Only differs from
 179          * encoder while a modeset is in progress.
 180          */
 181         struct intel_encoder *new_encoder;
 182
 183         /* Reads out the current hw, returning true if the connector is enabled
 184          * and active (i.e. dpms ON state). */
 185         bool (*get_hw_state)(struct intel_connector *);
 186
 187         /*
 188          * Removes all interfaces through which the connector is accessible
 189          * - like sysfs, debugfs entries -, so that no new operations can be
 190          * started on the connector. Also makes sure all currently pending
 191          * operations finish before returing.
 192          */
 193         void (*unregister)(struct intel_connector *);
 194
 195         /* Panel info for eDP and LVDS */
 196         struct intel_panel panel;
 197
 198         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 199         struct edid *edid;
 200
 201         /* since POLL and HPD connectors may use the same HPD line keep the native
 202            state of connector->polled in case hotplug storm detection changes it */
 203         u8 polled;
 204 };
 205
 206 typedef struct dpll {
 207         /* given values */
 208         int n;
 209         int m1, m2;
 210         int p1, p2;
 211         /* derived values */
 212         int     dot;
 213         int     vco;
 214         int     m;
 215         int     p;
 216 } intel_clock_t;
 217
 218 struct intel_plane_config {
 219         bool tiled;
 220         int size;
 221         u32 base;
 222 };
 223
 224 struct intel_crtc_config {
 225         /**
 226          * quirks - bitfield with hw state readout quirks
 227          *
 228          * For various reasons the hw state readout code might not be able to
 229          * completely faithfully read out the current state. These cases are
 230          * tracked with quirk flags so that fastboot and state checker can act
 231          * accordingly.
 232          */
 233 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
 234         unsigned long quirks;
 235
 236         /* User requested mode, only valid as a starting point to
 237          * compute adjusted_mode, except in the case of (S)DVO where
 238          * it's also for the output timings of the (S)DVO chip.
 239          * adjusted_mode will then correspond to the S(DVO) chip's
 240          * preferred input timings. */
 241         struct drm_display_mode requested_mode;
 242         /* Actual pipe timings ie. what we program into the pipe timing
 243          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 244         struct drm_display_mode adjusted_mode;
 245
 246         /* Pipe source size (ie. panel fitter input size)
 247          * All planes will be positioned inside this space,
 248          * and get clipped at the edges. */
 249         int pipe_src_w, pipe_src_h;
 250
 251         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 252          * between pch encoders and cpu encoders. */
 253         bool has_pch_encoder;
 254
 255         /* CPU Transcoder for the pipe. Currently this can only differ from the
 256          * pipe on Haswell (where we have a special eDP transcoder). */
 257         enum transcoder cpu_transcoder;
 258
 259         /*
 260          * Use reduced/limited/broadcast rbg range, compressing from the full
 261          * range fed into the crtcs.
 262          */
 263         bool limited_color_range;
 264
 265         /* DP has a bunch of special case unfortunately, so mark the pipe
 266          * accordingly. */
 267         bool has_dp_encoder;
 268
 269         /*
 270          * Enable dithering, used when the selected pipe bpp doesn't match the
 271          * plane bpp.
 272          */
 273         bool dither;
 274
 275         /* Controls for the clock computation, to override various stages. */
 276         bool clock_set;
 277
 278         /* SDVO TV has a bunch of special case. To make multifunction encoders
 279          * work correctly, we need to track this at runtime.*/
 280         bool sdvo_tv_clock;
 281
 282         /*
 283          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 284          * required. This is set in the 2nd loop of calling encoder's
 285          * ->compute_config if the first pick doesn't work out.
 286          */
 287         bool bw_constrained;
 288
 289         /* Settings for the intel dpll used on pretty much everything but
 290          * haswell. */
 291         struct dpll dpll;
 292
 293         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 294         enum intel_dpll_id shared_dpll;
 295
 296         /* Actual register state of the dpll, for shared dpll cross-checking. */
 297         struct intel_dpll_hw_state dpll_hw_state;
 298
 299         int pipe_bpp;
 300         struct intel_link_m_n dp_m_n;
 301
 302         /*
 303          * Frequence the dpll for the port should run at. Differs from the
 304          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 305          * already multiplied by pixel_multiplier.
 306          */
 307         int port_clock;
 308
 309         /* Used by SDVO (and if we ever fix it, HDMI). */
 310         unsigned pixel_multiplier;
 311
 312         /* Panel fitter controls for gen2-gen4 + VLV */
 313         struct {
 314                 u32 control;
 315                 u32 pgm_ratios;
 316                 u32 lvds_border_bits;
 317         } gmch_pfit;
 318
 319         /* Panel fitter placement and size for Ironlake+ */
 320         struct {
 321                 u32 pos;
 322                 u32 size;
 323                 bool enabled;
 324         } pch_pfit;
 325
 326         /* FDI configuration, only valid if has_pch_encoder is set. */
 327         int fdi_lanes;
 328         struct intel_link_m_n fdi_m_n;
 329
 330         bool ips_enabled;
 331
 332         bool double_wide;
 333 };
 334
 335 struct intel_pipe_wm {
 336         struct intel_wm_level wm[5];
 337         uint32_t linetime;
 338         bool fbc_wm_enabled;
 339 };
 340
 341 struct intel_crtc {
 342         struct drm_crtc base;
 343         enum pipe pipe;
 344         enum plane plane;
 345         u8 lut_r[256], lut_g[256], lut_b[256];
 346         /*
 347          * Whether the crtc and the connected output pipeline is active. Implies
 348          * that crtc->enabled is set, i.e. the current mode configuration has
 349          * some outputs connected to this crtc.
 350          */
 351         bool active;
 352         unsigned long enabled_power_domains;
 353         bool eld_vld;
 354         bool primary_enabled; /* is the primary plane (partially) visible? */
 355         bool lowfreq_avail;
 356         struct intel_overlay *overlay;
 357         struct intel_unpin_work *unpin_work;
 358
 359         atomic_t unpin_work_count;
 360
 361         /* Display surface base address adjustement for pageflips. Note that on
 362          * gen4+ this only adjusts up to a tile, offsets within a tile are
 363          * handled in the hw itself (with the TILEOFF register). */
 364         unsigned long dspaddr_offset;
 365
 366         struct drm_i915_gem_object *cursor_bo;
 367         uint32_t cursor_addr;
 368         int16_t cursor_x, cursor_y;
 369         int16_t cursor_width, cursor_height;
 370         bool cursor_visible;
 371
 372         struct intel_plane_config plane_config;
 373         struct intel_crtc_config config;
 374         struct intel_crtc_config *new_config;
 375         bool new_enabled;
 376
 377         uint32_t ddi_pll_sel;
 378
 379         /* reset counter value when the last flip was submitted */
 380         unsigned int reset_counter;
 381
 382         /* Access to these should be protected by dev_priv->irq_lock. */
 383         bool cpu_fifo_underrun_disabled;
 384         bool pch_fifo_underrun_disabled;
 385
 386         /* per-pipe watermark state */
 387         struct {
 388                 /* watermarks currently being used  */
 389                 struct intel_pipe_wm active;
 390         } wm;
 391 };
 392
 393 struct intel_plane_wm_parameters {
 394         uint32_t horiz_pixels;
 395         uint8_t bytes_per_pixel;
 396         bool enabled;
 397         bool scaled;
 398 };
 399
 400 struct intel_plane {
 401         struct drm_plane base;
 402         int plane;
 403         enum pipe pipe;
 404         struct drm_i915_gem_object *obj;
 405         bool can_scale;
 406         int max_downscale;
 407         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 408         int crtc_x, crtc_y;
 409         unsigned int crtc_w, crtc_h;
 410         uint32_t src_x, src_y;
 411         uint32_t src_w, src_h;
 412
 413         /* Since we need to change the watermarks before/after
 414          * enabling/disabling the planes, we need to store the parameters here
 415          * as the other pieces of the struct may not reflect the values we want
 416          * for the watermark calculations. Currently only Haswell uses this.
 417          */
 418         struct intel_plane_wm_parameters wm;
 419
 420         void (*update_plane)(struct drm_plane *plane,
 421                              struct drm_crtc *crtc,
 422                              struct drm_framebuffer *fb,
 423                              struct drm_i915_gem_object *obj,
 424                              int crtc_x, int crtc_y,
 425                              unsigned int crtc_w, unsigned int crtc_h,
 426                              uint32_t x, uint32_t y,
 427                              uint32_t src_w, uint32_t src_h);
 428         void (*disable_plane)(struct drm_plane *plane,
 429                               struct drm_crtc *crtc);
 430         int (*update_colorkey)(struct drm_plane *plane,
 431                                struct drm_intel_sprite_colorkey *key);
 432         void (*get_colorkey)(struct drm_plane *plane,
 433                              struct drm_intel_sprite_colorkey *key);
 434 };
 435
 436 struct intel_watermark_params {
 437         unsigned long fifo_size;
 438         unsigned long max_wm;
 439         unsigned long default_wm;
 440         unsigned long guard_size;
 441         unsigned long cacheline_size;
 442 };
 443
 444 struct cxsr_latency {
 445         int is_desktop;
 446         int is_ddr3;
 447         unsigned long fsb_freq;
 448         unsigned long mem_freq;
 449         unsigned long display_sr;
 450         unsigned long display_hpll_disable;
 451         unsigned long cursor_sr;
 452         unsigned long cursor_hpll_disable;
 453 };
 454
 455 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 456 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 457 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 458 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 459 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 460
 461 struct intel_hdmi {
 462         u32 hdmi_reg;
 463         int ddc_bus;
 464         uint32_t color_range;
 465         bool color_range_auto;
 466         bool has_hdmi_sink;
 467         bool has_audio;
 468         enum hdmi_force_audio force_audio;
 469         bool rgb_quant_range_selectable;
 470         void (*write_infoframe)(struct drm_encoder *encoder,
 471                                 enum hdmi_infoframe_type type,
 472                                 const void *frame, ssize_t len);
 473         void (*set_infoframes)(struct drm_encoder *encoder,
 474                                struct drm_display_mode *adjusted_mode);
 475 };
 476
 477 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 478
 479 struct intel_dp {
 480         uint32_t output_reg;
 481         uint32_t aux_ch_ctl_reg;
 482         uint32_t DP;
 483         bool has_audio;
 484         enum hdmi_force_audio force_audio;
 485         uint32_t color_range;
 486         bool color_range_auto;
 487         uint8_t link_bw;
 488         uint8_t lane_count;
 489         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 490         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 491         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 492         struct drm_dp_aux aux;
 493         uint8_t train_set[4];
 494         int panel_power_up_delay;
 495         int panel_power_down_delay;
 496         int panel_power_cycle_delay;
 497         int backlight_on_delay;
 498         int backlight_off_delay;
 499         struct delayed_work panel_vdd_work;
 500         bool want_panel_vdd;
 501         unsigned long last_power_cycle;
 502         unsigned long last_power_on;
 503         unsigned long last_backlight_off;
 504         bool psr_setup_done;
 505         bool use_tps3;
 506         struct intel_connector *attached_connector;
 507
 508         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 509         /*
 510          * This function returns the value we have to program the AUX_CTL
 511          * register with to kick off an AUX transaction.
 512          */
 513         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 514                                      bool has_aux_irq,
 515                                      int send_bytes,
 516                                      uint32_t aux_clock_divider);
 517 };
 518
 519 struct intel_digital_port {
 520         struct intel_encoder base;
 521         enum port port;
 522         u32 saved_port_bits;
 523         struct intel_dp dp;
 524         struct intel_hdmi hdmi;
 525 };
 526
 527 static inline int
 528 vlv_dport_to_channel(struct intel_digital_port *dport)
 529 {
 530         switch (dport->port) {
 531         case PORT_B:
 532                 return DPIO_CH0;
 533         case PORT_C:
 534                 return DPIO_CH1;
 535         default:
 536                 BUG();
 537         }
 538 }
 539
 540 static inline struct drm_crtc *
 541 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 542 {
 543         struct drm_i915_private *dev_priv = dev->dev_private;
 544         return dev_priv->pipe_to_crtc_mapping[pipe];
 545 }
 546
 547 static inline struct drm_crtc *
 548 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 549 {
 550         struct drm_i915_private *dev_priv = dev->dev_private;
 551         return dev_priv->plane_to_crtc_mapping[plane];
 552 }
 553
 554 struct intel_unpin_work {
 555         struct work_struct work;
 556         struct drm_crtc *crtc;
 557         struct drm_i915_gem_object *old_fb_obj;
 558         struct drm_i915_gem_object *pending_flip_obj;
 559         struct drm_pending_vblank_event *event;
 560         atomic_t pending;
 561 #define INTEL_FLIP_INACTIVE     0
 562 #define INTEL_FLIP_PENDING      1
 563 #define INTEL_FLIP_COMPLETE     2
 564         bool enable_stall_check;
 565 };
 566
 567 struct intel_set_config {
 568         struct drm_encoder **save_connector_encoders;
 569         struct drm_crtc **save_encoder_crtcs;
 570         bool *save_crtc_enabled;
 571
 572         bool fb_changed;
 573         bool mode_changed;
 574 };
 575
 576 struct intel_load_detect_pipe {
 577         struct drm_framebuffer *release_fb;
 578         bool load_detect_temp;
 579         int dpms_mode;
 580 };
 581
 582 static inline struct intel_encoder *
 583 intel_attached_encoder(struct drm_connector *connector)
 584 {
 585         return to_intel_connector(connector)->encoder;
 586 }
 587
 588 static inline struct intel_digital_port *
 589 enc_to_dig_port(struct drm_encoder *encoder)
 590 {
 591         return container_of(encoder, struct intel_digital_port, base.base);
 592 }
 593
 594 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 595 {
 596         return &enc_to_dig_port(encoder)->dp;
 597 }
 598
 599 static inline struct intel_digital_port *
 600 dp_to_dig_port(struct intel_dp *intel_dp)
 601 {
 602         return container_of(intel_dp, struct intel_digital_port, dp);
 603 }
 604
 605 static inline struct intel_digital_port *
 606 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 607 {
 608         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 609 }
 610
 611
 612 /* i915_irq.c */
 613 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 614                                            enum pipe pipe, bool enable);
 615 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 616                                              enum pipe pipe, bool enable);
 617 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 618                                            enum transcoder pch_transcoder,
 619                                            bool enable);
 620 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 621 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 622 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 623 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 624 void hsw_pc8_disable_interrupts(struct drm_device *dev);
 625 void hsw_pc8_restore_interrupts(struct drm_device *dev);
 626
 627
 628 /* intel_crt.c */
 629 void intel_crt_init(struct drm_device *dev);
 630
 631
 632 /* intel_ddi.c */
 633 void intel_prepare_ddi(struct drm_device *dev);
 634 void hsw_fdi_link_train(struct drm_crtc *crtc);
 635 void intel_ddi_init(struct drm_device *dev, enum port port);
 636 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 637 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 638 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 639 void intel_ddi_pll_init(struct drm_device *dev);
 640 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 641 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 642                                        enum transcoder cpu_transcoder);
 643 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 644 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 645 void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 646 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 647 void intel_ddi_pll_enable(struct intel_crtc *crtc);
 648 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 649 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 650 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 651 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 652 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 653 void intel_ddi_get_config(struct intel_encoder *encoder,
 654                           struct intel_crtc_config *pipe_config);
 655
 656
 657 /* intel_display.c */
 658 const char *intel_output_name(int output);
 659 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 660 int intel_pch_rawclk(struct drm_device *dev);
 661 void intel_mark_busy(struct drm_device *dev);
 662 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 663                         struct intel_ring_buffer *ring);
 664 void intel_mark_idle(struct drm_device *dev);
 665 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 666 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 667 void intel_encoder_destroy(struct drm_encoder *encoder);
 668 void intel_connector_dpms(struct drm_connector *, int mode);
 669 bool intel_connector_get_hw_state(struct intel_connector *connector);
 670 void intel_modeset_check_state(struct drm_device *dev);
 671 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 672                                 struct intel_digital_port *port);
 673 void intel_connector_attach_encoder(struct intel_connector *connector,
 674                                     struct intel_encoder *encoder);
 675 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 676 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 677                                              struct drm_crtc *crtc);
 678 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 679 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 680                                 struct drm_file *file_priv);
 681 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 682                                              enum pipe pipe);
 683 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 684 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 685 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 686 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 687                          struct intel_digital_port *dport);
 688 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 689                                 struct drm_display_mode *mode,
 690                                 struct intel_load_detect_pipe *old);
 691 void intel_release_load_detect_pipe(struct drm_connector *connector,
 692                                     struct intel_load_detect_pipe *old);
 693 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 694                                struct drm_i915_gem_object *obj,
 695                                struct intel_ring_buffer *pipelined);
 696 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 697 struct drm_framebuffer *
 698 __intel_framebuffer_create(struct drm_device *dev,
 699                            struct drm_mode_fb_cmd2 *mode_cmd,
 700                            struct drm_i915_gem_object *obj);
 701 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 702 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 703 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 704 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 705 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 706                         struct intel_shared_dpll *pll,
 707                         bool state);
 708 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 709 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 710 void assert_pll(struct drm_i915_private *dev_priv,
 711                 enum pipe pipe, bool state);
 712 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 713 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 714 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 715                        enum pipe pipe, bool state);
 716 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 717 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 718 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 719 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 720 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 721 void intel_write_eld(struct drm_encoder *encoder,
 722                      struct drm_display_mode *mode);
 723 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 724                                              unsigned int tiling_mode,
 725                                              unsigned int bpp,
 726                                              unsigned int pitch);
 727 void intel_display_handle_reset(struct drm_device *dev);
 728 void __hsw_do_enable_pc8(struct drm_i915_private *dev_priv);
 729 void __hsw_do_disable_pc8(struct drm_i915_private *dev_priv);
 730 void intel_dp_get_m_n(struct intel_crtc *crtc,
 731                       struct intel_crtc_config *pipe_config);
 732 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 733 void
 734 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 735                                 int dotclock);
 736 bool intel_crtc_active(struct drm_crtc *crtc);
 737 void hsw_enable_ips(struct intel_crtc *crtc);
 738 void hsw_disable_ips(struct intel_crtc *crtc);
 739 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
 740 enum intel_display_power_domain
 741 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 742 int valleyview_get_vco(struct drm_i915_private *dev_priv);
 743 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 744                                  struct intel_crtc_config *pipe_config);
 745 int intel_format_to_fourcc(int format);
 746
 747 /* intel_dp.c */
 748 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 749 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 750                              struct intel_connector *intel_connector);
 751 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 752 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 753 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 754 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 755 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 756 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 757 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 758 bool intel_dp_compute_config(struct intel_encoder *encoder,
 759                              struct intel_crtc_config *pipe_config);
 760 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 761 void intel_edp_backlight_on(struct intel_dp *intel_dp);
 762 void intel_edp_backlight_off(struct intel_dp *intel_dp);
 763 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 764 void intel_edp_panel_on(struct intel_dp *intel_dp);
 765 void intel_edp_panel_off(struct intel_dp *intel_dp);
 766 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 767 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 768 void intel_edp_psr_update(struct drm_device *dev);
 769
 770
 771 /* intel_dsi.c */
 772 bool intel_dsi_init(struct drm_device *dev);
 773
 774
 775 /* intel_dvo.c */
 776 void intel_dvo_init(struct drm_device *dev);
 777
 778
 779 /* legacy fbdev emulation in intel_fbdev.c */
 780 #ifdef CONFIG_DRM_I915_FBDEV
 781 extern int intel_fbdev_init(struct drm_device *dev);
 782 extern void intel_fbdev_initial_config(struct drm_device *dev);
 783 extern void intel_fbdev_fini(struct drm_device *dev);
 784 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 785 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 786 extern void intel_fbdev_restore_mode(struct drm_device *dev);
 787 #else
 788 static inline int intel_fbdev_init(struct drm_device *dev)
 789 {
 790         return 0;
 791 }
 792
 793 static inline void intel_fbdev_initial_config(struct drm_device *dev)
 794 {
 795 }
 796
 797 static inline void intel_fbdev_fini(struct drm_device *dev)
 798 {
 799 }
 800
 801 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
 802 {
 803 }
 804
 805 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 806 {
 807 }
 808 #endif
 809
 810 /* intel_hdmi.c */
 811 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 812 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 813                                struct intel_connector *intel_connector);
 814 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 815 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 816                                struct intel_crtc_config *pipe_config);
 817
 818
 819 /* intel_lvds.c */
 820 void intel_lvds_init(struct drm_device *dev);
 821 bool intel_is_dual_link_lvds(struct drm_device *dev);
 822
 823
 824 /* intel_modes.c */
 825 int intel_connector_update_modes(struct drm_connector *connector,
 826                                  struct edid *edid);
 827 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 828 void intel_attach_force_audio_property(struct drm_connector *connector);
 829 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 830
 831
 832 /* intel_overlay.c */
 833 void intel_setup_overlay(struct drm_device *dev);
 834 void intel_cleanup_overlay(struct drm_device *dev);
 835 int intel_overlay_switch_off(struct intel_overlay *overlay);
 836 int intel_overlay_put_image(struct drm_device *dev, void *data,
 837                             struct drm_file *file_priv);
 838 int intel_overlay_attrs(struct drm_device *dev, void *data,
 839                         struct drm_file *file_priv);
 840
 841
 842 /* intel_panel.c */
 843 int intel_panel_init(struct intel_panel *panel,
 844                      struct drm_display_mode *fixed_mode,
 845                      struct drm_display_mode *downclock_mode);
 846 void intel_panel_fini(struct intel_panel *panel);
 847 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
 848                             struct drm_display_mode *adjusted_mode);
 849 void intel_pch_panel_fitting(struct intel_crtc *crtc,
 850                              struct intel_crtc_config *pipe_config,
 851                              int fitting_mode);
 852 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 853                               struct intel_crtc_config *pipe_config,
 854                               int fitting_mode);
 855 void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
 856                                u32 max);
 857 int intel_panel_setup_backlight(struct drm_connector *connector);
 858 void intel_panel_enable_backlight(struct intel_connector *connector);
 859 void intel_panel_disable_backlight(struct intel_connector *connector);
 860 void intel_panel_destroy_backlight(struct drm_connector *connector);
 861 void intel_panel_init_backlight_funcs(struct drm_device *dev);
 862 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 863 extern struct drm_display_mode *intel_find_panel_downclock(
 864                                 struct drm_device *dev,
 865                                 struct drm_display_mode *fixed_mode,
 866                                 struct drm_connector *connector);
 867
 868 /* intel_pm.c */
 869 void intel_init_clock_gating(struct drm_device *dev);
 870 void intel_suspend_hw(struct drm_device *dev);
 871 void intel_update_watermarks(struct drm_crtc *crtc);
 872 void intel_update_sprite_watermarks(struct drm_plane *plane,
 873                                     struct drm_crtc *crtc,
 874                                     uint32_t sprite_width, int pixel_size,
 875                                     bool enabled, bool scaled);
 876 void intel_init_pm(struct drm_device *dev);
 877 void intel_pm_setup(struct drm_device *dev);
 878 bool intel_fbc_enabled(struct drm_device *dev);
 879 void intel_update_fbc(struct drm_device *dev);
 880 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 881 void intel_gpu_ips_teardown(void);
 882 int intel_power_domains_init(struct drm_i915_private *);
 883 void intel_power_domains_remove(struct drm_i915_private *);
 884 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
 885                                  enum intel_display_power_domain domain);
 886 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
 887                                     enum intel_display_power_domain domain);
 888 void intel_display_power_get(struct drm_i915_private *dev_priv,
 889                              enum intel_display_power_domain domain);
 890 void intel_display_power_put(struct drm_i915_private *dev_priv,
 891                              enum intel_display_power_domain domain);
 892 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
 893 void intel_enable_gt_powersave(struct drm_device *dev);
 894 void intel_disable_gt_powersave(struct drm_device *dev);
 895 void ironlake_teardown_rc6(struct drm_device *dev);
 896 void gen6_update_ring_freq(struct drm_device *dev);
 897 void gen6_rps_idle(struct drm_i915_private *dev_priv);
 898 void gen6_rps_boost(struct drm_i915_private *dev_priv);
 899 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
 900 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 901 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
 902 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
 903 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
 904 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
 905 void ilk_wm_get_hw_state(struct drm_device *dev);
 906
 907
 908 /* intel_sdvo.c */
 909 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
 910
 911
 912 /* intel_sprite.c */
 913 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 914 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 915                                enum plane plane);
 916 void intel_plane_restore(struct drm_plane *plane);
 917 void intel_plane_disable(struct drm_plane *plane);
 918 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 919                               struct drm_file *file_priv);
 920 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 921                               struct drm_file *file_priv);
 922
 923
 924 /* intel_tv.c */
 925 void intel_tv_init(struct drm_device *dev);
 926
 927 #endif /* __INTEL_DRV_H__ */