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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
32 #include "i915_drv.h"
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
39
40 /**
41 * _wait_for - magic (register) wait macro
42 *
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
47 */
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
50 int ret__ = 0; \
51 while (!(COND)) { \
52 if (time_after(jiffies, timeout__)) { \
53 if (!(COND)) \
54 ret__ = -ETIMEDOUT; \
55 break; \
56 } \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
59 } else { \
60 cpu_relax(); \
61 } \
62 } \
63 ret__; \
64 })
65
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
70
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
73
74 /*
75 * Display related stuff
76 */
77
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
81 #define MAX_OUTPUTS 6
82 /* maximum connectors per crtcs in the mode set */
83
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
89
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
92
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type {
96 INTEL_OUTPUT_UNUSED = 0,
97 INTEL_OUTPUT_ANALOG = 1,
98 INTEL_OUTPUT_DVO = 2,
99 INTEL_OUTPUT_SDVO = 3,
100 INTEL_OUTPUT_LVDS = 4,
101 INTEL_OUTPUT_TVOUT = 5,
102 INTEL_OUTPUT_HDMI = 6,
103 INTEL_OUTPUT_DISPLAYPORT = 7,
104 INTEL_OUTPUT_EDP = 8,
105 INTEL_OUTPUT_DSI = 9,
106 INTEL_OUTPUT_UNKNOWN = 10,
107 INTEL_OUTPUT_DP_MST = 11,
108 };
109
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
114
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
117
118 struct intel_framebuffer {
119 struct drm_framebuffer base;
120 struct drm_i915_gem_object *obj;
121 };
122
123 struct intel_fbdev {
124 struct drm_fb_helper helper;
125 struct intel_framebuffer *fb;
126 struct list_head fbdev_list;
127 struct drm_display_mode *our_mode;
128 int preferred_bpp;
129 };
130
131 struct intel_encoder {
132 struct drm_encoder base;
133 /*
134 * The new crtc this encoder will be driven from. Only differs from
135 * base->crtc while a modeset is in progress.
136 */
137 struct intel_crtc *new_crtc;
138
139 enum intel_output_type type;
140 unsigned int cloneable;
141 bool connectors_active;
142 void (*hot_plug)(struct intel_encoder *);
143 bool (*compute_config)(struct intel_encoder *,
144 struct intel_crtc_state *);
145 void (*pre_pll_enable)(struct intel_encoder *);
146 void (*pre_enable)(struct intel_encoder *);
147 void (*enable)(struct intel_encoder *);
148 void (*mode_set)(struct intel_encoder *intel_encoder);
149 void (*disable)(struct intel_encoder *);
150 void (*post_disable)(struct intel_encoder *);
151 /* Read out the current hw state of this connector, returning true if
152 * the encoder is active. If the encoder is enabled it also set the pipe
153 * it is connected to in the pipe parameter. */
154 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
155 /* Reconstructs the equivalent mode flags for the current hardware
156 * state. This must be called _after_ display->get_pipe_config has
157 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
158 * be set correctly before calling this function. */
159 void (*get_config)(struct intel_encoder *,
160 struct intel_crtc_state *pipe_config);
161 /*
162 * Called during system suspend after all pending requests for the
163 * encoder are flushed (for example for DP AUX transactions) and
164 * device interrupts are disabled.
165 */
166 void (*suspend)(struct intel_encoder *);
167 int crtc_mask;
168 enum hpd_pin hpd_pin;
169 };
170
171 struct intel_panel {
172 struct drm_display_mode *fixed_mode;
173 struct drm_display_mode *downclock_mode;
174 int fitting_mode;
175
176 /* backlight */
177 struct {
178 bool present;
179 u32 level;
180 u32 min;
181 u32 max;
182 bool enabled;
183 bool combination_mode; /* gen 2/4 only */
184 bool active_low_pwm;
185 struct backlight_device *device;
186 } backlight;
187
188 void (*backlight_power)(struct intel_connector *, bool enable);
189 };
190
191 struct intel_connector {
192 struct drm_connector base;
193 /*
194 * The fixed encoder this connector is connected to.
195 */
196 struct intel_encoder *encoder;
197
198 /*
199 * The new encoder this connector will be driven. Only differs from
200 * encoder while a modeset is in progress.
201 */
202 struct intel_encoder *new_encoder;
203
204 /* Reads out the current hw, returning true if the connector is enabled
205 * and active (i.e. dpms ON state). */
206 bool (*get_hw_state)(struct intel_connector *);
207
208 /*
209 * Removes all interfaces through which the connector is accessible
210 * - like sysfs, debugfs entries -, so that no new operations can be
211 * started on the connector. Also makes sure all currently pending
212 * operations finish before returing.
213 */
214 void (*unregister)(struct intel_connector *);
215
216 /* Panel info for eDP and LVDS */
217 struct intel_panel panel;
218
219 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
220 struct edid *edid;
221 struct edid *detect_edid;
222
223 /* since POLL and HPD connectors may use the same HPD line keep the native
224 state of connector->polled in case hotplug storm detection changes it */
225 u8 polled;
226
227 void *port; /* store this opaque as its illegal to dereference it */
228
229 struct intel_dp *mst_port;
230 };
231
232 typedef struct dpll {
233 /* given values */
234 int n;
235 int m1, m2;
236 int p1, p2;
237 /* derived values */
238 int dot;
239 int vco;
240 int m;
241 int p;
242 } intel_clock_t;
243
244 struct intel_atomic_state {
245 struct drm_atomic_state base;
246
247 unsigned int cdclk;
248 bool dpll_set;
249 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
250 };
251
252 struct intel_plane_state {
253 struct drm_plane_state base;
254 struct drm_rect src;
255 struct drm_rect dst;
256 struct drm_rect clip;
257 bool visible;
258
259 /*
260 * scaler_id
261 * = -1 : not using a scaler
262 * >= 0 : using a scalers
263 *
264 * plane requiring a scaler:
265 * - During check_plane, its bit is set in
266 * crtc_state->scaler_state.scaler_users by calling helper function
267 * update_scaler_plane.
268 * - scaler_id indicates the scaler it got assigned.
269 *
270 * plane doesn't require a scaler:
271 * - this can happen when scaling is no more required or plane simply
272 * got disabled.
273 * - During check_plane, corresponding bit is reset in
274 * crtc_state->scaler_state.scaler_users by calling helper function
275 * update_scaler_plane.
276 */
277 int scaler_id;
278
279 struct drm_intel_sprite_colorkey ckey;
280 };
281
282 struct intel_initial_plane_config {
283 struct intel_framebuffer *fb;
284 unsigned int tiling;
285 int size;
286 u32 base;
287 };
288
289 #define SKL_MIN_SRC_W 8
290 #define SKL_MAX_SRC_W 4096
291 #define SKL_MIN_SRC_H 8
292 #define SKL_MAX_SRC_H 4096
293 #define SKL_MIN_DST_W 8
294 #define SKL_MAX_DST_W 4096
295 #define SKL_MIN_DST_H 8
296 #define SKL_MAX_DST_H 4096
297
298 struct intel_scaler {
299 int in_use;
300 uint32_t mode;
301 };
302
303 struct intel_crtc_scaler_state {
304 #define SKL_NUM_SCALERS 2
305 struct intel_scaler scalers[SKL_NUM_SCALERS];
306
307 /*
308 * scaler_users: keeps track of users requesting scalers on this crtc.
309 *
310 * If a bit is set, a user is using a scaler.
311 * Here user can be a plane or crtc as defined below:
312 * bits 0-30 - plane (bit position is index from drm_plane_index)
313 * bit 31 - crtc
314 *
315 * Instead of creating a new index to cover planes and crtc, using
316 * existing drm_plane_index for planes which is well less than 31
317 * planes and bit 31 for crtc. This should be fine to cover all
318 * our platforms.
319 *
320 * intel_atomic_setup_scalers will setup available scalers to users
321 * requesting scalers. It will gracefully fail if request exceeds
322 * avilability.
323 */
324 #define SKL_CRTC_INDEX 31
325 unsigned scaler_users;
326
327 /* scaler used by crtc for panel fitting purpose */
328 int scaler_id;
329 };
330
331 struct intel_crtc_state {
332 struct drm_crtc_state base;
333
334 /**
335 * quirks - bitfield with hw state readout quirks
336 *
337 * For various reasons the hw state readout code might not be able to
338 * completely faithfully read out the current state. These cases are
339 * tracked with quirk flags so that fastboot and state checker can act
340 * accordingly.
341 */
342 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
343 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
344 #define PIPE_CONFIG_QUIRK_INITIAL_PLANES (1<<2) /* planes are in unknown state */
345 unsigned long quirks;
346
347 /* Pipe source size (ie. panel fitter input size)
348 * All planes will be positioned inside this space,
349 * and get clipped at the edges. */
350 int pipe_src_w, pipe_src_h;
351
352 /* Whether to set up the PCH/FDI. Note that we never allow sharing
353 * between pch encoders and cpu encoders. */
354 bool has_pch_encoder;
355
356 /* Are we sending infoframes on the attached port */
357 bool has_infoframe;
358
359 /* CPU Transcoder for the pipe. Currently this can only differ from the
360 * pipe on Haswell (where we have a special eDP transcoder). */
361 enum transcoder cpu_transcoder;
362
363 /*
364 * Use reduced/limited/broadcast rbg range, compressing from the full
365 * range fed into the crtcs.
366 */
367 bool limited_color_range;
368
369 /* DP has a bunch of special case unfortunately, so mark the pipe
370 * accordingly. */
371 bool has_dp_encoder;
372
373 /* Whether we should send NULL infoframes. Required for audio. */
374 bool has_hdmi_sink;
375
376 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
377 * has_dp_encoder is set. */
378 bool has_audio;
379
380 /*
381 * Enable dithering, used when the selected pipe bpp doesn't match the
382 * plane bpp.
383 */
384 bool dither;
385
386 /* Controls for the clock computation, to override various stages. */
387 bool clock_set;
388
389 /* SDVO TV has a bunch of special case. To make multifunction encoders
390 * work correctly, we need to track this at runtime.*/
391 bool sdvo_tv_clock;
392
393 /*
394 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
395 * required. This is set in the 2nd loop of calling encoder's
396 * ->compute_config if the first pick doesn't work out.
397 */
398 bool bw_constrained;
399
400 /* Settings for the intel dpll used on pretty much everything but
401 * haswell. */
402 struct dpll dpll;
403
404 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
405 enum intel_dpll_id shared_dpll;
406
407 /*
408 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
409 * - enum skl_dpll on SKL
410 */
411 uint32_t ddi_pll_sel;
412
413 /* Actual register state of the dpll, for shared dpll cross-checking. */
414 struct intel_dpll_hw_state dpll_hw_state;
415
416 int pipe_bpp;
417 struct intel_link_m_n dp_m_n;
418
419 /* m2_n2 for eDP downclock */
420 struct intel_link_m_n dp_m2_n2;
421 bool has_drrs;
422
423 /*
424 * Frequence the dpll for the port should run at. Differs from the
425 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
426 * already multiplied by pixel_multiplier.
427 */
428 int port_clock;
429
430 /* Used by SDVO (and if we ever fix it, HDMI). */
431 unsigned pixel_multiplier;
432
433 /* Panel fitter controls for gen2-gen4 + VLV */
434 struct {
435 u32 control;
436 u32 pgm_ratios;
437 u32 lvds_border_bits;
438 } gmch_pfit;
439
440 /* Panel fitter placement and size for Ironlake+ */
441 struct {
442 u32 pos;
443 u32 size;
444 bool enabled;
445 bool force_thru;
446 } pch_pfit;
447
448 /* FDI configuration, only valid if has_pch_encoder is set. */
449 int fdi_lanes;
450 struct intel_link_m_n fdi_m_n;
451
452 bool ips_enabled;
453
454 bool double_wide;
455
456 bool dp_encoder_is_mst;
457 int pbn;
458
459 struct intel_crtc_scaler_state scaler_state;
460
461 /* w/a for waiting 2 vblanks during crtc enable */
462 enum pipe hsw_workaround_pipe;
463 };
464
465 struct intel_pipe_wm {
466 struct intel_wm_level wm[5];
467 uint32_t linetime;
468 bool fbc_wm_enabled;
469 bool pipe_enabled;
470 bool sprites_enabled;
471 bool sprites_scaled;
472 };
473
474 struct intel_mmio_flip {
475 struct work_struct work;
476 struct drm_i915_private *i915;
477 struct drm_i915_gem_request *req;
478 struct intel_crtc *crtc;
479 };
480
481 struct skl_pipe_wm {
482 struct skl_wm_level wm[8];
483 struct skl_wm_level trans_wm;
484 uint32_t linetime;
485 };
486
487 /*
488 * Tracking of operations that need to be performed at the beginning/end of an
489 * atomic commit, outside the atomic section where interrupts are disabled.
490 * These are generally operations that grab mutexes or might otherwise sleep
491 * and thus can't be run with interrupts disabled.
492 */
493 struct intel_crtc_atomic_commit {
494 /* vblank evasion */
495 bool evade;
496 unsigned start_vbl_count;
497
498 /* Sleepable operations to perform before commit */
499 bool wait_for_flips;
500 bool disable_fbc;
501 bool pre_disable_primary;
502 bool update_wm;
503 unsigned disabled_planes;
504
505 /* Sleepable operations to perform after commit */
506 unsigned fb_bits;
507 bool wait_vblank;
508 bool update_fbc;
509 bool post_enable_primary;
510 unsigned update_sprite_watermarks;
511 };
512
513 struct intel_crtc {
514 struct drm_crtc base;
515 enum pipe pipe;
516 enum plane plane;
517 u8 lut_r[256], lut_g[256], lut_b[256];
518 /*
519 * Whether the crtc and the connected output pipeline is active. Implies
520 * that crtc->enabled is set, i.e. the current mode configuration has
521 * some outputs connected to this crtc.
522 */
523 bool active;
524 unsigned long enabled_power_domains;
525 bool lowfreq_avail;
526 struct intel_overlay *overlay;
527 struct intel_unpin_work *unpin_work;
528
529 atomic_t unpin_work_count;
530
531 /* Display surface base address adjustement for pageflips. Note that on
532 * gen4+ this only adjusts up to a tile, offsets within a tile are
533 * handled in the hw itself (with the TILEOFF register). */
534 unsigned long dspaddr_offset;
535
536 struct drm_i915_gem_object *cursor_bo;
537 uint32_t cursor_addr;
538 uint32_t cursor_cntl;
539 uint32_t cursor_size;
540 uint32_t cursor_base;
541
542 struct intel_initial_plane_config plane_config;
543 struct intel_crtc_state *config;
544 bool new_enabled;
545
546 /* reset counter value when the last flip was submitted */
547 unsigned int reset_counter;
548
549 /* Access to these should be protected by dev_priv->irq_lock. */
550 bool cpu_fifo_underrun_disabled;
551 bool pch_fifo_underrun_disabled;
552
553 /* per-pipe watermark state */
554 struct {
555 /* watermarks currently being used */
556 struct intel_pipe_wm active;
557 /* SKL wm values currently in use */
558 struct skl_pipe_wm skl_active;
559 } wm;
560
561 int scanline_offset;
562
563 struct intel_crtc_atomic_commit atomic;
564
565 /* scalers available on this crtc */
566 int num_scalers;
567 };
568
569 struct intel_plane_wm_parameters {
570 uint32_t horiz_pixels;
571 uint32_t vert_pixels;
572 /*
573 * For packed pixel formats:
574 * bytes_per_pixel - holds bytes per pixel
575 * For planar pixel formats:
576 * bytes_per_pixel - holds bytes per pixel for uv-plane
577 * y_bytes_per_pixel - holds bytes per pixel for y-plane
578 */
579 uint8_t bytes_per_pixel;
580 uint8_t y_bytes_per_pixel;
581 bool enabled;
582 bool scaled;
583 u64 tiling;
584 unsigned int rotation;
585 };
586
587 struct intel_plane {
588 struct drm_plane base;
589 int plane;
590 enum pipe pipe;
591 bool can_scale;
592 int max_downscale;
593
594 /* Since we need to change the watermarks before/after
595 * enabling/disabling the planes, we need to store the parameters here
596 * as the other pieces of the struct may not reflect the values we want
597 * for the watermark calculations. Currently only Haswell uses this.
598 */
599 struct intel_plane_wm_parameters wm;
600
601 /*
602 * NOTE: Do not place new plane state fields here (e.g., when adding
603 * new plane properties). New runtime state should now be placed in
604 * the intel_plane_state structure and accessed via drm_plane->state.
605 */
606
607 void (*update_plane)(struct drm_plane *plane,
608 struct drm_crtc *crtc,
609 struct drm_framebuffer *fb,
610 int crtc_x, int crtc_y,
611 unsigned int crtc_w, unsigned int crtc_h,
612 uint32_t x, uint32_t y,
613 uint32_t src_w, uint32_t src_h);
614 void (*disable_plane)(struct drm_plane *plane,
615 struct drm_crtc *crtc);
616 int (*check_plane)(struct drm_plane *plane,
617 struct intel_crtc_state *crtc_state,
618 struct intel_plane_state *state);
619 void (*commit_plane)(struct drm_plane *plane,
620 struct intel_plane_state *state);
621 };
622
623 struct intel_watermark_params {
624 unsigned long fifo_size;
625 unsigned long max_wm;
626 unsigned long default_wm;
627 unsigned long guard_size;
628 unsigned long cacheline_size;
629 };
630
631 struct cxsr_latency {
632 int is_desktop;
633 int is_ddr3;
634 unsigned long fsb_freq;
635 unsigned long mem_freq;
636 unsigned long display_sr;
637 unsigned long display_hpll_disable;
638 unsigned long cursor_sr;
639 unsigned long cursor_hpll_disable;
640 };
641
642 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
643 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
644 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
645 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
646 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
647 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
648 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
649 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
650 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
651
652 struct intel_hdmi {
653 u32 hdmi_reg;
654 int ddc_bus;
655 uint32_t color_range;
656 bool color_range_auto;
657 bool has_hdmi_sink;
658 bool has_audio;
659 enum hdmi_force_audio force_audio;
660 bool rgb_quant_range_selectable;
661 enum hdmi_picture_aspect aspect_ratio;
662 void (*write_infoframe)(struct drm_encoder *encoder,
663 enum hdmi_infoframe_type type,
664 const void *frame, ssize_t len);
665 void (*set_infoframes)(struct drm_encoder *encoder,
666 bool enable,
667 struct drm_display_mode *adjusted_mode);
668 bool (*infoframe_enabled)(struct drm_encoder *encoder);
669 };
670
671 struct intel_dp_mst_encoder;
672 #define DP_MAX_DOWNSTREAM_PORTS 0x10
673
674 /*
675 * enum link_m_n_set:
676 * When platform provides two set of M_N registers for dp, we can
677 * program them and switch between them incase of DRRS.
678 * But When only one such register is provided, we have to program the
679 * required divider value on that registers itself based on the DRRS state.
680 *
681 * M1_N1 : Program dp_m_n on M1_N1 registers
682 * dp_m2_n2 on M2_N2 registers (If supported)
683 *
684 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
685 * M2_N2 registers are not supported
686 */
687
688 enum link_m_n_set {
689 /* Sets the m1_n1 and m2_n2 */
690 M1_N1 = 0,
691 M2_N2
692 };
693
694 struct intel_dp {
695 uint32_t output_reg;
696 uint32_t aux_ch_ctl_reg;
697 uint32_t DP;
698 bool has_audio;
699 enum hdmi_force_audio force_audio;
700 uint32_t color_range;
701 bool color_range_auto;
702 uint8_t link_bw;
703 uint8_t rate_select;
704 uint8_t lane_count;
705 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
706 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
707 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
708 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
709 uint8_t num_sink_rates;
710 int sink_rates[DP_MAX_SUPPORTED_RATES];
711 struct drm_dp_aux aux;
712 uint8_t train_set[4];
713 int panel_power_up_delay;
714 int panel_power_down_delay;
715 int panel_power_cycle_delay;
716 int backlight_on_delay;
717 int backlight_off_delay;
718 struct delayed_work panel_vdd_work;
719 bool want_panel_vdd;
720 unsigned long last_power_cycle;
721 unsigned long last_power_on;
722 unsigned long last_backlight_off;
723
724 struct notifier_block edp_notifier;
725
726 /*
727 * Pipe whose power sequencer is currently locked into
728 * this port. Only relevant on VLV/CHV.
729 */
730 enum pipe pps_pipe;
731 struct edp_power_seq pps_delays;
732
733 bool use_tps3;
734 bool can_mst; /* this port supports mst */
735 bool is_mst;
736 int active_mst_links;
737 /* connector directly attached - won't be use for modeset in mst world */
738 struct intel_connector *attached_connector;
739
740 /* mst connector list */
741 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
742 struct drm_dp_mst_topology_mgr mst_mgr;
743
744 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
745 /*
746 * This function returns the value we have to program the AUX_CTL
747 * register with to kick off an AUX transaction.
748 */
749 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
750 bool has_aux_irq,
751 int send_bytes,
752 uint32_t aux_clock_divider);
753 bool train_set_valid;
754
755 /* Displayport compliance testing */
756 unsigned long compliance_test_type;
757 unsigned long compliance_test_data;
758 bool compliance_test_active;
759 };
760
761 struct intel_digital_port {
762 struct intel_encoder base;
763 enum port port;
764 u32 saved_port_bits;
765 struct intel_dp dp;
766 struct intel_hdmi hdmi;
767 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
768 };
769
770 struct intel_dp_mst_encoder {
771 struct intel_encoder base;
772 enum pipe pipe;
773 struct intel_digital_port *primary;
774 void *port; /* store this opaque as its illegal to dereference it */
775 };
776
777 static inline int
778 vlv_dport_to_channel(struct intel_digital_port *dport)
779 {
780 switch (dport->port) {
781 case PORT_B:
782 case PORT_D:
783 return DPIO_CH0;
784 case PORT_C:
785 return DPIO_CH1;
786 default:
787 BUG();
788 }
789 }
790
791 static inline int
792 vlv_pipe_to_channel(enum pipe pipe)
793 {
794 switch (pipe) {
795 case PIPE_A:
796 case PIPE_C:
797 return DPIO_CH0;
798 case PIPE_B:
799 return DPIO_CH1;
800 default:
801 BUG();
802 }
803 }
804
805 static inline struct drm_crtc *
806 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
807 {
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 return dev_priv->pipe_to_crtc_mapping[pipe];
810 }
811
812 static inline struct drm_crtc *
813 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
814 {
815 struct drm_i915_private *dev_priv = dev->dev_private;
816 return dev_priv->plane_to_crtc_mapping[plane];
817 }
818
819 struct intel_unpin_work {
820 struct work_struct work;
821 struct drm_crtc *crtc;
822 struct drm_framebuffer *old_fb;
823 struct drm_i915_gem_object *pending_flip_obj;
824 struct drm_pending_vblank_event *event;
825 atomic_t pending;
826 #define INTEL_FLIP_INACTIVE 0
827 #define INTEL_FLIP_PENDING 1
828 #define INTEL_FLIP_COMPLETE 2
829 u32 flip_count;
830 u32 gtt_offset;
831 struct drm_i915_gem_request *flip_queued_req;
832 int flip_queued_vblank;
833 int flip_ready_vblank;
834 bool enable_stall_check;
835 };
836
837 struct intel_load_detect_pipe {
838 struct drm_framebuffer *release_fb;
839 bool load_detect_temp;
840 int dpms_mode;
841 };
842
843 static inline struct intel_encoder *
844 intel_attached_encoder(struct drm_connector *connector)
845 {
846 return to_intel_connector(connector)->encoder;
847 }
848
849 static inline struct intel_digital_port *
850 enc_to_dig_port(struct drm_encoder *encoder)
851 {
852 return container_of(encoder, struct intel_digital_port, base.base);
853 }
854
855 static inline struct intel_dp_mst_encoder *
856 enc_to_mst(struct drm_encoder *encoder)
857 {
858 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
859 }
860
861 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
862 {
863 return &enc_to_dig_port(encoder)->dp;
864 }
865
866 static inline struct intel_digital_port *
867 dp_to_dig_port(struct intel_dp *intel_dp)
868 {
869 return container_of(intel_dp, struct intel_digital_port, dp);
870 }
871
872 static inline struct intel_digital_port *
873 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
874 {
875 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
876 }
877
878 /*
879 * Returns the number of planes for this pipe, ie the number of sprites + 1
880 * (primary plane). This doesn't count the cursor plane then.
881 */
882 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
883 {
884 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
885 }
886
887 /* intel_fifo_underrun.c */
888 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
889 enum pipe pipe, bool enable);
890 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
891 enum transcoder pch_transcoder,
892 bool enable);
893 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
894 enum pipe pipe);
895 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
896 enum transcoder pch_transcoder);
897 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
898
899 /* i915_irq.c */
900 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
901 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
902 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
903 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
904 void gen6_reset_rps_interrupts(struct drm_device *dev);
905 void gen6_enable_rps_interrupts(struct drm_device *dev);
906 void gen6_disable_rps_interrupts(struct drm_device *dev);
907 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
908 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
909 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
910 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
911 {
912 /*
913 * We only use drm_irq_uninstall() at unload and VT switch, so
914 * this is the only thing we need to check.
915 */
916 return dev_priv->pm.irqs_enabled;
917 }
918
919 int intel_get_crtc_scanline(struct intel_crtc *crtc);
920 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
921 unsigned int pipe_mask);
922
923 /* intel_crt.c */
924 void intel_crt_init(struct drm_device *dev);
925
926
927 /* intel_ddi.c */
928 void intel_prepare_ddi(struct drm_device *dev);
929 void hsw_fdi_link_train(struct drm_crtc *crtc);
930 void intel_ddi_init(struct drm_device *dev, enum port port);
931 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
932 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
933 void intel_ddi_pll_init(struct drm_device *dev);
934 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
935 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
936 enum transcoder cpu_transcoder);
937 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
938 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
939 bool intel_ddi_pll_select(struct intel_crtc *crtc,
940 struct intel_crtc_state *crtc_state);
941 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
942 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
943 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
944 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
945 void intel_ddi_get_config(struct intel_encoder *encoder,
946 struct intel_crtc_state *pipe_config);
947 struct intel_encoder *
948 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
949
950 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
951 void intel_ddi_clock_get(struct intel_encoder *encoder,
952 struct intel_crtc_state *pipe_config);
953 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
954 void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
955 enum port port, int type);
956
957 /* intel_frontbuffer.c */
958 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
959 enum fb_op_origin origin);
960 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
961 unsigned frontbuffer_bits);
962 void intel_frontbuffer_flip_complete(struct drm_device *dev,
963 unsigned frontbuffer_bits);
964 void intel_frontbuffer_flush(struct drm_device *dev,
965 unsigned frontbuffer_bits);
966 /**
967 * intel_frontbuffer_flip - synchronous frontbuffer flip
968 * @dev: DRM device
969 * @frontbuffer_bits: frontbuffer plane tracking bits
970 *
971 * This function gets called after scheduling a flip on @obj. This is for
972 * synchronous plane updates which will happen on the next vblank and which will
973 * not get delayed by pending gpu rendering.
974 *
975 * Can be called without any locks held.
976 */
977 static inline
978 void intel_frontbuffer_flip(struct drm_device *dev,
979 unsigned frontbuffer_bits)
980 {
981 intel_frontbuffer_flush(dev, frontbuffer_bits);
982 }
983
984 unsigned int intel_fb_align_height(struct drm_device *dev,
985 unsigned int height,
986 uint32_t pixel_format,
987 uint64_t fb_format_modifier);
988 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
989
990 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
991 uint32_t pixel_format);
992
993 /* intel_audio.c */
994 void intel_init_audio(struct drm_device *dev);
995 void intel_audio_codec_enable(struct intel_encoder *encoder);
996 void intel_audio_codec_disable(struct intel_encoder *encoder);
997 void i915_audio_component_init(struct drm_i915_private *dev_priv);
998 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
999
1000 /* intel_display.c */
1001 extern const struct drm_plane_funcs intel_plane_funcs;
1002 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1003 int intel_pch_rawclk(struct drm_device *dev);
1004 void intel_mark_busy(struct drm_device *dev);
1005 void intel_mark_idle(struct drm_device *dev);
1006 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1007 void intel_display_suspend(struct drm_device *dev);
1008 int intel_crtc_control(struct drm_crtc *crtc, bool enable);
1009 void intel_crtc_update_dpms(struct drm_crtc *crtc);
1010 void intel_encoder_destroy(struct drm_encoder *encoder);
1011 int intel_connector_init(struct intel_connector *);
1012 struct intel_connector *intel_connector_alloc(void);
1013 void intel_connector_dpms(struct drm_connector *, int mode);
1014 bool intel_connector_get_hw_state(struct intel_connector *connector);
1015 void intel_modeset_check_state(struct drm_device *dev);
1016 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1017 struct intel_digital_port *port);
1018 void intel_connector_attach_encoder(struct intel_connector *connector,
1019 struct intel_encoder *encoder);
1020 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1021 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1022 struct drm_crtc *crtc);
1023 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1024 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv);
1026 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1027 enum pipe pipe);
1028 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1029 static inline void
1030 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1031 {
1032 drm_wait_one_vblank(dev, pipe);
1033 }
1034 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1035 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1036 struct intel_digital_port *dport,
1037 unsigned int expected_mask);
1038 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1039 struct drm_display_mode *mode,
1040 struct intel_load_detect_pipe *old,
1041 struct drm_modeset_acquire_ctx *ctx);
1042 void intel_release_load_detect_pipe(struct drm_connector *connector,
1043 struct intel_load_detect_pipe *old,
1044 struct drm_modeset_acquire_ctx *ctx);
1045 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1046 struct drm_framebuffer *fb,
1047 const struct drm_plane_state *plane_state,
1048 struct intel_engine_cs *pipelined,
1049 struct drm_i915_gem_request **pipelined_request);
1050 struct drm_framebuffer *
1051 __intel_framebuffer_create(struct drm_device *dev,
1052 struct drm_mode_fb_cmd2 *mode_cmd,
1053 struct drm_i915_gem_object *obj);
1054 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1055 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1056 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1057 void intel_check_page_flip(struct drm_device *dev, int pipe);
1058 int intel_prepare_plane_fb(struct drm_plane *plane,
1059 struct drm_framebuffer *fb,
1060 const struct drm_plane_state *new_state);
1061 void intel_cleanup_plane_fb(struct drm_plane *plane,
1062 struct drm_framebuffer *fb,
1063 const struct drm_plane_state *old_state);
1064 int intel_plane_atomic_get_property(struct drm_plane *plane,
1065 const struct drm_plane_state *state,
1066 struct drm_property *property,
1067 uint64_t *val);
1068 int intel_plane_atomic_set_property(struct drm_plane *plane,
1069 struct drm_plane_state *state,
1070 struct drm_property *property,
1071 uint64_t val);
1072 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1073 struct drm_plane_state *plane_state);
1074
1075 unsigned int
1076 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1077 uint64_t fb_format_modifier);
1078
1079 static inline bool
1080 intel_rotation_90_or_270(unsigned int rotation)
1081 {
1082 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1083 }
1084
1085 void intel_create_rotation_property(struct drm_device *dev,
1086 struct intel_plane *plane);
1087
1088 /* shared dpll functions */
1089 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1090 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1091 struct intel_shared_dpll *pll,
1092 bool state);
1093 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1094 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1095 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1096 struct intel_crtc_state *state);
1097
1098 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1099 const struct dpll *dpll);
1100 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1101
1102 /* modesetting asserts */
1103 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1104 enum pipe pipe);
1105 void assert_pll(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state);
1107 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1108 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1109 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state);
1111 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1112 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1113 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1114 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1115 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1116 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1117 int *x, int *y,
1118 unsigned int tiling_mode,
1119 unsigned int bpp,
1120 unsigned int pitch);
1121 void intel_prepare_reset(struct drm_device *dev);
1122 void intel_finish_reset(struct drm_device *dev);
1123 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1124 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1125 void broxton_init_cdclk(struct drm_device *dev);
1126 void broxton_uninit_cdclk(struct drm_device *dev);
1127 void broxton_ddi_phy_init(struct drm_device *dev);
1128 void broxton_ddi_phy_uninit(struct drm_device *dev);
1129 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1130 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1131 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1132 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1133 void intel_dp_get_m_n(struct intel_crtc *crtc,
1134 struct intel_crtc_state *pipe_config);
1135 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1136 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1137 void
1138 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1139 int dotclock);
1140 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1141 intel_clock_t *best_clock);
1142 bool intel_crtc_active(struct drm_crtc *crtc);
1143 void hsw_enable_ips(struct intel_crtc *crtc);
1144 void hsw_disable_ips(struct intel_crtc *crtc);
1145 enum intel_display_power_domain
1146 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1147 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1148 struct intel_crtc_state *pipe_config);
1149 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1150 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1151
1152 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state, int force_detach);
1153 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1154
1155 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1156 struct drm_i915_gem_object *obj);
1157 u32 skl_plane_ctl_format(uint32_t pixel_format);
1158 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1159 u32 skl_plane_ctl_rotation(unsigned int rotation);
1160
1161 /* intel_csr.c */
1162 void intel_csr_ucode_init(struct drm_device *dev);
1163 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1164 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1165 enum csr_state state);
1166 void intel_csr_load_program(struct drm_device *dev);
1167 void intel_csr_ucode_fini(struct drm_device *dev);
1168 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1169
1170 /* intel_dp.c */
1171 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1172 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1173 struct intel_connector *intel_connector);
1174 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1175 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1176 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1177 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1178 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1179 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1180 bool intel_dp_compute_config(struct intel_encoder *encoder,
1181 struct intel_crtc_state *pipe_config);
1182 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1183 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1184 bool long_hpd);
1185 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1186 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1187 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1188 void intel_edp_panel_on(struct intel_dp *intel_dp);
1189 void intel_edp_panel_off(struct intel_dp *intel_dp);
1190 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1191 void intel_dp_mst_suspend(struct drm_device *dev);
1192 void intel_dp_mst_resume(struct drm_device *dev);
1193 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1194 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1195 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1196 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1197 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1198 void intel_plane_destroy(struct drm_plane *plane);
1199 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1200 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1201 void intel_edp_drrs_invalidate(struct drm_device *dev,
1202 unsigned frontbuffer_bits);
1203 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1204
1205 /* intel_dp_mst.c */
1206 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1207 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1208 /* intel_dsi.c */
1209 void intel_dsi_init(struct drm_device *dev);
1210
1211
1212 /* intel_dvo.c */
1213 void intel_dvo_init(struct drm_device *dev);
1214
1215
1216 /* legacy fbdev emulation in intel_fbdev.c */
1217 #ifdef CONFIG_DRM_I915_FBDEV
1218 extern int intel_fbdev_init(struct drm_device *dev);
1219 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1220 extern void intel_fbdev_fini(struct drm_device *dev);
1221 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1222 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1223 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1224 #else
1225 static inline int intel_fbdev_init(struct drm_device *dev)
1226 {
1227 return 0;
1228 }
1229
1230 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1231 {
1232 }
1233
1234 static inline void intel_fbdev_fini(struct drm_device *dev)
1235 {
1236 }
1237
1238 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1239 {
1240 }
1241
1242 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1243 {
1244 }
1245 #endif
1246
1247 /* intel_fbc.c */
1248 bool intel_fbc_enabled(struct drm_device *dev);
1249 void intel_fbc_update(struct drm_device *dev);
1250 void intel_fbc_init(struct drm_i915_private *dev_priv);
1251 void intel_fbc_disable(struct drm_device *dev);
1252 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1253 unsigned int frontbuffer_bits,
1254 enum fb_op_origin origin);
1255 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1256 unsigned int frontbuffer_bits);
1257 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1258
1259 /* intel_hdmi.c */
1260 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1261 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1262 struct intel_connector *intel_connector);
1263 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1264 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1265 struct intel_crtc_state *pipe_config);
1266
1267
1268 /* intel_lvds.c */
1269 void intel_lvds_init(struct drm_device *dev);
1270 bool intel_is_dual_link_lvds(struct drm_device *dev);
1271
1272
1273 /* intel_modes.c */
1274 int intel_connector_update_modes(struct drm_connector *connector,
1275 struct edid *edid);
1276 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1277 void intel_attach_force_audio_property(struct drm_connector *connector);
1278 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1279
1280
1281 /* intel_overlay.c */
1282 void intel_setup_overlay(struct drm_device *dev);
1283 void intel_cleanup_overlay(struct drm_device *dev);
1284 int intel_overlay_switch_off(struct intel_overlay *overlay);
1285 int intel_overlay_put_image(struct drm_device *dev, void *data,
1286 struct drm_file *file_priv);
1287 int intel_overlay_attrs(struct drm_device *dev, void *data,
1288 struct drm_file *file_priv);
1289 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1290
1291
1292 /* intel_panel.c */
1293 int intel_panel_init(struct intel_panel *panel,
1294 struct drm_display_mode *fixed_mode,
1295 struct drm_display_mode *downclock_mode);
1296 void intel_panel_fini(struct intel_panel *panel);
1297 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1298 struct drm_display_mode *adjusted_mode);
1299 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1300 struct intel_crtc_state *pipe_config,
1301 int fitting_mode);
1302 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1303 struct intel_crtc_state *pipe_config,
1304 int fitting_mode);
1305 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1306 u32 level, u32 max);
1307 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1308 void intel_panel_enable_backlight(struct intel_connector *connector);
1309 void intel_panel_disable_backlight(struct intel_connector *connector);
1310 void intel_panel_destroy_backlight(struct drm_connector *connector);
1311 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1312 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1313 extern struct drm_display_mode *intel_find_panel_downclock(
1314 struct drm_device *dev,
1315 struct drm_display_mode *fixed_mode,
1316 struct drm_connector *connector);
1317 void intel_backlight_register(struct drm_device *dev);
1318 void intel_backlight_unregister(struct drm_device *dev);
1319
1320
1321 /* intel_psr.c */
1322 void intel_psr_enable(struct intel_dp *intel_dp);
1323 void intel_psr_disable(struct intel_dp *intel_dp);
1324 void intel_psr_invalidate(struct drm_device *dev,
1325 unsigned frontbuffer_bits);
1326 void intel_psr_flush(struct drm_device *dev,
1327 unsigned frontbuffer_bits);
1328 void intel_psr_init(struct drm_device *dev);
1329 void intel_psr_single_frame_update(struct drm_device *dev);
1330
1331 /* intel_runtime_pm.c */
1332 int intel_power_domains_init(struct drm_i915_private *);
1333 void intel_power_domains_fini(struct drm_i915_private *);
1334 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1335 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1336
1337 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1338 enum intel_display_power_domain domain);
1339 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1340 enum intel_display_power_domain domain);
1341 void intel_display_power_get(struct drm_i915_private *dev_priv,
1342 enum intel_display_power_domain domain);
1343 void intel_display_power_put(struct drm_i915_private *dev_priv,
1344 enum intel_display_power_domain domain);
1345 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1346 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1347 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1348 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1349 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1350
1351 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1352
1353 /* intel_pm.c */
1354 void intel_init_clock_gating(struct drm_device *dev);
1355 void intel_suspend_hw(struct drm_device *dev);
1356 int ilk_wm_max_level(const struct drm_device *dev);
1357 void intel_update_watermarks(struct drm_crtc *crtc);
1358 void intel_update_sprite_watermarks(struct drm_plane *plane,
1359 struct drm_crtc *crtc,
1360 uint32_t sprite_width,
1361 uint32_t sprite_height,
1362 int pixel_size,
1363 bool enabled, bool scaled);
1364 void intel_init_pm(struct drm_device *dev);
1365 void intel_pm_setup(struct drm_device *dev);
1366 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1367 void intel_gpu_ips_teardown(void);
1368 void intel_init_gt_powersave(struct drm_device *dev);
1369 void intel_cleanup_gt_powersave(struct drm_device *dev);
1370 void intel_enable_gt_powersave(struct drm_device *dev);
1371 void intel_disable_gt_powersave(struct drm_device *dev);
1372 void intel_suspend_gt_powersave(struct drm_device *dev);
1373 void intel_reset_gt_powersave(struct drm_device *dev);
1374 void gen6_update_ring_freq(struct drm_device *dev);
1375 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1376 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1377 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1378 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1379 struct intel_rps_client *rps,
1380 unsigned long submitted);
1381 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1382 struct drm_i915_gem_request *req);
1383 void ilk_wm_get_hw_state(struct drm_device *dev);
1384 void skl_wm_get_hw_state(struct drm_device *dev);
1385 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1386 struct skl_ddb_allocation *ddb /* out */);
1387 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1388
1389 /* intel_sdvo.c */
1390 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1391
1392
1393 /* intel_sprite.c */
1394 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1395 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1396 struct drm_file *file_priv);
1397 bool intel_pipe_update_start(struct intel_crtc *crtc,
1398 uint32_t *start_vbl_count);
1399 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1400
1401 /* intel_tv.c */
1402 void intel_tv_init(struct drm_device *dev);
1403
1404 /* intel_atomic.c */
1405 int intel_atomic_check(struct drm_device *dev,
1406 struct drm_atomic_state *state);
1407 int intel_atomic_commit(struct drm_device *dev,
1408 struct drm_atomic_state *state,
1409 bool async);
1410 int intel_connector_atomic_get_property(struct drm_connector *connector,
1411 const struct drm_connector_state *state,
1412 struct drm_property *property,
1413 uint64_t *val);
1414 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1415 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1416 struct drm_crtc_state *state);
1417 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1418 void intel_atomic_state_clear(struct drm_atomic_state *);
1419 struct intel_shared_dpll_config *
1420 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1421
1422 static inline struct intel_crtc_state *
1423 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1424 struct intel_crtc *crtc)
1425 {
1426 struct drm_crtc_state *crtc_state;
1427 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1428 if (IS_ERR(crtc_state))
1429 return ERR_CAST(crtc_state);
1430
1431 return to_intel_crtc_state(crtc_state);
1432 }
1433 int intel_atomic_setup_scalers(struct drm_device *dev,
1434 struct intel_crtc *intel_crtc,
1435 struct intel_crtc_state *crtc_state);
1436
1437 /* intel_atomic_plane.c */
1438 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1439 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1440 void intel_plane_destroy_state(struct drm_plane *plane,
1441 struct drm_plane_state *state);
1442 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1443
1444 #endif /* __INTEL_DRV_H__ */
Linux kernel - Deliverables
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