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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
32 #include "i915_drv.h"
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
39
40 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
41 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
42
43 /**
44 * _wait_for - magic (register) wait macro
45 *
46 * Does the right thing for modeset paths when run under kdgb or similar atomic
47 * contexts. Note that it's important that we check the condition again after
48 * having timed out, since the timeout could be due to preemption or similar and
49 * we've never had a chance to check the condition before the timeout.
50 */
51 #define _wait_for(COND, MS, W) ({ \
52 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
53 int ret__ = 0; \
54 while (!(COND)) { \
55 if (time_after(jiffies, timeout__)) { \
56 if (!(COND)) \
57 ret__ = -ETIMEDOUT; \
58 break; \
59 } \
60 if ((W) && drm_can_sleep()) { \
61 usleep_range((W)*1000, (W)*2000); \
62 } else { \
63 cpu_relax(); \
64 } \
65 } \
66 ret__; \
67 })
68
69 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
70 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
71 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
72 DIV_ROUND_UP((US), 1000), 0)
73
74 #define KHz(x) (1000 * (x))
75 #define MHz(x) KHz(1000 * (x))
76
77 /*
78 * Display related stuff
79 */
80
81 /* store information about an Ixxx DVO */
82 /* The i830->i865 use multiple DVOs with multiple i2cs */
83 /* the i915, i945 have a single sDVO i2c bus - which is different */
84 #define MAX_OUTPUTS 6
85 /* maximum connectors per crtcs in the mode set */
86
87 /* Maximum cursor sizes */
88 #define GEN2_CURSOR_WIDTH 64
89 #define GEN2_CURSOR_HEIGHT 64
90 #define MAX_CURSOR_WIDTH 256
91 #define MAX_CURSOR_HEIGHT 256
92
93 #define INTEL_I2C_BUS_DVO 1
94 #define INTEL_I2C_BUS_SDVO 2
95
96 /* these are outputs from the chip - integrated only
97 external chips are via DVO or SDVO output */
98 enum intel_output_type {
99 INTEL_OUTPUT_UNUSED = 0,
100 INTEL_OUTPUT_ANALOG = 1,
101 INTEL_OUTPUT_DVO = 2,
102 INTEL_OUTPUT_SDVO = 3,
103 INTEL_OUTPUT_LVDS = 4,
104 INTEL_OUTPUT_TVOUT = 5,
105 INTEL_OUTPUT_HDMI = 6,
106 INTEL_OUTPUT_DISPLAYPORT = 7,
107 INTEL_OUTPUT_EDP = 8,
108 INTEL_OUTPUT_DSI = 9,
109 INTEL_OUTPUT_UNKNOWN = 10,
110 INTEL_OUTPUT_DP_MST = 11,
111 };
112
113 #define INTEL_DVO_CHIP_NONE 0
114 #define INTEL_DVO_CHIP_LVDS 1
115 #define INTEL_DVO_CHIP_TMDS 2
116 #define INTEL_DVO_CHIP_TVOUT 4
117
118 #define INTEL_DSI_VIDEO_MODE 0
119 #define INTEL_DSI_COMMAND_MODE 1
120
121 struct intel_framebuffer {
122 struct drm_framebuffer base;
123 struct drm_i915_gem_object *obj;
124 };
125
126 struct intel_fbdev {
127 struct drm_fb_helper helper;
128 struct intel_framebuffer *fb;
129 struct list_head fbdev_list;
130 struct drm_display_mode *our_mode;
131 int preferred_bpp;
132 };
133
134 struct intel_encoder {
135 struct drm_encoder base;
136 /*
137 * The new crtc this encoder will be driven from. Only differs from
138 * base->crtc while a modeset is in progress.
139 */
140 struct intel_crtc *new_crtc;
141
142 enum intel_output_type type;
143 unsigned int cloneable;
144 bool connectors_active;
145 void (*hot_plug)(struct intel_encoder *);
146 bool (*compute_config)(struct intel_encoder *,
147 struct intel_crtc_state *);
148 void (*pre_pll_enable)(struct intel_encoder *);
149 void (*pre_enable)(struct intel_encoder *);
150 void (*enable)(struct intel_encoder *);
151 void (*mode_set)(struct intel_encoder *intel_encoder);
152 void (*disable)(struct intel_encoder *);
153 void (*post_disable)(struct intel_encoder *);
154 /* Read out the current hw state of this connector, returning true if
155 * the encoder is active. If the encoder is enabled it also set the pipe
156 * it is connected to in the pipe parameter. */
157 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
158 /* Reconstructs the equivalent mode flags for the current hardware
159 * state. This must be called _after_ display->get_pipe_config has
160 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
161 * be set correctly before calling this function. */
162 void (*get_config)(struct intel_encoder *,
163 struct intel_crtc_state *pipe_config);
164 /*
165 * Called during system suspend after all pending requests for the
166 * encoder are flushed (for example for DP AUX transactions) and
167 * device interrupts are disabled.
168 */
169 void (*suspend)(struct intel_encoder *);
170 int crtc_mask;
171 enum hpd_pin hpd_pin;
172 };
173
174 struct intel_panel {
175 struct drm_display_mode *fixed_mode;
176 struct drm_display_mode *downclock_mode;
177 int fitting_mode;
178
179 /* backlight */
180 struct {
181 bool present;
182 u32 level;
183 u32 min;
184 u32 max;
185 bool enabled;
186 bool combination_mode; /* gen 2/4 only */
187 bool active_low_pwm;
188 struct backlight_device *device;
189 } backlight;
190
191 void (*backlight_power)(struct intel_connector *, bool enable);
192 };
193
194 struct intel_connector {
195 struct drm_connector base;
196 /*
197 * The fixed encoder this connector is connected to.
198 */
199 struct intel_encoder *encoder;
200
201 /*
202 * The new encoder this connector will be driven. Only differs from
203 * encoder while a modeset is in progress.
204 */
205 struct intel_encoder *new_encoder;
206
207 /* Reads out the current hw, returning true if the connector is enabled
208 * and active (i.e. dpms ON state). */
209 bool (*get_hw_state)(struct intel_connector *);
210
211 /*
212 * Removes all interfaces through which the connector is accessible
213 * - like sysfs, debugfs entries -, so that no new operations can be
214 * started on the connector. Also makes sure all currently pending
215 * operations finish before returing.
216 */
217 void (*unregister)(struct intel_connector *);
218
219 /* Panel info for eDP and LVDS */
220 struct intel_panel panel;
221
222 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
223 struct edid *edid;
224 struct edid *detect_edid;
225
226 /* since POLL and HPD connectors may use the same HPD line keep the native
227 state of connector->polled in case hotplug storm detection changes it */
228 u8 polled;
229
230 void *port; /* store this opaque as its illegal to dereference it */
231
232 struct intel_dp *mst_port;
233 };
234
235 typedef struct dpll {
236 /* given values */
237 int n;
238 int m1, m2;
239 int p1, p2;
240 /* derived values */
241 int dot;
242 int vco;
243 int m;
244 int p;
245 } intel_clock_t;
246
247 struct intel_plane_state {
248 struct drm_plane_state base;
249 struct drm_rect src;
250 struct drm_rect dst;
251 struct drm_rect clip;
252 bool visible;
253
254 /*
255 * used only for sprite planes to determine when to implicitly
256 * enable/disable the primary plane
257 */
258 bool hides_primary;
259 };
260
261 struct intel_initial_plane_config {
262 struct intel_framebuffer *fb;
263 unsigned int tiling;
264 int size;
265 u32 base;
266 };
267
268 struct intel_crtc_state {
269 struct drm_crtc_state base;
270
271 /**
272 * quirks - bitfield with hw state readout quirks
273 *
274 * For various reasons the hw state readout code might not be able to
275 * completely faithfully read out the current state. These cases are
276 * tracked with quirk flags so that fastboot and state checker can act
277 * accordingly.
278 */
279 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
280 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
281 unsigned long quirks;
282
283 /* Pipe source size (ie. panel fitter input size)
284 * All planes will be positioned inside this space,
285 * and get clipped at the edges. */
286 int pipe_src_w, pipe_src_h;
287
288 /* Whether to set up the PCH/FDI. Note that we never allow sharing
289 * between pch encoders and cpu encoders. */
290 bool has_pch_encoder;
291
292 /* Are we sending infoframes on the attached port */
293 bool has_infoframe;
294
295 /* CPU Transcoder for the pipe. Currently this can only differ from the
296 * pipe on Haswell (where we have a special eDP transcoder). */
297 enum transcoder cpu_transcoder;
298
299 /*
300 * Use reduced/limited/broadcast rbg range, compressing from the full
301 * range fed into the crtcs.
302 */
303 bool limited_color_range;
304
305 /* DP has a bunch of special case unfortunately, so mark the pipe
306 * accordingly. */
307 bool has_dp_encoder;
308
309 /* Whether we should send NULL infoframes. Required for audio. */
310 bool has_hdmi_sink;
311
312 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
313 * has_dp_encoder is set. */
314 bool has_audio;
315
316 /*
317 * Enable dithering, used when the selected pipe bpp doesn't match the
318 * plane bpp.
319 */
320 bool dither;
321
322 /* Controls for the clock computation, to override various stages. */
323 bool clock_set;
324
325 /* SDVO TV has a bunch of special case. To make multifunction encoders
326 * work correctly, we need to track this at runtime.*/
327 bool sdvo_tv_clock;
328
329 /*
330 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
331 * required. This is set in the 2nd loop of calling encoder's
332 * ->compute_config if the first pick doesn't work out.
333 */
334 bool bw_constrained;
335
336 /* Settings for the intel dpll used on pretty much everything but
337 * haswell. */
338 struct dpll dpll;
339
340 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
341 enum intel_dpll_id shared_dpll;
342
343 /*
344 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
345 * - enum skl_dpll on SKL
346 */
347 uint32_t ddi_pll_sel;
348
349 /* Actual register state of the dpll, for shared dpll cross-checking. */
350 struct intel_dpll_hw_state dpll_hw_state;
351
352 int pipe_bpp;
353 struct intel_link_m_n dp_m_n;
354
355 /* m2_n2 for eDP downclock */
356 struct intel_link_m_n dp_m2_n2;
357 bool has_drrs;
358
359 /*
360 * Frequence the dpll for the port should run at. Differs from the
361 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
362 * already multiplied by pixel_multiplier.
363 */
364 int port_clock;
365
366 /* Used by SDVO (and if we ever fix it, HDMI). */
367 unsigned pixel_multiplier;
368
369 /* Panel fitter controls for gen2-gen4 + VLV */
370 struct {
371 u32 control;
372 u32 pgm_ratios;
373 u32 lvds_border_bits;
374 } gmch_pfit;
375
376 /* Panel fitter placement and size for Ironlake+ */
377 struct {
378 u32 pos;
379 u32 size;
380 bool enabled;
381 bool force_thru;
382 } pch_pfit;
383
384 /* FDI configuration, only valid if has_pch_encoder is set. */
385 int fdi_lanes;
386 struct intel_link_m_n fdi_m_n;
387
388 bool ips_enabled;
389
390 bool double_wide;
391
392 bool dp_encoder_is_mst;
393 int pbn;
394 };
395
396 struct intel_pipe_wm {
397 struct intel_wm_level wm[5];
398 uint32_t linetime;
399 bool fbc_wm_enabled;
400 bool pipe_enabled;
401 bool sprites_enabled;
402 bool sprites_scaled;
403 };
404
405 struct intel_mmio_flip {
406 struct drm_i915_gem_request *req;
407 struct work_struct work;
408 };
409
410 struct skl_pipe_wm {
411 struct skl_wm_level wm[8];
412 struct skl_wm_level trans_wm;
413 uint32_t linetime;
414 };
415
416 /*
417 * Tracking of operations that need to be performed at the beginning/end of an
418 * atomic commit, outside the atomic section where interrupts are disabled.
419 * These are generally operations that grab mutexes or might otherwise sleep
420 * and thus can't be run with interrupts disabled.
421 */
422 struct intel_crtc_atomic_commit {
423 /* vblank evasion */
424 bool evade;
425 unsigned start_vbl_count;
426
427 /* Sleepable operations to perform before commit */
428 bool wait_for_flips;
429 bool disable_fbc;
430 bool pre_disable_primary;
431 bool update_wm;
432 unsigned disabled_planes;
433
434 /* Sleepable operations to perform after commit */
435 unsigned fb_bits;
436 bool wait_vblank;
437 bool update_fbc;
438 bool post_enable_primary;
439 unsigned update_sprite_watermarks;
440 };
441
442 struct intel_crtc {
443 struct drm_crtc base;
444 enum pipe pipe;
445 enum plane plane;
446 u8 lut_r[256], lut_g[256], lut_b[256];
447 /*
448 * Whether the crtc and the connected output pipeline is active. Implies
449 * that crtc->enabled is set, i.e. the current mode configuration has
450 * some outputs connected to this crtc.
451 */
452 bool active;
453 unsigned long enabled_power_domains;
454 bool primary_enabled; /* is the primary plane (partially) visible? */
455 bool lowfreq_avail;
456 struct intel_overlay *overlay;
457 struct intel_unpin_work *unpin_work;
458
459 atomic_t unpin_work_count;
460
461 /* Display surface base address adjustement for pageflips. Note that on
462 * gen4+ this only adjusts up to a tile, offsets within a tile are
463 * handled in the hw itself (with the TILEOFF register). */
464 unsigned long dspaddr_offset;
465
466 struct drm_i915_gem_object *cursor_bo;
467 uint32_t cursor_addr;
468 uint32_t cursor_cntl;
469 uint32_t cursor_size;
470 uint32_t cursor_base;
471
472 struct intel_initial_plane_config plane_config;
473 struct intel_crtc_state *config;
474 struct intel_crtc_state *new_config;
475 bool new_enabled;
476
477 /* reset counter value when the last flip was submitted */
478 unsigned int reset_counter;
479
480 /* Access to these should be protected by dev_priv->irq_lock. */
481 bool cpu_fifo_underrun_disabled;
482 bool pch_fifo_underrun_disabled;
483
484 /* per-pipe watermark state */
485 struct {
486 /* watermarks currently being used */
487 struct intel_pipe_wm active;
488 /* SKL wm values currently in use */
489 struct skl_pipe_wm skl_active;
490 } wm;
491
492 int scanline_offset;
493 struct intel_mmio_flip mmio_flip;
494
495 struct intel_crtc_atomic_commit atomic;
496 };
497
498 struct intel_plane_wm_parameters {
499 uint32_t horiz_pixels;
500 uint32_t vert_pixels;
501 uint8_t bytes_per_pixel;
502 bool enabled;
503 bool scaled;
504 u64 tiling;
505 unsigned int rotation;
506 };
507
508 struct intel_plane {
509 struct drm_plane base;
510 int plane;
511 enum pipe pipe;
512 bool can_scale;
513 int max_downscale;
514
515 /* FIXME convert to properties */
516 struct drm_intel_sprite_colorkey ckey;
517
518 /* Since we need to change the watermarks before/after
519 * enabling/disabling the planes, we need to store the parameters here
520 * as the other pieces of the struct may not reflect the values we want
521 * for the watermark calculations. Currently only Haswell uses this.
522 */
523 struct intel_plane_wm_parameters wm;
524
525 /*
526 * NOTE: Do not place new plane state fields here (e.g., when adding
527 * new plane properties). New runtime state should now be placed in
528 * the intel_plane_state structure and accessed via drm_plane->state.
529 */
530
531 void (*update_plane)(struct drm_plane *plane,
532 struct drm_crtc *crtc,
533 struct drm_framebuffer *fb,
534 int crtc_x, int crtc_y,
535 unsigned int crtc_w, unsigned int crtc_h,
536 uint32_t x, uint32_t y,
537 uint32_t src_w, uint32_t src_h);
538 void (*disable_plane)(struct drm_plane *plane,
539 struct drm_crtc *crtc);
540 int (*check_plane)(struct drm_plane *plane,
541 struct intel_plane_state *state);
542 void (*commit_plane)(struct drm_plane *plane,
543 struct intel_plane_state *state);
544 };
545
546 struct intel_watermark_params {
547 unsigned long fifo_size;
548 unsigned long max_wm;
549 unsigned long default_wm;
550 unsigned long guard_size;
551 unsigned long cacheline_size;
552 };
553
554 struct cxsr_latency {
555 int is_desktop;
556 int is_ddr3;
557 unsigned long fsb_freq;
558 unsigned long mem_freq;
559 unsigned long display_sr;
560 unsigned long display_hpll_disable;
561 unsigned long cursor_sr;
562 unsigned long cursor_hpll_disable;
563 };
564
565 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
566 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
567 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
568 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
569 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
570 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
571 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
572 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
573
574 struct intel_hdmi {
575 u32 hdmi_reg;
576 int ddc_bus;
577 uint32_t color_range;
578 bool color_range_auto;
579 bool has_hdmi_sink;
580 bool has_audio;
581 enum hdmi_force_audio force_audio;
582 bool rgb_quant_range_selectable;
583 enum hdmi_picture_aspect aspect_ratio;
584 void (*write_infoframe)(struct drm_encoder *encoder,
585 enum hdmi_infoframe_type type,
586 const void *frame, ssize_t len);
587 void (*set_infoframes)(struct drm_encoder *encoder,
588 bool enable,
589 struct drm_display_mode *adjusted_mode);
590 bool (*infoframe_enabled)(struct drm_encoder *encoder);
591 };
592
593 struct intel_dp_mst_encoder;
594 #define DP_MAX_DOWNSTREAM_PORTS 0x10
595
596 /*
597 * enum link_m_n_set:
598 * When platform provides two set of M_N registers for dp, we can
599 * program them and switch between them incase of DRRS.
600 * But When only one such register is provided, we have to program the
601 * required divider value on that registers itself based on the DRRS state.
602 *
603 * M1_N1 : Program dp_m_n on M1_N1 registers
604 * dp_m2_n2 on M2_N2 registers (If supported)
605 *
606 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
607 * M2_N2 registers are not supported
608 */
609
610 enum link_m_n_set {
611 /* Sets the m1_n1 and m2_n2 */
612 M1_N1 = 0,
613 M2_N2
614 };
615
616 struct intel_dp {
617 uint32_t output_reg;
618 uint32_t aux_ch_ctl_reg;
619 uint32_t DP;
620 bool has_audio;
621 enum hdmi_force_audio force_audio;
622 uint32_t color_range;
623 bool color_range_auto;
624 uint8_t link_bw;
625 uint8_t rate_select;
626 uint8_t lane_count;
627 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
628 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
629 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
630 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
631 uint8_t num_sink_rates;
632 int sink_rates[DP_MAX_SUPPORTED_RATES];
633 struct drm_dp_aux aux;
634 uint8_t train_set[4];
635 int panel_power_up_delay;
636 int panel_power_down_delay;
637 int panel_power_cycle_delay;
638 int backlight_on_delay;
639 int backlight_off_delay;
640 struct delayed_work panel_vdd_work;
641 bool want_panel_vdd;
642 unsigned long last_power_cycle;
643 unsigned long last_power_on;
644 unsigned long last_backlight_off;
645
646 struct notifier_block edp_notifier;
647
648 /*
649 * Pipe whose power sequencer is currently locked into
650 * this port. Only relevant on VLV/CHV.
651 */
652 enum pipe pps_pipe;
653 struct edp_power_seq pps_delays;
654
655 bool use_tps3;
656 bool can_mst; /* this port supports mst */
657 bool is_mst;
658 int active_mst_links;
659 /* connector directly attached - won't be use for modeset in mst world */
660 struct intel_connector *attached_connector;
661
662 /* mst connector list */
663 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
664 struct drm_dp_mst_topology_mgr mst_mgr;
665
666 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
667 /*
668 * This function returns the value we have to program the AUX_CTL
669 * register with to kick off an AUX transaction.
670 */
671 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
672 bool has_aux_irq,
673 int send_bytes,
674 uint32_t aux_clock_divider);
675 };
676
677 struct intel_digital_port {
678 struct intel_encoder base;
679 enum port port;
680 u32 saved_port_bits;
681 struct intel_dp dp;
682 struct intel_hdmi hdmi;
683 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
684 };
685
686 struct intel_dp_mst_encoder {
687 struct intel_encoder base;
688 enum pipe pipe;
689 struct intel_digital_port *primary;
690 void *port; /* store this opaque as its illegal to dereference it */
691 };
692
693 static inline int
694 vlv_dport_to_channel(struct intel_digital_port *dport)
695 {
696 switch (dport->port) {
697 case PORT_B:
698 case PORT_D:
699 return DPIO_CH0;
700 case PORT_C:
701 return DPIO_CH1;
702 default:
703 BUG();
704 }
705 }
706
707 static inline int
708 vlv_pipe_to_channel(enum pipe pipe)
709 {
710 switch (pipe) {
711 case PIPE_A:
712 case PIPE_C:
713 return DPIO_CH0;
714 case PIPE_B:
715 return DPIO_CH1;
716 default:
717 BUG();
718 }
719 }
720
721 static inline struct drm_crtc *
722 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
723 {
724 struct drm_i915_private *dev_priv = dev->dev_private;
725 return dev_priv->pipe_to_crtc_mapping[pipe];
726 }
727
728 static inline struct drm_crtc *
729 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
730 {
731 struct drm_i915_private *dev_priv = dev->dev_private;
732 return dev_priv->plane_to_crtc_mapping[plane];
733 }
734
735 struct intel_unpin_work {
736 struct work_struct work;
737 struct drm_crtc *crtc;
738 struct drm_framebuffer *old_fb;
739 struct drm_i915_gem_object *pending_flip_obj;
740 struct drm_pending_vblank_event *event;
741 atomic_t pending;
742 #define INTEL_FLIP_INACTIVE 0
743 #define INTEL_FLIP_PENDING 1
744 #define INTEL_FLIP_COMPLETE 2
745 u32 flip_count;
746 u32 gtt_offset;
747 struct drm_i915_gem_request *flip_queued_req;
748 int flip_queued_vblank;
749 int flip_ready_vblank;
750 bool enable_stall_check;
751 };
752
753 struct intel_set_config {
754 struct drm_encoder **save_connector_encoders;
755 struct drm_crtc **save_encoder_crtcs;
756 bool *save_crtc_enabled;
757
758 bool fb_changed;
759 bool mode_changed;
760 };
761
762 struct intel_load_detect_pipe {
763 struct drm_framebuffer *release_fb;
764 bool load_detect_temp;
765 int dpms_mode;
766 };
767
768 static inline struct intel_encoder *
769 intel_attached_encoder(struct drm_connector *connector)
770 {
771 return to_intel_connector(connector)->encoder;
772 }
773
774 static inline struct intel_digital_port *
775 enc_to_dig_port(struct drm_encoder *encoder)
776 {
777 return container_of(encoder, struct intel_digital_port, base.base);
778 }
779
780 static inline struct intel_dp_mst_encoder *
781 enc_to_mst(struct drm_encoder *encoder)
782 {
783 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
784 }
785
786 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
787 {
788 return &enc_to_dig_port(encoder)->dp;
789 }
790
791 static inline struct intel_digital_port *
792 dp_to_dig_port(struct intel_dp *intel_dp)
793 {
794 return container_of(intel_dp, struct intel_digital_port, dp);
795 }
796
797 static inline struct intel_digital_port *
798 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
799 {
800 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
801 }
802
803 /*
804 * Returns the number of planes for this pipe, ie the number of sprites + 1
805 * (primary plane). This doesn't count the cursor plane then.
806 */
807 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
808 {
809 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
810 }
811
812 /* intel_fifo_underrun.c */
813 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool enable);
815 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
816 enum transcoder pch_transcoder,
817 bool enable);
818 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
819 enum pipe pipe);
820 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
821 enum transcoder pch_transcoder);
822 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
823
824 /* i915_irq.c */
825 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
826 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
827 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
828 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
829 void gen6_reset_rps_interrupts(struct drm_device *dev);
830 void gen6_enable_rps_interrupts(struct drm_device *dev);
831 void gen6_disable_rps_interrupts(struct drm_device *dev);
832 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
833 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
834 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
835 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
836 {
837 /*
838 * We only use drm_irq_uninstall() at unload and VT switch, so
839 * this is the only thing we need to check.
840 */
841 return dev_priv->pm.irqs_enabled;
842 }
843
844 int intel_get_crtc_scanline(struct intel_crtc *crtc);
845 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
846 unsigned int pipe_mask);
847
848 /* intel_crt.c */
849 void intel_crt_init(struct drm_device *dev);
850
851
852 /* intel_ddi.c */
853 void intel_prepare_ddi(struct drm_device *dev);
854 void hsw_fdi_link_train(struct drm_crtc *crtc);
855 void intel_ddi_init(struct drm_device *dev, enum port port);
856 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
857 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
858 void intel_ddi_pll_init(struct drm_device *dev);
859 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
860 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
861 enum transcoder cpu_transcoder);
862 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
863 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
864 bool intel_ddi_pll_select(struct intel_crtc *crtc,
865 struct intel_crtc_state *crtc_state);
866 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
867 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
868 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
869 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
870 void intel_ddi_get_config(struct intel_encoder *encoder,
871 struct intel_crtc_state *pipe_config);
872
873 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
874 void intel_ddi_clock_get(struct intel_encoder *encoder,
875 struct intel_crtc_state *pipe_config);
876 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
877
878 /* intel_frontbuffer.c */
879 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
880 struct intel_engine_cs *ring,
881 enum fb_op_origin origin);
882 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
883 unsigned frontbuffer_bits);
884 void intel_frontbuffer_flip_complete(struct drm_device *dev,
885 unsigned frontbuffer_bits);
886 void intel_frontbuffer_flush(struct drm_device *dev,
887 unsigned frontbuffer_bits);
888 /**
889 * intel_frontbuffer_flip - synchronous frontbuffer flip
890 * @dev: DRM device
891 * @frontbuffer_bits: frontbuffer plane tracking bits
892 *
893 * This function gets called after scheduling a flip on @obj. This is for
894 * synchronous plane updates which will happen on the next vblank and which will
895 * not get delayed by pending gpu rendering.
896 *
897 * Can be called without any locks held.
898 */
899 static inline
900 void intel_frontbuffer_flip(struct drm_device *dev,
901 unsigned frontbuffer_bits)
902 {
903 intel_frontbuffer_flush(dev, frontbuffer_bits);
904 }
905
906 unsigned int intel_fb_align_height(struct drm_device *dev,
907 unsigned int height,
908 uint32_t pixel_format,
909 uint64_t fb_format_modifier);
910 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
911
912 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
913 uint32_t pixel_format);
914
915 /* intel_audio.c */
916 void intel_init_audio(struct drm_device *dev);
917 void intel_audio_codec_enable(struct intel_encoder *encoder);
918 void intel_audio_codec_disable(struct intel_encoder *encoder);
919 void i915_audio_component_init(struct drm_i915_private *dev_priv);
920 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
921
922 /* intel_display.c */
923 extern const struct drm_plane_funcs intel_plane_funcs;
924 bool intel_has_pending_fb_unpin(struct drm_device *dev);
925 int intel_pch_rawclk(struct drm_device *dev);
926 void intel_mark_busy(struct drm_device *dev);
927 void intel_mark_idle(struct drm_device *dev);
928 void intel_crtc_restore_mode(struct drm_crtc *crtc);
929 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
930 void intel_crtc_update_dpms(struct drm_crtc *crtc);
931 void intel_encoder_destroy(struct drm_encoder *encoder);
932 void intel_connector_dpms(struct drm_connector *, int mode);
933 bool intel_connector_get_hw_state(struct intel_connector *connector);
934 void intel_modeset_check_state(struct drm_device *dev);
935 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
936 struct intel_digital_port *port);
937 void intel_connector_attach_encoder(struct intel_connector *connector,
938 struct intel_encoder *encoder);
939 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
940 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
941 struct drm_crtc *crtc);
942 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
943 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
944 struct drm_file *file_priv);
945 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
946 enum pipe pipe);
947 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
948 static inline void
949 intel_wait_for_vblank(struct drm_device *dev, int pipe)
950 {
951 drm_wait_one_vblank(dev, pipe);
952 }
953 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
954 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
955 struct intel_digital_port *dport);
956 bool intel_get_load_detect_pipe(struct drm_connector *connector,
957 struct drm_display_mode *mode,
958 struct intel_load_detect_pipe *old,
959 struct drm_modeset_acquire_ctx *ctx);
960 void intel_release_load_detect_pipe(struct drm_connector *connector,
961 struct intel_load_detect_pipe *old,
962 struct drm_modeset_acquire_ctx *ctx);
963 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
964 struct drm_framebuffer *fb,
965 const struct drm_plane_state *plane_state,
966 struct intel_engine_cs *pipelined);
967 struct drm_framebuffer *
968 __intel_framebuffer_create(struct drm_device *dev,
969 struct drm_mode_fb_cmd2 *mode_cmd,
970 struct drm_i915_gem_object *obj);
971 void intel_prepare_page_flip(struct drm_device *dev, int plane);
972 void intel_finish_page_flip(struct drm_device *dev, int pipe);
973 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
974 void intel_check_page_flip(struct drm_device *dev, int pipe);
975 int intel_prepare_plane_fb(struct drm_plane *plane,
976 struct drm_framebuffer *fb,
977 const struct drm_plane_state *new_state);
978 void intel_cleanup_plane_fb(struct drm_plane *plane,
979 struct drm_framebuffer *fb,
980 const struct drm_plane_state *old_state);
981 int intel_plane_atomic_get_property(struct drm_plane *plane,
982 const struct drm_plane_state *state,
983 struct drm_property *property,
984 uint64_t *val);
985 int intel_plane_atomic_set_property(struct drm_plane *plane,
986 struct drm_plane_state *state,
987 struct drm_property *property,
988 uint64_t val);
989
990 unsigned int
991 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
992 uint64_t fb_format_modifier);
993
994 static inline bool
995 intel_rotation_90_or_270(unsigned int rotation)
996 {
997 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
998 }
999
1000 bool intel_wm_need_update(struct drm_plane *plane,
1001 struct drm_plane_state *state);
1002
1003 /* shared dpll functions */
1004 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1005 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1006 struct intel_shared_dpll *pll,
1007 bool state);
1008 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1009 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1010 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1011 struct intel_crtc_state *state);
1012 void intel_put_shared_dpll(struct intel_crtc *crtc);
1013
1014 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1015 const struct dpll *dpll);
1016 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1017
1018 /* modesetting asserts */
1019 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1020 enum pipe pipe);
1021 void assert_pll(struct drm_i915_private *dev_priv,
1022 enum pipe pipe, bool state);
1023 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1024 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1025 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1026 enum pipe pipe, bool state);
1027 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1028 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1029 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1030 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1031 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1032 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1033 unsigned int tiling_mode,
1034 unsigned int bpp,
1035 unsigned int pitch);
1036 void intel_prepare_reset(struct drm_device *dev);
1037 void intel_finish_reset(struct drm_device *dev);
1038 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1039 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1040 void intel_dp_get_m_n(struct intel_crtc *crtc,
1041 struct intel_crtc_state *pipe_config);
1042 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1043 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1044 void
1045 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1046 int dotclock);
1047 bool intel_crtc_active(struct drm_crtc *crtc);
1048 void hsw_enable_ips(struct intel_crtc *crtc);
1049 void hsw_disable_ips(struct intel_crtc *crtc);
1050 enum intel_display_power_domain
1051 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1052 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1053 struct intel_crtc_state *pipe_config);
1054 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1055 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1056
1057 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1058 struct drm_i915_gem_object *obj);
1059
1060 /* intel_dp.c */
1061 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1062 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1063 struct intel_connector *intel_connector);
1064 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1065 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1066 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1067 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1068 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1069 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1070 bool intel_dp_compute_config(struct intel_encoder *encoder,
1071 struct intel_crtc_state *pipe_config);
1072 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1073 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1074 bool long_hpd);
1075 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1076 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1077 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1078 void intel_edp_panel_on(struct intel_dp *intel_dp);
1079 void intel_edp_panel_off(struct intel_dp *intel_dp);
1080 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1081 void intel_dp_mst_suspend(struct drm_device *dev);
1082 void intel_dp_mst_resume(struct drm_device *dev);
1083 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1084 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1085 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1086 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1087 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1088 void intel_plane_destroy(struct drm_plane *plane);
1089 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1090 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1091 void intel_edp_drrs_invalidate(struct drm_device *dev,
1092 unsigned frontbuffer_bits);
1093 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1094
1095 /* intel_dp_mst.c */
1096 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1097 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1098 /* intel_dsi.c */
1099 void intel_dsi_init(struct drm_device *dev);
1100
1101
1102 /* intel_dvo.c */
1103 void intel_dvo_init(struct drm_device *dev);
1104
1105
1106 /* legacy fbdev emulation in intel_fbdev.c */
1107 #ifdef CONFIG_DRM_I915_FBDEV
1108 extern int intel_fbdev_init(struct drm_device *dev);
1109 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1110 extern void intel_fbdev_fini(struct drm_device *dev);
1111 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1112 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1113 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1114 #else
1115 static inline int intel_fbdev_init(struct drm_device *dev)
1116 {
1117 return 0;
1118 }
1119
1120 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1121 {
1122 }
1123
1124 static inline void intel_fbdev_fini(struct drm_device *dev)
1125 {
1126 }
1127
1128 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1129 {
1130 }
1131
1132 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1133 {
1134 }
1135 #endif
1136
1137 /* intel_fbc.c */
1138 bool intel_fbc_enabled(struct drm_device *dev);
1139 void intel_fbc_update(struct drm_device *dev);
1140 void intel_fbc_init(struct drm_i915_private *dev_priv);
1141 void intel_fbc_disable(struct drm_device *dev);
1142 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1143 unsigned int frontbuffer_bits,
1144 enum fb_op_origin origin);
1145 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1146 unsigned int frontbuffer_bits);
1147
1148 /* intel_hdmi.c */
1149 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1150 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1151 struct intel_connector *intel_connector);
1152 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1153 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1154 struct intel_crtc_state *pipe_config);
1155
1156
1157 /* intel_lvds.c */
1158 void intel_lvds_init(struct drm_device *dev);
1159 bool intel_is_dual_link_lvds(struct drm_device *dev);
1160
1161
1162 /* intel_modes.c */
1163 int intel_connector_update_modes(struct drm_connector *connector,
1164 struct edid *edid);
1165 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1166 void intel_attach_force_audio_property(struct drm_connector *connector);
1167 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1168
1169
1170 /* intel_overlay.c */
1171 void intel_setup_overlay(struct drm_device *dev);
1172 void intel_cleanup_overlay(struct drm_device *dev);
1173 int intel_overlay_switch_off(struct intel_overlay *overlay);
1174 int intel_overlay_put_image(struct drm_device *dev, void *data,
1175 struct drm_file *file_priv);
1176 int intel_overlay_attrs(struct drm_device *dev, void *data,
1177 struct drm_file *file_priv);
1178 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1179
1180
1181 /* intel_panel.c */
1182 int intel_panel_init(struct intel_panel *panel,
1183 struct drm_display_mode *fixed_mode,
1184 struct drm_display_mode *downclock_mode);
1185 void intel_panel_fini(struct intel_panel *panel);
1186 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1187 struct drm_display_mode *adjusted_mode);
1188 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1189 struct intel_crtc_state *pipe_config,
1190 int fitting_mode);
1191 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1192 struct intel_crtc_state *pipe_config,
1193 int fitting_mode);
1194 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1195 u32 level, u32 max);
1196 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1197 void intel_panel_enable_backlight(struct intel_connector *connector);
1198 void intel_panel_disable_backlight(struct intel_connector *connector);
1199 void intel_panel_destroy_backlight(struct drm_connector *connector);
1200 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1201 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1202 extern struct drm_display_mode *intel_find_panel_downclock(
1203 struct drm_device *dev,
1204 struct drm_display_mode *fixed_mode,
1205 struct drm_connector *connector);
1206 void intel_backlight_register(struct drm_device *dev);
1207 void intel_backlight_unregister(struct drm_device *dev);
1208
1209
1210 /* intel_psr.c */
1211 void intel_psr_enable(struct intel_dp *intel_dp);
1212 void intel_psr_disable(struct intel_dp *intel_dp);
1213 void intel_psr_invalidate(struct drm_device *dev,
1214 unsigned frontbuffer_bits);
1215 void intel_psr_flush(struct drm_device *dev,
1216 unsigned frontbuffer_bits);
1217 void intel_psr_init(struct drm_device *dev);
1218
1219 /* intel_runtime_pm.c */
1220 int intel_power_domains_init(struct drm_i915_private *);
1221 void intel_power_domains_fini(struct drm_i915_private *);
1222 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1223 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1224
1225 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1226 enum intel_display_power_domain domain);
1227 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1228 enum intel_display_power_domain domain);
1229 void intel_display_power_get(struct drm_i915_private *dev_priv,
1230 enum intel_display_power_domain domain);
1231 void intel_display_power_put(struct drm_i915_private *dev_priv,
1232 enum intel_display_power_domain domain);
1233 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1234 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1235 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1236 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1237 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1238
1239 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1240
1241 /* intel_pm.c */
1242 void intel_init_clock_gating(struct drm_device *dev);
1243 void intel_suspend_hw(struct drm_device *dev);
1244 int ilk_wm_max_level(const struct drm_device *dev);
1245 void intel_update_watermarks(struct drm_crtc *crtc);
1246 void intel_update_sprite_watermarks(struct drm_plane *plane,
1247 struct drm_crtc *crtc,
1248 uint32_t sprite_width,
1249 uint32_t sprite_height,
1250 int pixel_size,
1251 bool enabled, bool scaled);
1252 void intel_init_pm(struct drm_device *dev);
1253 void intel_pm_setup(struct drm_device *dev);
1254 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1255 void intel_gpu_ips_teardown(void);
1256 void intel_init_gt_powersave(struct drm_device *dev);
1257 void intel_cleanup_gt_powersave(struct drm_device *dev);
1258 void intel_enable_gt_powersave(struct drm_device *dev);
1259 void intel_disable_gt_powersave(struct drm_device *dev);
1260 void intel_suspend_gt_powersave(struct drm_device *dev);
1261 void intel_reset_gt_powersave(struct drm_device *dev);
1262 void gen6_update_ring_freq(struct drm_device *dev);
1263 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1264 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1265 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1266 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1267 void ilk_wm_get_hw_state(struct drm_device *dev);
1268 void skl_wm_get_hw_state(struct drm_device *dev);
1269 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1270 struct skl_ddb_allocation *ddb /* out */);
1271
1272
1273 /* intel_sdvo.c */
1274 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1275
1276
1277 /* intel_sprite.c */
1278 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1279 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1280 enum plane plane);
1281 int intel_plane_restore(struct drm_plane *plane);
1282 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1283 struct drm_file *file_priv);
1284 bool intel_pipe_update_start(struct intel_crtc *crtc,
1285 uint32_t *start_vbl_count);
1286 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1287 void intel_post_enable_primary(struct drm_crtc *crtc);
1288 void intel_pre_disable_primary(struct drm_crtc *crtc);
1289
1290 /* intel_tv.c */
1291 void intel_tv_init(struct drm_device *dev);
1292
1293 /* intel_atomic.c */
1294 int intel_atomic_check(struct drm_device *dev,
1295 struct drm_atomic_state *state);
1296 int intel_atomic_commit(struct drm_device *dev,
1297 struct drm_atomic_state *state,
1298 bool async);
1299 int intel_connector_atomic_get_property(struct drm_connector *connector,
1300 const struct drm_connector_state *state,
1301 struct drm_property *property,
1302 uint64_t *val);
1303 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1304 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1305 struct drm_crtc_state *state);
1306 static inline struct intel_crtc_state *
1307 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1308 struct intel_crtc *crtc)
1309 {
1310 struct drm_crtc_state *crtc_state;
1311 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1312 if (IS_ERR(crtc_state))
1313 return ERR_PTR(PTR_ERR(crtc_state));
1314
1315 return to_intel_crtc_state(crtc_state);
1316 }
1317
1318 /* intel_atomic_plane.c */
1319 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1320 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1321 void intel_plane_destroy_state(struct drm_plane *plane,
1322 struct drm_plane_state *state);
1323 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1324
1325 #endif /* __INTEL_DRV_H__ */
Linux kernel - Deliverables
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