drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000 * (x))
  69 #define MHz(x) KHz(1000 * (x))
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80
  81 /* Maximum cursor sizes */
  82 #define GEN2_CURSOR_WIDTH 64
  83 #define GEN2_CURSOR_HEIGHT 64
  84 #define MAX_CURSOR_WIDTH 256
  85 #define MAX_CURSOR_HEIGHT 256
  86
  87 #define INTEL_I2C_BUS_DVO 1
  88 #define INTEL_I2C_BUS_SDVO 2
  89
  90 /* these are outputs from the chip - integrated only
  91    external chips are via DVO or SDVO output */
  92 #define INTEL_OUTPUT_UNUSED 0
  93 #define INTEL_OUTPUT_ANALOG 1
  94 #define INTEL_OUTPUT_DVO 2
  95 #define INTEL_OUTPUT_SDVO 3
  96 #define INTEL_OUTPUT_LVDS 4
  97 #define INTEL_OUTPUT_TVOUT 5
  98 #define INTEL_OUTPUT_HDMI 6
  99 #define INTEL_OUTPUT_DISPLAYPORT 7
 100 #define INTEL_OUTPUT_EDP 8
 101 #define INTEL_OUTPUT_DSI 9
 102 #define INTEL_OUTPUT_UNKNOWN 10
 103
 104 #define INTEL_DVO_CHIP_NONE 0
 105 #define INTEL_DVO_CHIP_LVDS 1
 106 #define INTEL_DVO_CHIP_TMDS 2
 107 #define INTEL_DVO_CHIP_TVOUT 4
 108
 109 #define INTEL_DSI_VIDEO_MODE    0
 110 #define INTEL_DSI_COMMAND_MODE  1
 111
 112 struct intel_framebuffer {
 113         struct drm_framebuffer base;
 114         struct drm_i915_gem_object *obj;
 115 };
 116
 117 struct intel_fbdev {
 118         struct drm_fb_helper helper;
 119         struct intel_framebuffer *fb;
 120         struct list_head fbdev_list;
 121         struct drm_display_mode *our_mode;
 122         int preferred_bpp;
 123 };
 124
 125 struct intel_encoder {
 126         struct drm_encoder base;
 127         /*
 128          * The new crtc this encoder will be driven from. Only differs from
 129          * base->crtc while a modeset is in progress.
 130          */
 131         struct intel_crtc *new_crtc;
 132
 133         int type;
 134         unsigned int cloneable;
 135         bool connectors_active;
 136         void (*hot_plug)(struct intel_encoder *);
 137         bool (*compute_config)(struct intel_encoder *,
 138                                struct intel_crtc_config *);
 139         void (*pre_pll_enable)(struct intel_encoder *);
 140         void (*pre_enable)(struct intel_encoder *);
 141         void (*enable)(struct intel_encoder *);
 142         void (*mode_set)(struct intel_encoder *intel_encoder);
 143         void (*disable)(struct intel_encoder *);
 144         void (*post_disable)(struct intel_encoder *);
 145         /* Read out the current hw state of this connector, returning true if
 146          * the encoder is active. If the encoder is enabled it also set the pipe
 147          * it is connected to in the pipe parameter. */
 148         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 149         /* Reconstructs the equivalent mode flags for the current hardware
 150          * state. This must be called _after_ display->get_pipe_config has
 151          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 152          * be set correctly before calling this function. */
 153         void (*get_config)(struct intel_encoder *,
 154                            struct intel_crtc_config *pipe_config);
 155         int crtc_mask;
 156         enum hpd_pin hpd_pin;
 157 };
 158
 159 struct intel_panel {
 160         struct drm_display_mode *fixed_mode;
 161         struct drm_display_mode *downclock_mode;
 162         int fitting_mode;
 163
 164         /* backlight */
 165         struct {
 166                 bool present;
 167                 u32 level;
 168                 u32 max;
 169                 bool enabled;
 170                 bool combination_mode;  /* gen 2/4 only */
 171                 bool active_low_pwm;
 172                 struct backlight_device *device;
 173         } backlight;
 174 };
 175
 176 struct intel_connector {
 177         struct drm_connector base;
 178         /*
 179          * The fixed encoder this connector is connected to.
 180          */
 181         struct intel_encoder *encoder;
 182
 183         /*
 184          * The new encoder this connector will be driven. Only differs from
 185          * encoder while a modeset is in progress.
 186          */
 187         struct intel_encoder *new_encoder;
 188
 189         /* Reads out the current hw, returning true if the connector is enabled
 190          * and active (i.e. dpms ON state). */
 191         bool (*get_hw_state)(struct intel_connector *);
 192
 193         /*
 194          * Removes all interfaces through which the connector is accessible
 195          * - like sysfs, debugfs entries -, so that no new operations can be
 196          * started on the connector. Also makes sure all currently pending
 197          * operations finish before returing.
 198          */
 199         void (*unregister)(struct intel_connector *);
 200
 201         /* Panel info for eDP and LVDS */
 202         struct intel_panel panel;
 203
 204         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 205         struct edid *edid;
 206
 207         /* since POLL and HPD connectors may use the same HPD line keep the native
 208            state of connector->polled in case hotplug storm detection changes it */
 209         u8 polled;
 210 };
 211
 212 typedef struct dpll {
 213         /* given values */
 214         int n;
 215         int m1, m2;
 216         int p1, p2;
 217         /* derived values */
 218         int     dot;
 219         int     vco;
 220         int     m;
 221         int     p;
 222 } intel_clock_t;
 223
 224 struct intel_plane_config {
 225         bool tiled;
 226         int size;
 227         u32 base;
 228 };
 229
 230 struct intel_crtc_config {
 231         /**
 232          * quirks - bitfield with hw state readout quirks
 233          *
 234          * For various reasons the hw state readout code might not be able to
 235          * completely faithfully read out the current state. These cases are
 236          * tracked with quirk flags so that fastboot and state checker can act
 237          * accordingly.
 238          */
 239 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 240 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 241         unsigned long quirks;
 242
 243         /* User requested mode, only valid as a starting point to
 244          * compute adjusted_mode, except in the case of (S)DVO where
 245          * it's also for the output timings of the (S)DVO chip.
 246          * adjusted_mode will then correspond to the S(DVO) chip's
 247          * preferred input timings. */
 248         struct drm_display_mode requested_mode;
 249         /* Actual pipe timings ie. what we program into the pipe timing
 250          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 251         struct drm_display_mode adjusted_mode;
 252
 253         /* Pipe source size (ie. panel fitter input size)
 254          * All planes will be positioned inside this space,
 255          * and get clipped at the edges. */
 256         int pipe_src_w, pipe_src_h;
 257
 258         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 259          * between pch encoders and cpu encoders. */
 260         bool has_pch_encoder;
 261
 262         /* CPU Transcoder for the pipe. Currently this can only differ from the
 263          * pipe on Haswell (where we have a special eDP transcoder). */
 264         enum transcoder cpu_transcoder;
 265
 266         /*
 267          * Use reduced/limited/broadcast rbg range, compressing from the full
 268          * range fed into the crtcs.
 269          */
 270         bool limited_color_range;
 271
 272         /* DP has a bunch of special case unfortunately, so mark the pipe
 273          * accordingly. */
 274         bool has_dp_encoder;
 275
 276         /*
 277          * Enable dithering, used when the selected pipe bpp doesn't match the
 278          * plane bpp.
 279          */
 280         bool dither;
 281
 282         /* Controls for the clock computation, to override various stages. */
 283         bool clock_set;
 284
 285         /* SDVO TV has a bunch of special case. To make multifunction encoders
 286          * work correctly, we need to track this at runtime.*/
 287         bool sdvo_tv_clock;
 288
 289         /*
 290          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 291          * required. This is set in the 2nd loop of calling encoder's
 292          * ->compute_config if the first pick doesn't work out.
 293          */
 294         bool bw_constrained;
 295
 296         /* Settings for the intel dpll used on pretty much everything but
 297          * haswell. */
 298         struct dpll dpll;
 299
 300         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 301         enum intel_dpll_id shared_dpll;
 302
 303         /* Actual register state of the dpll, for shared dpll cross-checking. */
 304         struct intel_dpll_hw_state dpll_hw_state;
 305
 306         int pipe_bpp;
 307         struct intel_link_m_n dp_m_n;
 308
 309         /* m2_n2 for eDP downclock */
 310         struct intel_link_m_n dp_m2_n2;
 311
 312         /*
 313          * Frequence the dpll for the port should run at. Differs from the
 314          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 315          * already multiplied by pixel_multiplier.
 316          */
 317         int port_clock;
 318
 319         /* Used by SDVO (and if we ever fix it, HDMI). */
 320         unsigned pixel_multiplier;
 321
 322         /* Panel fitter controls for gen2-gen4 + VLV */
 323         struct {
 324                 u32 control;
 325                 u32 pgm_ratios;
 326                 u32 lvds_border_bits;
 327         } gmch_pfit;
 328
 329         /* Panel fitter placement and size for Ironlake+ */
 330         struct {
 331                 u32 pos;
 332                 u32 size;
 333                 bool enabled;
 334         } pch_pfit;
 335
 336         /* FDI configuration, only valid if has_pch_encoder is set. */
 337         int fdi_lanes;
 338         struct intel_link_m_n fdi_m_n;
 339
 340         bool ips_enabled;
 341
 342         bool double_wide;
 343 };
 344
 345 struct intel_pipe_wm {
 346         struct intel_wm_level wm[5];
 347         uint32_t linetime;
 348         bool fbc_wm_enabled;
 349         bool pipe_enabled;
 350         bool sprites_enabled;
 351         bool sprites_scaled;
 352 };
 353
 354 struct intel_crtc {
 355         struct drm_crtc base;
 356         enum pipe pipe;
 357         enum plane plane;
 358         u8 lut_r[256], lut_g[256], lut_b[256];
 359         /*
 360          * Whether the crtc and the connected output pipeline is active. Implies
 361          * that crtc->enabled is set, i.e. the current mode configuration has
 362          * some outputs connected to this crtc.
 363          */
 364         bool active;
 365         unsigned long enabled_power_domains;
 366         bool eld_vld;
 367         bool primary_enabled; /* is the primary plane (partially) visible? */
 368         bool lowfreq_avail;
 369         struct intel_overlay *overlay;
 370         struct intel_unpin_work *unpin_work;
 371
 372         atomic_t unpin_work_count;
 373
 374         /* Display surface base address adjustement for pageflips. Note that on
 375          * gen4+ this only adjusts up to a tile, offsets within a tile are
 376          * handled in the hw itself (with the TILEOFF register). */
 377         unsigned long dspaddr_offset;
 378
 379         struct drm_i915_gem_object *cursor_bo;
 380         uint32_t cursor_addr;
 381         int16_t cursor_x, cursor_y;
 382         int16_t cursor_width, cursor_height;
 383         bool cursor_visible;
 384
 385         struct intel_plane_config plane_config;
 386         struct intel_crtc_config config;
 387         struct intel_crtc_config *new_config;
 388         bool new_enabled;
 389
 390         uint32_t ddi_pll_sel;
 391
 392         /* reset counter value when the last flip was submitted */
 393         unsigned int reset_counter;
 394
 395         /* Access to these should be protected by dev_priv->irq_lock. */
 396         bool cpu_fifo_underrun_disabled;
 397         bool pch_fifo_underrun_disabled;
 398
 399         /* per-pipe watermark state */
 400         struct {
 401                 /* watermarks currently being used  */
 402                 struct intel_pipe_wm active;
 403         } wm;
 404
 405         wait_queue_head_t vbl_wait;
 406 };
 407
 408 struct intel_plane_wm_parameters {
 409         uint32_t horiz_pixels;
 410         uint8_t bytes_per_pixel;
 411         bool enabled;
 412         bool scaled;
 413 };
 414
 415 struct intel_plane {
 416         struct drm_plane base;
 417         int plane;
 418         enum pipe pipe;
 419         struct drm_i915_gem_object *obj;
 420         bool can_scale;
 421         int max_downscale;
 422         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 423         int crtc_x, crtc_y;
 424         unsigned int crtc_w, crtc_h;
 425         uint32_t src_x, src_y;
 426         uint32_t src_w, src_h;
 427
 428         /* Since we need to change the watermarks before/after
 429          * enabling/disabling the planes, we need to store the parameters here
 430          * as the other pieces of the struct may not reflect the values we want
 431          * for the watermark calculations. Currently only Haswell uses this.
 432          */
 433         struct intel_plane_wm_parameters wm;
 434
 435         void (*update_plane)(struct drm_plane *plane,
 436                              struct drm_crtc *crtc,
 437                              struct drm_framebuffer *fb,
 438                              struct drm_i915_gem_object *obj,
 439                              int crtc_x, int crtc_y,
 440                              unsigned int crtc_w, unsigned int crtc_h,
 441                              uint32_t x, uint32_t y,
 442                              uint32_t src_w, uint32_t src_h);
 443         void (*disable_plane)(struct drm_plane *plane,
 444                               struct drm_crtc *crtc);
 445         int (*update_colorkey)(struct drm_plane *plane,
 446                                struct drm_intel_sprite_colorkey *key);
 447         void (*get_colorkey)(struct drm_plane *plane,
 448                              struct drm_intel_sprite_colorkey *key);
 449 };
 450
 451 struct intel_watermark_params {
 452         unsigned long fifo_size;
 453         unsigned long max_wm;
 454         unsigned long default_wm;
 455         unsigned long guard_size;
 456         unsigned long cacheline_size;
 457 };
 458
 459 struct cxsr_latency {
 460         int is_desktop;
 461         int is_ddr3;
 462         unsigned long fsb_freq;
 463         unsigned long mem_freq;
 464         unsigned long display_sr;
 465         unsigned long display_hpll_disable;
 466         unsigned long cursor_sr;
 467         unsigned long cursor_hpll_disable;
 468 };
 469
 470 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 471 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 472 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 473 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 474 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 475
 476 struct intel_hdmi {
 477         u32 hdmi_reg;
 478         int ddc_bus;
 479         uint32_t color_range;
 480         bool color_range_auto;
 481         bool has_hdmi_sink;
 482         bool has_audio;
 483         enum hdmi_force_audio force_audio;
 484         bool rgb_quant_range_selectable;
 485         void (*write_infoframe)(struct drm_encoder *encoder,
 486                                 enum hdmi_infoframe_type type,
 487                                 const void *frame, ssize_t len);
 488         void (*set_infoframes)(struct drm_encoder *encoder,
 489                                struct drm_display_mode *adjusted_mode);
 490 };
 491
 492 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 493
 494 /**
 495  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 496  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 497  * parsing for same resolution.
 498  */
 499 enum edp_drrs_refresh_rate_type {
 500         DRRS_HIGH_RR,
 501         DRRS_LOW_RR,
 502         DRRS_MAX_RR, /* RR count */
 503 };
 504
 505 struct intel_dp {
 506         uint32_t output_reg;
 507         uint32_t aux_ch_ctl_reg;
 508         uint32_t DP;
 509         bool has_audio;
 510         enum hdmi_force_audio force_audio;
 511         uint32_t color_range;
 512         bool color_range_auto;
 513         uint8_t link_bw;
 514         uint8_t lane_count;
 515         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 516         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 517         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 518         struct drm_dp_aux aux;
 519         uint8_t train_set[4];
 520         int panel_power_up_delay;
 521         int panel_power_down_delay;
 522         int panel_power_cycle_delay;
 523         int backlight_on_delay;
 524         int backlight_off_delay;
 525         struct delayed_work panel_vdd_work;
 526         bool want_panel_vdd;
 527         unsigned long last_power_cycle;
 528         unsigned long last_power_on;
 529         unsigned long last_backlight_off;
 530         bool psr_setup_done;
 531         bool use_tps3;
 532         struct intel_connector *attached_connector;
 533
 534         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 535         /*
 536          * This function returns the value we have to program the AUX_CTL
 537          * register with to kick off an AUX transaction.
 538          */
 539         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 540                                      bool has_aux_irq,
 541                                      int send_bytes,
 542                                      uint32_t aux_clock_divider);
 543         struct {
 544                 enum drrs_support_type type;
 545                 enum edp_drrs_refresh_rate_type refresh_rate_type;
 546                 struct mutex mutex;
 547         } drrs_state;
 548
 549 };
 550
 551 struct intel_digital_port {
 552         struct intel_encoder base;
 553         enum port port;
 554         u32 saved_port_bits;
 555         struct intel_dp dp;
 556         struct intel_hdmi hdmi;
 557 };
 558
 559 static inline int
 560 vlv_dport_to_channel(struct intel_digital_port *dport)
 561 {
 562         switch (dport->port) {
 563         case PORT_B:
 564         case PORT_D:
 565                 return DPIO_CH0;
 566         case PORT_C:
 567                 return DPIO_CH1;
 568         default:
 569                 BUG();
 570         }
 571 }
 572
 573 static inline int
 574 vlv_pipe_to_channel(enum pipe pipe)
 575 {
 576         switch (pipe) {
 577         case PIPE_A:
 578         case PIPE_C:
 579                 return DPIO_CH0;
 580         case PIPE_B:
 581                 return DPIO_CH1;
 582         default:
 583                 BUG();
 584         }
 585 }
 586
 587 static inline struct drm_crtc *
 588 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 589 {
 590         struct drm_i915_private *dev_priv = dev->dev_private;
 591         return dev_priv->pipe_to_crtc_mapping[pipe];
 592 }
 593
 594 static inline struct drm_crtc *
 595 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 596 {
 597         struct drm_i915_private *dev_priv = dev->dev_private;
 598         return dev_priv->plane_to_crtc_mapping[plane];
 599 }
 600
 601 struct intel_unpin_work {
 602         struct work_struct work;
 603         struct drm_crtc *crtc;
 604         struct drm_i915_gem_object *old_fb_obj;
 605         struct drm_i915_gem_object *pending_flip_obj;
 606         struct drm_pending_vblank_event *event;
 607         atomic_t pending;
 608 #define INTEL_FLIP_INACTIVE     0
 609 #define INTEL_FLIP_PENDING      1
 610 #define INTEL_FLIP_COMPLETE     2
 611         bool enable_stall_check;
 612 };
 613
 614 struct intel_set_config {
 615         struct drm_encoder **save_connector_encoders;
 616         struct drm_crtc **save_encoder_crtcs;
 617         bool *save_crtc_enabled;
 618
 619         bool fb_changed;
 620         bool mode_changed;
 621 };
 622
 623 struct intel_load_detect_pipe {
 624         struct drm_framebuffer *release_fb;
 625         bool load_detect_temp;
 626         int dpms_mode;
 627 };
 628
 629 static inline struct intel_encoder *
 630 intel_attached_encoder(struct drm_connector *connector)
 631 {
 632         return to_intel_connector(connector)->encoder;
 633 }
 634
 635 static inline struct intel_digital_port *
 636 enc_to_dig_port(struct drm_encoder *encoder)
 637 {
 638         return container_of(encoder, struct intel_digital_port, base.base);
 639 }
 640
 641 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 642 {
 643         return &enc_to_dig_port(encoder)->dp;
 644 }
 645
 646 static inline struct intel_digital_port *
 647 dp_to_dig_port(struct intel_dp *intel_dp)
 648 {
 649         return container_of(intel_dp, struct intel_digital_port, dp);
 650 }
 651
 652 static inline struct intel_digital_port *
 653 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 654 {
 655         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 656 }
 657
 658
 659 /* i915_irq.c */
 660 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 661                                            enum pipe pipe, bool enable);
 662 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 663                                              enum pipe pipe, bool enable);
 664 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 665                                            enum transcoder pch_transcoder,
 666                                            bool enable);
 667 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 668 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 669 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 670 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 671 void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 672 void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 673 void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
 674 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
 675 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 676
 677
 678 /* intel_crt.c */
 679 void intel_crt_init(struct drm_device *dev);
 680
 681
 682 /* intel_ddi.c */
 683 void intel_prepare_ddi(struct drm_device *dev);
 684 void hsw_fdi_link_train(struct drm_crtc *crtc);
 685 void intel_ddi_init(struct drm_device *dev, enum port port);
 686 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 687 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 688 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 689 void intel_ddi_pll_init(struct drm_device *dev);
 690 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 691 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 692                                        enum transcoder cpu_transcoder);
 693 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 694 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 695 void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 696 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 697 void intel_ddi_pll_enable(struct intel_crtc *crtc);
 698 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 699 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 700 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 701 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 702 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 703 void intel_ddi_get_config(struct intel_encoder *encoder,
 704                           struct intel_crtc_config *pipe_config);
 705
 706
 707 /* intel_display.c */
 708 const char *intel_output_name(int output);
 709 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 710 int intel_pch_rawclk(struct drm_device *dev);
 711 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv);
 712 void intel_mark_busy(struct drm_device *dev);
 713 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 714                         struct intel_ring_buffer *ring);
 715 void intel_mark_idle(struct drm_device *dev);
 716 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 717 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 718 void intel_encoder_destroy(struct drm_encoder *encoder);
 719 void intel_connector_dpms(struct drm_connector *, int mode);
 720 bool intel_connector_get_hw_state(struct intel_connector *connector);
 721 void intel_modeset_check_state(struct drm_device *dev);
 722 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 723                                 struct intel_digital_port *port);
 724 void intel_connector_attach_encoder(struct intel_connector *connector,
 725                                     struct intel_encoder *encoder);
 726 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 727 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 728                                              struct drm_crtc *crtc);
 729 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 730 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 731                                 struct drm_file *file_priv);
 732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 733                                              enum pipe pipe);
 734 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 735 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 736 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 737 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 738                          struct intel_digital_port *dport);
 739 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 740                                 struct drm_display_mode *mode,
 741                                 struct intel_load_detect_pipe *old);
 742 void intel_release_load_detect_pipe(struct drm_connector *connector,
 743                                     struct intel_load_detect_pipe *old);
 744 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 745                                struct drm_i915_gem_object *obj,
 746                                struct intel_ring_buffer *pipelined);
 747 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 748 struct drm_framebuffer *
 749 __intel_framebuffer_create(struct drm_device *dev,
 750                            struct drm_mode_fb_cmd2 *mode_cmd,
 751                            struct drm_i915_gem_object *obj);
 752 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 753 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 754 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 755 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 756 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 757                         struct intel_shared_dpll *pll,
 758                         bool state);
 759 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 760 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 761 void assert_pll(struct drm_i915_private *dev_priv,
 762                 enum pipe pipe, bool state);
 763 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 764 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 765 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 766                        enum pipe pipe, bool state);
 767 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 768 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 769 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 770 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 771 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 772 void intel_write_eld(struct drm_encoder *encoder,
 773                      struct drm_display_mode *mode);
 774 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 775                                              unsigned int tiling_mode,
 776                                              unsigned int bpp,
 777                                              unsigned int pitch);
 778 void intel_display_handle_reset(struct drm_device *dev);
 779 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 780 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 781 void intel_dp_get_m_n(struct intel_crtc *crtc,
 782                       struct intel_crtc_config *pipe_config);
 783 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 784 void
 785 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 786                                 int dotclock);
 787 bool intel_crtc_active(struct drm_crtc *crtc);
 788 void hsw_enable_ips(struct intel_crtc *crtc);
 789 void hsw_disable_ips(struct intel_crtc *crtc);
 790 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
 791 enum intel_display_power_domain
 792 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 793 int valleyview_get_vco(struct drm_i915_private *dev_priv);
 794 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 795                                  struct intel_crtc_config *pipe_config);
 796 int intel_format_to_fourcc(int format);
 797
 798 /* intel_dp.c */
 799 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 800 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 801                              struct intel_connector *intel_connector);
 802 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 803 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 804 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 805 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 806 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 807 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 808 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 809 bool intel_dp_compute_config(struct intel_encoder *encoder,
 810                              struct intel_crtc_config *pipe_config);
 811 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 812 void intel_edp_backlight_on(struct intel_dp *intel_dp);
 813 void intel_edp_backlight_off(struct intel_dp *intel_dp);
 814 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 815 void intel_edp_panel_on(struct intel_dp *intel_dp);
 816 void intel_edp_panel_off(struct intel_dp *intel_dp);
 817 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 818 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 819 void intel_edp_psr_update(struct drm_device *dev);
 820 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
 821
 822 /* intel_dsi.c */
 823 bool intel_dsi_init(struct drm_device *dev);
 824
 825
 826 /* intel_dvo.c */
 827 void intel_dvo_init(struct drm_device *dev);
 828
 829
 830 /* legacy fbdev emulation in intel_fbdev.c */
 831 #ifdef CONFIG_DRM_I915_FBDEV
 832 extern int intel_fbdev_init(struct drm_device *dev);
 833 extern void intel_fbdev_initial_config(struct drm_device *dev);
 834 extern void intel_fbdev_fini(struct drm_device *dev);
 835 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 836 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 837 extern void intel_fbdev_restore_mode(struct drm_device *dev);
 838 #else
 839 static inline int intel_fbdev_init(struct drm_device *dev)
 840 {
 841         return 0;
 842 }
 843
 844 static inline void intel_fbdev_initial_config(struct drm_device *dev)
 845 {
 846 }
 847
 848 static inline void intel_fbdev_fini(struct drm_device *dev)
 849 {
 850 }
 851
 852 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
 853 {
 854 }
 855
 856 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 857 {
 858 }
 859 #endif
 860
 861 /* intel_hdmi.c */
 862 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 863 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 864                                struct intel_connector *intel_connector);
 865 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 866 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 867                                struct intel_crtc_config *pipe_config);
 868
 869
 870 /* intel_lvds.c */
 871 void intel_lvds_init(struct drm_device *dev);
 872 bool intel_is_dual_link_lvds(struct drm_device *dev);
 873
 874
 875 /* intel_modes.c */
 876 int intel_connector_update_modes(struct drm_connector *connector,
 877                                  struct edid *edid);
 878 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 879 void intel_attach_force_audio_property(struct drm_connector *connector);
 880 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 881
 882
 883 /* intel_overlay.c */
 884 void intel_setup_overlay(struct drm_device *dev);
 885 void intel_cleanup_overlay(struct drm_device *dev);
 886 int intel_overlay_switch_off(struct intel_overlay *overlay);
 887 int intel_overlay_put_image(struct drm_device *dev, void *data,
 888                             struct drm_file *file_priv);
 889 int intel_overlay_attrs(struct drm_device *dev, void *data,
 890                         struct drm_file *file_priv);
 891
 892
 893 /* intel_panel.c */
 894 int intel_panel_init(struct intel_panel *panel,
 895                      struct drm_display_mode *fixed_mode,
 896                      struct drm_display_mode *downclock_mode);
 897 void intel_panel_fini(struct intel_panel *panel);
 898 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
 899                             struct drm_display_mode *adjusted_mode);
 900 void intel_pch_panel_fitting(struct intel_crtc *crtc,
 901                              struct intel_crtc_config *pipe_config,
 902                              int fitting_mode);
 903 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 904                               struct intel_crtc_config *pipe_config,
 905                               int fitting_mode);
 906 void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
 907                                u32 max);
 908 int intel_panel_setup_backlight(struct drm_connector *connector);
 909 void intel_panel_enable_backlight(struct intel_connector *connector);
 910 void intel_panel_disable_backlight(struct intel_connector *connector);
 911 void intel_panel_destroy_backlight(struct drm_connector *connector);
 912 void intel_panel_init_backlight_funcs(struct drm_device *dev);
 913 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 914 extern struct drm_display_mode *intel_find_panel_downclock(
 915                                 struct drm_device *dev,
 916                                 struct drm_display_mode *fixed_mode,
 917                                 struct drm_connector *connector);
 918
 919 /* intel_pm.c */
 920 void intel_init_clock_gating(struct drm_device *dev);
 921 void intel_suspend_hw(struct drm_device *dev);
 922 int ilk_wm_max_level(const struct drm_device *dev);
 923 void intel_update_watermarks(struct drm_crtc *crtc);
 924 void intel_update_sprite_watermarks(struct drm_plane *plane,
 925                                     struct drm_crtc *crtc,
 926                                     uint32_t sprite_width, int pixel_size,
 927                                     bool enabled, bool scaled);
 928 void intel_init_pm(struct drm_device *dev);
 929 void intel_pm_setup(struct drm_device *dev);
 930 bool intel_fbc_enabled(struct drm_device *dev);
 931 void intel_update_fbc(struct drm_device *dev);
 932 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 933 void intel_gpu_ips_teardown(void);
 934 int intel_power_domains_init(struct drm_i915_private *);
 935 void intel_power_domains_remove(struct drm_i915_private *);
 936 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
 937                                  enum intel_display_power_domain domain);
 938 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
 939                                     enum intel_display_power_domain domain);
 940 void intel_display_power_get(struct drm_i915_private *dev_priv,
 941                              enum intel_display_power_domain domain);
 942 void intel_display_power_put(struct drm_i915_private *dev_priv,
 943                              enum intel_display_power_domain domain);
 944 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
 945 void intel_init_gt_powersave(struct drm_device *dev);
 946 void intel_cleanup_gt_powersave(struct drm_device *dev);
 947 void intel_enable_gt_powersave(struct drm_device *dev);
 948 void intel_disable_gt_powersave(struct drm_device *dev);
 949 void intel_reset_gt_powersave(struct drm_device *dev);
 950 void ironlake_teardown_rc6(struct drm_device *dev);
 951 void gen6_update_ring_freq(struct drm_device *dev);
 952 void gen6_rps_idle(struct drm_i915_private *dev_priv);
 953 void gen6_rps_boost(struct drm_i915_private *dev_priv);
 954 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
 955 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 956 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
 957 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
 958 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
 959 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
 960 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
 961 void ilk_wm_get_hw_state(struct drm_device *dev);
 962
 963
 964 /* intel_sdvo.c */
 965 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
 966
 967
 968 /* intel_sprite.c */
 969 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 970 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 971                                enum plane plane);
 972 void intel_plane_restore(struct drm_plane *plane);
 973 void intel_plane_disable(struct drm_plane *plane);
 974 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 975                               struct drm_file *file_priv);
 976 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 977                               struct drm_file *file_priv);
 978
 979
 980 /* intel_tv.c */
 981 void intel_tv_init(struct drm_device *dev);
 982
 983 #endif /* __INTEL_DRV_H__ */