drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000 * (x))
  69 #define MHz(x) KHz(1000 * (x))
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80
  81 #define INTEL_I2C_BUS_DVO 1
  82 #define INTEL_I2C_BUS_SDVO 2
  83
  84 /* these are outputs from the chip - integrated only
  85    external chips are via DVO or SDVO output */
  86 #define INTEL_OUTPUT_UNUSED 0
  87 #define INTEL_OUTPUT_ANALOG 1
  88 #define INTEL_OUTPUT_DVO 2
  89 #define INTEL_OUTPUT_SDVO 3
  90 #define INTEL_OUTPUT_LVDS 4
  91 #define INTEL_OUTPUT_TVOUT 5
  92 #define INTEL_OUTPUT_HDMI 6
  93 #define INTEL_OUTPUT_DISPLAYPORT 7
  94 #define INTEL_OUTPUT_EDP 8
  95 #define INTEL_OUTPUT_DSI 9
  96 #define INTEL_OUTPUT_UNKNOWN 10
  97
  98 #define INTEL_DVO_CHIP_NONE 0
  99 #define INTEL_DVO_CHIP_LVDS 1
 100 #define INTEL_DVO_CHIP_TMDS 2
 101 #define INTEL_DVO_CHIP_TVOUT 4
 102
 103 #define INTEL_DSI_COMMAND_MODE  0
 104 #define INTEL_DSI_VIDEO_MODE    1
 105
 106 struct intel_framebuffer {
 107         struct drm_framebuffer base;
 108         struct drm_i915_gem_object *obj;
 109 };
 110
 111 struct intel_fbdev {
 112         struct drm_fb_helper helper;
 113         struct intel_framebuffer *fb;
 114         struct list_head fbdev_list;
 115         struct drm_display_mode *our_mode;
 116 };
 117
 118 struct intel_encoder {
 119         struct drm_encoder base;
 120         /*
 121          * The new crtc this encoder will be driven from. Only differs from
 122          * base->crtc while a modeset is in progress.
 123          */
 124         struct intel_crtc *new_crtc;
 125
 126         int type;
 127         /*
 128          * Intel hw has only one MUX where encoders could be clone, hence a
 129          * simple flag is enough to compute the possible_clones mask.
 130          */
 131         bool cloneable;
 132         bool connectors_active;
 133         void (*hot_plug)(struct intel_encoder *);
 134         bool (*compute_config)(struct intel_encoder *,
 135                                struct intel_crtc_config *);
 136         void (*pre_pll_enable)(struct intel_encoder *);
 137         void (*pre_enable)(struct intel_encoder *);
 138         void (*enable)(struct intel_encoder *);
 139         void (*mode_set)(struct intel_encoder *intel_encoder);
 140         void (*disable)(struct intel_encoder *);
 141         void (*post_disable)(struct intel_encoder *);
 142         /* Read out the current hw state of this connector, returning true if
 143          * the encoder is active. If the encoder is enabled it also set the pipe
 144          * it is connected to in the pipe parameter. */
 145         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 146         /* Reconstructs the equivalent mode flags for the current hardware
 147          * state. This must be called _after_ display->get_pipe_config has
 148          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 149          * be set correctly before calling this function. */
 150         void (*get_config)(struct intel_encoder *,
 151                            struct intel_crtc_config *pipe_config);
 152         int crtc_mask;
 153         enum hpd_pin hpd_pin;
 154 };
 155
 156 struct intel_panel {
 157         struct drm_display_mode *fixed_mode;
 158         struct drm_display_mode *downclock_mode;
 159         int fitting_mode;
 160
 161         /* backlight */
 162         struct {
 163                 bool present;
 164                 u32 level;
 165                 u32 max;
 166                 bool enabled;
 167                 bool combination_mode;  /* gen 2/4 only */
 168                 bool active_low_pwm;
 169                 struct backlight_device *device;
 170         } backlight;
 171 };
 172
 173 struct intel_connector {
 174         struct drm_connector base;
 175         /*
 176          * The fixed encoder this connector is connected to.
 177          */
 178         struct intel_encoder *encoder;
 179
 180         /*
 181          * The new encoder this connector will be driven. Only differs from
 182          * encoder while a modeset is in progress.
 183          */
 184         struct intel_encoder *new_encoder;
 185
 186         /* Reads out the current hw, returning true if the connector is enabled
 187          * and active (i.e. dpms ON state). */
 188         bool (*get_hw_state)(struct intel_connector *);
 189
 190         /*
 191          * Removes all interfaces through which the connector is accessible
 192          * - like sysfs, debugfs entries -, so that no new operations can be
 193          * started on the connector. Also makes sure all currently pending
 194          * operations finish before returing.
 195          */
 196         void (*unregister)(struct intel_connector *);
 197
 198         /* Panel info for eDP and LVDS */
 199         struct intel_panel panel;
 200
 201         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 202         struct edid *edid;
 203
 204         /* since POLL and HPD connectors may use the same HPD line keep the native
 205            state of connector->polled in case hotplug storm detection changes it */
 206         u8 polled;
 207 };
 208
 209 typedef struct dpll {
 210         /* given values */
 211         int n;
 212         int m1, m2;
 213         int p1, p2;
 214         /* derived values */
 215         int     dot;
 216         int     vco;
 217         int     m;
 218         int     p;
 219 } intel_clock_t;
 220
 221 struct intel_crtc_config {
 222         /**
 223          * quirks - bitfield with hw state readout quirks
 224          *
 225          * For various reasons the hw state readout code might not be able to
 226          * completely faithfully read out the current state. These cases are
 227          * tracked with quirk flags so that fastboot and state checker can act
 228          * accordingly.
 229          */
 230 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
 231         unsigned long quirks;
 232
 233         /* User requested mode, only valid as a starting point to
 234          * compute adjusted_mode, except in the case of (S)DVO where
 235          * it's also for the output timings of the (S)DVO chip.
 236          * adjusted_mode will then correspond to the S(DVO) chip's
 237          * preferred input timings. */
 238         struct drm_display_mode requested_mode;
 239         /* Actual pipe timings ie. what we program into the pipe timing
 240          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 241         struct drm_display_mode adjusted_mode;
 242
 243         /* Pipe source size (ie. panel fitter input size)
 244          * All planes will be positioned inside this space,
 245          * and get clipped at the edges. */
 246         int pipe_src_w, pipe_src_h;
 247
 248         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 249          * between pch encoders and cpu encoders. */
 250         bool has_pch_encoder;
 251
 252         /* CPU Transcoder for the pipe. Currently this can only differ from the
 253          * pipe on Haswell (where we have a special eDP transcoder). */
 254         enum transcoder cpu_transcoder;
 255
 256         /*
 257          * Use reduced/limited/broadcast rbg range, compressing from the full
 258          * range fed into the crtcs.
 259          */
 260         bool limited_color_range;
 261
 262         /* DP has a bunch of special case unfortunately, so mark the pipe
 263          * accordingly. */
 264         bool has_dp_encoder;
 265
 266         /*
 267          * Enable dithering, used when the selected pipe bpp doesn't match the
 268          * plane bpp.
 269          */
 270         bool dither;
 271
 272         /* Controls for the clock computation, to override various stages. */
 273         bool clock_set;
 274
 275         /* SDVO TV has a bunch of special case. To make multifunction encoders
 276          * work correctly, we need to track this at runtime.*/
 277         bool sdvo_tv_clock;
 278
 279         /*
 280          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 281          * required. This is set in the 2nd loop of calling encoder's
 282          * ->compute_config if the first pick doesn't work out.
 283          */
 284         bool bw_constrained;
 285
 286         /* Settings for the intel dpll used on pretty much everything but
 287          * haswell. */
 288         struct dpll dpll;
 289
 290         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 291         enum intel_dpll_id shared_dpll;
 292
 293         /* Actual register state of the dpll, for shared dpll cross-checking. */
 294         struct intel_dpll_hw_state dpll_hw_state;
 295
 296         int pipe_bpp;
 297         struct intel_link_m_n dp_m_n;
 298
 299         /*
 300          * Frequence the dpll for the port should run at. Differs from the
 301          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 302          * already multiplied by pixel_multiplier.
 303          */
 304         int port_clock;
 305
 306         /* Used by SDVO (and if we ever fix it, HDMI). */
 307         unsigned pixel_multiplier;
 308
 309         /* Panel fitter controls for gen2-gen4 + VLV */
 310         struct {
 311                 u32 control;
 312                 u32 pgm_ratios;
 313                 u32 lvds_border_bits;
 314         } gmch_pfit;
 315
 316         /* Panel fitter placement and size for Ironlake+ */
 317         struct {
 318                 u32 pos;
 319                 u32 size;
 320                 bool enabled;
 321         } pch_pfit;
 322
 323         /* FDI configuration, only valid if has_pch_encoder is set. */
 324         int fdi_lanes;
 325         struct intel_link_m_n fdi_m_n;
 326
 327         bool ips_enabled;
 328
 329         bool double_wide;
 330 };
 331
 332 struct intel_pipe_wm {
 333         struct intel_wm_level wm[5];
 334         uint32_t linetime;
 335         bool fbc_wm_enabled;
 336 };
 337
 338 struct intel_crtc {
 339         struct drm_crtc base;
 340         enum pipe pipe;
 341         enum plane plane;
 342         u8 lut_r[256], lut_g[256], lut_b[256];
 343         /*
 344          * Whether the crtc and the connected output pipeline is active. Implies
 345          * that crtc->enabled is set, i.e. the current mode configuration has
 346          * some outputs connected to this crtc.
 347          */
 348         bool active;
 349         unsigned long enabled_power_domains;
 350         bool eld_vld;
 351         bool primary_enabled; /* is the primary plane (partially) visible? */
 352         bool lowfreq_avail;
 353         struct intel_overlay *overlay;
 354         struct intel_unpin_work *unpin_work;
 355
 356         atomic_t unpin_work_count;
 357
 358         /* Display surface base address adjustement for pageflips. Note that on
 359          * gen4+ this only adjusts up to a tile, offsets within a tile are
 360          * handled in the hw itself (with the TILEOFF register). */
 361         unsigned long dspaddr_offset;
 362
 363         struct drm_i915_gem_object *cursor_bo;
 364         uint32_t cursor_addr;
 365         int16_t cursor_x, cursor_y;
 366         int16_t cursor_width, cursor_height;
 367         bool cursor_visible;
 368
 369         struct intel_crtc_config config;
 370         struct intel_crtc_config *new_config;
 371         bool new_enabled;
 372
 373         uint32_t ddi_pll_sel;
 374
 375         /* reset counter value when the last flip was submitted */
 376         unsigned int reset_counter;
 377
 378         /* Access to these should be protected by dev_priv->irq_lock. */
 379         bool cpu_fifo_underrun_disabled;
 380         bool pch_fifo_underrun_disabled;
 381
 382         /* per-pipe watermark state */
 383         struct {
 384                 /* watermarks currently being used  */
 385                 struct intel_pipe_wm active;
 386         } wm;
 387 };
 388
 389 struct intel_plane_wm_parameters {
 390         uint32_t horiz_pixels;
 391         uint8_t bytes_per_pixel;
 392         bool enabled;
 393         bool scaled;
 394 };
 395
 396 struct intel_plane {
 397         struct drm_plane base;
 398         int plane;
 399         enum pipe pipe;
 400         struct drm_i915_gem_object *obj;
 401         bool can_scale;
 402         int max_downscale;
 403         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 404         int crtc_x, crtc_y;
 405         unsigned int crtc_w, crtc_h;
 406         uint32_t src_x, src_y;
 407         uint32_t src_w, src_h;
 408
 409         /* Since we need to change the watermarks before/after
 410          * enabling/disabling the planes, we need to store the parameters here
 411          * as the other pieces of the struct may not reflect the values we want
 412          * for the watermark calculations. Currently only Haswell uses this.
 413          */
 414         struct intel_plane_wm_parameters wm;
 415
 416         void (*update_plane)(struct drm_plane *plane,
 417                              struct drm_crtc *crtc,
 418                              struct drm_framebuffer *fb,
 419                              struct drm_i915_gem_object *obj,
 420                              int crtc_x, int crtc_y,
 421                              unsigned int crtc_w, unsigned int crtc_h,
 422                              uint32_t x, uint32_t y,
 423                              uint32_t src_w, uint32_t src_h);
 424         void (*disable_plane)(struct drm_plane *plane,
 425                               struct drm_crtc *crtc);
 426         int (*update_colorkey)(struct drm_plane *plane,
 427                                struct drm_intel_sprite_colorkey *key);
 428         void (*get_colorkey)(struct drm_plane *plane,
 429                              struct drm_intel_sprite_colorkey *key);
 430 };
 431
 432 struct intel_watermark_params {
 433         unsigned long fifo_size;
 434         unsigned long max_wm;
 435         unsigned long default_wm;
 436         unsigned long guard_size;
 437         unsigned long cacheline_size;
 438 };
 439
 440 struct cxsr_latency {
 441         int is_desktop;
 442         int is_ddr3;
 443         unsigned long fsb_freq;
 444         unsigned long mem_freq;
 445         unsigned long display_sr;
 446         unsigned long display_hpll_disable;
 447         unsigned long cursor_sr;
 448         unsigned long cursor_hpll_disable;
 449 };
 450
 451 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 452 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 453 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 454 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 455 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 456
 457 struct intel_hdmi {
 458         u32 hdmi_reg;
 459         int ddc_bus;
 460         uint32_t color_range;
 461         bool color_range_auto;
 462         bool has_hdmi_sink;
 463         bool has_audio;
 464         enum hdmi_force_audio force_audio;
 465         bool rgb_quant_range_selectable;
 466         void (*write_infoframe)(struct drm_encoder *encoder,
 467                                 enum hdmi_infoframe_type type,
 468                                 const void *frame, ssize_t len);
 469         void (*set_infoframes)(struct drm_encoder *encoder,
 470                                struct drm_display_mode *adjusted_mode);
 471 };
 472
 473 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 474
 475 struct intel_dp {
 476         uint32_t output_reg;
 477         uint32_t aux_ch_ctl_reg;
 478         uint32_t DP;
 479         bool has_audio;
 480         enum hdmi_force_audio force_audio;
 481         uint32_t color_range;
 482         bool color_range_auto;
 483         uint8_t link_bw;
 484         uint8_t lane_count;
 485         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 486         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 487         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 488         struct drm_dp_aux aux;
 489         uint8_t train_set[4];
 490         int panel_power_up_delay;
 491         int panel_power_down_delay;
 492         int panel_power_cycle_delay;
 493         int backlight_on_delay;
 494         int backlight_off_delay;
 495         struct delayed_work panel_vdd_work;
 496         bool want_panel_vdd;
 497         unsigned long last_power_cycle;
 498         unsigned long last_power_on;
 499         unsigned long last_backlight_off;
 500         bool psr_setup_done;
 501         bool use_tps3;
 502         struct intel_connector *attached_connector;
 503
 504         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 505         /*
 506          * This function returns the value we have to program the AUX_CTL
 507          * register with to kick off an AUX transaction.
 508          */
 509         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 510                                      bool has_aux_irq,
 511                                      int send_bytes,
 512                                      uint32_t aux_clock_divider);
 513 };
 514
 515 struct intel_digital_port {
 516         struct intel_encoder base;
 517         enum port port;
 518         u32 saved_port_bits;
 519         struct intel_dp dp;
 520         struct intel_hdmi hdmi;
 521 };
 522
 523 static inline int
 524 vlv_dport_to_channel(struct intel_digital_port *dport)
 525 {
 526         switch (dport->port) {
 527         case PORT_B:
 528                 return DPIO_CH0;
 529         case PORT_C:
 530                 return DPIO_CH1;
 531         default:
 532                 BUG();
 533         }
 534 }
 535
 536 static inline struct drm_crtc *
 537 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 538 {
 539         struct drm_i915_private *dev_priv = dev->dev_private;
 540         return dev_priv->pipe_to_crtc_mapping[pipe];
 541 }
 542
 543 static inline struct drm_crtc *
 544 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 545 {
 546         struct drm_i915_private *dev_priv = dev->dev_private;
 547         return dev_priv->plane_to_crtc_mapping[plane];
 548 }
 549
 550 struct intel_unpin_work {
 551         struct work_struct work;
 552         struct drm_crtc *crtc;
 553         struct drm_i915_gem_object *old_fb_obj;
 554         struct drm_i915_gem_object *pending_flip_obj;
 555         struct drm_pending_vblank_event *event;
 556         atomic_t pending;
 557 #define INTEL_FLIP_INACTIVE     0
 558 #define INTEL_FLIP_PENDING      1
 559 #define INTEL_FLIP_COMPLETE     2
 560         bool enable_stall_check;
 561 };
 562
 563 struct intel_set_config {
 564         struct drm_encoder **save_connector_encoders;
 565         struct drm_crtc **save_encoder_crtcs;
 566         bool *save_crtc_enabled;
 567
 568         bool fb_changed;
 569         bool mode_changed;
 570 };
 571
 572 struct intel_load_detect_pipe {
 573         struct drm_framebuffer *release_fb;
 574         bool load_detect_temp;
 575         int dpms_mode;
 576 };
 577
 578 static inline struct intel_encoder *
 579 intel_attached_encoder(struct drm_connector *connector)
 580 {
 581         return to_intel_connector(connector)->encoder;
 582 }
 583
 584 static inline struct intel_digital_port *
 585 enc_to_dig_port(struct drm_encoder *encoder)
 586 {
 587         return container_of(encoder, struct intel_digital_port, base.base);
 588 }
 589
 590 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 591 {
 592         return &enc_to_dig_port(encoder)->dp;
 593 }
 594
 595 static inline struct intel_digital_port *
 596 dp_to_dig_port(struct intel_dp *intel_dp)
 597 {
 598         return container_of(intel_dp, struct intel_digital_port, dp);
 599 }
 600
 601 static inline struct intel_digital_port *
 602 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 603 {
 604         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 605 }
 606
 607
 608 /* i915_irq.c */
 609 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 610                                            enum pipe pipe, bool enable);
 611 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 612                                              enum pipe pipe, bool enable);
 613 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 614                                            enum transcoder pch_transcoder,
 615                                            bool enable);
 616 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 617 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 618 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 619 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 620 void hsw_pc8_disable_interrupts(struct drm_device *dev);
 621 void hsw_pc8_restore_interrupts(struct drm_device *dev);
 622
 623
 624 /* intel_crt.c */
 625 void intel_crt_init(struct drm_device *dev);
 626
 627
 628 /* intel_ddi.c */
 629 void intel_prepare_ddi(struct drm_device *dev);
 630 void hsw_fdi_link_train(struct drm_crtc *crtc);
 631 void intel_ddi_init(struct drm_device *dev, enum port port);
 632 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 633 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 634 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 635 void intel_ddi_pll_init(struct drm_device *dev);
 636 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 637 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 638                                        enum transcoder cpu_transcoder);
 639 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 640 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 641 void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 642 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 643 void intel_ddi_pll_enable(struct intel_crtc *crtc);
 644 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 645 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 646 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 647 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 648 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 649 void intel_ddi_get_config(struct intel_encoder *encoder,
 650                           struct intel_crtc_config *pipe_config);
 651
 652
 653 /* intel_display.c */
 654 const char *intel_output_name(int output);
 655 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 656 int intel_pch_rawclk(struct drm_device *dev);
 657 void intel_mark_busy(struct drm_device *dev);
 658 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 659                         struct intel_ring_buffer *ring);
 660 void intel_mark_idle(struct drm_device *dev);
 661 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 662 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 663 void intel_encoder_destroy(struct drm_encoder *encoder);
 664 void intel_connector_dpms(struct drm_connector *, int mode);
 665 bool intel_connector_get_hw_state(struct intel_connector *connector);
 666 void intel_modeset_check_state(struct drm_device *dev);
 667 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 668                                 struct intel_digital_port *port);
 669 void intel_connector_attach_encoder(struct intel_connector *connector,
 670                                     struct intel_encoder *encoder);
 671 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 672 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 673                                              struct drm_crtc *crtc);
 674 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 675 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 676                                 struct drm_file *file_priv);
 677 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 678                                              enum pipe pipe);
 679 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 680 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 681 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 682 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 683                          struct intel_digital_port *dport);
 684 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 685                                 struct drm_display_mode *mode,
 686                                 struct intel_load_detect_pipe *old);
 687 void intel_release_load_detect_pipe(struct drm_connector *connector,
 688                                     struct intel_load_detect_pipe *old);
 689 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 690                                struct drm_i915_gem_object *obj,
 691                                struct intel_ring_buffer *pipelined);
 692 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 693 struct drm_framebuffer *
 694 __intel_framebuffer_create(struct drm_device *dev,
 695                            struct drm_mode_fb_cmd2 *mode_cmd,
 696                            struct drm_i915_gem_object *obj);
 697 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 698 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 699 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 700 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 701 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 702                         struct intel_shared_dpll *pll,
 703                         bool state);
 704 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 705 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 706 void assert_pll(struct drm_i915_private *dev_priv,
 707                 enum pipe pipe, bool state);
 708 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 709 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 710 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 711                        enum pipe pipe, bool state);
 712 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 713 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 714 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 715 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 716 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 717 void intel_write_eld(struct drm_encoder *encoder,
 718                      struct drm_display_mode *mode);
 719 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 720                                              unsigned int tiling_mode,
 721                                              unsigned int bpp,
 722                                              unsigned int pitch);
 723 void intel_display_handle_reset(struct drm_device *dev);
 724 void hsw_enable_pc8_work(struct work_struct *__work);
 725 void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
 726 void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
 727 void intel_dp_get_m_n(struct intel_crtc *crtc,
 728                       struct intel_crtc_config *pipe_config);
 729 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 730 void
 731 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 732                                 int dotclock);
 733 bool intel_crtc_active(struct drm_crtc *crtc);
 734 void hsw_enable_ips(struct intel_crtc *crtc);
 735 void hsw_disable_ips(struct intel_crtc *crtc);
 736 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
 737 enum intel_display_power_domain
 738 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 739 int valleyview_get_vco(struct drm_i915_private *dev_priv);
 740 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 741                                  struct intel_crtc_config *pipe_config);
 742
 743 /* intel_dp.c */
 744 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 745 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 746                              struct intel_connector *intel_connector);
 747 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 748 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 749 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 750 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 751 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 752 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 753 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 754 bool intel_dp_compute_config(struct intel_encoder *encoder,
 755                              struct intel_crtc_config *pipe_config);
 756 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 757 void intel_edp_backlight_on(struct intel_dp *intel_dp);
 758 void intel_edp_backlight_off(struct intel_dp *intel_dp);
 759 void intel_edp_panel_on(struct intel_dp *intel_dp);
 760 void intel_edp_panel_off(struct intel_dp *intel_dp);
 761 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 762 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 763 void intel_edp_psr_update(struct drm_device *dev);
 764
 765
 766 /* intel_dsi.c */
 767 bool intel_dsi_init(struct drm_device *dev);
 768
 769
 770 /* intel_dvo.c */
 771 void intel_dvo_init(struct drm_device *dev);
 772
 773
 774 /* legacy fbdev emulation in intel_fbdev.c */
 775 #ifdef CONFIG_DRM_I915_FBDEV
 776 extern int intel_fbdev_init(struct drm_device *dev);
 777 extern void intel_fbdev_initial_config(struct drm_device *dev);
 778 extern void intel_fbdev_fini(struct drm_device *dev);
 779 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 780 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 781 extern void intel_fbdev_restore_mode(struct drm_device *dev);
 782 #else
 783 static inline int intel_fbdev_init(struct drm_device *dev)
 784 {
 785         return 0;
 786 }
 787
 788 static inline void intel_fbdev_initial_config(struct drm_device *dev)
 789 {
 790 }
 791
 792 static inline void intel_fbdev_fini(struct drm_device *dev)
 793 {
 794 }
 795
 796 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
 797 {
 798 }
 799
 800 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 801 {
 802 }
 803 #endif
 804
 805 /* intel_hdmi.c */
 806 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 807 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 808                                struct intel_connector *intel_connector);
 809 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 810 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 811                                struct intel_crtc_config *pipe_config);
 812
 813
 814 /* intel_lvds.c */
 815 void intel_lvds_init(struct drm_device *dev);
 816 bool intel_is_dual_link_lvds(struct drm_device *dev);
 817
 818
 819 /* intel_modes.c */
 820 int intel_connector_update_modes(struct drm_connector *connector,
 821                                  struct edid *edid);
 822 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 823 void intel_attach_force_audio_property(struct drm_connector *connector);
 824 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 825
 826
 827 /* intel_overlay.c */
 828 void intel_setup_overlay(struct drm_device *dev);
 829 void intel_cleanup_overlay(struct drm_device *dev);
 830 int intel_overlay_switch_off(struct intel_overlay *overlay);
 831 int intel_overlay_put_image(struct drm_device *dev, void *data,
 832                             struct drm_file *file_priv);
 833 int intel_overlay_attrs(struct drm_device *dev, void *data,
 834                         struct drm_file *file_priv);
 835
 836
 837 /* intel_panel.c */
 838 int intel_panel_init(struct intel_panel *panel,
 839                      struct drm_display_mode *fixed_mode,
 840                      struct drm_display_mode *downclock_mode);
 841 void intel_panel_fini(struct intel_panel *panel);
 842 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
 843                             struct drm_display_mode *adjusted_mode);
 844 void intel_pch_panel_fitting(struct intel_crtc *crtc,
 845                              struct intel_crtc_config *pipe_config,
 846                              int fitting_mode);
 847 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 848                               struct intel_crtc_config *pipe_config,
 849                               int fitting_mode);
 850 void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
 851                                u32 max);
 852 int intel_panel_setup_backlight(struct drm_connector *connector);
 853 void intel_panel_enable_backlight(struct intel_connector *connector);
 854 void intel_panel_disable_backlight(struct intel_connector *connector);
 855 void intel_panel_destroy_backlight(struct drm_connector *connector);
 856 void intel_panel_init_backlight_funcs(struct drm_device *dev);
 857 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 858 extern struct drm_display_mode *intel_find_panel_downclock(
 859                                 struct drm_device *dev,
 860                                 struct drm_display_mode *fixed_mode,
 861                                 struct drm_connector *connector);
 862
 863 /* intel_pm.c */
 864 void intel_init_clock_gating(struct drm_device *dev);
 865 void intel_suspend_hw(struct drm_device *dev);
 866 void intel_update_watermarks(struct drm_crtc *crtc);
 867 void intel_update_sprite_watermarks(struct drm_plane *plane,
 868                                     struct drm_crtc *crtc,
 869                                     uint32_t sprite_width, int pixel_size,
 870                                     bool enabled, bool scaled);
 871 void intel_init_pm(struct drm_device *dev);
 872 void intel_pm_setup(struct drm_device *dev);
 873 bool intel_fbc_enabled(struct drm_device *dev);
 874 void intel_update_fbc(struct drm_device *dev);
 875 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 876 void intel_gpu_ips_teardown(void);
 877 int intel_power_domains_init(struct drm_i915_private *);
 878 void intel_power_domains_remove(struct drm_i915_private *);
 879 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
 880                                  enum intel_display_power_domain domain);
 881 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
 882                                     enum intel_display_power_domain domain);
 883 void intel_display_power_get(struct drm_i915_private *dev_priv,
 884                              enum intel_display_power_domain domain);
 885 void intel_display_power_put(struct drm_i915_private *dev_priv,
 886                              enum intel_display_power_domain domain);
 887 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
 888 void intel_enable_gt_powersave(struct drm_device *dev);
 889 void intel_disable_gt_powersave(struct drm_device *dev);
 890 void ironlake_teardown_rc6(struct drm_device *dev);
 891 void gen6_update_ring_freq(struct drm_device *dev);
 892 void gen6_rps_idle(struct drm_i915_private *dev_priv);
 893 void gen6_rps_boost(struct drm_i915_private *dev_priv);
 894 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
 895 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 896 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
 897 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
 898 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
 899 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
 900 void ilk_wm_get_hw_state(struct drm_device *dev);
 901
 902
 903 /* intel_sdvo.c */
 904 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
 905
 906
 907 /* intel_sprite.c */
 908 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 909 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 910                                enum plane plane);
 911 void intel_plane_restore(struct drm_plane *plane);
 912 void intel_plane_disable(struct drm_plane *plane);
 913 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 914                               struct drm_file *file_priv);
 915 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 916                               struct drm_file *file_priv);
 917
 918
 919 /* intel_tv.c */
 920 void intel_tv_init(struct drm_device *dev);
 921
 922 #endif /* __INTEL_DRV_H__ */