drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include <drm/drm_crtc.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include <drm/drm_dp_helper.h>
  35
  36 /**
  37  * _wait_for - magic (register) wait macro
  38  *
  39  * Does the right thing for modeset paths when run under kdgb or similar atomic
  40  * contexts. Note that it's important that we check the condition again after
  41  * having timed out, since the timeout could be due to preemption or similar and
  42  * we've never had a chance to check the condition before the timeout.
  43  */
  44 #define _wait_for(COND, MS, W) ({ \
  45         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  46         int ret__ = 0;                                                  \
  47         while (!(COND)) {                                               \
  48                 if (time_after(jiffies, timeout__)) {                   \
  49                         if (!(COND))                                    \
  50                                 ret__ = -ETIMEDOUT;                     \
  51                         break;                                          \
  52                 }                                                       \
  53                 if (W && drm_can_sleep())  {                            \
  54                         msleep(W);                                      \
  55                 } else {                                                \
  56                         cpu_relax();                                    \
  57                 }                                                       \
  58         }                                                               \
  59         ret__;                                                          \
  60 })
  61
  62 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  63 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  64 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  65                                                DIV_ROUND_UP((US), 1000), 0)
  66
  67 #define KHz(x) (1000*x)
  68 #define MHz(x) KHz(1000*x)
  69
  70 /*
  71  * Display related stuff
  72  */
  73
  74 /* store information about an Ixxx DVO */
  75 /* The i830->i865 use multiple DVOs with multiple i2cs */
  76 /* the i915, i945 have a single sDVO i2c bus - which is different */
  77 #define MAX_OUTPUTS 6
  78 /* maximum connectors per crtcs in the mode set */
  79 #define INTELFB_CONN_LIMIT 4
  80
  81 #define INTEL_I2C_BUS_DVO 1
  82 #define INTEL_I2C_BUS_SDVO 2
  83
  84 /* these are outputs from the chip - integrated only
  85    external chips are via DVO or SDVO output */
  86 #define INTEL_OUTPUT_UNUSED 0
  87 #define INTEL_OUTPUT_ANALOG 1
  88 #define INTEL_OUTPUT_DVO 2
  89 #define INTEL_OUTPUT_SDVO 3
  90 #define INTEL_OUTPUT_LVDS 4
  91 #define INTEL_OUTPUT_TVOUT 5
  92 #define INTEL_OUTPUT_HDMI 6
  93 #define INTEL_OUTPUT_DISPLAYPORT 7
  94 #define INTEL_OUTPUT_EDP 8
  95 #define INTEL_OUTPUT_UNKNOWN 9
  96
  97 #define INTEL_DVO_CHIP_NONE 0
  98 #define INTEL_DVO_CHIP_LVDS 1
  99 #define INTEL_DVO_CHIP_TMDS 2
 100 #define INTEL_DVO_CHIP_TVOUT 4
 101
 102 struct intel_framebuffer {
 103         struct drm_framebuffer base;
 104         struct drm_i915_gem_object *obj;
 105 };
 106
 107 struct intel_fbdev {
 108         struct drm_fb_helper helper;
 109         struct intel_framebuffer ifb;
 110         struct list_head fbdev_list;
 111         struct drm_display_mode *our_mode;
 112 };
 113
 114 struct intel_encoder {
 115         struct drm_encoder base;
 116         /*
 117          * The new crtc this encoder will be driven from. Only differs from
 118          * base->crtc while a modeset is in progress.
 119          */
 120         struct intel_crtc *new_crtc;
 121
 122         int type;
 123         /*
 124          * Intel hw has only one MUX where encoders could be clone, hence a
 125          * simple flag is enough to compute the possible_clones mask.
 126          */
 127         bool cloneable;
 128         bool connectors_active;
 129         void (*hot_plug)(struct intel_encoder *);
 130         bool (*compute_config)(struct intel_encoder *,
 131                                struct intel_crtc_config *);
 132         void (*pre_pll_enable)(struct intel_encoder *);
 133         void (*pre_enable)(struct intel_encoder *);
 134         void (*enable)(struct intel_encoder *);
 135         void (*mode_set)(struct intel_encoder *intel_encoder);
 136         void (*disable)(struct intel_encoder *);
 137         void (*post_disable)(struct intel_encoder *);
 138         /* Read out the current hw state of this connector, returning true if
 139          * the encoder is active. If the encoder is enabled it also set the pipe
 140          * it is connected to in the pipe parameter. */
 141         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 142         /* Reconstructs the equivalent mode flags for the current hardware
 143          * state. This must be called _after_ display->get_pipe_config has
 144          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 145          * be set correctly before calling this function. */
 146         void (*get_config)(struct intel_encoder *,
 147                            struct intel_crtc_config *pipe_config);
 148         int crtc_mask;
 149         enum hpd_pin hpd_pin;
 150 };
 151
 152 struct intel_panel {
 153         struct drm_display_mode *fixed_mode;
 154         int fitting_mode;
 155 };
 156
 157 struct intel_connector {
 158         struct drm_connector base;
 159         /*
 160          * The fixed encoder this connector is connected to.
 161          */
 162         struct intel_encoder *encoder;
 163
 164         /*
 165          * The new encoder this connector will be driven. Only differs from
 166          * encoder while a modeset is in progress.
 167          */
 168         struct intel_encoder *new_encoder;
 169
 170         /* Reads out the current hw, returning true if the connector is enabled
 171          * and active (i.e. dpms ON state). */
 172         bool (*get_hw_state)(struct intel_connector *);
 173
 174         /* Panel info for eDP and LVDS */
 175         struct intel_panel panel;
 176
 177         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 178         struct edid *edid;
 179
 180         /* since POLL and HPD connectors may use the same HPD line keep the native
 181            state of connector->polled in case hotplug storm detection changes it */
 182         u8 polled;
 183 };
 184
 185 typedef struct dpll {
 186         /* given values */
 187         int n;
 188         int m1, m2;
 189         int p1, p2;
 190         /* derived values */
 191         int     dot;
 192         int     vco;
 193         int     m;
 194         int     p;
 195 } intel_clock_t;
 196
 197 struct intel_crtc_config {
 198         /**
 199          * quirks - bitfield with hw state readout quirks
 200          *
 201          * For various reasons the hw state readout code might not be able to
 202          * completely faithfully read out the current state. These cases are
 203          * tracked with quirk flags so that fastboot and state checker can act
 204          * accordingly.
 205          */
 206 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
 207         unsigned long quirks;
 208
 209         struct drm_display_mode requested_mode;
 210         struct drm_display_mode adjusted_mode;
 211         /* This flag must be set by the encoder's compute_config callback if it
 212          * changes the crtc timings in the mode to prevent the crtc fixup from
 213          * overwriting them.  Currently only lvds needs that. */
 214         bool timings_set;
 215         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 216          * between pch encoders and cpu encoders. */
 217         bool has_pch_encoder;
 218
 219         /* CPU Transcoder for the pipe. Currently this can only differ from the
 220          * pipe on Haswell (where we have a special eDP transcoder). */
 221         enum transcoder cpu_transcoder;
 222
 223         /*
 224          * Use reduced/limited/broadcast rbg range, compressing from the full
 225          * range fed into the crtcs.
 226          */
 227         bool limited_color_range;
 228
 229         /* DP has a bunch of special case unfortunately, so mark the pipe
 230          * accordingly. */
 231         bool has_dp_encoder;
 232
 233         /*
 234          * Enable dithering, used when the selected pipe bpp doesn't match the
 235          * plane bpp.
 236          */
 237         bool dither;
 238
 239         /* Controls for the clock computation, to override various stages. */
 240         bool clock_set;
 241
 242         /* SDVO TV has a bunch of special case. To make multifunction encoders
 243          * work correctly, we need to track this at runtime.*/
 244         bool sdvo_tv_clock;
 245
 246         /*
 247          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 248          * required. This is set in the 2nd loop of calling encoder's
 249          * ->compute_config if the first pick doesn't work out.
 250          */
 251         bool bw_constrained;
 252
 253         /* Settings for the intel dpll used on pretty much everything but
 254          * haswell. */
 255         struct dpll dpll;
 256
 257         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 258         enum intel_dpll_id shared_dpll;
 259
 260         /* Actual register state of the dpll, for shared dpll cross-checking. */
 261         struct intel_dpll_hw_state dpll_hw_state;
 262
 263         int pipe_bpp;
 264         struct intel_link_m_n dp_m_n;
 265
 266         /*
 267          * Frequence the dpll for the port should run at. Differs from the
 268          * adjusted dotclock e.g. for DP or 12bpc hdmi mode.
 269          */
 270         int port_clock;
 271
 272         /* Used by SDVO (and if we ever fix it, HDMI). */
 273         unsigned pixel_multiplier;
 274
 275         /* Panel fitter controls for gen2-gen4 + VLV */
 276         struct {
 277                 u32 control;
 278                 u32 pgm_ratios;
 279                 u32 lvds_border_bits;
 280         } gmch_pfit;
 281
 282         /* Panel fitter placement and size for Ironlake+ */
 283         struct {
 284                 u32 pos;
 285                 u32 size;
 286         } pch_pfit;
 287
 288         /* FDI configuration, only valid if has_pch_encoder is set. */
 289         int fdi_lanes;
 290         struct intel_link_m_n fdi_m_n;
 291
 292         bool ips_enabled;
 293 };
 294
 295 struct intel_crtc {
 296         struct drm_crtc base;
 297         enum pipe pipe;
 298         enum plane plane;
 299         u8 lut_r[256], lut_g[256], lut_b[256];
 300         /*
 301          * Whether the crtc and the connected output pipeline is active. Implies
 302          * that crtc->enabled is set, i.e. the current mode configuration has
 303          * some outputs connected to this crtc.
 304          */
 305         bool active;
 306         bool eld_vld;
 307         bool primary_disabled; /* is the crtc obscured by a plane? */
 308         bool lowfreq_avail;
 309         struct intel_overlay *overlay;
 310         struct intel_unpin_work *unpin_work;
 311
 312         atomic_t unpin_work_count;
 313
 314         /* Display surface base address adjustement for pageflips. Note that on
 315          * gen4+ this only adjusts up to a tile, offsets within a tile are
 316          * handled in the hw itself (with the TILEOFF register). */
 317         unsigned long dspaddr_offset;
 318
 319         struct drm_i915_gem_object *cursor_bo;
 320         uint32_t cursor_addr;
 321         int16_t cursor_x, cursor_y;
 322         int16_t cursor_width, cursor_height;
 323         bool cursor_visible;
 324
 325         struct intel_crtc_config config;
 326
 327         uint32_t ddi_pll_sel;
 328
 329         /* reset counter value when the last flip was submitted */
 330         unsigned int reset_counter;
 331
 332         /* Access to these should be protected by dev_priv->irq_lock. */
 333         bool cpu_fifo_underrun_disabled;
 334         bool pch_fifo_underrun_disabled;
 335 };
 336
 337 struct intel_plane {
 338         struct drm_plane base;
 339         int plane;
 340         enum pipe pipe;
 341         struct drm_i915_gem_object *obj;
 342         bool can_scale;
 343         int max_downscale;
 344         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 345         int crtc_x, crtc_y;
 346         unsigned int crtc_w, crtc_h;
 347         uint32_t src_x, src_y;
 348         uint32_t src_w, src_h;
 349
 350         /* Since we need to change the watermarks before/after
 351          * enabling/disabling the planes, we need to store the parameters here
 352          * as the other pieces of the struct may not reflect the values we want
 353          * for the watermark calculations. Currently only Haswell uses this.
 354          */
 355         struct {
 356                 bool enable;
 357                 uint8_t bytes_per_pixel;
 358                 uint32_t horiz_pixels;
 359         } wm;
 360
 361         void (*update_plane)(struct drm_plane *plane,
 362                              struct drm_framebuffer *fb,
 363                              struct drm_i915_gem_object *obj,
 364                              int crtc_x, int crtc_y,
 365                              unsigned int crtc_w, unsigned int crtc_h,
 366                              uint32_t x, uint32_t y,
 367                              uint32_t src_w, uint32_t src_h);
 368         void (*disable_plane)(struct drm_plane *plane);
 369         int (*update_colorkey)(struct drm_plane *plane,
 370                                struct drm_intel_sprite_colorkey *key);
 371         void (*get_colorkey)(struct drm_plane *plane,
 372                              struct drm_intel_sprite_colorkey *key);
 373 };
 374
 375 struct intel_watermark_params {
 376         unsigned long fifo_size;
 377         unsigned long max_wm;
 378         unsigned long default_wm;
 379         unsigned long guard_size;
 380         unsigned long cacheline_size;
 381 };
 382
 383 struct cxsr_latency {
 384         int is_desktop;
 385         int is_ddr3;
 386         unsigned long fsb_freq;
 387         unsigned long mem_freq;
 388         unsigned long display_sr;
 389         unsigned long display_hpll_disable;
 390         unsigned long cursor_sr;
 391         unsigned long cursor_hpll_disable;
 392 };
 393
 394 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 395 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 396 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 397 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 398 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 399
 400 #define DIP_HEADER_SIZE 5
 401
 402 #define DIP_TYPE_AVI    0x82
 403 #define DIP_VERSION_AVI 0x2
 404 #define DIP_LEN_AVI     13
 405 #define DIP_AVI_PR_1    0
 406 #define DIP_AVI_PR_2    1
 407 #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
 408 #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
 409 #define DIP_AVI_RGB_QUANT_RANGE_FULL    (2 << 2)
 410
 411 #define DIP_TYPE_SPD    0x83
 412 #define DIP_VERSION_SPD 0x1
 413 #define DIP_LEN_SPD     25
 414 #define DIP_SPD_UNKNOWN 0
 415 #define DIP_SPD_DSTB    0x1
 416 #define DIP_SPD_DVDP    0x2
 417 #define DIP_SPD_DVHS    0x3
 418 #define DIP_SPD_HDDVR   0x4
 419 #define DIP_SPD_DVC     0x5
 420 #define DIP_SPD_DSC     0x6
 421 #define DIP_SPD_VCD     0x7
 422 #define DIP_SPD_GAME    0x8
 423 #define DIP_SPD_PC      0x9
 424 #define DIP_SPD_BD      0xa
 425 #define DIP_SPD_SCD     0xb
 426
 427 struct dip_infoframe {
 428         uint8_t type;           /* HB0 */
 429         uint8_t ver;            /* HB1 */
 430         uint8_t len;            /* HB2 - body len, not including checksum */
 431         uint8_t ecc;            /* Header ECC */
 432         uint8_t checksum;       /* PB0 */
 433         union {
 434                 struct {
 435                         /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
 436                         uint8_t Y_A_B_S;
 437                         /* PB2 - C 7:6, M 5:4, R 3:0 */
 438                         uint8_t C_M_R;
 439                         /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
 440                         uint8_t ITC_EC_Q_SC;
 441                         /* PB4 - VIC 6:0 */
 442                         uint8_t VIC;
 443                         /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
 444                         uint8_t YQ_CN_PR;
 445                         /* PB6 to PB13 */
 446                         uint16_t top_bar_end;
 447                         uint16_t bottom_bar_start;
 448                         uint16_t left_bar_end;
 449                         uint16_t right_bar_start;
 450                 } __attribute__ ((packed)) avi;
 451                 struct {
 452                         uint8_t vn[8];
 453                         uint8_t pd[16];
 454                         uint8_t sdi;
 455                 } __attribute__ ((packed)) spd;
 456                 uint8_t payload[27];
 457         } __attribute__ ((packed)) body;
 458 } __attribute__((packed));
 459
 460 struct intel_hdmi {
 461         u32 hdmi_reg;
 462         int ddc_bus;
 463         uint32_t color_range;
 464         bool color_range_auto;
 465         bool has_hdmi_sink;
 466         bool has_audio;
 467         enum hdmi_force_audio force_audio;
 468         bool rgb_quant_range_selectable;
 469         void (*write_infoframe)(struct drm_encoder *encoder,
 470                                 struct dip_infoframe *frame);
 471         void (*set_infoframes)(struct drm_encoder *encoder,
 472                                struct drm_display_mode *adjusted_mode);
 473 };
 474
 475 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 476 #define DP_LINK_CONFIGURATION_SIZE      9
 477
 478 struct intel_dp {
 479         uint32_t output_reg;
 480         uint32_t aux_ch_ctl_reg;
 481         uint32_t DP;
 482         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
 483         bool has_audio;
 484         enum hdmi_force_audio force_audio;
 485         uint32_t color_range;
 486         bool color_range_auto;
 487         uint8_t link_bw;
 488         uint8_t lane_count;
 489         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 490         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 491         struct i2c_adapter adapter;
 492         struct i2c_algo_dp_aux_data algo;
 493         uint8_t train_set[4];
 494         int panel_power_up_delay;
 495         int panel_power_down_delay;
 496         int panel_power_cycle_delay;
 497         int backlight_on_delay;
 498         int backlight_off_delay;
 499         struct delayed_work panel_vdd_work;
 500         bool want_panel_vdd;
 501         struct intel_connector *attached_connector;
 502 };
 503
 504 struct intel_digital_port {
 505         struct intel_encoder base;
 506         enum port port;
 507         u32 port_reversal;
 508         struct intel_dp dp;
 509         struct intel_hdmi hdmi;
 510 };
 511
 512 static inline int
 513 vlv_dport_to_channel(struct intel_digital_port *dport)
 514 {
 515         switch (dport->port) {
 516         case PORT_B:
 517                 return 0;
 518         case PORT_C:
 519                 return 1;
 520         default:
 521                 BUG();
 522         }
 523 }
 524
 525 static inline struct drm_crtc *
 526 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 527 {
 528         struct drm_i915_private *dev_priv = dev->dev_private;
 529         return dev_priv->pipe_to_crtc_mapping[pipe];
 530 }
 531
 532 static inline struct drm_crtc *
 533 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 534 {
 535         struct drm_i915_private *dev_priv = dev->dev_private;
 536         return dev_priv->plane_to_crtc_mapping[plane];
 537 }
 538
 539 struct intel_unpin_work {
 540         struct work_struct work;
 541         struct drm_crtc *crtc;
 542         struct drm_i915_gem_object *old_fb_obj;
 543         struct drm_i915_gem_object *pending_flip_obj;
 544         struct drm_pending_vblank_event *event;
 545         atomic_t pending;
 546 #define INTEL_FLIP_INACTIVE     0
 547 #define INTEL_FLIP_PENDING      1
 548 #define INTEL_FLIP_COMPLETE     2
 549         bool enable_stall_check;
 550 };
 551
 552 int intel_pch_rawclk(struct drm_device *dev);
 553
 554 int intel_connector_update_modes(struct drm_connector *connector,
 555                                 struct edid *edid);
 556 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 557
 558 extern void intel_attach_force_audio_property(struct drm_connector *connector);
 559 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 560
 561 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
 562 extern void intel_crt_init(struct drm_device *dev);
 563 extern void intel_hdmi_init(struct drm_device *dev,
 564                             int hdmi_reg, enum port port);
 565 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 566                                       struct intel_connector *intel_connector);
 567 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 568 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 569                                       struct intel_crtc_config *pipe_config);
 570 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
 571 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
 572                             bool is_sdvob);
 573 extern void intel_dvo_init(struct drm_device *dev);
 574 extern void intel_tv_init(struct drm_device *dev);
 575 extern void intel_mark_busy(struct drm_device *dev);
 576 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 577                                struct intel_ring_buffer *ring);
 578 extern void intel_mark_idle(struct drm_device *dev);
 579 extern void intel_lvds_init(struct drm_device *dev);
 580 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
 581 extern void intel_dp_init(struct drm_device *dev, int output_reg,
 582                           enum port port);
 583 extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 584                                     struct intel_connector *intel_connector);
 585 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
 586 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
 587 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 588 extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 589 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 590 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 591 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
 592 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
 593                                     struct intel_crtc_config *pipe_config);
 594 extern bool intel_dpd_is_edp(struct drm_device *dev);
 595 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
 596 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
 597 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
 598 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
 599 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 600 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 601 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 602 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
 603                                       enum plane plane);
 604
 605 /* intel_panel.c */
 606 extern int intel_panel_init(struct intel_panel *panel,
 607                             struct drm_display_mode *fixed_mode);
 608 extern void intel_panel_fini(struct intel_panel *panel);
 609
 610 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
 611                                    struct drm_display_mode *adjusted_mode);
 612 extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
 613                                     struct intel_crtc_config *pipe_config,
 614                                     int fitting_mode);
 615 extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 616                                      struct intel_crtc_config *pipe_config,
 617                                      int fitting_mode);
 618 extern void intel_panel_set_backlight(struct drm_device *dev,
 619                                       u32 level, u32 max);
 620 extern int intel_panel_setup_backlight(struct drm_connector *connector);
 621 extern void intel_panel_enable_backlight(struct drm_device *dev,
 622                                          enum pipe pipe);
 623 extern void intel_panel_disable_backlight(struct drm_device *dev);
 624 extern void intel_panel_destroy_backlight(struct drm_device *dev);
 625 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 626
 627 struct intel_set_config {
 628         struct drm_encoder **save_connector_encoders;
 629         struct drm_crtc **save_encoder_crtcs;
 630
 631         bool fb_changed;
 632         bool mode_changed;
 633 };
 634
 635 extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
 636                           int x, int y, struct drm_framebuffer *old_fb);
 637 extern void intel_modeset_disable(struct drm_device *dev);
 638 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
 639 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
 640 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
 641 extern void intel_encoder_destroy(struct drm_encoder *encoder);
 642 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
 643 extern void intel_connector_dpms(struct drm_connector *, int mode);
 644 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
 645 extern void intel_modeset_check_state(struct drm_device *dev);
 646 extern void intel_plane_restore(struct drm_plane *plane);
 647 extern void intel_plane_disable(struct drm_plane *plane);
 648
 649
 650 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
 651 {
 652         return to_intel_connector(connector)->encoder;
 653 }
 654
 655 static inline struct intel_digital_port *
 656 enc_to_dig_port(struct drm_encoder *encoder)
 657 {
 658         return container_of(encoder, struct intel_digital_port, base.base);
 659 }
 660
 661 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 662 {
 663         return &enc_to_dig_port(encoder)->dp;
 664 }
 665
 666 static inline struct intel_digital_port *
 667 dp_to_dig_port(struct intel_dp *intel_dp)
 668 {
 669         return container_of(intel_dp, struct intel_digital_port, dp);
 670 }
 671
 672 static inline struct intel_digital_port *
 673 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 674 {
 675         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 676 }
 677
 678 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 679                                 struct intel_digital_port *port);
 680
 681 extern void intel_connector_attach_encoder(struct intel_connector *connector,
 682                                            struct intel_encoder *encoder);
 683 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 684
 685 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 686                                                     struct drm_crtc *crtc);
 687 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 688                                 struct drm_file *file_priv);
 689 extern enum transcoder
 690 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 691                              enum pipe pipe);
 692 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 693 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 694 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 695 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
 696
 697 struct intel_load_detect_pipe {
 698         struct drm_framebuffer *release_fb;
 699         bool load_detect_temp;
 700         int dpms_mode;
 701 };
 702 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
 703                                        struct drm_display_mode *mode,
 704                                        struct intel_load_detect_pipe *old);
 705 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
 706                                            struct intel_load_detect_pipe *old);
 707
 708 extern void intelfb_restore(void);
 709 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 710                                     u16 blue, int regno);
 711 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 712                                     u16 *blue, int regno);
 713 extern void intel_enable_clock_gating(struct drm_device *dev);
 714
 715 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 716                                       struct drm_i915_gem_object *obj,
 717                                       struct intel_ring_buffer *pipelined);
 718 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 719
 720 extern int intel_framebuffer_init(struct drm_device *dev,
 721                                   struct intel_framebuffer *ifb,
 722                                   struct drm_mode_fb_cmd2 *mode_cmd,
 723                                   struct drm_i915_gem_object *obj);
 724 extern int intel_fbdev_init(struct drm_device *dev);
 725 extern void intel_fbdev_initial_config(struct drm_device *dev);
 726 extern void intel_fbdev_fini(struct drm_device *dev);
 727 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 728 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
 729 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
 730 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 731
 732 extern void intel_setup_overlay(struct drm_device *dev);
 733 extern void intel_cleanup_overlay(struct drm_device *dev);
 734 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
 735 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
 736                                    struct drm_file *file_priv);
 737 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
 738                                struct drm_file *file_priv);
 739
 740 extern void intel_fb_output_poll_changed(struct drm_device *dev);
 741 extern void intel_fb_restore_mode(struct drm_device *dev);
 742
 743 struct intel_shared_dpll *
 744 intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 745
 746 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 747                         struct intel_shared_dpll *pll,
 748                         bool state);
 749 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 750 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 751 void assert_pll(struct drm_i915_private *dev_priv,
 752                 enum pipe pipe, bool state);
 753 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 754 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 755 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 756                        enum pipe pipe, bool state);
 757 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 758 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 759 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 760                         bool state);
 761 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 762 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 763
 764 extern void intel_init_clock_gating(struct drm_device *dev);
 765 extern void intel_suspend_hw(struct drm_device *dev);
 766 extern void intel_write_eld(struct drm_encoder *encoder,
 767                             struct drm_display_mode *mode);
 768 extern void intel_prepare_ddi(struct drm_device *dev);
 769 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
 770 extern void intel_ddi_init(struct drm_device *dev, enum port port);
 771
 772 /* For use by IVB LP watermark workaround in intel_sprite.c */
 773 extern void intel_update_watermarks(struct drm_device *dev);
 774 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
 775                                            uint32_t sprite_width,
 776                                            int pixel_size, bool enable);
 777
 778 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 779                                                     unsigned int tiling_mode,
 780                                                     unsigned int bpp,
 781                                                     unsigned int pitch);
 782
 783 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 784                                      struct drm_file *file_priv);
 785 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 786                                      struct drm_file *file_priv);
 787
 788 /* Power-related functions, located in intel_pm.c */
 789 extern void intel_init_pm(struct drm_device *dev);
 790 /* FBC */
 791 extern bool intel_fbc_enabled(struct drm_device *dev);
 792 extern void intel_update_fbc(struct drm_device *dev);
 793 /* IPS */
 794 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 795 extern void intel_gpu_ips_teardown(void);
 796
 797 /* Power well */
 798 extern int i915_init_power_well(struct drm_device *dev);
 799 extern void i915_remove_power_well(struct drm_device *dev);
 800
 801 extern bool intel_display_power_enabled(struct drm_device *dev,
 802                                         enum intel_display_power_domain domain);
 803 extern void intel_init_power_well(struct drm_device *dev);
 804 extern void intel_set_power_well(struct drm_device *dev, bool enable);
 805 extern void intel_enable_gt_powersave(struct drm_device *dev);
 806 extern void intel_disable_gt_powersave(struct drm_device *dev);
 807 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
 808 extern void ironlake_teardown_rc6(struct drm_device *dev);
 809
 810 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 811                                    enum pipe *pipe);
 812 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 813 extern void intel_ddi_pll_init(struct drm_device *dev);
 814 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 815 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 816                                               enum transcoder cpu_transcoder);
 817 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 818 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 819 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 820 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
 821 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 822 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 823 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 824 extern bool
 825 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 826 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 827
 828 extern void intel_display_handle_reset(struct drm_device *dev);
 829 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 830                                                   enum pipe pipe,
 831                                                   bool enable);
 832 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 833                                                  enum transcoder pch_transcoder,
 834                                                  bool enable);
 835
 836 #endif /* __INTEL_DRV_H__ */