2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <linux/hdmi.h>
30 #include <drm/i915_drm.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_dp_helper.h>
38 * _wait_for - magic (register) wait macro
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
45 #define _wait_for(COND, MS, W) ({ \
46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
49 if (time_after(jiffies, timeout__)) { \
54 if (W && drm_can_sleep()) { \
63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
68 #define KHz(x) (1000 * (x))
69 #define MHz(x) KHz(1000 * (x))
72 * Display related stuff
75 /* store information about an Ixxx DVO */
76 /* The i830->i865 use multiple DVOs with multiple i2cs */
77 /* the i915, i945 have a single sDVO i2c bus - which is different */
79 /* maximum connectors per crtcs in the mode set */
81 #define INTEL_I2C_BUS_DVO 1
82 #define INTEL_I2C_BUS_SDVO 2
84 /* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86 #define INTEL_OUTPUT_UNUSED 0
87 #define INTEL_OUTPUT_ANALOG 1
88 #define INTEL_OUTPUT_DVO 2
89 #define INTEL_OUTPUT_SDVO 3
90 #define INTEL_OUTPUT_LVDS 4
91 #define INTEL_OUTPUT_TVOUT 5
92 #define INTEL_OUTPUT_HDMI 6
93 #define INTEL_OUTPUT_DISPLAYPORT 7
94 #define INTEL_OUTPUT_EDP 8
95 #define INTEL_OUTPUT_DSI 9
96 #define INTEL_OUTPUT_UNKNOWN 10
98 #define INTEL_DVO_CHIP_NONE 0
99 #define INTEL_DVO_CHIP_LVDS 1
100 #define INTEL_DVO_CHIP_TMDS 2
101 #define INTEL_DVO_CHIP_TVOUT 4
103 #define INTEL_DSI_COMMAND_MODE 0
104 #define INTEL_DSI_VIDEO_MODE 1
106 struct intel_framebuffer
{
107 struct drm_framebuffer base
;
108 struct drm_i915_gem_object
*obj
;
112 struct drm_fb_helper helper
;
113 struct intel_framebuffer ifb
;
114 struct list_head fbdev_list
;
115 struct drm_display_mode
*our_mode
;
118 struct intel_encoder
{
119 struct drm_encoder base
;
121 * The new crtc this encoder will be driven from. Only differs from
122 * base->crtc while a modeset is in progress.
124 struct intel_crtc
*new_crtc
;
128 * Intel hw has only one MUX where encoders could be clone, hence a
129 * simple flag is enough to compute the possible_clones mask.
132 bool connectors_active
;
133 void (*hot_plug
)(struct intel_encoder
*);
134 bool (*compute_config
)(struct intel_encoder
*,
135 struct intel_crtc_config
*);
136 void (*pre_pll_enable
)(struct intel_encoder
*);
137 void (*pre_enable
)(struct intel_encoder
*);
138 void (*enable
)(struct intel_encoder
*);
139 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
140 void (*disable
)(struct intel_encoder
*);
141 void (*post_disable
)(struct intel_encoder
*);
142 /* Read out the current hw state of this connector, returning true if
143 * the encoder is active. If the encoder is enabled it also set the pipe
144 * it is connected to in the pipe parameter. */
145 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
146 /* Reconstructs the equivalent mode flags for the current hardware
147 * state. This must be called _after_ display->get_pipe_config has
148 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
149 * be set correctly before calling this function. */
150 void (*get_config
)(struct intel_encoder
*,
151 struct intel_crtc_config
*pipe_config
);
153 enum hpd_pin hpd_pin
;
157 struct drm_display_mode
*fixed_mode
;
158 struct drm_display_mode
*downclock_mode
;
167 bool combination_mode
; /* gen 2/4 only */
169 struct backlight_device
*device
;
173 struct intel_connector
{
174 struct drm_connector base
;
176 * The fixed encoder this connector is connected to.
178 struct intel_encoder
*encoder
;
181 * The new encoder this connector will be driven. Only differs from
182 * encoder while a modeset is in progress.
184 struct intel_encoder
*new_encoder
;
186 /* Reads out the current hw, returning true if the connector is enabled
187 * and active (i.e. dpms ON state). */
188 bool (*get_hw_state
)(struct intel_connector
*);
190 /* Panel info for eDP and LVDS */
191 struct intel_panel panel
;
193 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
196 /* since POLL and HPD connectors may use the same HPD line keep the native
197 state of connector->polled in case hotplug storm detection changes it */
201 typedef struct dpll
{
213 struct intel_crtc_config
{
215 * quirks - bitfield with hw state readout quirks
217 * For various reasons the hw state readout code might not be able to
218 * completely faithfully read out the current state. These cases are
219 * tracked with quirk flags so that fastboot and state checker can act
222 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
223 unsigned long quirks
;
225 /* User requested mode, only valid as a starting point to
226 * compute adjusted_mode, except in the case of (S)DVO where
227 * it's also for the output timings of the (S)DVO chip.
228 * adjusted_mode will then correspond to the S(DVO) chip's
229 * preferred input timings. */
230 struct drm_display_mode requested_mode
;
231 /* Actual pipe timings ie. what we program into the pipe timing
232 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
233 struct drm_display_mode adjusted_mode
;
235 /* Pipe source size (ie. panel fitter input size)
236 * All planes will be positioned inside this space,
237 * and get clipped at the edges. */
238 int pipe_src_w
, pipe_src_h
;
240 /* Whether to set up the PCH/FDI. Note that we never allow sharing
241 * between pch encoders and cpu encoders. */
242 bool has_pch_encoder
;
244 /* CPU Transcoder for the pipe. Currently this can only differ from the
245 * pipe on Haswell (where we have a special eDP transcoder). */
246 enum transcoder cpu_transcoder
;
249 * Use reduced/limited/broadcast rbg range, compressing from the full
250 * range fed into the crtcs.
252 bool limited_color_range
;
254 /* DP has a bunch of special case unfortunately, so mark the pipe
259 * Enable dithering, used when the selected pipe bpp doesn't match the
264 /* Controls for the clock computation, to override various stages. */
267 /* SDVO TV has a bunch of special case. To make multifunction encoders
268 * work correctly, we need to track this at runtime.*/
272 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
273 * required. This is set in the 2nd loop of calling encoder's
274 * ->compute_config if the first pick doesn't work out.
278 /* Settings for the intel dpll used on pretty much everything but
282 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
283 enum intel_dpll_id shared_dpll
;
285 /* Actual register state of the dpll, for shared dpll cross-checking. */
286 struct intel_dpll_hw_state dpll_hw_state
;
289 struct intel_link_m_n dp_m_n
;
292 * Frequence the dpll for the port should run at. Differs from the
293 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
294 * already multiplied by pixel_multiplier.
298 /* Used by SDVO (and if we ever fix it, HDMI). */
299 unsigned pixel_multiplier
;
301 /* Panel fitter controls for gen2-gen4 + VLV */
305 u32 lvds_border_bits
;
308 /* Panel fitter placement and size for Ironlake+ */
315 /* FDI configuration, only valid if has_pch_encoder is set. */
317 struct intel_link_m_n fdi_m_n
;
324 struct intel_pipe_wm
{
325 struct intel_wm_level wm
[5];
331 struct drm_crtc base
;
334 u8 lut_r
[256], lut_g
[256], lut_b
[256];
336 * Whether the crtc and the connected output pipeline is active. Implies
337 * that crtc->enabled is set, i.e. the current mode configuration has
338 * some outputs connected to this crtc.
341 unsigned long enabled_power_domains
;
343 bool primary_enabled
; /* is the primary plane (partially) visible? */
345 struct intel_overlay
*overlay
;
346 struct intel_unpin_work
*unpin_work
;
348 atomic_t unpin_work_count
;
350 /* Display surface base address adjustement for pageflips. Note that on
351 * gen4+ this only adjusts up to a tile, offsets within a tile are
352 * handled in the hw itself (with the TILEOFF register). */
353 unsigned long dspaddr_offset
;
355 struct drm_i915_gem_object
*cursor_bo
;
356 uint32_t cursor_addr
;
357 int16_t cursor_x
, cursor_y
;
358 int16_t cursor_width
, cursor_height
;
361 struct intel_crtc_config config
;
362 struct intel_crtc_config
*new_config
;
365 uint32_t ddi_pll_sel
;
367 /* reset counter value when the last flip was submitted */
368 unsigned int reset_counter
;
370 /* Access to these should be protected by dev_priv->irq_lock. */
371 bool cpu_fifo_underrun_disabled
;
372 bool pch_fifo_underrun_disabled
;
374 /* per-pipe watermark state */
376 /* watermarks currently being used */
377 struct intel_pipe_wm active
;
381 struct intel_plane_wm_parameters
{
382 uint32_t horiz_pixels
;
383 uint8_t bytes_per_pixel
;
389 struct drm_plane base
;
392 struct drm_i915_gem_object
*obj
;
395 u32 lut_r
[1024], lut_g
[1024], lut_b
[1024];
397 unsigned int crtc_w
, crtc_h
;
398 uint32_t src_x
, src_y
;
399 uint32_t src_w
, src_h
;
401 /* Since we need to change the watermarks before/after
402 * enabling/disabling the planes, we need to store the parameters here
403 * as the other pieces of the struct may not reflect the values we want
404 * for the watermark calculations. Currently only Haswell uses this.
406 struct intel_plane_wm_parameters wm
;
408 void (*update_plane
)(struct drm_plane
*plane
,
409 struct drm_crtc
*crtc
,
410 struct drm_framebuffer
*fb
,
411 struct drm_i915_gem_object
*obj
,
412 int crtc_x
, int crtc_y
,
413 unsigned int crtc_w
, unsigned int crtc_h
,
414 uint32_t x
, uint32_t y
,
415 uint32_t src_w
, uint32_t src_h
);
416 void (*disable_plane
)(struct drm_plane
*plane
,
417 struct drm_crtc
*crtc
);
418 int (*update_colorkey
)(struct drm_plane
*plane
,
419 struct drm_intel_sprite_colorkey
*key
);
420 void (*get_colorkey
)(struct drm_plane
*plane
,
421 struct drm_intel_sprite_colorkey
*key
);
424 struct intel_watermark_params
{
425 unsigned long fifo_size
;
426 unsigned long max_wm
;
427 unsigned long default_wm
;
428 unsigned long guard_size
;
429 unsigned long cacheline_size
;
432 struct cxsr_latency
{
435 unsigned long fsb_freq
;
436 unsigned long mem_freq
;
437 unsigned long display_sr
;
438 unsigned long display_hpll_disable
;
439 unsigned long cursor_sr
;
440 unsigned long cursor_hpll_disable
;
443 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
444 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
445 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
446 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
447 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
452 uint32_t color_range
;
453 bool color_range_auto
;
456 enum hdmi_force_audio force_audio
;
457 bool rgb_quant_range_selectable
;
458 void (*write_infoframe
)(struct drm_encoder
*encoder
,
459 enum hdmi_infoframe_type type
,
460 const void *frame
, ssize_t len
);
461 void (*set_infoframes
)(struct drm_encoder
*encoder
,
462 struct drm_display_mode
*adjusted_mode
);
465 #define DP_MAX_DOWNSTREAM_PORTS 0x10
469 uint32_t aux_ch_ctl_reg
;
472 enum hdmi_force_audio force_audio
;
473 uint32_t color_range
;
474 bool color_range_auto
;
477 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
478 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
479 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
480 struct i2c_adapter adapter
;
481 struct i2c_algo_dp_aux_data algo
;
482 uint8_t train_set
[4];
483 int panel_power_up_delay
;
484 int panel_power_down_delay
;
485 int panel_power_cycle_delay
;
486 int backlight_on_delay
;
487 int backlight_off_delay
;
488 struct delayed_work panel_vdd_work
;
490 unsigned long last_power_cycle
;
491 unsigned long last_power_on
;
492 unsigned long last_backlight_off
;
494 struct intel_connector
*attached_connector
;
497 struct intel_digital_port
{
498 struct intel_encoder base
;
502 struct intel_hdmi hdmi
;
506 vlv_dport_to_channel(struct intel_digital_port
*dport
)
508 switch (dport
->port
) {
518 static inline struct drm_crtc
*
519 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
522 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
525 static inline struct drm_crtc
*
526 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
529 return dev_priv
->plane_to_crtc_mapping
[plane
];
532 struct intel_unpin_work
{
533 struct work_struct work
;
534 struct drm_crtc
*crtc
;
535 struct drm_i915_gem_object
*old_fb_obj
;
536 struct drm_i915_gem_object
*pending_flip_obj
;
537 struct drm_pending_vblank_event
*event
;
539 #define INTEL_FLIP_INACTIVE 0
540 #define INTEL_FLIP_PENDING 1
541 #define INTEL_FLIP_COMPLETE 2
542 bool enable_stall_check
;
545 struct intel_set_config
{
546 struct drm_encoder
**save_connector_encoders
;
547 struct drm_crtc
**save_encoder_crtcs
;
548 bool *save_crtc_enabled
;
554 struct intel_load_detect_pipe
{
555 struct drm_framebuffer
*release_fb
;
556 bool load_detect_temp
;
560 static inline struct intel_encoder
*
561 intel_attached_encoder(struct drm_connector
*connector
)
563 return to_intel_connector(connector
)->encoder
;
566 static inline struct intel_digital_port
*
567 enc_to_dig_port(struct drm_encoder
*encoder
)
569 return container_of(encoder
, struct intel_digital_port
, base
.base
);
572 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
574 return &enc_to_dig_port(encoder
)->dp
;
577 static inline struct intel_digital_port
*
578 dp_to_dig_port(struct intel_dp
*intel_dp
)
580 return container_of(intel_dp
, struct intel_digital_port
, dp
);
583 static inline struct intel_digital_port
*
584 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
586 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
591 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
592 enum pipe pipe
, bool enable
);
593 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
594 enum transcoder pch_transcoder
,
596 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
597 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
598 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
599 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
600 void hsw_pc8_disable_interrupts(struct drm_device
*dev
);
601 void hsw_pc8_restore_interrupts(struct drm_device
*dev
);
605 void intel_crt_init(struct drm_device
*dev
);
609 void intel_prepare_ddi(struct drm_device
*dev
);
610 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
611 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
612 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
613 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
614 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
);
615 void intel_ddi_pll_init(struct drm_device
*dev
);
616 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
617 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
618 enum transcoder cpu_transcoder
);
619 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
620 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
621 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
);
622 bool intel_ddi_pll_select(struct intel_crtc
*crtc
);
623 void intel_ddi_pll_enable(struct intel_crtc
*crtc
);
624 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
);
625 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
626 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
);
627 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
628 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
629 void intel_ddi_get_config(struct intel_encoder
*encoder
,
630 struct intel_crtc_config
*pipe_config
);
633 /* intel_display.c */
634 const char *intel_output_name(int output
);
635 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
636 int intel_pch_rawclk(struct drm_device
*dev
);
637 void intel_mark_busy(struct drm_device
*dev
);
638 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
639 struct intel_ring_buffer
*ring
);
640 void intel_mark_idle(struct drm_device
*dev
);
641 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
642 void intel_crtc_update_dpms(struct drm_crtc
*crtc
);
643 void intel_encoder_destroy(struct drm_encoder
*encoder
);
644 void intel_connector_dpms(struct drm_connector
*, int mode
);
645 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
646 void intel_modeset_check_state(struct drm_device
*dev
);
647 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
648 struct intel_digital_port
*port
);
649 void intel_connector_attach_encoder(struct intel_connector
*connector
,
650 struct intel_encoder
*encoder
);
651 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
652 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
653 struct drm_crtc
*crtc
);
654 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
655 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
656 struct drm_file
*file_priv
);
657 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
659 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
);
660 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
);
661 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
662 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
663 struct intel_digital_port
*dport
);
664 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
665 struct drm_display_mode
*mode
,
666 struct intel_load_detect_pipe
*old
);
667 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
668 struct intel_load_detect_pipe
*old
);
669 int intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
670 struct drm_i915_gem_object
*obj
,
671 struct intel_ring_buffer
*pipelined
);
672 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
);
673 int intel_framebuffer_init(struct drm_device
*dev
,
674 struct intel_framebuffer
*ifb
,
675 struct drm_mode_fb_cmd2
*mode_cmd
,
676 struct drm_i915_gem_object
*obj
);
677 void intel_framebuffer_fini(struct intel_framebuffer
*fb
);
678 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
679 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
680 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
681 struct intel_shared_dpll
*intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
);
682 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
683 struct intel_shared_dpll
*pll
,
685 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
686 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
687 void assert_pll(struct drm_i915_private
*dev_priv
,
688 enum pipe pipe
, bool state
);
689 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
690 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
691 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
692 enum pipe pipe
, bool state
);
693 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
694 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
695 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
696 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
697 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
698 void intel_write_eld(struct drm_encoder
*encoder
,
699 struct drm_display_mode
*mode
);
700 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
701 unsigned int tiling_mode
,
704 void intel_display_handle_reset(struct drm_device
*dev
);
705 void hsw_enable_pc8_work(struct work_struct
*__work
);
706 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
);
707 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
);
708 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
709 struct intel_crtc_config
*pipe_config
);
710 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
712 ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
714 bool intel_crtc_active(struct drm_crtc
*crtc
);
715 void hsw_enable_ips(struct intel_crtc
*crtc
);
716 void hsw_disable_ips(struct intel_crtc
*crtc
);
717 void intel_display_set_init_power(struct drm_device
*dev
, bool enable
);
718 int valleyview_get_vco(struct drm_i915_private
*dev_priv
);
721 void intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
);
722 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
723 struct intel_connector
*intel_connector
);
724 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
725 void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
726 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
727 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
728 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
729 void intel_dp_check_link_status(struct intel_dp
*intel_dp
);
730 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
731 struct intel_crtc_config
*pipe_config
);
732 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
733 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
734 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
735 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
736 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
737 void intel_edp_psr_enable(struct intel_dp
*intel_dp
);
738 void intel_edp_psr_disable(struct intel_dp
*intel_dp
);
739 void intel_edp_psr_update(struct drm_device
*dev
);
743 bool intel_dsi_init(struct drm_device
*dev
);
747 void intel_dvo_init(struct drm_device
*dev
);
750 /* legacy fbdev emulation in intel_fbdev.c */
751 #ifdef CONFIG_DRM_I915_FBDEV
752 extern int intel_fbdev_init(struct drm_device
*dev
);
753 extern void intel_fbdev_initial_config(struct drm_device
*dev
);
754 extern void intel_fbdev_fini(struct drm_device
*dev
);
755 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
);
756 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
757 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
759 static inline int intel_fbdev_init(struct drm_device
*dev
)
764 static inline void intel_fbdev_initial_config(struct drm_device
*dev
)
768 static inline void intel_fbdev_fini(struct drm_device
*dev
)
772 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
)
776 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
782 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
);
783 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
784 struct intel_connector
*intel_connector
);
785 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
786 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
787 struct intel_crtc_config
*pipe_config
);
791 void intel_lvds_init(struct drm_device
*dev
);
792 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
796 int intel_connector_update_modes(struct drm_connector
*connector
,
798 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
799 void intel_attach_force_audio_property(struct drm_connector
*connector
);
800 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
803 /* intel_overlay.c */
804 void intel_setup_overlay(struct drm_device
*dev
);
805 void intel_cleanup_overlay(struct drm_device
*dev
);
806 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
807 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
808 struct drm_file
*file_priv
);
809 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
810 struct drm_file
*file_priv
);
814 int intel_panel_init(struct intel_panel
*panel
,
815 struct drm_display_mode
*fixed_mode
);
816 void intel_panel_fini(struct intel_panel
*panel
);
817 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
818 struct drm_display_mode
*adjusted_mode
);
819 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
820 struct intel_crtc_config
*pipe_config
,
822 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
823 struct intel_crtc_config
*pipe_config
,
825 void intel_panel_set_backlight(struct intel_connector
*connector
, u32 level
,
827 int intel_panel_setup_backlight(struct drm_connector
*connector
);
828 void intel_panel_enable_backlight(struct intel_connector
*connector
);
829 void intel_panel_disable_backlight(struct intel_connector
*connector
);
830 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
831 void intel_panel_init_backlight_funcs(struct drm_device
*dev
);
832 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
833 extern struct drm_display_mode
*intel_find_panel_downclock(
834 struct drm_device
*dev
,
835 struct drm_display_mode
*fixed_mode
,
836 struct drm_connector
*connector
);
839 void intel_init_clock_gating(struct drm_device
*dev
);
840 void intel_suspend_hw(struct drm_device
*dev
);
841 void intel_update_watermarks(struct drm_crtc
*crtc
);
842 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
843 struct drm_crtc
*crtc
,
844 uint32_t sprite_width
, int pixel_size
,
845 bool enabled
, bool scaled
);
846 void intel_init_pm(struct drm_device
*dev
);
847 void intel_pm_setup(struct drm_device
*dev
);
848 bool intel_fbc_enabled(struct drm_device
*dev
);
849 void intel_update_fbc(struct drm_device
*dev
);
850 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
851 void intel_gpu_ips_teardown(void);
852 int intel_power_domains_init(struct drm_device
*dev
);
853 void intel_power_domains_remove(struct drm_device
*dev
);
854 bool intel_display_power_enabled(struct drm_device
*dev
,
855 enum intel_display_power_domain domain
);
856 bool intel_display_power_enabled_sw(struct drm_device
*dev
,
857 enum intel_display_power_domain domain
);
858 void intel_display_power_get(struct drm_device
*dev
,
859 enum intel_display_power_domain domain
);
860 void intel_display_power_put(struct drm_device
*dev
,
861 enum intel_display_power_domain domain
);
862 void intel_power_domains_init_hw(struct drm_device
*dev
);
863 void intel_set_power_well(struct drm_device
*dev
, bool enable
);
864 void intel_enable_gt_powersave(struct drm_device
*dev
);
865 void intel_disable_gt_powersave(struct drm_device
*dev
);
866 void ironlake_teardown_rc6(struct drm_device
*dev
);
867 void gen6_update_ring_freq(struct drm_device
*dev
);
868 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
869 void gen6_rps_boost(struct drm_i915_private
*dev_priv
);
870 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
);
871 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
);
872 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
873 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
874 void intel_init_runtime_pm(struct drm_i915_private
*dev_priv
);
875 void intel_fini_runtime_pm(struct drm_i915_private
*dev_priv
);
876 void ilk_wm_get_hw_state(struct drm_device
*dev
);
880 bool intel_sdvo_init(struct drm_device
*dev
, uint32_t sdvo_reg
, bool is_sdvob
);
884 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
885 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
887 void intel_plane_restore(struct drm_plane
*plane
);
888 void intel_plane_disable(struct drm_plane
*plane
);
889 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
890 struct drm_file
*file_priv
);
891 int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
892 struct drm_file
*file_priv
);
896 void intel_tv_init(struct drm_device
*dev
);
898 #endif /* __INTEL_DRV_H__ */