drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000 * (x))
  69 #define MHz(x) KHz(1000 * (x))
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80
  81 /* Maximum cursor sizes */
  82 #define GEN2_CURSOR_WIDTH 64
  83 #define GEN2_CURSOR_HEIGHT 64
  84 #define MAX_CURSOR_WIDTH 256
  85 #define MAX_CURSOR_HEIGHT 256
  86
  87 #define INTEL_I2C_BUS_DVO 1
  88 #define INTEL_I2C_BUS_SDVO 2
  89
  90 /* these are outputs from the chip - integrated only
  91    external chips are via DVO or SDVO output */
  92 #define INTEL_OUTPUT_UNUSED 0
  93 #define INTEL_OUTPUT_ANALOG 1
  94 #define INTEL_OUTPUT_DVO 2
  95 #define INTEL_OUTPUT_SDVO 3
  96 #define INTEL_OUTPUT_LVDS 4
  97 #define INTEL_OUTPUT_TVOUT 5
  98 #define INTEL_OUTPUT_HDMI 6
  99 #define INTEL_OUTPUT_DISPLAYPORT 7
 100 #define INTEL_OUTPUT_EDP 8
 101 #define INTEL_OUTPUT_DSI 9
 102 #define INTEL_OUTPUT_UNKNOWN 10
 103
 104 #define INTEL_DVO_CHIP_NONE 0
 105 #define INTEL_DVO_CHIP_LVDS 1
 106 #define INTEL_DVO_CHIP_TMDS 2
 107 #define INTEL_DVO_CHIP_TVOUT 4
 108
 109 #define INTEL_DSI_COMMAND_MODE  0
 110 #define INTEL_DSI_VIDEO_MODE    1
 111
 112 struct intel_framebuffer {
 113         struct drm_framebuffer base;
 114         struct drm_i915_gem_object *obj;
 115 };
 116
 117 struct intel_fbdev {
 118         struct drm_fb_helper helper;
 119         struct intel_framebuffer *fb;
 120         struct list_head fbdev_list;
 121         struct drm_display_mode *our_mode;
 122         int preferred_bpp;
 123 };
 124
 125 struct intel_encoder {
 126         struct drm_encoder base;
 127         /*
 128          * The new crtc this encoder will be driven from. Only differs from
 129          * base->crtc while a modeset is in progress.
 130          */
 131         struct intel_crtc *new_crtc;
 132
 133         int type;
 134         unsigned int cloneable;
 135         bool connectors_active;
 136         void (*hot_plug)(struct intel_encoder *);
 137         bool (*compute_config)(struct intel_encoder *,
 138                                struct intel_crtc_config *);
 139         void (*pre_pll_enable)(struct intel_encoder *);
 140         void (*pre_enable)(struct intel_encoder *);
 141         void (*enable)(struct intel_encoder *);
 142         void (*mode_set)(struct intel_encoder *intel_encoder);
 143         void (*disable)(struct intel_encoder *);
 144         void (*post_disable)(struct intel_encoder *);
 145         /* Read out the current hw state of this connector, returning true if
 146          * the encoder is active. If the encoder is enabled it also set the pipe
 147          * it is connected to in the pipe parameter. */
 148         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 149         /* Reconstructs the equivalent mode flags for the current hardware
 150          * state. This must be called _after_ display->get_pipe_config has
 151          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 152          * be set correctly before calling this function. */
 153         void (*get_config)(struct intel_encoder *,
 154                            struct intel_crtc_config *pipe_config);
 155         int crtc_mask;
 156         enum hpd_pin hpd_pin;
 157 };
 158
 159 struct intel_panel {
 160         struct drm_display_mode *fixed_mode;
 161         struct drm_display_mode *downclock_mode;
 162         int fitting_mode;
 163
 164         /* backlight */
 165         struct {
 166                 bool present;
 167                 u32 level;
 168                 u32 max;
 169                 bool enabled;
 170                 bool combination_mode;  /* gen 2/4 only */
 171                 bool active_low_pwm;
 172                 struct backlight_device *device;
 173         } backlight;
 174 };
 175
 176 struct intel_connector {
 177         struct drm_connector base;
 178         /*
 179          * The fixed encoder this connector is connected to.
 180          */
 181         struct intel_encoder *encoder;
 182
 183         /*
 184          * The new encoder this connector will be driven. Only differs from
 185          * encoder while a modeset is in progress.
 186          */
 187         struct intel_encoder *new_encoder;
 188
 189         /* Reads out the current hw, returning true if the connector is enabled
 190          * and active (i.e. dpms ON state). */
 191         bool (*get_hw_state)(struct intel_connector *);
 192
 193         /*
 194          * Removes all interfaces through which the connector is accessible
 195          * - like sysfs, debugfs entries -, so that no new operations can be
 196          * started on the connector. Also makes sure all currently pending
 197          * operations finish before returing.
 198          */
 199         void (*unregister)(struct intel_connector *);
 200
 201         /* Panel info for eDP and LVDS */
 202         struct intel_panel panel;
 203
 204         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 205         struct edid *edid;
 206
 207         /* since POLL and HPD connectors may use the same HPD line keep the native
 208            state of connector->polled in case hotplug storm detection changes it */
 209         u8 polled;
 210 };
 211
 212 typedef struct dpll {
 213         /* given values */
 214         int n;
 215         int m1, m2;
 216         int p1, p2;
 217         /* derived values */
 218         int     dot;
 219         int     vco;
 220         int     m;
 221         int     p;
 222 } intel_clock_t;
 223
 224 struct intel_plane_config {
 225         bool tiled;
 226         int size;
 227         u32 base;
 228 };
 229
 230 struct intel_crtc_config {
 231         /**
 232          * quirks - bitfield with hw state readout quirks
 233          *
 234          * For various reasons the hw state readout code might not be able to
 235          * completely faithfully read out the current state. These cases are
 236          * tracked with quirk flags so that fastboot and state checker can act
 237          * accordingly.
 238          */
 239 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
 240         unsigned long quirks;
 241
 242         /* User requested mode, only valid as a starting point to
 243          * compute adjusted_mode, except in the case of (S)DVO where
 244          * it's also for the output timings of the (S)DVO chip.
 245          * adjusted_mode will then correspond to the S(DVO) chip's
 246          * preferred input timings. */
 247         struct drm_display_mode requested_mode;
 248         /* Actual pipe timings ie. what we program into the pipe timing
 249          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 250         struct drm_display_mode adjusted_mode;
 251
 252         /* Pipe source size (ie. panel fitter input size)
 253          * All planes will be positioned inside this space,
 254          * and get clipped at the edges. */
 255         int pipe_src_w, pipe_src_h;
 256
 257         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 258          * between pch encoders and cpu encoders. */
 259         bool has_pch_encoder;
 260
 261         /* CPU Transcoder for the pipe. Currently this can only differ from the
 262          * pipe on Haswell (where we have a special eDP transcoder). */
 263         enum transcoder cpu_transcoder;
 264
 265         /*
 266          * Use reduced/limited/broadcast rbg range, compressing from the full
 267          * range fed into the crtcs.
 268          */
 269         bool limited_color_range;
 270
 271         /* DP has a bunch of special case unfortunately, so mark the pipe
 272          * accordingly. */
 273         bool has_dp_encoder;
 274
 275         /*
 276          * Enable dithering, used when the selected pipe bpp doesn't match the
 277          * plane bpp.
 278          */
 279         bool dither;
 280
 281         /* Controls for the clock computation, to override various stages. */
 282         bool clock_set;
 283
 284         /* SDVO TV has a bunch of special case. To make multifunction encoders
 285          * work correctly, we need to track this at runtime.*/
 286         bool sdvo_tv_clock;
 287
 288         /*
 289          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 290          * required. This is set in the 2nd loop of calling encoder's
 291          * ->compute_config if the first pick doesn't work out.
 292          */
 293         bool bw_constrained;
 294
 295         /* Settings for the intel dpll used on pretty much everything but
 296          * haswell. */
 297         struct dpll dpll;
 298
 299         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 300         enum intel_dpll_id shared_dpll;
 301
 302         /* Actual register state of the dpll, for shared dpll cross-checking. */
 303         struct intel_dpll_hw_state dpll_hw_state;
 304
 305         int pipe_bpp;
 306         struct intel_link_m_n dp_m_n;
 307
 308         /*
 309          * Frequence the dpll for the port should run at. Differs from the
 310          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 311          * already multiplied by pixel_multiplier.
 312          */
 313         int port_clock;
 314
 315         /* Used by SDVO (and if we ever fix it, HDMI). */
 316         unsigned pixel_multiplier;
 317
 318         /* Panel fitter controls for gen2-gen4 + VLV */
 319         struct {
 320                 u32 control;
 321                 u32 pgm_ratios;
 322                 u32 lvds_border_bits;
 323         } gmch_pfit;
 324
 325         /* Panel fitter placement and size for Ironlake+ */
 326         struct {
 327                 u32 pos;
 328                 u32 size;
 329                 bool enabled;
 330         } pch_pfit;
 331
 332         /* FDI configuration, only valid if has_pch_encoder is set. */
 333         int fdi_lanes;
 334         struct intel_link_m_n fdi_m_n;
 335
 336         bool ips_enabled;
 337
 338         bool double_wide;
 339 };
 340
 341 struct intel_pipe_wm {
 342         struct intel_wm_level wm[5];
 343         uint32_t linetime;
 344         bool fbc_wm_enabled;
 345 };
 346
 347 struct intel_crtc {
 348         struct drm_crtc base;
 349         enum pipe pipe;
 350         enum plane plane;
 351         u8 lut_r[256], lut_g[256], lut_b[256];
 352         /*
 353          * Whether the crtc and the connected output pipeline is active. Implies
 354          * that crtc->enabled is set, i.e. the current mode configuration has
 355          * some outputs connected to this crtc.
 356          */
 357         bool active;
 358         unsigned long enabled_power_domains;
 359         bool eld_vld;
 360         bool primary_enabled; /* is the primary plane (partially) visible? */
 361         bool lowfreq_avail;
 362         struct intel_overlay *overlay;
 363         struct intel_unpin_work *unpin_work;
 364
 365         atomic_t unpin_work_count;
 366
 367         /* Display surface base address adjustement for pageflips. Note that on
 368          * gen4+ this only adjusts up to a tile, offsets within a tile are
 369          * handled in the hw itself (with the TILEOFF register). */
 370         unsigned long dspaddr_offset;
 371
 372         struct drm_i915_gem_object *cursor_bo;
 373         uint32_t cursor_addr;
 374         int16_t cursor_x, cursor_y;
 375         int16_t cursor_width, cursor_height;
 376         bool cursor_visible;
 377
 378         struct intel_plane_config plane_config;
 379         struct intel_crtc_config config;
 380         struct intel_crtc_config *new_config;
 381         bool new_enabled;
 382
 383         uint32_t ddi_pll_sel;
 384
 385         /* reset counter value when the last flip was submitted */
 386         unsigned int reset_counter;
 387
 388         /* Access to these should be protected by dev_priv->irq_lock. */
 389         bool cpu_fifo_underrun_disabled;
 390         bool pch_fifo_underrun_disabled;
 391
 392         /* per-pipe watermark state */
 393         struct {
 394                 /* watermarks currently being used  */
 395                 struct intel_pipe_wm active;
 396         } wm;
 397 };
 398
 399 struct intel_plane_wm_parameters {
 400         uint32_t horiz_pixels;
 401         uint8_t bytes_per_pixel;
 402         bool enabled;
 403         bool scaled;
 404 };
 405
 406 struct intel_plane {
 407         struct drm_plane base;
 408         int plane;
 409         enum pipe pipe;
 410         struct drm_i915_gem_object *obj;
 411         bool can_scale;
 412         int max_downscale;
 413         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 414         int crtc_x, crtc_y;
 415         unsigned int crtc_w, crtc_h;
 416         uint32_t src_x, src_y;
 417         uint32_t src_w, src_h;
 418
 419         /* Since we need to change the watermarks before/after
 420          * enabling/disabling the planes, we need to store the parameters here
 421          * as the other pieces of the struct may not reflect the values we want
 422          * for the watermark calculations. Currently only Haswell uses this.
 423          */
 424         struct intel_plane_wm_parameters wm;
 425
 426         void (*update_plane)(struct drm_plane *plane,
 427                              struct drm_crtc *crtc,
 428                              struct drm_framebuffer *fb,
 429                              struct drm_i915_gem_object *obj,
 430                              int crtc_x, int crtc_y,
 431                              unsigned int crtc_w, unsigned int crtc_h,
 432                              uint32_t x, uint32_t y,
 433                              uint32_t src_w, uint32_t src_h);
 434         void (*disable_plane)(struct drm_plane *plane,
 435                               struct drm_crtc *crtc);
 436         int (*update_colorkey)(struct drm_plane *plane,
 437                                struct drm_intel_sprite_colorkey *key);
 438         void (*get_colorkey)(struct drm_plane *plane,
 439                              struct drm_intel_sprite_colorkey *key);
 440 };
 441
 442 struct intel_watermark_params {
 443         unsigned long fifo_size;
 444         unsigned long max_wm;
 445         unsigned long default_wm;
 446         unsigned long guard_size;
 447         unsigned long cacheline_size;
 448 };
 449
 450 struct cxsr_latency {
 451         int is_desktop;
 452         int is_ddr3;
 453         unsigned long fsb_freq;
 454         unsigned long mem_freq;
 455         unsigned long display_sr;
 456         unsigned long display_hpll_disable;
 457         unsigned long cursor_sr;
 458         unsigned long cursor_hpll_disable;
 459 };
 460
 461 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 462 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 463 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 464 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 465 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 466
 467 struct intel_hdmi {
 468         u32 hdmi_reg;
 469         int ddc_bus;
 470         uint32_t color_range;
 471         bool color_range_auto;
 472         bool has_hdmi_sink;
 473         bool has_audio;
 474         enum hdmi_force_audio force_audio;
 475         bool rgb_quant_range_selectable;
 476         void (*write_infoframe)(struct drm_encoder *encoder,
 477                                 enum hdmi_infoframe_type type,
 478                                 const void *frame, ssize_t len);
 479         void (*set_infoframes)(struct drm_encoder *encoder,
 480                                struct drm_display_mode *adjusted_mode);
 481 };
 482
 483 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 484
 485 struct intel_dp {
 486         uint32_t output_reg;
 487         uint32_t aux_ch_ctl_reg;
 488         uint32_t DP;
 489         bool has_audio;
 490         enum hdmi_force_audio force_audio;
 491         uint32_t color_range;
 492         bool color_range_auto;
 493         uint8_t link_bw;
 494         uint8_t lane_count;
 495         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 496         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 497         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 498         struct drm_dp_aux aux;
 499         uint8_t train_set[4];
 500         int panel_power_up_delay;
 501         int panel_power_down_delay;
 502         int panel_power_cycle_delay;
 503         int backlight_on_delay;
 504         int backlight_off_delay;
 505         struct delayed_work panel_vdd_work;
 506         bool want_panel_vdd;
 507         unsigned long last_power_cycle;
 508         unsigned long last_power_on;
 509         unsigned long last_backlight_off;
 510         bool psr_setup_done;
 511         bool use_tps3;
 512         struct intel_connector *attached_connector;
 513
 514         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 515         /*
 516          * This function returns the value we have to program the AUX_CTL
 517          * register with to kick off an AUX transaction.
 518          */
 519         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 520                                      bool has_aux_irq,
 521                                      int send_bytes,
 522                                      uint32_t aux_clock_divider);
 523 };
 524
 525 struct intel_digital_port {
 526         struct intel_encoder base;
 527         enum port port;
 528         u32 saved_port_bits;
 529         struct intel_dp dp;
 530         struct intel_hdmi hdmi;
 531 };
 532
 533 static inline int
 534 vlv_dport_to_channel(struct intel_digital_port *dport)
 535 {
 536         switch (dport->port) {
 537         case PORT_B:
 538                 return DPIO_CH0;
 539         case PORT_C:
 540                 return DPIO_CH1;
 541         default:
 542                 BUG();
 543         }
 544 }
 545
 546 static inline struct drm_crtc *
 547 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 548 {
 549         struct drm_i915_private *dev_priv = dev->dev_private;
 550         return dev_priv->pipe_to_crtc_mapping[pipe];
 551 }
 552
 553 static inline struct drm_crtc *
 554 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 555 {
 556         struct drm_i915_private *dev_priv = dev->dev_private;
 557         return dev_priv->plane_to_crtc_mapping[plane];
 558 }
 559
 560 struct intel_unpin_work {
 561         struct work_struct work;
 562         struct drm_crtc *crtc;
 563         struct drm_i915_gem_object *old_fb_obj;
 564         struct drm_i915_gem_object *pending_flip_obj;
 565         struct drm_pending_vblank_event *event;
 566         atomic_t pending;
 567 #define INTEL_FLIP_INACTIVE     0
 568 #define INTEL_FLIP_PENDING      1
 569 #define INTEL_FLIP_COMPLETE     2
 570         bool enable_stall_check;
 571 };
 572
 573 struct intel_set_config {
 574         struct drm_encoder **save_connector_encoders;
 575         struct drm_crtc **save_encoder_crtcs;
 576         bool *save_crtc_enabled;
 577
 578         bool fb_changed;
 579         bool mode_changed;
 580 };
 581
 582 struct intel_load_detect_pipe {
 583         struct drm_framebuffer *release_fb;
 584         bool load_detect_temp;
 585         int dpms_mode;
 586 };
 587
 588 static inline struct intel_encoder *
 589 intel_attached_encoder(struct drm_connector *connector)
 590 {
 591         return to_intel_connector(connector)->encoder;
 592 }
 593
 594 static inline struct intel_digital_port *
 595 enc_to_dig_port(struct drm_encoder *encoder)
 596 {
 597         return container_of(encoder, struct intel_digital_port, base.base);
 598 }
 599
 600 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 601 {
 602         return &enc_to_dig_port(encoder)->dp;
 603 }
 604
 605 static inline struct intel_digital_port *
 606 dp_to_dig_port(struct intel_dp *intel_dp)
 607 {
 608         return container_of(intel_dp, struct intel_digital_port, dp);
 609 }
 610
 611 static inline struct intel_digital_port *
 612 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 613 {
 614         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 615 }
 616
 617
 618 /* i915_irq.c */
 619 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 620                                            enum pipe pipe, bool enable);
 621 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 622                                              enum pipe pipe, bool enable);
 623 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 624                                            enum transcoder pch_transcoder,
 625                                            bool enable);
 626 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 627 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 628 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 629 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 630 void hsw_runtime_pm_disable_interrupts(struct drm_device *dev);
 631 void hsw_runtime_pm_restore_interrupts(struct drm_device *dev);
 632
 633
 634 /* intel_crt.c */
 635 void intel_crt_init(struct drm_device *dev);
 636
 637
 638 /* intel_ddi.c */
 639 void intel_prepare_ddi(struct drm_device *dev);
 640 void hsw_fdi_link_train(struct drm_crtc *crtc);
 641 void intel_ddi_init(struct drm_device *dev, enum port port);
 642 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 643 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 644 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 645 void intel_ddi_pll_init(struct drm_device *dev);
 646 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 647 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 648                                        enum transcoder cpu_transcoder);
 649 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 650 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 651 void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 652 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 653 void intel_ddi_pll_enable(struct intel_crtc *crtc);
 654 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 655 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 656 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 657 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 658 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 659 void intel_ddi_get_config(struct intel_encoder *encoder,
 660                           struct intel_crtc_config *pipe_config);
 661
 662
 663 /* intel_display.c */
 664 const char *intel_output_name(int output);
 665 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 666 int intel_pch_rawclk(struct drm_device *dev);
 667 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv);
 668 void intel_mark_busy(struct drm_device *dev);
 669 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 670                         struct intel_ring_buffer *ring);
 671 void intel_mark_idle(struct drm_device *dev);
 672 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 673 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 674 void intel_encoder_destroy(struct drm_encoder *encoder);
 675 void intel_connector_dpms(struct drm_connector *, int mode);
 676 bool intel_connector_get_hw_state(struct intel_connector *connector);
 677 void intel_modeset_check_state(struct drm_device *dev);
 678 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 679                                 struct intel_digital_port *port);
 680 void intel_connector_attach_encoder(struct intel_connector *connector,
 681                                     struct intel_encoder *encoder);
 682 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 683 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 684                                              struct drm_crtc *crtc);
 685 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 686 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 687                                 struct drm_file *file_priv);
 688 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 689                                              enum pipe pipe);
 690 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 691 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 692 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 693 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 694                          struct intel_digital_port *dport);
 695 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 696                                 struct drm_display_mode *mode,
 697                                 struct intel_load_detect_pipe *old);
 698 void intel_release_load_detect_pipe(struct drm_connector *connector,
 699                                     struct intel_load_detect_pipe *old);
 700 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 701                                struct drm_i915_gem_object *obj,
 702                                struct intel_ring_buffer *pipelined);
 703 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 704 struct drm_framebuffer *
 705 __intel_framebuffer_create(struct drm_device *dev,
 706                            struct drm_mode_fb_cmd2 *mode_cmd,
 707                            struct drm_i915_gem_object *obj);
 708 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 709 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 710 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 711 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 712 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 713                         struct intel_shared_dpll *pll,
 714                         bool state);
 715 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 716 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 717 void assert_pll(struct drm_i915_private *dev_priv,
 718                 enum pipe pipe, bool state);
 719 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 720 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 721 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 722                        enum pipe pipe, bool state);
 723 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 724 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 725 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 726 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 727 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 728 void intel_write_eld(struct drm_encoder *encoder,
 729                      struct drm_display_mode *mode);
 730 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 731                                              unsigned int tiling_mode,
 732                                              unsigned int bpp,
 733                                              unsigned int pitch);
 734 void intel_display_handle_reset(struct drm_device *dev);
 735 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 736 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 737 void intel_dp_get_m_n(struct intel_crtc *crtc,
 738                       struct intel_crtc_config *pipe_config);
 739 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 740 void
 741 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 742                                 int dotclock);
 743 bool intel_crtc_active(struct drm_crtc *crtc);
 744 void hsw_enable_ips(struct intel_crtc *crtc);
 745 void hsw_disable_ips(struct intel_crtc *crtc);
 746 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
 747 enum intel_display_power_domain
 748 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 749 int valleyview_get_vco(struct drm_i915_private *dev_priv);
 750 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 751                                  struct intel_crtc_config *pipe_config);
 752 int intel_format_to_fourcc(int format);
 753
 754 /* intel_dp.c */
 755 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 756 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 757                              struct intel_connector *intel_connector);
 758 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 759 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 760 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 761 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 762 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 763 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 764 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 765 bool intel_dp_compute_config(struct intel_encoder *encoder,
 766                              struct intel_crtc_config *pipe_config);
 767 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 768 void intel_edp_backlight_on(struct intel_dp *intel_dp);
 769 void intel_edp_backlight_off(struct intel_dp *intel_dp);
 770 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 771 void intel_edp_panel_on(struct intel_dp *intel_dp);
 772 void intel_edp_panel_off(struct intel_dp *intel_dp);
 773 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 774 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 775 void intel_edp_psr_update(struct drm_device *dev);
 776
 777
 778 /* intel_dsi.c */
 779 bool intel_dsi_init(struct drm_device *dev);
 780
 781
 782 /* intel_dvo.c */
 783 void intel_dvo_init(struct drm_device *dev);
 784
 785
 786 /* legacy fbdev emulation in intel_fbdev.c */
 787 #ifdef CONFIG_DRM_I915_FBDEV
 788 extern int intel_fbdev_init(struct drm_device *dev);
 789 extern void intel_fbdev_initial_config(struct drm_device *dev);
 790 extern void intel_fbdev_fini(struct drm_device *dev);
 791 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 792 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 793 extern void intel_fbdev_restore_mode(struct drm_device *dev);
 794 #else
 795 static inline int intel_fbdev_init(struct drm_device *dev)
 796 {
 797         return 0;
 798 }
 799
 800 static inline void intel_fbdev_initial_config(struct drm_device *dev)
 801 {
 802 }
 803
 804 static inline void intel_fbdev_fini(struct drm_device *dev)
 805 {
 806 }
 807
 808 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
 809 {
 810 }
 811
 812 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 813 {
 814 }
 815 #endif
 816
 817 /* intel_hdmi.c */
 818 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 819 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 820                                struct intel_connector *intel_connector);
 821 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 822 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 823                                struct intel_crtc_config *pipe_config);
 824
 825
 826 /* intel_lvds.c */
 827 void intel_lvds_init(struct drm_device *dev);
 828 bool intel_is_dual_link_lvds(struct drm_device *dev);
 829
 830
 831 /* intel_modes.c */
 832 int intel_connector_update_modes(struct drm_connector *connector,
 833                                  struct edid *edid);
 834 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 835 void intel_attach_force_audio_property(struct drm_connector *connector);
 836 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 837
 838
 839 /* intel_overlay.c */
 840 void intel_setup_overlay(struct drm_device *dev);
 841 void intel_cleanup_overlay(struct drm_device *dev);
 842 int intel_overlay_switch_off(struct intel_overlay *overlay);
 843 int intel_overlay_put_image(struct drm_device *dev, void *data,
 844                             struct drm_file *file_priv);
 845 int intel_overlay_attrs(struct drm_device *dev, void *data,
 846                         struct drm_file *file_priv);
 847
 848
 849 /* intel_panel.c */
 850 int intel_panel_init(struct intel_panel *panel,
 851                      struct drm_display_mode *fixed_mode,
 852                      struct drm_display_mode *downclock_mode);
 853 void intel_panel_fini(struct intel_panel *panel);
 854 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
 855                             struct drm_display_mode *adjusted_mode);
 856 void intel_pch_panel_fitting(struct intel_crtc *crtc,
 857                              struct intel_crtc_config *pipe_config,
 858                              int fitting_mode);
 859 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 860                               struct intel_crtc_config *pipe_config,
 861                               int fitting_mode);
 862 void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
 863                                u32 max);
 864 int intel_panel_setup_backlight(struct drm_connector *connector);
 865 void intel_panel_enable_backlight(struct intel_connector *connector);
 866 void intel_panel_disable_backlight(struct intel_connector *connector);
 867 void intel_panel_destroy_backlight(struct drm_connector *connector);
 868 void intel_panel_init_backlight_funcs(struct drm_device *dev);
 869 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 870 extern struct drm_display_mode *intel_find_panel_downclock(
 871                                 struct drm_device *dev,
 872                                 struct drm_display_mode *fixed_mode,
 873                                 struct drm_connector *connector);
 874
 875 /* intel_pm.c */
 876 void intel_init_clock_gating(struct drm_device *dev);
 877 void intel_suspend_hw(struct drm_device *dev);
 878 void intel_update_watermarks(struct drm_crtc *crtc);
 879 void intel_update_sprite_watermarks(struct drm_plane *plane,
 880                                     struct drm_crtc *crtc,
 881                                     uint32_t sprite_width, int pixel_size,
 882                                     bool enabled, bool scaled);
 883 void intel_init_pm(struct drm_device *dev);
 884 void intel_pm_setup(struct drm_device *dev);
 885 bool intel_fbc_enabled(struct drm_device *dev);
 886 void intel_update_fbc(struct drm_device *dev);
 887 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 888 void intel_gpu_ips_teardown(void);
 889 int intel_power_domains_init(struct drm_i915_private *);
 890 void intel_power_domains_remove(struct drm_i915_private *);
 891 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
 892                                  enum intel_display_power_domain domain);
 893 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
 894                                     enum intel_display_power_domain domain);
 895 void intel_display_power_get(struct drm_i915_private *dev_priv,
 896                              enum intel_display_power_domain domain);
 897 void intel_display_power_put(struct drm_i915_private *dev_priv,
 898                              enum intel_display_power_domain domain);
 899 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
 900 void intel_init_gt_powersave(struct drm_device *dev);
 901 void intel_cleanup_gt_powersave(struct drm_device *dev);
 902 void intel_enable_gt_powersave(struct drm_device *dev);
 903 void intel_disable_gt_powersave(struct drm_device *dev);
 904 void ironlake_teardown_rc6(struct drm_device *dev);
 905 void gen6_update_ring_freq(struct drm_device *dev);
 906 void gen6_rps_idle(struct drm_i915_private *dev_priv);
 907 void gen6_rps_boost(struct drm_i915_private *dev_priv);
 908 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
 909 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 910 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
 911 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
 912 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
 913 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
 914 void ilk_wm_get_hw_state(struct drm_device *dev);
 915
 916
 917 /* intel_sdvo.c */
 918 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
 919
 920
 921 /* intel_sprite.c */
 922 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 923 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 924                                enum plane plane);
 925 void intel_plane_restore(struct drm_plane *plane);
 926 void intel_plane_disable(struct drm_plane *plane);
 927 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 928                               struct drm_file *file_priv);
 929 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 930                               struct drm_file *file_priv);
 931
 932
 933 /* intel_tv.c */
 934 void intel_tv_init(struct drm_device *dev);
 935
 936 #endif /* __INTEL_DRV_H__ */