drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include "i915_drm.h"
  30 #include "i915_drv.h"
  31 #include "drm_crtc.h"
  32 #include "drm_crtc_helper.h"
  33 #include "drm_fb_helper.h"
  34 #include "drm_dp_helper.h"
  35
  36 #define _wait_for(COND, MS, W) ({ \
  37         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);       \
  38         int ret__ = 0;                                                  \
  39         while (!(COND)) {                                               \
  40                 if (time_after(jiffies, timeout__)) {                   \
  41                         ret__ = -ETIMEDOUT;                             \
  42                         break;                                          \
  43                 }                                                       \
  44                 if (W && drm_can_sleep())  {                            \
  45                         msleep(W);                                      \
  46                 } else {                                                \
  47                         cpu_relax();                                    \
  48                 }                                                       \
  49         }                                                               \
  50         ret__;                                                          \
  51 })
  52
  53 #define wait_for_atomic_us(COND, US) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US);       \
  55         int ret__ = 0;                                                  \
  56         while (!(COND)) {                                               \
  57                 if (time_after(jiffies, timeout__)) {                   \
  58                         ret__ = -ETIMEDOUT;                             \
  59                         break;                                          \
  60                 }                                                       \
  61                 cpu_relax();                                            \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68
  69 #define KHz(x) (1000*x)
  70 #define MHz(x) KHz(1000*x)
  71
  72 /*
  73  * Display related stuff
  74  */
  75
  76 /* store information about an Ixxx DVO */
  77 /* The i830->i865 use multiple DVOs with multiple i2cs */
  78 /* the i915, i945 have a single sDVO i2c bus - which is different */
  79 #define MAX_OUTPUTS 6
  80 /* maximum connectors per crtcs in the mode set */
  81 #define INTELFB_CONN_LIMIT 4
  82
  83 #define INTEL_I2C_BUS_DVO 1
  84 #define INTEL_I2C_BUS_SDVO 2
  85
  86 /* these are outputs from the chip - integrated only
  87    external chips are via DVO or SDVO output */
  88 #define INTEL_OUTPUT_UNUSED 0
  89 #define INTEL_OUTPUT_ANALOG 1
  90 #define INTEL_OUTPUT_DVO 2
  91 #define INTEL_OUTPUT_SDVO 3
  92 #define INTEL_OUTPUT_LVDS 4
  93 #define INTEL_OUTPUT_TVOUT 5
  94 #define INTEL_OUTPUT_HDMI 6
  95 #define INTEL_OUTPUT_DISPLAYPORT 7
  96 #define INTEL_OUTPUT_EDP 8
  97
  98 #define INTEL_DVO_CHIP_NONE 0
  99 #define INTEL_DVO_CHIP_LVDS 1
 100 #define INTEL_DVO_CHIP_TMDS 2
 101 #define INTEL_DVO_CHIP_TVOUT 4
 102
 103 /* drm_display_mode->private_flags */
 104 #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
 105 #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
 106 #define INTEL_MODE_DP_FORCE_6BPC (0x10)
 107 /* This flag must be set by the encoder's mode_fixup if it changes the crtc
 108  * timings in the mode to prevent the crtc fixup from overwriting them.
 109  * Currently only lvds needs that. */
 110 #define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
 111
 112 static inline void
 113 intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
 114                                 int multiplier)
 115 {
 116         mode->clock *= multiplier;
 117         mode->private_flags |= multiplier;
 118 }
 119
 120 static inline int
 121 intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
 122 {
 123         return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
 124 }
 125
 126 struct intel_framebuffer {
 127         struct drm_framebuffer base;
 128         struct drm_i915_gem_object *obj;
 129 };
 130
 131 struct intel_fbdev {
 132         struct drm_fb_helper helper;
 133         struct intel_framebuffer ifb;
 134         struct list_head fbdev_list;
 135         struct drm_display_mode *our_mode;
 136 };
 137
 138 struct intel_encoder {
 139         struct drm_encoder base;
 140         /*
 141          * The new crtc this encoder will be driven from. Only differs from
 142          * base->crtc while a modeset is in progress.
 143          */
 144         struct intel_crtc *new_crtc;
 145
 146         int type;
 147         bool needs_tv_clock;
 148         /*
 149          * Intel hw has only one MUX where encoders could be clone, hence a
 150          * simple flag is enough to compute the possible_clones mask.
 151          */
 152         bool cloneable;
 153         bool connectors_active;
 154         void (*hot_plug)(struct intel_encoder *);
 155         void (*pre_enable)(struct intel_encoder *);
 156         void (*enable)(struct intel_encoder *);
 157         void (*disable)(struct intel_encoder *);
 158         void (*post_disable)(struct intel_encoder *);
 159         /* Read out the current hw state of this connector, returning true if
 160          * the encoder is active. If the encoder is enabled it also set the pipe
 161          * it is connected to in the pipe parameter. */
 162         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 163         int crtc_mask;
 164 };
 165
 166 struct intel_connector {
 167         struct drm_connector base;
 168         /*
 169          * The fixed encoder this connector is connected to.
 170          */
 171         struct intel_encoder *encoder;
 172
 173         /*
 174          * The new encoder this connector will be driven. Only differs from
 175          * encoder while a modeset is in progress.
 176          */
 177         struct intel_encoder *new_encoder;
 178
 179         /* Reads out the current hw, returning true if the connector is enabled
 180          * and active (i.e. dpms ON state). */
 181         bool (*get_hw_state)(struct intel_connector *);
 182 };
 183
 184 struct intel_crtc {
 185         struct drm_crtc base;
 186         enum pipe pipe;
 187         enum plane plane;
 188         u8 lut_r[256], lut_g[256], lut_b[256];
 189         /*
 190          * Whether the crtc and the connected output pipeline is active. Implies
 191          * that crtc->enabled is set, i.e. the current mode configuration has
 192          * some outputs connected to this crtc.
 193          */
 194         bool active;
 195         bool primary_disabled; /* is the crtc obscured by a plane? */
 196         bool lowfreq_avail;
 197         struct intel_overlay *overlay;
 198         struct intel_unpin_work *unpin_work;
 199         int fdi_lanes;
 200
 201         /* Display surface base address adjustement for pageflips. Note that on
 202          * gen4+ this only adjusts up to a tile, offsets within a tile are
 203          * handled in the hw itself (with the TILEOFF register). */
 204         unsigned long dspaddr_offset;
 205
 206         struct drm_i915_gem_object *cursor_bo;
 207         uint32_t cursor_addr;
 208         int16_t cursor_x, cursor_y;
 209         int16_t cursor_width, cursor_height;
 210         bool cursor_visible;
 211         unsigned int bpp;
 212
 213         /* We can share PLLs across outputs if the timings match */
 214         struct intel_pch_pll *pch_pll;
 215         uint32_t ddi_pll_sel;
 216 };
 217
 218 struct intel_plane {
 219         struct drm_plane base;
 220         enum pipe pipe;
 221         struct drm_i915_gem_object *obj;
 222         int max_downscale;
 223         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 224         void (*update_plane)(struct drm_plane *plane,
 225                              struct drm_framebuffer *fb,
 226                              struct drm_i915_gem_object *obj,
 227                              int crtc_x, int crtc_y,
 228                              unsigned int crtc_w, unsigned int crtc_h,
 229                              uint32_t x, uint32_t y,
 230                              uint32_t src_w, uint32_t src_h);
 231         void (*disable_plane)(struct drm_plane *plane);
 232         int (*update_colorkey)(struct drm_plane *plane,
 233                                struct drm_intel_sprite_colorkey *key);
 234         void (*get_colorkey)(struct drm_plane *plane,
 235                              struct drm_intel_sprite_colorkey *key);
 236 };
 237
 238 struct intel_watermark_params {
 239         unsigned long fifo_size;
 240         unsigned long max_wm;
 241         unsigned long default_wm;
 242         unsigned long guard_size;
 243         unsigned long cacheline_size;
 244 };
 245
 246 struct cxsr_latency {
 247         int is_desktop;
 248         int is_ddr3;
 249         unsigned long fsb_freq;
 250         unsigned long mem_freq;
 251         unsigned long display_sr;
 252         unsigned long display_hpll_disable;
 253         unsigned long cursor_sr;
 254         unsigned long cursor_hpll_disable;
 255 };
 256
 257 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 258 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 259 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 260 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 261 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 262
 263 #define DIP_HEADER_SIZE 5
 264
 265 #define DIP_TYPE_AVI    0x82
 266 #define DIP_VERSION_AVI 0x2
 267 #define DIP_LEN_AVI     13
 268 #define DIP_AVI_PR_1    0
 269 #define DIP_AVI_PR_2    1
 270
 271 #define DIP_TYPE_SPD    0x83
 272 #define DIP_VERSION_SPD 0x1
 273 #define DIP_LEN_SPD     25
 274 #define DIP_SPD_UNKNOWN 0
 275 #define DIP_SPD_DSTB    0x1
 276 #define DIP_SPD_DVDP    0x2
 277 #define DIP_SPD_DVHS    0x3
 278 #define DIP_SPD_HDDVR   0x4
 279 #define DIP_SPD_DVC     0x5
 280 #define DIP_SPD_DSC     0x6
 281 #define DIP_SPD_VCD     0x7
 282 #define DIP_SPD_GAME    0x8
 283 #define DIP_SPD_PC      0x9
 284 #define DIP_SPD_BD      0xa
 285 #define DIP_SPD_SCD     0xb
 286
 287 struct dip_infoframe {
 288         uint8_t type;           /* HB0 */
 289         uint8_t ver;            /* HB1 */
 290         uint8_t len;            /* HB2 - body len, not including checksum */
 291         uint8_t ecc;            /* Header ECC */
 292         uint8_t checksum;       /* PB0 */
 293         union {
 294                 struct {
 295                         /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
 296                         uint8_t Y_A_B_S;
 297                         /* PB2 - C 7:6, M 5:4, R 3:0 */
 298                         uint8_t C_M_R;
 299                         /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
 300                         uint8_t ITC_EC_Q_SC;
 301                         /* PB4 - VIC 6:0 */
 302                         uint8_t VIC;
 303                         /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
 304                         uint8_t YQ_CN_PR;
 305                         /* PB6 to PB13 */
 306                         uint16_t top_bar_end;
 307                         uint16_t bottom_bar_start;
 308                         uint16_t left_bar_end;
 309                         uint16_t right_bar_start;
 310                 } __attribute__ ((packed)) avi;
 311                 struct {
 312                         uint8_t vn[8];
 313                         uint8_t pd[16];
 314                         uint8_t sdi;
 315                 } __attribute__ ((packed)) spd;
 316                 uint8_t payload[27];
 317         } __attribute__ ((packed)) body;
 318 } __attribute__((packed));
 319
 320 struct intel_hdmi {
 321         struct intel_encoder base;
 322         u32 sdvox_reg;
 323         int ddc_bus;
 324         int ddi_port;
 325         uint32_t color_range;
 326         bool has_hdmi_sink;
 327         bool has_audio;
 328         enum hdmi_force_audio force_audio;
 329         void (*write_infoframe)(struct drm_encoder *encoder,
 330                                 struct dip_infoframe *frame);
 331         void (*set_infoframes)(struct drm_encoder *encoder,
 332                                struct drm_display_mode *adjusted_mode);
 333 };
 334
 335 #define DP_RECEIVER_CAP_SIZE            0xf
 336 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 337 #define DP_LINK_CONFIGURATION_SIZE      9
 338
 339 struct intel_dp {
 340         struct intel_encoder base;
 341         uint32_t output_reg;
 342         uint32_t DP;
 343         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
 344         bool has_audio;
 345         enum hdmi_force_audio force_audio;
 346         enum port port;
 347         uint32_t color_range;
 348         uint8_t link_bw;
 349         uint8_t lane_count;
 350         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 351         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 352         struct i2c_adapter adapter;
 353         struct i2c_algo_dp_aux_data algo;
 354         bool is_pch_edp;
 355         uint8_t train_set[4];
 356         int panel_power_up_delay;
 357         int panel_power_down_delay;
 358         int panel_power_cycle_delay;
 359         int backlight_on_delay;
 360         int backlight_off_delay;
 361         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
 362         struct delayed_work panel_vdd_work;
 363         bool want_panel_vdd;
 364         struct edid *edid; /* cached EDID for eDP */
 365         int edid_mode_count;
 366 };
 367
 368 static inline struct drm_crtc *
 369 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 370 {
 371         struct drm_i915_private *dev_priv = dev->dev_private;
 372         return dev_priv->pipe_to_crtc_mapping[pipe];
 373 }
 374
 375 static inline struct drm_crtc *
 376 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 377 {
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379         return dev_priv->plane_to_crtc_mapping[plane];
 380 }
 381
 382 struct intel_unpin_work {
 383         struct work_struct work;
 384         struct drm_device *dev;
 385         struct drm_i915_gem_object *old_fb_obj;
 386         struct drm_i915_gem_object *pending_flip_obj;
 387         struct drm_pending_vblank_event *event;
 388         int pending;
 389         bool enable_stall_check;
 390 };
 391
 392 struct intel_fbc_work {
 393         struct delayed_work work;
 394         struct drm_crtc *crtc;
 395         struct drm_framebuffer *fb;
 396         int interval;
 397 };
 398
 399 int intel_connector_update_modes(struct drm_connector *connector,
 400                                 struct edid *edid);
 401 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 402
 403 extern void intel_attach_force_audio_property(struct drm_connector *connector);
 404 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 405
 406 extern void intel_crt_init(struct drm_device *dev);
 407 extern void intel_hdmi_init(struct drm_device *dev,
 408                             int sdvox_reg, enum port port);
 409 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 410 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
 411 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
 412                             bool is_sdvob);
 413 extern void intel_dvo_init(struct drm_device *dev);
 414 extern void intel_tv_init(struct drm_device *dev);
 415 extern void intel_mark_busy(struct drm_device *dev);
 416 extern void intel_mark_idle(struct drm_device *dev);
 417 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
 418 extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
 419 extern bool intel_lvds_init(struct drm_device *dev);
 420 extern void intel_dp_init(struct drm_device *dev, int output_reg,
 421                           enum port port);
 422 void
 423 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 424                  struct drm_display_mode *adjusted_mode);
 425 extern bool intel_dpd_is_edp(struct drm_device *dev);
 426 extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
 427 extern int intel_edp_target_clock(struct intel_encoder *,
 428                                   struct drm_display_mode *mode);
 429 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
 430 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
 431 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
 432                                       enum plane plane);
 433
 434 /* intel_panel.c */
 435 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
 436                                    struct drm_display_mode *adjusted_mode);
 437 extern void intel_pch_panel_fitting(struct drm_device *dev,
 438                                     int fitting_mode,
 439                                     const struct drm_display_mode *mode,
 440                                     struct drm_display_mode *adjusted_mode);
 441 extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
 442 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
 443 extern int intel_panel_setup_backlight(struct drm_device *dev);
 444 extern void intel_panel_enable_backlight(struct drm_device *dev,
 445                                          enum pipe pipe);
 446 extern void intel_panel_disable_backlight(struct drm_device *dev);
 447 extern void intel_panel_destroy_backlight(struct drm_device *dev);
 448 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 449
 450 struct intel_set_config {
 451         struct drm_encoder **save_connector_encoders;
 452         struct drm_crtc **save_encoder_crtcs;
 453
 454         bool fb_changed;
 455         bool mode_changed;
 456 };
 457
 458 extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
 459                            int x, int y, struct drm_framebuffer *old_fb);
 460 extern void intel_modeset_disable(struct drm_device *dev);
 461 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
 462 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
 463 extern void intel_encoder_noop(struct drm_encoder *encoder);
 464 extern void intel_encoder_destroy(struct drm_encoder *encoder);
 465 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
 466 extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
 467 extern void intel_connector_dpms(struct drm_connector *, int mode);
 468 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
 469 extern void intel_modeset_check_state(struct drm_device *dev);
 470
 471
 472 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
 473 {
 474         return to_intel_connector(connector)->encoder;
 475 }
 476
 477 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 478 {
 479         return container_of(encoder, struct intel_dp, base.base);
 480 }
 481
 482 extern void intel_connector_attach_encoder(struct intel_connector *connector,
 483                                            struct intel_encoder *encoder);
 484 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 485
 486 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 487                                                     struct drm_crtc *crtc);
 488 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 489                                 struct drm_file *file_priv);
 490 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 491 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 492
 493 struct intel_load_detect_pipe {
 494         struct drm_framebuffer *release_fb;
 495         bool load_detect_temp;
 496         int dpms_mode;
 497 };
 498 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
 499                                        struct drm_display_mode *mode,
 500                                        struct intel_load_detect_pipe *old);
 501 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
 502                                            struct intel_load_detect_pipe *old);
 503
 504 extern void intelfb_restore(void);
 505 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 506                                     u16 blue, int regno);
 507 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 508                                     u16 *blue, int regno);
 509 extern void intel_enable_clock_gating(struct drm_device *dev);
 510
 511 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 512                                       struct drm_i915_gem_object *obj,
 513                                       struct intel_ring_buffer *pipelined);
 514 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 515
 516 extern int intel_framebuffer_init(struct drm_device *dev,
 517                                   struct intel_framebuffer *ifb,
 518                                   struct drm_mode_fb_cmd2 *mode_cmd,
 519                                   struct drm_i915_gem_object *obj);
 520 extern int intel_fbdev_init(struct drm_device *dev);
 521 extern void intel_fbdev_fini(struct drm_device *dev);
 522 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 523 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
 524 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
 525 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 526
 527 extern void intel_setup_overlay(struct drm_device *dev);
 528 extern void intel_cleanup_overlay(struct drm_device *dev);
 529 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
 530 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
 531                                    struct drm_file *file_priv);
 532 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
 533                                struct drm_file *file_priv);
 534
 535 extern void intel_fb_output_poll_changed(struct drm_device *dev);
 536 extern void intel_fb_restore_mode(struct drm_device *dev);
 537
 538 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 539                         bool state);
 540 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 541 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 542
 543 extern void intel_init_clock_gating(struct drm_device *dev);
 544 extern void intel_write_eld(struct drm_encoder *encoder,
 545                             struct drm_display_mode *mode);
 546 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
 547 extern void intel_prepare_ddi(struct drm_device *dev);
 548 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
 549 extern void intel_ddi_init(struct drm_device *dev, enum port port);
 550
 551 /* For use by IVB LP watermark workaround in intel_sprite.c */
 552 extern void intel_update_watermarks(struct drm_device *dev);
 553 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
 554                                            uint32_t sprite_width,
 555                                            int pixel_size);
 556 extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
 557                          struct drm_display_mode *mode);
 558
 559 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 560                                      struct drm_file *file_priv);
 561 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 562                                      struct drm_file *file_priv);
 563
 564 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
 565
 566 /* Power-related functions, located in intel_pm.c */
 567 extern void intel_init_pm(struct drm_device *dev);
 568 /* FBC */
 569 extern bool intel_fbc_enabled(struct drm_device *dev);
 570 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
 571 extern void intel_update_fbc(struct drm_device *dev);
 572 /* IPS */
 573 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 574 extern void intel_gpu_ips_teardown(void);
 575
 576 extern void intel_init_power_wells(struct drm_device *dev);
 577 extern void intel_enable_gt_powersave(struct drm_device *dev);
 578 extern void intel_disable_gt_powersave(struct drm_device *dev);
 579 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
 580 extern void ironlake_teardown_rc6(struct drm_device *dev);
 581
 582 extern void intel_enable_ddi(struct intel_encoder *encoder);
 583 extern void intel_disable_ddi(struct intel_encoder *encoder);
 584 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 585                                    enum pipe *pipe);
 586 extern void intel_ddi_mode_set(struct drm_encoder *encoder,
 587                                 struct drm_display_mode *mode,
 588                                 struct drm_display_mode *adjusted_mode);
 589 extern void intel_ddi_pll_init(struct drm_device *dev);
 590 extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
 591 extern void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,
 592                                         enum pipe pipe);
 593 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 594 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 595 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 596 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
 597 extern void intel_ddi_pre_enable(struct intel_encoder *intel_encoder);
 598 extern void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
 599 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 600
 601 #endif /* __INTEL_DRV_H__ */