drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000*x)
  69 #define MHz(x) KHz(1000*x)
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80 #define INTELFB_CONN_LIMIT 4
  81
  82 #define INTEL_I2C_BUS_DVO 1
  83 #define INTEL_I2C_BUS_SDVO 2
  84
  85 /* these are outputs from the chip - integrated only
  86    external chips are via DVO or SDVO output */
  87 #define INTEL_OUTPUT_UNUSED 0
  88 #define INTEL_OUTPUT_ANALOG 1
  89 #define INTEL_OUTPUT_DVO 2
  90 #define INTEL_OUTPUT_SDVO 3
  91 #define INTEL_OUTPUT_LVDS 4
  92 #define INTEL_OUTPUT_TVOUT 5
  93 #define INTEL_OUTPUT_HDMI 6
  94 #define INTEL_OUTPUT_DISPLAYPORT 7
  95 #define INTEL_OUTPUT_EDP 8
  96 #define INTEL_OUTPUT_DSI 9
  97 #define INTEL_OUTPUT_UNKNOWN 10
  98
  99 #define INTEL_DVO_CHIP_NONE 0
 100 #define INTEL_DVO_CHIP_LVDS 1
 101 #define INTEL_DVO_CHIP_TMDS 2
 102 #define INTEL_DVO_CHIP_TVOUT 4
 103
 104 #define INTEL_DSI_COMMAND_MODE  0
 105 #define INTEL_DSI_VIDEO_MODE    1
 106
 107 struct intel_framebuffer {
 108         struct drm_framebuffer base;
 109         struct drm_i915_gem_object *obj;
 110 };
 111
 112 struct intel_fbdev {
 113         struct drm_fb_helper helper;
 114         struct intel_framebuffer ifb;
 115         struct list_head fbdev_list;
 116         struct drm_display_mode *our_mode;
 117 };
 118
 119 struct intel_encoder {
 120         struct drm_encoder base;
 121         /*
 122          * The new crtc this encoder will be driven from. Only differs from
 123          * base->crtc while a modeset is in progress.
 124          */
 125         struct intel_crtc *new_crtc;
 126
 127         int type;
 128         /*
 129          * Intel hw has only one MUX where encoders could be clone, hence a
 130          * simple flag is enough to compute the possible_clones mask.
 131          */
 132         bool cloneable;
 133         bool connectors_active;
 134         void (*hot_plug)(struct intel_encoder *);
 135         bool (*compute_config)(struct intel_encoder *,
 136                                struct intel_crtc_config *);
 137         void (*pre_pll_enable)(struct intel_encoder *);
 138         void (*pre_enable)(struct intel_encoder *);
 139         void (*enable)(struct intel_encoder *);
 140         void (*mode_set)(struct intel_encoder *intel_encoder);
 141         void (*disable)(struct intel_encoder *);
 142         void (*post_disable)(struct intel_encoder *);
 143         /* Read out the current hw state of this connector, returning true if
 144          * the encoder is active. If the encoder is enabled it also set the pipe
 145          * it is connected to in the pipe parameter. */
 146         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 147         /* Reconstructs the equivalent mode flags for the current hardware
 148          * state. This must be called _after_ display->get_pipe_config has
 149          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 150          * be set correctly before calling this function. */
 151         void (*get_config)(struct intel_encoder *,
 152                            struct intel_crtc_config *pipe_config);
 153         int crtc_mask;
 154         enum hpd_pin hpd_pin;
 155 };
 156
 157 struct intel_panel {
 158         struct drm_display_mode *fixed_mode;
 159         int fitting_mode;
 160 };
 161
 162 struct intel_connector {
 163         struct drm_connector base;
 164         /*
 165          * The fixed encoder this connector is connected to.
 166          */
 167         struct intel_encoder *encoder;
 168
 169         /*
 170          * The new encoder this connector will be driven. Only differs from
 171          * encoder while a modeset is in progress.
 172          */
 173         struct intel_encoder *new_encoder;
 174
 175         /* Reads out the current hw, returning true if the connector is enabled
 176          * and active (i.e. dpms ON state). */
 177         bool (*get_hw_state)(struct intel_connector *);
 178
 179         /* Panel info for eDP and LVDS */
 180         struct intel_panel panel;
 181
 182         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 183         struct edid *edid;
 184
 185         /* since POLL and HPD connectors may use the same HPD line keep the native
 186            state of connector->polled in case hotplug storm detection changes it */
 187         u8 polled;
 188 };
 189
 190 typedef struct dpll {
 191         /* given values */
 192         int n;
 193         int m1, m2;
 194         int p1, p2;
 195         /* derived values */
 196         int     dot;
 197         int     vco;
 198         int     m;
 199         int     p;
 200 } intel_clock_t;
 201
 202 struct intel_crtc_config {
 203         /**
 204          * quirks - bitfield with hw state readout quirks
 205          *
 206          * For various reasons the hw state readout code might not be able to
 207          * completely faithfully read out the current state. These cases are
 208          * tracked with quirk flags so that fastboot and state checker can act
 209          * accordingly.
 210          */
 211 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
 212         unsigned long quirks;
 213
 214         /* User requested mode, only valid as a starting point to
 215          * compute adjusted_mode, except in the case of (S)DVO where
 216          * it's also for the output timings of the (S)DVO chip.
 217          * adjusted_mode will then correspond to the S(DVO) chip's
 218          * preferred input timings. */
 219         struct drm_display_mode requested_mode;
 220         /* Actual pipe timings ie. what we program into the pipe timing
 221          * registers. adjusted_mode.clock is the pipe pixel clock. */
 222         struct drm_display_mode adjusted_mode;
 223
 224         /* Pipe source size (ie. panel fitter input size)
 225          * All planes will be positioned inside this space,
 226          * and get clipped at the edges. */
 227         int pipe_src_w, pipe_src_h;
 228
 229         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 230          * between pch encoders and cpu encoders. */
 231         bool has_pch_encoder;
 232
 233         /* CPU Transcoder for the pipe. Currently this can only differ from the
 234          * pipe on Haswell (where we have a special eDP transcoder). */
 235         enum transcoder cpu_transcoder;
 236
 237         /*
 238          * Use reduced/limited/broadcast rbg range, compressing from the full
 239          * range fed into the crtcs.
 240          */
 241         bool limited_color_range;
 242
 243         /* DP has a bunch of special case unfortunately, so mark the pipe
 244          * accordingly. */
 245         bool has_dp_encoder;
 246
 247         /*
 248          * Enable dithering, used when the selected pipe bpp doesn't match the
 249          * plane bpp.
 250          */
 251         bool dither;
 252
 253         /* Controls for the clock computation, to override various stages. */
 254         bool clock_set;
 255
 256         /* SDVO TV has a bunch of special case. To make multifunction encoders
 257          * work correctly, we need to track this at runtime.*/
 258         bool sdvo_tv_clock;
 259
 260         /*
 261          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 262          * required. This is set in the 2nd loop of calling encoder's
 263          * ->compute_config if the first pick doesn't work out.
 264          */
 265         bool bw_constrained;
 266
 267         /* Settings for the intel dpll used on pretty much everything but
 268          * haswell. */
 269         struct dpll dpll;
 270
 271         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 272         enum intel_dpll_id shared_dpll;
 273
 274         /* Actual register state of the dpll, for shared dpll cross-checking. */
 275         struct intel_dpll_hw_state dpll_hw_state;
 276
 277         int pipe_bpp;
 278         struct intel_link_m_n dp_m_n;
 279
 280         /*
 281          * Frequence the dpll for the port should run at. Differs from the
 282          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 283          * already multiplied by pixel_multiplier.
 284          */
 285         int port_clock;
 286
 287         /* Used by SDVO (and if we ever fix it, HDMI). */
 288         unsigned pixel_multiplier;
 289
 290         /* Panel fitter controls for gen2-gen4 + VLV */
 291         struct {
 292                 u32 control;
 293                 u32 pgm_ratios;
 294                 u32 lvds_border_bits;
 295         } gmch_pfit;
 296
 297         /* Panel fitter placement and size for Ironlake+ */
 298         struct {
 299                 u32 pos;
 300                 u32 size;
 301         } pch_pfit;
 302
 303         /* FDI configuration, only valid if has_pch_encoder is set. */
 304         int fdi_lanes;
 305         struct intel_link_m_n fdi_m_n;
 306
 307         bool ips_enabled;
 308 };
 309
 310 struct intel_crtc {
 311         struct drm_crtc base;
 312         enum pipe pipe;
 313         enum plane plane;
 314         u8 lut_r[256], lut_g[256], lut_b[256];
 315         /*
 316          * Whether the crtc and the connected output pipeline is active. Implies
 317          * that crtc->enabled is set, i.e. the current mode configuration has
 318          * some outputs connected to this crtc.
 319          */
 320         bool active;
 321         bool eld_vld;
 322         bool primary_disabled; /* is the crtc obscured by a plane? */
 323         bool lowfreq_avail;
 324         struct intel_overlay *overlay;
 325         struct intel_unpin_work *unpin_work;
 326
 327         atomic_t unpin_work_count;
 328
 329         /* Display surface base address adjustement for pageflips. Note that on
 330          * gen4+ this only adjusts up to a tile, offsets within a tile are
 331          * handled in the hw itself (with the TILEOFF register). */
 332         unsigned long dspaddr_offset;
 333
 334         struct drm_i915_gem_object *cursor_bo;
 335         uint32_t cursor_addr;
 336         int16_t cursor_x, cursor_y;
 337         int16_t cursor_width, cursor_height;
 338         bool cursor_visible;
 339
 340         struct intel_crtc_config config;
 341
 342         uint32_t ddi_pll_sel;
 343
 344         /* reset counter value when the last flip was submitted */
 345         unsigned int reset_counter;
 346
 347         /* Access to these should be protected by dev_priv->irq_lock. */
 348         bool cpu_fifo_underrun_disabled;
 349         bool pch_fifo_underrun_disabled;
 350 };
 351
 352 struct intel_plane_wm_parameters {
 353         uint32_t horiz_pixels;
 354         uint8_t bytes_per_pixel;
 355         bool enabled;
 356         bool scaled;
 357 };
 358
 359 struct intel_plane {
 360         struct drm_plane base;
 361         int plane;
 362         enum pipe pipe;
 363         struct drm_i915_gem_object *obj;
 364         bool can_scale;
 365         int max_downscale;
 366         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 367         int crtc_x, crtc_y;
 368         unsigned int crtc_w, crtc_h;
 369         uint32_t src_x, src_y;
 370         uint32_t src_w, src_h;
 371
 372         /* Since we need to change the watermarks before/after
 373          * enabling/disabling the planes, we need to store the parameters here
 374          * as the other pieces of the struct may not reflect the values we want
 375          * for the watermark calculations. Currently only Haswell uses this.
 376          */
 377         struct intel_plane_wm_parameters wm;
 378
 379         void (*update_plane)(struct drm_plane *plane,
 380                              struct drm_crtc *crtc,
 381                              struct drm_framebuffer *fb,
 382                              struct drm_i915_gem_object *obj,
 383                              int crtc_x, int crtc_y,
 384                              unsigned int crtc_w, unsigned int crtc_h,
 385                              uint32_t x, uint32_t y,
 386                              uint32_t src_w, uint32_t src_h);
 387         void (*disable_plane)(struct drm_plane *plane,
 388                               struct drm_crtc *crtc);
 389         int (*update_colorkey)(struct drm_plane *plane,
 390                                struct drm_intel_sprite_colorkey *key);
 391         void (*get_colorkey)(struct drm_plane *plane,
 392                              struct drm_intel_sprite_colorkey *key);
 393 };
 394
 395 struct intel_watermark_params {
 396         unsigned long fifo_size;
 397         unsigned long max_wm;
 398         unsigned long default_wm;
 399         unsigned long guard_size;
 400         unsigned long cacheline_size;
 401 };
 402
 403 struct cxsr_latency {
 404         int is_desktop;
 405         int is_ddr3;
 406         unsigned long fsb_freq;
 407         unsigned long mem_freq;
 408         unsigned long display_sr;
 409         unsigned long display_hpll_disable;
 410         unsigned long cursor_sr;
 411         unsigned long cursor_hpll_disable;
 412 };
 413
 414 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 415 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 416 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 417 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 418 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 419
 420 struct intel_hdmi {
 421         u32 hdmi_reg;
 422         int ddc_bus;
 423         uint32_t color_range;
 424         bool color_range_auto;
 425         bool has_hdmi_sink;
 426         bool has_audio;
 427         enum hdmi_force_audio force_audio;
 428         bool rgb_quant_range_selectable;
 429         void (*write_infoframe)(struct drm_encoder *encoder,
 430                                 enum hdmi_infoframe_type type,
 431                                 const uint8_t *frame, ssize_t len);
 432         void (*set_infoframes)(struct drm_encoder *encoder,
 433                                struct drm_display_mode *adjusted_mode);
 434 };
 435
 436 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 437 #define DP_LINK_CONFIGURATION_SIZE      9
 438
 439 struct intel_dp {
 440         uint32_t output_reg;
 441         uint32_t aux_ch_ctl_reg;
 442         uint32_t DP;
 443         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
 444         bool has_audio;
 445         enum hdmi_force_audio force_audio;
 446         uint32_t color_range;
 447         bool color_range_auto;
 448         uint8_t link_bw;
 449         uint8_t lane_count;
 450         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 451         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 452         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 453         struct i2c_adapter adapter;
 454         struct i2c_algo_dp_aux_data algo;
 455         uint8_t train_set[4];
 456         int panel_power_up_delay;
 457         int panel_power_down_delay;
 458         int panel_power_cycle_delay;
 459         int backlight_on_delay;
 460         int backlight_off_delay;
 461         struct delayed_work panel_vdd_work;
 462         bool want_panel_vdd;
 463         bool psr_setup_done;
 464         struct intel_connector *attached_connector;
 465 };
 466
 467 struct intel_digital_port {
 468         struct intel_encoder base;
 469         enum port port;
 470         u32 saved_port_bits;
 471         struct intel_dp dp;
 472         struct intel_hdmi hdmi;
 473 };
 474
 475 static inline int
 476 vlv_dport_to_channel(struct intel_digital_port *dport)
 477 {
 478         switch (dport->port) {
 479         case PORT_B:
 480                 return 0;
 481         case PORT_C:
 482                 return 1;
 483         default:
 484                 BUG();
 485         }
 486 }
 487
 488 static inline struct drm_crtc *
 489 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 490 {
 491         struct drm_i915_private *dev_priv = dev->dev_private;
 492         return dev_priv->pipe_to_crtc_mapping[pipe];
 493 }
 494
 495 static inline struct drm_crtc *
 496 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 497 {
 498         struct drm_i915_private *dev_priv = dev->dev_private;
 499         return dev_priv->plane_to_crtc_mapping[plane];
 500 }
 501
 502 struct intel_unpin_work {
 503         struct work_struct work;
 504         struct drm_crtc *crtc;
 505         struct drm_i915_gem_object *old_fb_obj;
 506         struct drm_i915_gem_object *pending_flip_obj;
 507         struct drm_pending_vblank_event *event;
 508         atomic_t pending;
 509 #define INTEL_FLIP_INACTIVE     0
 510 #define INTEL_FLIP_PENDING      1
 511 #define INTEL_FLIP_COMPLETE     2
 512         bool enable_stall_check;
 513 };
 514
 515 int intel_pch_rawclk(struct drm_device *dev);
 516
 517 int intel_connector_update_modes(struct drm_connector *connector,
 518                                 struct edid *edid);
 519 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 520
 521 extern void intel_attach_force_audio_property(struct drm_connector *connector);
 522 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 523
 524 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
 525 extern void intel_crt_init(struct drm_device *dev);
 526 extern void intel_hdmi_init(struct drm_device *dev,
 527                             int hdmi_reg, enum port port);
 528 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 529                                       struct intel_connector *intel_connector);
 530 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 531 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 532                                       struct intel_crtc_config *pipe_config);
 533 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
 534                             bool is_sdvob);
 535 extern void intel_dvo_init(struct drm_device *dev);
 536 extern void intel_tv_init(struct drm_device *dev);
 537 extern void intel_mark_busy(struct drm_device *dev);
 538 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 539                                struct intel_ring_buffer *ring);
 540 extern void intel_mark_idle(struct drm_device *dev);
 541 extern void intel_lvds_init(struct drm_device *dev);
 542 extern bool intel_dsi_init(struct drm_device *dev);
 543 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
 544 extern void intel_dp_init(struct drm_device *dev, int output_reg,
 545                           enum port port);
 546 extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 547                                     struct intel_connector *intel_connector);
 548 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
 549 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
 550 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 551 extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 552 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 553 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 554 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
 555 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
 556                                     struct intel_crtc_config *pipe_config);
 557 extern bool intel_dpd_is_edp(struct drm_device *dev);
 558 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
 559 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
 560 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
 561 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
 562 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 563 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 564 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 565 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
 566                                       enum plane plane);
 567
 568 /* intel_panel.c */
 569 extern int intel_panel_init(struct intel_panel *panel,
 570                             struct drm_display_mode *fixed_mode);
 571 extern void intel_panel_fini(struct intel_panel *panel);
 572
 573 extern void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
 574                                    struct drm_display_mode *adjusted_mode);
 575 extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
 576                                     struct intel_crtc_config *pipe_config,
 577                                     int fitting_mode);
 578 extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 579                                      struct intel_crtc_config *pipe_config,
 580                                      int fitting_mode);
 581 extern void intel_panel_set_backlight(struct drm_device *dev,
 582                                       u32 level, u32 max);
 583 extern int intel_panel_setup_backlight(struct drm_connector *connector);
 584 extern void intel_panel_enable_backlight(struct drm_device *dev,
 585                                          enum pipe pipe);
 586 extern void intel_panel_disable_backlight(struct drm_device *dev);
 587 extern void intel_panel_destroy_backlight(struct drm_device *dev);
 588 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 589
 590 struct intel_set_config {
 591         struct drm_encoder **save_connector_encoders;
 592         struct drm_crtc **save_encoder_crtcs;
 593
 594         bool fb_changed;
 595         bool mode_changed;
 596 };
 597
 598 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
 599 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
 600 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
 601 extern void intel_encoder_destroy(struct drm_encoder *encoder);
 602 extern void intel_connector_dpms(struct drm_connector *, int mode);
 603 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
 604 extern void intel_modeset_check_state(struct drm_device *dev);
 605 extern void intel_plane_restore(struct drm_plane *plane);
 606 extern void intel_plane_disable(struct drm_plane *plane);
 607
 608
 609 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
 610 {
 611         return to_intel_connector(connector)->encoder;
 612 }
 613
 614 static inline struct intel_digital_port *
 615 enc_to_dig_port(struct drm_encoder *encoder)
 616 {
 617         return container_of(encoder, struct intel_digital_port, base.base);
 618 }
 619
 620 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 621 {
 622         return &enc_to_dig_port(encoder)->dp;
 623 }
 624
 625 static inline struct intel_digital_port *
 626 dp_to_dig_port(struct intel_dp *intel_dp)
 627 {
 628         return container_of(intel_dp, struct intel_digital_port, dp);
 629 }
 630
 631 static inline struct intel_digital_port *
 632 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 633 {
 634         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 635 }
 636
 637 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 638                                 struct intel_digital_port *port);
 639
 640 extern void intel_connector_attach_encoder(struct intel_connector *connector,
 641                                            struct intel_encoder *encoder);
 642 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 643
 644 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 645                                                     struct drm_crtc *crtc);
 646 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 647                                 struct drm_file *file_priv);
 648 extern enum transcoder
 649 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 650                              enum pipe pipe);
 651 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 652 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 653 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 654 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
 655
 656 struct intel_load_detect_pipe {
 657         struct drm_framebuffer *release_fb;
 658         bool load_detect_temp;
 659         int dpms_mode;
 660 };
 661 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
 662                                        struct drm_display_mode *mode,
 663                                        struct intel_load_detect_pipe *old);
 664 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
 665                                            struct intel_load_detect_pipe *old);
 666
 667 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 668                                     u16 blue, int regno);
 669 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 670                                     u16 *blue, int regno);
 671
 672 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 673                                       struct drm_i915_gem_object *obj,
 674                                       struct intel_ring_buffer *pipelined);
 675 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 676
 677 extern int intel_framebuffer_init(struct drm_device *dev,
 678                                   struct intel_framebuffer *ifb,
 679                                   struct drm_mode_fb_cmd2 *mode_cmd,
 680                                   struct drm_i915_gem_object *obj);
 681 extern void intel_framebuffer_fini(struct intel_framebuffer *fb);
 682 extern int intel_fbdev_init(struct drm_device *dev);
 683 extern void intel_fbdev_initial_config(struct drm_device *dev);
 684 extern void intel_fbdev_fini(struct drm_device *dev);
 685 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 686 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
 687 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
 688 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 689
 690 extern void intel_setup_overlay(struct drm_device *dev);
 691 extern void intel_cleanup_overlay(struct drm_device *dev);
 692 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
 693 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
 694                                    struct drm_file *file_priv);
 695 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
 696                                struct drm_file *file_priv);
 697
 698 extern void intel_fb_output_poll_changed(struct drm_device *dev);
 699 extern void intel_fb_restore_mode(struct drm_device *dev);
 700
 701 struct intel_shared_dpll *
 702 intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 703
 704 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 705                         struct intel_shared_dpll *pll,
 706                         bool state);
 707 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 708 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 709 void assert_pll(struct drm_i915_private *dev_priv,
 710                 enum pipe pipe, bool state);
 711 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 712 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 713 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 714                        enum pipe pipe, bool state);
 715 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 716 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 717 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 718                         bool state);
 719 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 720 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 721
 722 extern void intel_init_clock_gating(struct drm_device *dev);
 723 extern void intel_suspend_hw(struct drm_device *dev);
 724 extern void intel_write_eld(struct drm_encoder *encoder,
 725                             struct drm_display_mode *mode);
 726 extern void intel_prepare_ddi(struct drm_device *dev);
 727 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
 728 extern void intel_ddi_init(struct drm_device *dev, enum port port);
 729 extern enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 730
 731 /* For use by IVB LP watermark workaround in intel_sprite.c */
 732 extern void intel_update_watermarks(struct drm_crtc *crtc);
 733 extern void intel_update_sprite_watermarks(struct drm_plane *plane,
 734                                            struct drm_crtc *crtc,
 735                                            uint32_t sprite_width, int pixel_size,
 736                                            bool enabled, bool scaled);
 737
 738 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 739                                                     unsigned int tiling_mode,
 740                                                     unsigned int bpp,
 741                                                     unsigned int pitch);
 742
 743 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 744                                      struct drm_file *file_priv);
 745 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 746                                      struct drm_file *file_priv);
 747
 748 /* Power-related functions, located in intel_pm.c */
 749 extern void intel_init_pm(struct drm_device *dev);
 750 /* FBC */
 751 extern bool intel_fbc_enabled(struct drm_device *dev);
 752 extern void intel_update_fbc(struct drm_device *dev);
 753 /* IPS */
 754 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 755 extern void intel_gpu_ips_teardown(void);
 756
 757 /* Power well */
 758 extern int i915_init_power_well(struct drm_device *dev);
 759 extern void i915_remove_power_well(struct drm_device *dev);
 760
 761 extern bool intel_display_power_enabled(struct drm_device *dev,
 762                                         enum intel_display_power_domain domain);
 763 extern void intel_init_power_well(struct drm_device *dev);
 764 extern void intel_set_power_well(struct drm_device *dev, bool enable);
 765 extern void intel_enable_gt_powersave(struct drm_device *dev);
 766 extern void intel_disable_gt_powersave(struct drm_device *dev);
 767 extern void ironlake_teardown_rc6(struct drm_device *dev);
 768 void gen6_update_ring_freq(struct drm_device *dev);
 769
 770 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 771                                    enum pipe *pipe);
 772 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 773 extern void intel_ddi_pll_init(struct drm_device *dev);
 774 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 775 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 776                                               enum transcoder cpu_transcoder);
 777 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 778 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 779 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 780 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
 781 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 782 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 783 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 784 extern bool
 785 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 786 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 787
 788 extern void intel_display_handle_reset(struct drm_device *dev);
 789 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 790                                                   enum pipe pipe,
 791                                                   bool enable);
 792 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 793                                                  enum transcoder pch_transcoder,
 794                                                  bool enable);
 795
 796 extern void intel_edp_psr_enable(struct intel_dp *intel_dp);
 797 extern void intel_edp_psr_disable(struct intel_dp *intel_dp);
 798 extern void intel_edp_psr_update(struct drm_device *dev);
 799 extern void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
 800                               bool switch_to_fclk, bool allow_power_down);
 801 extern void hsw_restore_lcpll(struct drm_i915_private *dev_priv);
 802 extern void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 803 extern void ilk_disable_gt_irq(struct drm_i915_private *dev_priv,
 804                                uint32_t mask);
 805 extern void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 806 extern void snb_disable_pm_irq(struct drm_i915_private *dev_priv,
 807                                uint32_t mask);
 808 extern void hsw_enable_pc8_work(struct work_struct *__work);
 809 extern void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
 810 extern void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
 811 extern void hsw_pc8_disable_interrupts(struct drm_device *dev);
 812 extern void hsw_pc8_restore_interrupts(struct drm_device *dev);
 813 extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
 814 extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 815 extern void intel_dp_get_m_n(struct intel_crtc *crtc,
 816                              struct intel_crtc_config *pipe_config);
 817 extern int intel_dotclock_calculate(int link_freq,
 818                                     const struct intel_link_m_n *m_n);
 819 extern void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 820                                             int dotclock);
 821
 822 extern bool intel_crtc_active(struct drm_crtc *crtc);
 823
 824 #endif /* __INTEL_DRV_H__ */