drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000*x)
  69 #define MHz(x) KHz(1000*x)
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80 #define INTELFB_CONN_LIMIT 4
  81
  82 #define INTEL_I2C_BUS_DVO 1
  83 #define INTEL_I2C_BUS_SDVO 2
  84
  85 /* these are outputs from the chip - integrated only
  86    external chips are via DVO or SDVO output */
  87 #define INTEL_OUTPUT_UNUSED 0
  88 #define INTEL_OUTPUT_ANALOG 1
  89 #define INTEL_OUTPUT_DVO 2
  90 #define INTEL_OUTPUT_SDVO 3
  91 #define INTEL_OUTPUT_LVDS 4
  92 #define INTEL_OUTPUT_TVOUT 5
  93 #define INTEL_OUTPUT_HDMI 6
  94 #define INTEL_OUTPUT_DISPLAYPORT 7
  95 #define INTEL_OUTPUT_EDP 8
  96 #define INTEL_OUTPUT_DSI 9
  97 #define INTEL_OUTPUT_UNKNOWN 10
  98
  99 #define INTEL_DVO_CHIP_NONE 0
 100 #define INTEL_DVO_CHIP_LVDS 1
 101 #define INTEL_DVO_CHIP_TMDS 2
 102 #define INTEL_DVO_CHIP_TVOUT 4
 103
 104 #define INTEL_DSI_COMMAND_MODE  0
 105 #define INTEL_DSI_VIDEO_MODE    1
 106
 107 struct intel_framebuffer {
 108         struct drm_framebuffer base;
 109         struct drm_i915_gem_object *obj;
 110 };
 111
 112 struct intel_fbdev {
 113         struct drm_fb_helper helper;
 114         struct intel_framebuffer ifb;
 115         struct list_head fbdev_list;
 116         struct drm_display_mode *our_mode;
 117 };
 118
 119 struct intel_encoder {
 120         struct drm_encoder base;
 121         /*
 122          * The new crtc this encoder will be driven from. Only differs from
 123          * base->crtc while a modeset is in progress.
 124          */
 125         struct intel_crtc *new_crtc;
 126
 127         int type;
 128         /*
 129          * Intel hw has only one MUX where encoders could be clone, hence a
 130          * simple flag is enough to compute the possible_clones mask.
 131          */
 132         bool cloneable;
 133         bool connectors_active;
 134         void (*hot_plug)(struct intel_encoder *);
 135         bool (*compute_config)(struct intel_encoder *,
 136                                struct intel_crtc_config *);
 137         void (*pre_pll_enable)(struct intel_encoder *);
 138         void (*pre_enable)(struct intel_encoder *);
 139         void (*enable)(struct intel_encoder *);
 140         void (*mode_set)(struct intel_encoder *intel_encoder);
 141         void (*disable)(struct intel_encoder *);
 142         void (*post_disable)(struct intel_encoder *);
 143         /* Read out the current hw state of this connector, returning true if
 144          * the encoder is active. If the encoder is enabled it also set the pipe
 145          * it is connected to in the pipe parameter. */
 146         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 147         /* Reconstructs the equivalent mode flags for the current hardware
 148          * state. This must be called _after_ display->get_pipe_config has
 149          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 150          * be set correctly before calling this function. */
 151         void (*get_config)(struct intel_encoder *,
 152                            struct intel_crtc_config *pipe_config);
 153         int crtc_mask;
 154         enum hpd_pin hpd_pin;
 155 };
 156
 157 struct intel_panel {
 158         struct drm_display_mode *fixed_mode;
 159         int fitting_mode;
 160 };
 161
 162 struct intel_connector {
 163         struct drm_connector base;
 164         /*
 165          * The fixed encoder this connector is connected to.
 166          */
 167         struct intel_encoder *encoder;
 168
 169         /*
 170          * The new encoder this connector will be driven. Only differs from
 171          * encoder while a modeset is in progress.
 172          */
 173         struct intel_encoder *new_encoder;
 174
 175         /* Reads out the current hw, returning true if the connector is enabled
 176          * and active (i.e. dpms ON state). */
 177         bool (*get_hw_state)(struct intel_connector *);
 178
 179         /* Panel info for eDP and LVDS */
 180         struct intel_panel panel;
 181
 182         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 183         struct edid *edid;
 184
 185         /* since POLL and HPD connectors may use the same HPD line keep the native
 186            state of connector->polled in case hotplug storm detection changes it */
 187         u8 polled;
 188 };
 189
 190 typedef struct dpll {
 191         /* given values */
 192         int n;
 193         int m1, m2;
 194         int p1, p2;
 195         /* derived values */
 196         int     dot;
 197         int     vco;
 198         int     m;
 199         int     p;
 200 } intel_clock_t;
 201
 202 struct intel_crtc_config {
 203         /**
 204          * quirks - bitfield with hw state readout quirks
 205          *
 206          * For various reasons the hw state readout code might not be able to
 207          * completely faithfully read out the current state. These cases are
 208          * tracked with quirk flags so that fastboot and state checker can act
 209          * accordingly.
 210          */
 211 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
 212         unsigned long quirks;
 213
 214         struct drm_display_mode requested_mode;
 215         /* Actual pipe timings ie. what we program into the pipe timing
 216          * registers. adjusted_mode.clock is the pipe pixel clock. */
 217         struct drm_display_mode adjusted_mode;
 218         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 219          * between pch encoders and cpu encoders. */
 220         bool has_pch_encoder;
 221
 222         /* CPU Transcoder for the pipe. Currently this can only differ from the
 223          * pipe on Haswell (where we have a special eDP transcoder). */
 224         enum transcoder cpu_transcoder;
 225
 226         /*
 227          * Use reduced/limited/broadcast rbg range, compressing from the full
 228          * range fed into the crtcs.
 229          */
 230         bool limited_color_range;
 231
 232         /* DP has a bunch of special case unfortunately, so mark the pipe
 233          * accordingly. */
 234         bool has_dp_encoder;
 235
 236         /*
 237          * Enable dithering, used when the selected pipe bpp doesn't match the
 238          * plane bpp.
 239          */
 240         bool dither;
 241
 242         /* Controls for the clock computation, to override various stages. */
 243         bool clock_set;
 244
 245         /* SDVO TV has a bunch of special case. To make multifunction encoders
 246          * work correctly, we need to track this at runtime.*/
 247         bool sdvo_tv_clock;
 248
 249         /*
 250          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 251          * required. This is set in the 2nd loop of calling encoder's
 252          * ->compute_config if the first pick doesn't work out.
 253          */
 254         bool bw_constrained;
 255
 256         /* Settings for the intel dpll used on pretty much everything but
 257          * haswell. */
 258         struct dpll dpll;
 259
 260         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 261         enum intel_dpll_id shared_dpll;
 262
 263         /* Actual register state of the dpll, for shared dpll cross-checking. */
 264         struct intel_dpll_hw_state dpll_hw_state;
 265
 266         int pipe_bpp;
 267         struct intel_link_m_n dp_m_n;
 268
 269         /*
 270          * Frequence the dpll for the port should run at. Differs from the
 271          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 272          * already multiplied by pixel_multiplier.
 273          */
 274         int port_clock;
 275
 276         /* Used by SDVO (and if we ever fix it, HDMI). */
 277         unsigned pixel_multiplier;
 278
 279         /* Panel fitter controls for gen2-gen4 + VLV */
 280         struct {
 281                 u32 control;
 282                 u32 pgm_ratios;
 283                 u32 lvds_border_bits;
 284         } gmch_pfit;
 285
 286         /* Panel fitter placement and size for Ironlake+ */
 287         struct {
 288                 u32 pos;
 289                 u32 size;
 290         } pch_pfit;
 291
 292         /* FDI configuration, only valid if has_pch_encoder is set. */
 293         int fdi_lanes;
 294         struct intel_link_m_n fdi_m_n;
 295
 296         bool ips_enabled;
 297 };
 298
 299 struct intel_crtc {
 300         struct drm_crtc base;
 301         enum pipe pipe;
 302         enum plane plane;
 303         u8 lut_r[256], lut_g[256], lut_b[256];
 304         /*
 305          * Whether the crtc and the connected output pipeline is active. Implies
 306          * that crtc->enabled is set, i.e. the current mode configuration has
 307          * some outputs connected to this crtc.
 308          */
 309         bool active;
 310         bool eld_vld;
 311         bool primary_disabled; /* is the crtc obscured by a plane? */
 312         bool lowfreq_avail;
 313         struct intel_overlay *overlay;
 314         struct intel_unpin_work *unpin_work;
 315
 316         atomic_t unpin_work_count;
 317
 318         /* Display surface base address adjustement for pageflips. Note that on
 319          * gen4+ this only adjusts up to a tile, offsets within a tile are
 320          * handled in the hw itself (with the TILEOFF register). */
 321         unsigned long dspaddr_offset;
 322
 323         struct drm_i915_gem_object *cursor_bo;
 324         uint32_t cursor_addr;
 325         int16_t cursor_x, cursor_y;
 326         int16_t cursor_width, cursor_height;
 327         bool cursor_visible;
 328
 329         struct intel_crtc_config config;
 330
 331         uint32_t ddi_pll_sel;
 332
 333         /* reset counter value when the last flip was submitted */
 334         unsigned int reset_counter;
 335
 336         /* Access to these should be protected by dev_priv->irq_lock. */
 337         bool cpu_fifo_underrun_disabled;
 338         bool pch_fifo_underrun_disabled;
 339 };
 340
 341 struct intel_plane_wm_parameters {
 342         uint32_t horiz_pixels;
 343         uint8_t bytes_per_pixel;
 344         bool enabled;
 345         bool scaled;
 346 };
 347
 348 struct intel_plane {
 349         struct drm_plane base;
 350         int plane;
 351         enum pipe pipe;
 352         struct drm_i915_gem_object *obj;
 353         bool can_scale;
 354         int max_downscale;
 355         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 356         int crtc_x, crtc_y;
 357         unsigned int crtc_w, crtc_h;
 358         uint32_t src_x, src_y;
 359         uint32_t src_w, src_h;
 360
 361         /* Since we need to change the watermarks before/after
 362          * enabling/disabling the planes, we need to store the parameters here
 363          * as the other pieces of the struct may not reflect the values we want
 364          * for the watermark calculations. Currently only Haswell uses this.
 365          */
 366         struct intel_plane_wm_parameters wm;
 367
 368         void (*update_plane)(struct drm_plane *plane,
 369                              struct drm_crtc *crtc,
 370                              struct drm_framebuffer *fb,
 371                              struct drm_i915_gem_object *obj,
 372                              int crtc_x, int crtc_y,
 373                              unsigned int crtc_w, unsigned int crtc_h,
 374                              uint32_t x, uint32_t y,
 375                              uint32_t src_w, uint32_t src_h);
 376         void (*disable_plane)(struct drm_plane *plane,
 377                               struct drm_crtc *crtc);
 378         int (*update_colorkey)(struct drm_plane *plane,
 379                                struct drm_intel_sprite_colorkey *key);
 380         void (*get_colorkey)(struct drm_plane *plane,
 381                              struct drm_intel_sprite_colorkey *key);
 382 };
 383
 384 struct intel_watermark_params {
 385         unsigned long fifo_size;
 386         unsigned long max_wm;
 387         unsigned long default_wm;
 388         unsigned long guard_size;
 389         unsigned long cacheline_size;
 390 };
 391
 392 struct cxsr_latency {
 393         int is_desktop;
 394         int is_ddr3;
 395         unsigned long fsb_freq;
 396         unsigned long mem_freq;
 397         unsigned long display_sr;
 398         unsigned long display_hpll_disable;
 399         unsigned long cursor_sr;
 400         unsigned long cursor_hpll_disable;
 401 };
 402
 403 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 404 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 405 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 406 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 407 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 408
 409 struct intel_hdmi {
 410         u32 hdmi_reg;
 411         int ddc_bus;
 412         uint32_t color_range;
 413         bool color_range_auto;
 414         bool has_hdmi_sink;
 415         bool has_audio;
 416         enum hdmi_force_audio force_audio;
 417         bool rgb_quant_range_selectable;
 418         void (*write_infoframe)(struct drm_encoder *encoder,
 419                                 enum hdmi_infoframe_type type,
 420                                 const uint8_t *frame, ssize_t len);
 421         void (*set_infoframes)(struct drm_encoder *encoder,
 422                                struct drm_display_mode *adjusted_mode);
 423 };
 424
 425 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 426 #define DP_LINK_CONFIGURATION_SIZE      9
 427
 428 struct intel_dp {
 429         uint32_t output_reg;
 430         uint32_t aux_ch_ctl_reg;
 431         uint32_t DP;
 432         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
 433         bool has_audio;
 434         enum hdmi_force_audio force_audio;
 435         uint32_t color_range;
 436         bool color_range_auto;
 437         uint8_t link_bw;
 438         uint8_t lane_count;
 439         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 440         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 441         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 442         struct i2c_adapter adapter;
 443         struct i2c_algo_dp_aux_data algo;
 444         uint8_t train_set[4];
 445         int panel_power_up_delay;
 446         int panel_power_down_delay;
 447         int panel_power_cycle_delay;
 448         int backlight_on_delay;
 449         int backlight_off_delay;
 450         struct delayed_work panel_vdd_work;
 451         bool want_panel_vdd;
 452         bool psr_setup_done;
 453         struct intel_connector *attached_connector;
 454 };
 455
 456 struct intel_digital_port {
 457         struct intel_encoder base;
 458         enum port port;
 459         u32 saved_port_bits;
 460         struct intel_dp dp;
 461         struct intel_hdmi hdmi;
 462 };
 463
 464 static inline int
 465 vlv_dport_to_channel(struct intel_digital_port *dport)
 466 {
 467         switch (dport->port) {
 468         case PORT_B:
 469                 return 0;
 470         case PORT_C:
 471                 return 1;
 472         default:
 473                 BUG();
 474         }
 475 }
 476
 477 static inline struct drm_crtc *
 478 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 479 {
 480         struct drm_i915_private *dev_priv = dev->dev_private;
 481         return dev_priv->pipe_to_crtc_mapping[pipe];
 482 }
 483
 484 static inline struct drm_crtc *
 485 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 486 {
 487         struct drm_i915_private *dev_priv = dev->dev_private;
 488         return dev_priv->plane_to_crtc_mapping[plane];
 489 }
 490
 491 struct intel_unpin_work {
 492         struct work_struct work;
 493         struct drm_crtc *crtc;
 494         struct drm_i915_gem_object *old_fb_obj;
 495         struct drm_i915_gem_object *pending_flip_obj;
 496         struct drm_pending_vblank_event *event;
 497         atomic_t pending;
 498 #define INTEL_FLIP_INACTIVE     0
 499 #define INTEL_FLIP_PENDING      1
 500 #define INTEL_FLIP_COMPLETE     2
 501         bool enable_stall_check;
 502 };
 503
 504 int intel_pch_rawclk(struct drm_device *dev);
 505
 506 int intel_connector_update_modes(struct drm_connector *connector,
 507                                 struct edid *edid);
 508 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 509
 510 extern void intel_attach_force_audio_property(struct drm_connector *connector);
 511 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 512
 513 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
 514 extern void intel_crt_init(struct drm_device *dev);
 515 extern void intel_hdmi_init(struct drm_device *dev,
 516                             int hdmi_reg, enum port port);
 517 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 518                                       struct intel_connector *intel_connector);
 519 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 520 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 521                                       struct intel_crtc_config *pipe_config);
 522 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
 523                             bool is_sdvob);
 524 extern void intel_dvo_init(struct drm_device *dev);
 525 extern void intel_tv_init(struct drm_device *dev);
 526 extern void intel_mark_busy(struct drm_device *dev);
 527 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 528                                struct intel_ring_buffer *ring);
 529 extern void intel_mark_idle(struct drm_device *dev);
 530 extern void intel_lvds_init(struct drm_device *dev);
 531 extern bool intel_dsi_init(struct drm_device *dev);
 532 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
 533 extern void intel_dp_init(struct drm_device *dev, int output_reg,
 534                           enum port port);
 535 extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 536                                     struct intel_connector *intel_connector);
 537 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
 538 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
 539 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 540 extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 541 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 542 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 543 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
 544 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
 545                                     struct intel_crtc_config *pipe_config);
 546 extern bool intel_dpd_is_edp(struct drm_device *dev);
 547 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
 548 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
 549 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
 550 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
 551 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 552 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 553 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 554 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
 555                                       enum plane plane);
 556
 557 /* intel_panel.c */
 558 extern int intel_panel_init(struct intel_panel *panel,
 559                             struct drm_display_mode *fixed_mode);
 560 extern void intel_panel_fini(struct intel_panel *panel);
 561
 562 extern void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
 563                                    struct drm_display_mode *adjusted_mode);
 564 extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
 565                                     struct intel_crtc_config *pipe_config,
 566                                     int fitting_mode);
 567 extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 568                                      struct intel_crtc_config *pipe_config,
 569                                      int fitting_mode);
 570 extern void intel_panel_set_backlight(struct drm_device *dev,
 571                                       u32 level, u32 max);
 572 extern int intel_panel_setup_backlight(struct drm_connector *connector);
 573 extern void intel_panel_enable_backlight(struct drm_device *dev,
 574                                          enum pipe pipe);
 575 extern void intel_panel_disable_backlight(struct drm_device *dev);
 576 extern void intel_panel_destroy_backlight(struct drm_device *dev);
 577 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 578
 579 struct intel_set_config {
 580         struct drm_encoder **save_connector_encoders;
 581         struct drm_crtc **save_encoder_crtcs;
 582
 583         bool fb_changed;
 584         bool mode_changed;
 585 };
 586
 587 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
 588 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
 589 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
 590 extern void intel_encoder_destroy(struct drm_encoder *encoder);
 591 extern void intel_connector_dpms(struct drm_connector *, int mode);
 592 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
 593 extern void intel_modeset_check_state(struct drm_device *dev);
 594 extern void intel_plane_restore(struct drm_plane *plane);
 595 extern void intel_plane_disable(struct drm_plane *plane);
 596
 597
 598 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
 599 {
 600         return to_intel_connector(connector)->encoder;
 601 }
 602
 603 static inline struct intel_digital_port *
 604 enc_to_dig_port(struct drm_encoder *encoder)
 605 {
 606         return container_of(encoder, struct intel_digital_port, base.base);
 607 }
 608
 609 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 610 {
 611         return &enc_to_dig_port(encoder)->dp;
 612 }
 613
 614 static inline struct intel_digital_port *
 615 dp_to_dig_port(struct intel_dp *intel_dp)
 616 {
 617         return container_of(intel_dp, struct intel_digital_port, dp);
 618 }
 619
 620 static inline struct intel_digital_port *
 621 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 622 {
 623         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 624 }
 625
 626 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 627                                 struct intel_digital_port *port);
 628
 629 extern void intel_connector_attach_encoder(struct intel_connector *connector,
 630                                            struct intel_encoder *encoder);
 631 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 632
 633 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 634                                                     struct drm_crtc *crtc);
 635 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 636                                 struct drm_file *file_priv);
 637 extern enum transcoder
 638 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 639                              enum pipe pipe);
 640 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 641 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 642 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 643 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
 644
 645 struct intel_load_detect_pipe {
 646         struct drm_framebuffer *release_fb;
 647         bool load_detect_temp;
 648         int dpms_mode;
 649 };
 650 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
 651                                        struct drm_display_mode *mode,
 652                                        struct intel_load_detect_pipe *old);
 653 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
 654                                            struct intel_load_detect_pipe *old);
 655
 656 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 657                                     u16 blue, int regno);
 658 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 659                                     u16 *blue, int regno);
 660
 661 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 662                                       struct drm_i915_gem_object *obj,
 663                                       struct intel_ring_buffer *pipelined);
 664 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 665
 666 extern int intel_framebuffer_init(struct drm_device *dev,
 667                                   struct intel_framebuffer *ifb,
 668                                   struct drm_mode_fb_cmd2 *mode_cmd,
 669                                   struct drm_i915_gem_object *obj);
 670 extern void intel_framebuffer_fini(struct intel_framebuffer *fb);
 671 extern int intel_fbdev_init(struct drm_device *dev);
 672 extern void intel_fbdev_initial_config(struct drm_device *dev);
 673 extern void intel_fbdev_fini(struct drm_device *dev);
 674 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 675 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
 676 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
 677 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 678
 679 extern void intel_setup_overlay(struct drm_device *dev);
 680 extern void intel_cleanup_overlay(struct drm_device *dev);
 681 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
 682 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
 683                                    struct drm_file *file_priv);
 684 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
 685                                struct drm_file *file_priv);
 686
 687 extern void intel_fb_output_poll_changed(struct drm_device *dev);
 688 extern void intel_fb_restore_mode(struct drm_device *dev);
 689
 690 struct intel_shared_dpll *
 691 intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 692
 693 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 694                         struct intel_shared_dpll *pll,
 695                         bool state);
 696 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 697 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 698 void assert_pll(struct drm_i915_private *dev_priv,
 699                 enum pipe pipe, bool state);
 700 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 701 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 702 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 703                        enum pipe pipe, bool state);
 704 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 705 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 706 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 707                         bool state);
 708 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 709 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 710
 711 extern void intel_init_clock_gating(struct drm_device *dev);
 712 extern void intel_suspend_hw(struct drm_device *dev);
 713 extern void intel_write_eld(struct drm_encoder *encoder,
 714                             struct drm_display_mode *mode);
 715 extern void intel_prepare_ddi(struct drm_device *dev);
 716 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
 717 extern void intel_ddi_init(struct drm_device *dev, enum port port);
 718 extern enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 719
 720 /* For use by IVB LP watermark workaround in intel_sprite.c */
 721 extern void intel_update_watermarks(struct drm_crtc *crtc);
 722 extern void intel_update_sprite_watermarks(struct drm_plane *plane,
 723                                            struct drm_crtc *crtc,
 724                                            uint32_t sprite_width, int pixel_size,
 725                                            bool enabled, bool scaled);
 726
 727 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 728                                                     unsigned int tiling_mode,
 729                                                     unsigned int bpp,
 730                                                     unsigned int pitch);
 731
 732 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 733                                      struct drm_file *file_priv);
 734 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 735                                      struct drm_file *file_priv);
 736
 737 /* Power-related functions, located in intel_pm.c */
 738 extern void intel_init_pm(struct drm_device *dev);
 739 /* FBC */
 740 extern bool intel_fbc_enabled(struct drm_device *dev);
 741 extern void intel_update_fbc(struct drm_device *dev);
 742 /* IPS */
 743 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 744 extern void intel_gpu_ips_teardown(void);
 745
 746 /* Power well */
 747 extern int i915_init_power_well(struct drm_device *dev);
 748 extern void i915_remove_power_well(struct drm_device *dev);
 749
 750 extern bool intel_display_power_enabled(struct drm_device *dev,
 751                                         enum intel_display_power_domain domain);
 752 extern void intel_init_power_well(struct drm_device *dev);
 753 extern void intel_set_power_well(struct drm_device *dev, bool enable);
 754 extern void intel_enable_gt_powersave(struct drm_device *dev);
 755 extern void intel_disable_gt_powersave(struct drm_device *dev);
 756 extern void ironlake_teardown_rc6(struct drm_device *dev);
 757 void gen6_update_ring_freq(struct drm_device *dev);
 758
 759 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 760                                    enum pipe *pipe);
 761 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 762 extern void intel_ddi_pll_init(struct drm_device *dev);
 763 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 764 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 765                                               enum transcoder cpu_transcoder);
 766 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 767 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 768 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 769 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
 770 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 771 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 772 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 773 extern bool
 774 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 775 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 776
 777 extern void intel_display_handle_reset(struct drm_device *dev);
 778 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 779                                                   enum pipe pipe,
 780                                                   bool enable);
 781 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 782                                                  enum transcoder pch_transcoder,
 783                                                  bool enable);
 784
 785 extern void intel_edp_psr_enable(struct intel_dp *intel_dp);
 786 extern void intel_edp_psr_disable(struct intel_dp *intel_dp);
 787 extern void intel_edp_psr_update(struct drm_device *dev);
 788 extern void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
 789                               bool switch_to_fclk, bool allow_power_down);
 790 extern void hsw_restore_lcpll(struct drm_i915_private *dev_priv);
 791 extern void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 792 extern void ilk_disable_gt_irq(struct drm_i915_private *dev_priv,
 793                                uint32_t mask);
 794 extern void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 795 extern void snb_disable_pm_irq(struct drm_i915_private *dev_priv,
 796                                uint32_t mask);
 797 extern void hsw_enable_pc8_work(struct work_struct *__work);
 798 extern void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
 799 extern void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
 800 extern void hsw_pc8_disable_interrupts(struct drm_device *dev);
 801 extern void hsw_pc8_restore_interrupts(struct drm_device *dev);
 802 extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
 803 extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 804 extern void intel_dp_get_m_n(struct intel_crtc *crtc,
 805                              struct intel_crtc_config *pipe_config);
 806 extern int intel_dotclock_calculate(int link_freq,
 807                                     const struct intel_link_m_n *m_n);
 808
 809 #endif /* __INTEL_DRV_H__ */