drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38
  39 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  40 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  41
  42 /**
  43  * _wait_for - magic (register) wait macro
  44  *
  45  * Does the right thing for modeset paths when run under kdgb or similar atomic
  46  * contexts. Note that it's important that we check the condition again after
  47  * having timed out, since the timeout could be due to preemption or similar and
  48  * we've never had a chance to check the condition before the timeout.
  49  */
  50 #define _wait_for(COND, MS, W) ({ \
  51         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  52         int ret__ = 0;                                                  \
  53         while (!(COND)) {                                               \
  54                 if (time_after(jiffies, timeout__)) {                   \
  55                         if (!(COND))                                    \
  56                                 ret__ = -ETIMEDOUT;                     \
  57                         break;                                          \
  58                 }                                                       \
  59                 if ((W) && drm_can_sleep()) {                           \
  60                         usleep_range((W)*1000, (W)*2000);               \
  61                 } else {                                                \
  62                         cpu_relax();                                    \
  63                 }                                                       \
  64         }                                                               \
  65         ret__;                                                          \
  66 })
  67
  68 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  69 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  70 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  71                                                DIV_ROUND_UP((US), 1000), 0)
  72
  73 #define KHz(x) (1000 * (x))
  74 #define MHz(x) KHz(1000 * (x))
  75
  76 /*
  77  * Display related stuff
  78  */
  79
  80 /* store information about an Ixxx DVO */
  81 /* The i830->i865 use multiple DVOs with multiple i2cs */
  82 /* the i915, i945 have a single sDVO i2c bus - which is different */
  83 #define MAX_OUTPUTS 6
  84 /* maximum connectors per crtcs in the mode set */
  85
  86 /* Maximum cursor sizes */
  87 #define GEN2_CURSOR_WIDTH 64
  88 #define GEN2_CURSOR_HEIGHT 64
  89 #define MAX_CURSOR_WIDTH 256
  90 #define MAX_CURSOR_HEIGHT 256
  91
  92 #define INTEL_I2C_BUS_DVO 1
  93 #define INTEL_I2C_BUS_SDVO 2
  94
  95 /* these are outputs from the chip - integrated only
  96    external chips are via DVO or SDVO output */
  97 enum intel_output_type {
  98         INTEL_OUTPUT_UNUSED = 0,
  99         INTEL_OUTPUT_ANALOG = 1,
 100         INTEL_OUTPUT_DVO = 2,
 101         INTEL_OUTPUT_SDVO = 3,
 102         INTEL_OUTPUT_LVDS = 4,
 103         INTEL_OUTPUT_TVOUT = 5,
 104         INTEL_OUTPUT_HDMI = 6,
 105         INTEL_OUTPUT_DISPLAYPORT = 7,
 106         INTEL_OUTPUT_EDP = 8,
 107         INTEL_OUTPUT_DSI = 9,
 108         INTEL_OUTPUT_UNKNOWN = 10,
 109         INTEL_OUTPUT_DP_MST = 11,
 110 };
 111
 112 #define INTEL_DVO_CHIP_NONE 0
 113 #define INTEL_DVO_CHIP_LVDS 1
 114 #define INTEL_DVO_CHIP_TMDS 2
 115 #define INTEL_DVO_CHIP_TVOUT 4
 116
 117 #define INTEL_DSI_VIDEO_MODE    0
 118 #define INTEL_DSI_COMMAND_MODE  1
 119
 120 struct intel_framebuffer {
 121         struct drm_framebuffer base;
 122         struct drm_i915_gem_object *obj;
 123 };
 124
 125 struct intel_fbdev {
 126         struct drm_fb_helper helper;
 127         struct intel_framebuffer *fb;
 128         struct list_head fbdev_list;
 129         struct drm_display_mode *our_mode;
 130         int preferred_bpp;
 131 };
 132
 133 struct intel_encoder {
 134         struct drm_encoder base;
 135         /*
 136          * The new crtc this encoder will be driven from. Only differs from
 137          * base->crtc while a modeset is in progress.
 138          */
 139         struct intel_crtc *new_crtc;
 140
 141         enum intel_output_type type;
 142         unsigned int cloneable;
 143         bool connectors_active;
 144         void (*hot_plug)(struct intel_encoder *);
 145         bool (*compute_config)(struct intel_encoder *,
 146                                struct intel_crtc_state *);
 147         void (*pre_pll_enable)(struct intel_encoder *);
 148         void (*pre_enable)(struct intel_encoder *);
 149         void (*enable)(struct intel_encoder *);
 150         void (*mode_set)(struct intel_encoder *intel_encoder);
 151         void (*disable)(struct intel_encoder *);
 152         void (*post_disable)(struct intel_encoder *);
 153         /* Read out the current hw state of this connector, returning true if
 154          * the encoder is active. If the encoder is enabled it also set the pipe
 155          * it is connected to in the pipe parameter. */
 156         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 157         /* Reconstructs the equivalent mode flags for the current hardware
 158          * state. This must be called _after_ display->get_pipe_config has
 159          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 160          * be set correctly before calling this function. */
 161         void (*get_config)(struct intel_encoder *,
 162                            struct intel_crtc_state *pipe_config);
 163         /*
 164          * Called during system suspend after all pending requests for the
 165          * encoder are flushed (for example for DP AUX transactions) and
 166          * device interrupts are disabled.
 167          */
 168         void (*suspend)(struct intel_encoder *);
 169         int crtc_mask;
 170         enum hpd_pin hpd_pin;
 171 };
 172
 173 struct intel_panel {
 174         struct drm_display_mode *fixed_mode;
 175         struct drm_display_mode *downclock_mode;
 176         int fitting_mode;
 177
 178         /* backlight */
 179         struct {
 180                 bool present;
 181                 u32 level;
 182                 u32 min;
 183                 u32 max;
 184                 bool enabled;
 185                 bool combination_mode;  /* gen 2/4 only */
 186                 bool active_low_pwm;
 187                 struct backlight_device *device;
 188         } backlight;
 189
 190         void (*backlight_power)(struct intel_connector *, bool enable);
 191 };
 192
 193 struct intel_connector {
 194         struct drm_connector base;
 195         /*
 196          * The fixed encoder this connector is connected to.
 197          */
 198         struct intel_encoder *encoder;
 199
 200         /*
 201          * The new encoder this connector will be driven. Only differs from
 202          * encoder while a modeset is in progress.
 203          */
 204         struct intel_encoder *new_encoder;
 205
 206         /* Reads out the current hw, returning true if the connector is enabled
 207          * and active (i.e. dpms ON state). */
 208         bool (*get_hw_state)(struct intel_connector *);
 209
 210         /*
 211          * Removes all interfaces through which the connector is accessible
 212          * - like sysfs, debugfs entries -, so that no new operations can be
 213          * started on the connector. Also makes sure all currently pending
 214          * operations finish before returing.
 215          */
 216         void (*unregister)(struct intel_connector *);
 217
 218         /* Panel info for eDP and LVDS */
 219         struct intel_panel panel;
 220
 221         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 222         struct edid *edid;
 223         struct edid *detect_edid;
 224
 225         /* since POLL and HPD connectors may use the same HPD line keep the native
 226            state of connector->polled in case hotplug storm detection changes it */
 227         u8 polled;
 228
 229         void *port; /* store this opaque as its illegal to dereference it */
 230
 231         struct intel_dp *mst_port;
 232 };
 233
 234 typedef struct dpll {
 235         /* given values */
 236         int n;
 237         int m1, m2;
 238         int p1, p2;
 239         /* derived values */
 240         int     dot;
 241         int     vco;
 242         int     m;
 243         int     p;
 244 } intel_clock_t;
 245
 246 struct intel_plane_state {
 247         struct drm_plane_state base;
 248         struct drm_rect src;
 249         struct drm_rect dst;
 250         struct drm_rect clip;
 251         bool visible;
 252
 253         /*
 254          * used only for sprite planes to determine when to implicitly
 255          * enable/disable the primary plane
 256          */
 257         bool hides_primary;
 258 };
 259
 260 struct intel_initial_plane_config {
 261         struct intel_framebuffer *fb;
 262         unsigned int tiling;
 263         int size;
 264         u32 base;
 265 };
 266
 267 struct intel_crtc_state {
 268         struct drm_crtc_state base;
 269
 270         /**
 271          * quirks - bitfield with hw state readout quirks
 272          *
 273          * For various reasons the hw state readout code might not be able to
 274          * completely faithfully read out the current state. These cases are
 275          * tracked with quirk flags so that fastboot and state checker can act
 276          * accordingly.
 277          */
 278 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 279 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 280         unsigned long quirks;
 281
 282         /* Pipe source size (ie. panel fitter input size)
 283          * All planes will be positioned inside this space,
 284          * and get clipped at the edges. */
 285         int pipe_src_w, pipe_src_h;
 286
 287         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 288          * between pch encoders and cpu encoders. */
 289         bool has_pch_encoder;
 290
 291         /* Are we sending infoframes on the attached port */
 292         bool has_infoframe;
 293
 294         /* CPU Transcoder for the pipe. Currently this can only differ from the
 295          * pipe on Haswell (where we have a special eDP transcoder). */
 296         enum transcoder cpu_transcoder;
 297
 298         /*
 299          * Use reduced/limited/broadcast rbg range, compressing from the full
 300          * range fed into the crtcs.
 301          */
 302         bool limited_color_range;
 303
 304         /* DP has a bunch of special case unfortunately, so mark the pipe
 305          * accordingly. */
 306         bool has_dp_encoder;
 307
 308         /* Whether we should send NULL infoframes. Required for audio. */
 309         bool has_hdmi_sink;
 310
 311         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 312          * has_dp_encoder is set. */
 313         bool has_audio;
 314
 315         /*
 316          * Enable dithering, used when the selected pipe bpp doesn't match the
 317          * plane bpp.
 318          */
 319         bool dither;
 320
 321         /* Controls for the clock computation, to override various stages. */
 322         bool clock_set;
 323
 324         /* SDVO TV has a bunch of special case. To make multifunction encoders
 325          * work correctly, we need to track this at runtime.*/
 326         bool sdvo_tv_clock;
 327
 328         /*
 329          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 330          * required. This is set in the 2nd loop of calling encoder's
 331          * ->compute_config if the first pick doesn't work out.
 332          */
 333         bool bw_constrained;
 334
 335         /* Settings for the intel dpll used on pretty much everything but
 336          * haswell. */
 337         struct dpll dpll;
 338
 339         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 340         enum intel_dpll_id shared_dpll;
 341
 342         /*
 343          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 344          * - enum skl_dpll on SKL
 345          */
 346         uint32_t ddi_pll_sel;
 347
 348         /* Actual register state of the dpll, for shared dpll cross-checking. */
 349         struct intel_dpll_hw_state dpll_hw_state;
 350
 351         int pipe_bpp;
 352         struct intel_link_m_n dp_m_n;
 353
 354         /* m2_n2 for eDP downclock */
 355         struct intel_link_m_n dp_m2_n2;
 356         bool has_drrs;
 357
 358         /*
 359          * Frequence the dpll for the port should run at. Differs from the
 360          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 361          * already multiplied by pixel_multiplier.
 362          */
 363         int port_clock;
 364
 365         /* Used by SDVO (and if we ever fix it, HDMI). */
 366         unsigned pixel_multiplier;
 367
 368         /* Panel fitter controls for gen2-gen4 + VLV */
 369         struct {
 370                 u32 control;
 371                 u32 pgm_ratios;
 372                 u32 lvds_border_bits;
 373         } gmch_pfit;
 374
 375         /* Panel fitter placement and size for Ironlake+ */
 376         struct {
 377                 u32 pos;
 378                 u32 size;
 379                 bool enabled;
 380                 bool force_thru;
 381         } pch_pfit;
 382
 383         /* FDI configuration, only valid if has_pch_encoder is set. */
 384         int fdi_lanes;
 385         struct intel_link_m_n fdi_m_n;
 386
 387         bool ips_enabled;
 388
 389         bool double_wide;
 390
 391         bool dp_encoder_is_mst;
 392         int pbn;
 393 };
 394
 395 struct intel_pipe_wm {
 396         struct intel_wm_level wm[5];
 397         uint32_t linetime;
 398         bool fbc_wm_enabled;
 399         bool pipe_enabled;
 400         bool sprites_enabled;
 401         bool sprites_scaled;
 402 };
 403
 404 struct intel_mmio_flip {
 405         struct drm_i915_gem_request *req;
 406         struct work_struct work;
 407 };
 408
 409 struct skl_pipe_wm {
 410         struct skl_wm_level wm[8];
 411         struct skl_wm_level trans_wm;
 412         uint32_t linetime;
 413 };
 414
 415 /*
 416  * Tracking of operations that need to be performed at the beginning/end of an
 417  * atomic commit, outside the atomic section where interrupts are disabled.
 418  * These are generally operations that grab mutexes or might otherwise sleep
 419  * and thus can't be run with interrupts disabled.
 420  */
 421 struct intel_crtc_atomic_commit {
 422         /* vblank evasion */
 423         bool evade;
 424         unsigned start_vbl_count;
 425
 426         /* Sleepable operations to perform before commit */
 427         bool wait_for_flips;
 428         bool disable_fbc;
 429         bool pre_disable_primary;
 430         bool update_wm;
 431         unsigned disabled_planes;
 432
 433         /* Sleepable operations to perform after commit */
 434         unsigned fb_bits;
 435         bool wait_vblank;
 436         bool update_fbc;
 437         bool post_enable_primary;
 438         unsigned update_sprite_watermarks;
 439 };
 440
 441 struct intel_crtc {
 442         struct drm_crtc base;
 443         enum pipe pipe;
 444         enum plane plane;
 445         u8 lut_r[256], lut_g[256], lut_b[256];
 446         /*
 447          * Whether the crtc and the connected output pipeline is active. Implies
 448          * that crtc->enabled is set, i.e. the current mode configuration has
 449          * some outputs connected to this crtc.
 450          */
 451         bool active;
 452         unsigned long enabled_power_domains;
 453         bool primary_enabled; /* is the primary plane (partially) visible? */
 454         bool lowfreq_avail;
 455         struct intel_overlay *overlay;
 456         struct intel_unpin_work *unpin_work;
 457
 458         atomic_t unpin_work_count;
 459
 460         /* Display surface base address adjustement for pageflips. Note that on
 461          * gen4+ this only adjusts up to a tile, offsets within a tile are
 462          * handled in the hw itself (with the TILEOFF register). */
 463         unsigned long dspaddr_offset;
 464
 465         struct drm_i915_gem_object *cursor_bo;
 466         uint32_t cursor_addr;
 467         uint32_t cursor_cntl;
 468         uint32_t cursor_size;
 469         uint32_t cursor_base;
 470
 471         struct intel_initial_plane_config plane_config;
 472         struct intel_crtc_state *config;
 473         struct intel_crtc_state *new_config;
 474         bool new_enabled;
 475
 476         /* reset counter value when the last flip was submitted */
 477         unsigned int reset_counter;
 478
 479         /* Access to these should be protected by dev_priv->irq_lock. */
 480         bool cpu_fifo_underrun_disabled;
 481         bool pch_fifo_underrun_disabled;
 482
 483         /* per-pipe watermark state */
 484         struct {
 485                 /* watermarks currently being used  */
 486                 struct intel_pipe_wm active;
 487                 /* SKL wm values currently in use */
 488                 struct skl_pipe_wm skl_active;
 489         } wm;
 490
 491         int scanline_offset;
 492         struct intel_mmio_flip mmio_flip;
 493
 494         struct intel_crtc_atomic_commit atomic;
 495 };
 496
 497 struct intel_plane_wm_parameters {
 498         uint32_t horiz_pixels;
 499         uint32_t vert_pixels;
 500         uint8_t bytes_per_pixel;
 501         bool enabled;
 502         bool scaled;
 503         u64 tiling;
 504 };
 505
 506 struct intel_plane {
 507         struct drm_plane base;
 508         int plane;
 509         enum pipe pipe;
 510         bool can_scale;
 511         int max_downscale;
 512
 513         /* FIXME convert to properties */
 514         struct drm_intel_sprite_colorkey ckey;
 515
 516         /* Since we need to change the watermarks before/after
 517          * enabling/disabling the planes, we need to store the parameters here
 518          * as the other pieces of the struct may not reflect the values we want
 519          * for the watermark calculations. Currently only Haswell uses this.
 520          */
 521         struct intel_plane_wm_parameters wm;
 522
 523         /*
 524          * NOTE: Do not place new plane state fields here (e.g., when adding
 525          * new plane properties).  New runtime state should now be placed in
 526          * the intel_plane_state structure and accessed via drm_plane->state.
 527          */
 528
 529         void (*update_plane)(struct drm_plane *plane,
 530                              struct drm_crtc *crtc,
 531                              struct drm_framebuffer *fb,
 532                              int crtc_x, int crtc_y,
 533                              unsigned int crtc_w, unsigned int crtc_h,
 534                              uint32_t x, uint32_t y,
 535                              uint32_t src_w, uint32_t src_h);
 536         void (*disable_plane)(struct drm_plane *plane,
 537                               struct drm_crtc *crtc);
 538         int (*check_plane)(struct drm_plane *plane,
 539                            struct intel_plane_state *state);
 540         void (*commit_plane)(struct drm_plane *plane,
 541                              struct intel_plane_state *state);
 542 };
 543
 544 struct intel_watermark_params {
 545         unsigned long fifo_size;
 546         unsigned long max_wm;
 547         unsigned long default_wm;
 548         unsigned long guard_size;
 549         unsigned long cacheline_size;
 550 };
 551
 552 struct cxsr_latency {
 553         int is_desktop;
 554         int is_ddr3;
 555         unsigned long fsb_freq;
 556         unsigned long mem_freq;
 557         unsigned long display_sr;
 558         unsigned long display_hpll_disable;
 559         unsigned long cursor_sr;
 560         unsigned long cursor_hpll_disable;
 561 };
 562
 563 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 564 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 565 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 566 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 567 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 568 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 569 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 570
 571 struct intel_hdmi {
 572         u32 hdmi_reg;
 573         int ddc_bus;
 574         uint32_t color_range;
 575         bool color_range_auto;
 576         bool has_hdmi_sink;
 577         bool has_audio;
 578         enum hdmi_force_audio force_audio;
 579         bool rgb_quant_range_selectable;
 580         enum hdmi_picture_aspect aspect_ratio;
 581         void (*write_infoframe)(struct drm_encoder *encoder,
 582                                 enum hdmi_infoframe_type type,
 583                                 const void *frame, ssize_t len);
 584         void (*set_infoframes)(struct drm_encoder *encoder,
 585                                bool enable,
 586                                struct drm_display_mode *adjusted_mode);
 587         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 588 };
 589
 590 struct intel_dp_mst_encoder;
 591 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 592
 593 /*
 594  * enum link_m_n_set:
 595  *      When platform provides two set of M_N registers for dp, we can
 596  *      program them and switch between them incase of DRRS.
 597  *      But When only one such register is provided, we have to program the
 598  *      required divider value on that registers itself based on the DRRS state.
 599  *
 600  * M1_N1        : Program dp_m_n on M1_N1 registers
 601  *                        dp_m2_n2 on M2_N2 registers (If supported)
 602  *
 603  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 604  *                        M2_N2 registers are not supported
 605  */
 606
 607 enum link_m_n_set {
 608         /* Sets the m1_n1 and m2_n2 */
 609         M1_N1 = 0,
 610         M2_N2
 611 };
 612
 613 struct intel_dp {
 614         uint32_t output_reg;
 615         uint32_t aux_ch_ctl_reg;
 616         uint32_t DP;
 617         bool has_audio;
 618         enum hdmi_force_audio force_audio;
 619         uint32_t color_range;
 620         bool color_range_auto;
 621         uint8_t link_bw;
 622         uint8_t rate_select;
 623         uint8_t lane_count;
 624         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 625         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 626         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 627         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 628         uint8_t num_sink_rates;
 629         int sink_rates[DP_MAX_SUPPORTED_RATES];
 630         struct drm_dp_aux aux;
 631         uint8_t train_set[4];
 632         int panel_power_up_delay;
 633         int panel_power_down_delay;
 634         int panel_power_cycle_delay;
 635         int backlight_on_delay;
 636         int backlight_off_delay;
 637         struct delayed_work panel_vdd_work;
 638         bool want_panel_vdd;
 639         unsigned long last_power_cycle;
 640         unsigned long last_power_on;
 641         unsigned long last_backlight_off;
 642
 643         struct notifier_block edp_notifier;
 644
 645         /*
 646          * Pipe whose power sequencer is currently locked into
 647          * this port. Only relevant on VLV/CHV.
 648          */
 649         enum pipe pps_pipe;
 650         struct edp_power_seq pps_delays;
 651
 652         bool use_tps3;
 653         bool can_mst; /* this port supports mst */
 654         bool is_mst;
 655         int active_mst_links;
 656         /* connector directly attached - won't be use for modeset in mst world */
 657         struct intel_connector *attached_connector;
 658
 659         /* mst connector list */
 660         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 661         struct drm_dp_mst_topology_mgr mst_mgr;
 662
 663         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 664         /*
 665          * This function returns the value we have to program the AUX_CTL
 666          * register with to kick off an AUX transaction.
 667          */
 668         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 669                                      bool has_aux_irq,
 670                                      int send_bytes,
 671                                      uint32_t aux_clock_divider);
 672 };
 673
 674 struct intel_digital_port {
 675         struct intel_encoder base;
 676         enum port port;
 677         u32 saved_port_bits;
 678         struct intel_dp dp;
 679         struct intel_hdmi hdmi;
 680         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 681 };
 682
 683 struct intel_dp_mst_encoder {
 684         struct intel_encoder base;
 685         enum pipe pipe;
 686         struct intel_digital_port *primary;
 687         void *port; /* store this opaque as its illegal to dereference it */
 688 };
 689
 690 static inline int
 691 vlv_dport_to_channel(struct intel_digital_port *dport)
 692 {
 693         switch (dport->port) {
 694         case PORT_B:
 695         case PORT_D:
 696                 return DPIO_CH0;
 697         case PORT_C:
 698                 return DPIO_CH1;
 699         default:
 700                 BUG();
 701         }
 702 }
 703
 704 static inline int
 705 vlv_pipe_to_channel(enum pipe pipe)
 706 {
 707         switch (pipe) {
 708         case PIPE_A:
 709         case PIPE_C:
 710                 return DPIO_CH0;
 711         case PIPE_B:
 712                 return DPIO_CH1;
 713         default:
 714                 BUG();
 715         }
 716 }
 717
 718 static inline struct drm_crtc *
 719 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 720 {
 721         struct drm_i915_private *dev_priv = dev->dev_private;
 722         return dev_priv->pipe_to_crtc_mapping[pipe];
 723 }
 724
 725 static inline struct drm_crtc *
 726 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 727 {
 728         struct drm_i915_private *dev_priv = dev->dev_private;
 729         return dev_priv->plane_to_crtc_mapping[plane];
 730 }
 731
 732 struct intel_unpin_work {
 733         struct work_struct work;
 734         struct drm_crtc *crtc;
 735         struct drm_framebuffer *old_fb;
 736         struct drm_i915_gem_object *pending_flip_obj;
 737         struct drm_pending_vblank_event *event;
 738         atomic_t pending;
 739 #define INTEL_FLIP_INACTIVE     0
 740 #define INTEL_FLIP_PENDING      1
 741 #define INTEL_FLIP_COMPLETE     2
 742         u32 flip_count;
 743         u32 gtt_offset;
 744         struct drm_i915_gem_request *flip_queued_req;
 745         int flip_queued_vblank;
 746         int flip_ready_vblank;
 747         bool enable_stall_check;
 748 };
 749
 750 struct intel_set_config {
 751         struct drm_encoder **save_connector_encoders;
 752         struct drm_crtc **save_encoder_crtcs;
 753         bool *save_crtc_enabled;
 754
 755         bool fb_changed;
 756         bool mode_changed;
 757 };
 758
 759 struct intel_load_detect_pipe {
 760         struct drm_framebuffer *release_fb;
 761         bool load_detect_temp;
 762         int dpms_mode;
 763 };
 764
 765 static inline struct intel_encoder *
 766 intel_attached_encoder(struct drm_connector *connector)
 767 {
 768         return to_intel_connector(connector)->encoder;
 769 }
 770
 771 static inline struct intel_digital_port *
 772 enc_to_dig_port(struct drm_encoder *encoder)
 773 {
 774         return container_of(encoder, struct intel_digital_port, base.base);
 775 }
 776
 777 static inline struct intel_dp_mst_encoder *
 778 enc_to_mst(struct drm_encoder *encoder)
 779 {
 780         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 781 }
 782
 783 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 784 {
 785         return &enc_to_dig_port(encoder)->dp;
 786 }
 787
 788 static inline struct intel_digital_port *
 789 dp_to_dig_port(struct intel_dp *intel_dp)
 790 {
 791         return container_of(intel_dp, struct intel_digital_port, dp);
 792 }
 793
 794 static inline struct intel_digital_port *
 795 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 796 {
 797         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 798 }
 799
 800 /*
 801  * Returns the number of planes for this pipe, ie the number of sprites + 1
 802  * (primary plane). This doesn't count the cursor plane then.
 803  */
 804 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 805 {
 806         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 807 }
 808
 809 /* intel_fifo_underrun.c */
 810 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 811                                            enum pipe pipe, bool enable);
 812 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 813                                            enum transcoder pch_transcoder,
 814                                            bool enable);
 815 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 816                                          enum pipe pipe);
 817 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 818                                          enum transcoder pch_transcoder);
 819 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 820
 821 /* i915_irq.c */
 822 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 823 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 824 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 825 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 826 void gen6_reset_rps_interrupts(struct drm_device *dev);
 827 void gen6_enable_rps_interrupts(struct drm_device *dev);
 828 void gen6_disable_rps_interrupts(struct drm_device *dev);
 829 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 830 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 831 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 832 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 833 {
 834         /*
 835          * We only use drm_irq_uninstall() at unload and VT switch, so
 836          * this is the only thing we need to check.
 837          */
 838         return dev_priv->pm.irqs_enabled;
 839 }
 840
 841 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 842 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 843                                      unsigned int pipe_mask);
 844
 845 /* intel_crt.c */
 846 void intel_crt_init(struct drm_device *dev);
 847
 848
 849 /* intel_ddi.c */
 850 void intel_prepare_ddi(struct drm_device *dev);
 851 void hsw_fdi_link_train(struct drm_crtc *crtc);
 852 void intel_ddi_init(struct drm_device *dev, enum port port);
 853 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 854 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 855 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 856 void intel_ddi_pll_init(struct drm_device *dev);
 857 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 858 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 859                                        enum transcoder cpu_transcoder);
 860 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 861 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 862 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 863                           struct intel_crtc_state *crtc_state);
 864 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 865 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 866 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 867 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 868 void intel_ddi_get_config(struct intel_encoder *encoder,
 869                           struct intel_crtc_state *pipe_config);
 870
 871 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 872 void intel_ddi_clock_get(struct intel_encoder *encoder,
 873                          struct intel_crtc_state *pipe_config);
 874 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 875
 876 /* intel_frontbuffer.c */
 877 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 878                              struct intel_engine_cs *ring,
 879                              enum fb_op_origin origin);
 880 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 881                                     unsigned frontbuffer_bits);
 882 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 883                                      unsigned frontbuffer_bits);
 884 void intel_frontbuffer_flush(struct drm_device *dev,
 885                              unsigned frontbuffer_bits);
 886 /**
 887  * intel_frontbuffer_flip - synchronous frontbuffer flip
 888  * @dev: DRM device
 889  * @frontbuffer_bits: frontbuffer plane tracking bits
 890  *
 891  * This function gets called after scheduling a flip on @obj. This is for
 892  * synchronous plane updates which will happen on the next vblank and which will
 893  * not get delayed by pending gpu rendering.
 894  *
 895  * Can be called without any locks held.
 896  */
 897 static inline
 898 void intel_frontbuffer_flip(struct drm_device *dev,
 899                             unsigned frontbuffer_bits)
 900 {
 901         intel_frontbuffer_flush(dev, frontbuffer_bits);
 902 }
 903
 904 unsigned int intel_fb_align_height(struct drm_device *dev,
 905                                    unsigned int height,
 906                                    uint32_t pixel_format,
 907                                    uint64_t fb_format_modifier);
 908 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 909
 910 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
 911                               uint32_t pixel_format);
 912
 913 /* intel_audio.c */
 914 void intel_init_audio(struct drm_device *dev);
 915 void intel_audio_codec_enable(struct intel_encoder *encoder);
 916 void intel_audio_codec_disable(struct intel_encoder *encoder);
 917 void i915_audio_component_init(struct drm_i915_private *dev_priv);
 918 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
 919
 920 /* intel_display.c */
 921 extern const struct drm_plane_funcs intel_plane_funcs;
 922 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 923 int intel_pch_rawclk(struct drm_device *dev);
 924 void intel_mark_busy(struct drm_device *dev);
 925 void intel_mark_idle(struct drm_device *dev);
 926 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 927 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
 928 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 929 void intel_encoder_destroy(struct drm_encoder *encoder);
 930 void intel_connector_dpms(struct drm_connector *, int mode);
 931 bool intel_connector_get_hw_state(struct intel_connector *connector);
 932 void intel_modeset_check_state(struct drm_device *dev);
 933 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 934                                 struct intel_digital_port *port);
 935 void intel_connector_attach_encoder(struct intel_connector *connector,
 936                                     struct intel_encoder *encoder);
 937 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 938 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 939                                              struct drm_crtc *crtc);
 940 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 941 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 942                                 struct drm_file *file_priv);
 943 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 944                                              enum pipe pipe);
 945 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
 946 static inline void
 947 intel_wait_for_vblank(struct drm_device *dev, int pipe)
 948 {
 949         drm_wait_one_vblank(dev, pipe);
 950 }
 951 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 952 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 953                          struct intel_digital_port *dport);
 954 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 955                                 struct drm_display_mode *mode,
 956                                 struct intel_load_detect_pipe *old,
 957                                 struct drm_modeset_acquire_ctx *ctx);
 958 void intel_release_load_detect_pipe(struct drm_connector *connector,
 959                                     struct intel_load_detect_pipe *old);
 960 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 961                                struct drm_framebuffer *fb,
 962                                const struct drm_plane_state *plane_state,
 963                                struct intel_engine_cs *pipelined);
 964 struct drm_framebuffer *
 965 __intel_framebuffer_create(struct drm_device *dev,
 966                            struct drm_mode_fb_cmd2 *mode_cmd,
 967                            struct drm_i915_gem_object *obj);
 968 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 969 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 970 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 971 void intel_check_page_flip(struct drm_device *dev, int pipe);
 972 int intel_prepare_plane_fb(struct drm_plane *plane,
 973                            struct drm_framebuffer *fb,
 974                            const struct drm_plane_state *new_state);
 975 void intel_cleanup_plane_fb(struct drm_plane *plane,
 976                             struct drm_framebuffer *fb,
 977                             const struct drm_plane_state *old_state);
 978 int intel_plane_atomic_get_property(struct drm_plane *plane,
 979                                     const struct drm_plane_state *state,
 980                                     struct drm_property *property,
 981                                     uint64_t *val);
 982 int intel_plane_atomic_set_property(struct drm_plane *plane,
 983                                     struct drm_plane_state *state,
 984                                     struct drm_property *property,
 985                                     uint64_t val);
 986
 987 /* shared dpll functions */
 988 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 989 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 990                         struct intel_shared_dpll *pll,
 991                         bool state);
 992 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 993 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 994 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 995                                                 struct intel_crtc_state *state);
 996 void intel_put_shared_dpll(struct intel_crtc *crtc);
 997
 998 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
 999                       const struct dpll *dpll);
1000 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1001
1002 /* modesetting asserts */
1003 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1004                            enum pipe pipe);
1005 void assert_pll(struct drm_i915_private *dev_priv,
1006                 enum pipe pipe, bool state);
1007 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1008 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1009 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1010                        enum pipe pipe, bool state);
1011 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1012 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1013 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1014 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1015 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1016 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1017                                              unsigned int tiling_mode,
1018                                              unsigned int bpp,
1019                                              unsigned int pitch);
1020 void intel_prepare_reset(struct drm_device *dev);
1021 void intel_finish_reset(struct drm_device *dev);
1022 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1023 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1024 void intel_dp_get_m_n(struct intel_crtc *crtc,
1025                       struct intel_crtc_state *pipe_config);
1026 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1027 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1028 void
1029 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1030                                 int dotclock);
1031 bool intel_crtc_active(struct drm_crtc *crtc);
1032 void hsw_enable_ips(struct intel_crtc *crtc);
1033 void hsw_disable_ips(struct intel_crtc *crtc);
1034 enum intel_display_power_domain
1035 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1036 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1037                                  struct intel_crtc_state *pipe_config);
1038 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1039 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1040
1041 /* intel_dp.c */
1042 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1043 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1044                              struct intel_connector *intel_connector);
1045 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1046 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1047 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1048 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1049 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1050 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1051 bool intel_dp_compute_config(struct intel_encoder *encoder,
1052                              struct intel_crtc_state *pipe_config);
1053 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1054 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1055                                   bool long_hpd);
1056 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1057 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1058 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1059 void intel_edp_panel_on(struct intel_dp *intel_dp);
1060 void intel_edp_panel_off(struct intel_dp *intel_dp);
1061 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1062 void intel_dp_mst_suspend(struct drm_device *dev);
1063 void intel_dp_mst_resume(struct drm_device *dev);
1064 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1065 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1066 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1067 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1068 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1069 void intel_plane_destroy(struct drm_plane *plane);
1070 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1071 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1072 void intel_edp_drrs_invalidate(struct drm_device *dev,
1073                 unsigned frontbuffer_bits);
1074 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1075
1076 /* intel_dp_mst.c */
1077 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1078 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1079 /* intel_dsi.c */
1080 void intel_dsi_init(struct drm_device *dev);
1081
1082
1083 /* intel_dvo.c */
1084 void intel_dvo_init(struct drm_device *dev);
1085
1086
1087 /* legacy fbdev emulation in intel_fbdev.c */
1088 #ifdef CONFIG_DRM_I915_FBDEV
1089 extern int intel_fbdev_init(struct drm_device *dev);
1090 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1091 extern void intel_fbdev_fini(struct drm_device *dev);
1092 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1093 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1094 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1095 #else
1096 static inline int intel_fbdev_init(struct drm_device *dev)
1097 {
1098         return 0;
1099 }
1100
1101 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1102 {
1103 }
1104
1105 static inline void intel_fbdev_fini(struct drm_device *dev)
1106 {
1107 }
1108
1109 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1110 {
1111 }
1112
1113 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1114 {
1115 }
1116 #endif
1117
1118 /* intel_fbc.c */
1119 bool intel_fbc_enabled(struct drm_device *dev);
1120 void intel_fbc_update(struct drm_device *dev);
1121 void intel_fbc_init(struct drm_i915_private *dev_priv);
1122 void intel_fbc_disable(struct drm_device *dev);
1123 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1124                           unsigned int frontbuffer_bits,
1125                           enum fb_op_origin origin);
1126 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1127                      unsigned int frontbuffer_bits);
1128
1129 /* intel_hdmi.c */
1130 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1131 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1132                                struct intel_connector *intel_connector);
1133 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1134 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1135                                struct intel_crtc_state *pipe_config);
1136
1137
1138 /* intel_lvds.c */
1139 void intel_lvds_init(struct drm_device *dev);
1140 bool intel_is_dual_link_lvds(struct drm_device *dev);
1141
1142
1143 /* intel_modes.c */
1144 int intel_connector_update_modes(struct drm_connector *connector,
1145                                  struct edid *edid);
1146 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1147 void intel_attach_force_audio_property(struct drm_connector *connector);
1148 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1149
1150
1151 /* intel_overlay.c */
1152 void intel_setup_overlay(struct drm_device *dev);
1153 void intel_cleanup_overlay(struct drm_device *dev);
1154 int intel_overlay_switch_off(struct intel_overlay *overlay);
1155 int intel_overlay_put_image(struct drm_device *dev, void *data,
1156                             struct drm_file *file_priv);
1157 int intel_overlay_attrs(struct drm_device *dev, void *data,
1158                         struct drm_file *file_priv);
1159 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1160
1161
1162 /* intel_panel.c */
1163 int intel_panel_init(struct intel_panel *panel,
1164                      struct drm_display_mode *fixed_mode,
1165                      struct drm_display_mode *downclock_mode);
1166 void intel_panel_fini(struct intel_panel *panel);
1167 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1168                             struct drm_display_mode *adjusted_mode);
1169 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1170                              struct intel_crtc_state *pipe_config,
1171                              int fitting_mode);
1172 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1173                               struct intel_crtc_state *pipe_config,
1174                               int fitting_mode);
1175 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1176                                     u32 level, u32 max);
1177 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1178 void intel_panel_enable_backlight(struct intel_connector *connector);
1179 void intel_panel_disable_backlight(struct intel_connector *connector);
1180 void intel_panel_destroy_backlight(struct drm_connector *connector);
1181 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1182 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1183 extern struct drm_display_mode *intel_find_panel_downclock(
1184                                 struct drm_device *dev,
1185                                 struct drm_display_mode *fixed_mode,
1186                                 struct drm_connector *connector);
1187 void intel_backlight_register(struct drm_device *dev);
1188 void intel_backlight_unregister(struct drm_device *dev);
1189
1190
1191 /* intel_psr.c */
1192 void intel_psr_enable(struct intel_dp *intel_dp);
1193 void intel_psr_disable(struct intel_dp *intel_dp);
1194 void intel_psr_invalidate(struct drm_device *dev,
1195                               unsigned frontbuffer_bits);
1196 void intel_psr_flush(struct drm_device *dev,
1197                          unsigned frontbuffer_bits);
1198 void intel_psr_init(struct drm_device *dev);
1199
1200 /* intel_runtime_pm.c */
1201 int intel_power_domains_init(struct drm_i915_private *);
1202 void intel_power_domains_fini(struct drm_i915_private *);
1203 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1204 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1205
1206 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1207                                     enum intel_display_power_domain domain);
1208 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1209                                       enum intel_display_power_domain domain);
1210 void intel_display_power_get(struct drm_i915_private *dev_priv,
1211                              enum intel_display_power_domain domain);
1212 void intel_display_power_put(struct drm_i915_private *dev_priv,
1213                              enum intel_display_power_domain domain);
1214 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1215 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1216 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1217 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1218 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1219
1220 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1221
1222 /* intel_pm.c */
1223 void intel_init_clock_gating(struct drm_device *dev);
1224 void intel_suspend_hw(struct drm_device *dev);
1225 int ilk_wm_max_level(const struct drm_device *dev);
1226 void intel_update_watermarks(struct drm_crtc *crtc);
1227 void intel_update_sprite_watermarks(struct drm_plane *plane,
1228                                     struct drm_crtc *crtc,
1229                                     uint32_t sprite_width,
1230                                     uint32_t sprite_height,
1231                                     int pixel_size,
1232                                     bool enabled, bool scaled);
1233 void intel_init_pm(struct drm_device *dev);
1234 void intel_pm_setup(struct drm_device *dev);
1235 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1236 void intel_gpu_ips_teardown(void);
1237 void intel_init_gt_powersave(struct drm_device *dev);
1238 void intel_cleanup_gt_powersave(struct drm_device *dev);
1239 void intel_enable_gt_powersave(struct drm_device *dev);
1240 void intel_disable_gt_powersave(struct drm_device *dev);
1241 void intel_suspend_gt_powersave(struct drm_device *dev);
1242 void intel_reset_gt_powersave(struct drm_device *dev);
1243 void gen6_update_ring_freq(struct drm_device *dev);
1244 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1245 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1246 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1247 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1248 void ilk_wm_get_hw_state(struct drm_device *dev);
1249 void skl_wm_get_hw_state(struct drm_device *dev);
1250 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1251                           struct skl_ddb_allocation *ddb /* out */);
1252
1253
1254 /* intel_sdvo.c */
1255 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1256
1257
1258 /* intel_sprite.c */
1259 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1260 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1261                                enum plane plane);
1262 int intel_plane_restore(struct drm_plane *plane);
1263 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1264                               struct drm_file *file_priv);
1265 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1266                               struct drm_file *file_priv);
1267 bool intel_pipe_update_start(struct intel_crtc *crtc,
1268                              uint32_t *start_vbl_count);
1269 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1270 void intel_post_enable_primary(struct drm_crtc *crtc);
1271 void intel_pre_disable_primary(struct drm_crtc *crtc);
1272
1273 /* intel_tv.c */
1274 void intel_tv_init(struct drm_device *dev);
1275
1276 /* intel_atomic.c */
1277 int intel_atomic_check(struct drm_device *dev,
1278                        struct drm_atomic_state *state);
1279 int intel_atomic_commit(struct drm_device *dev,
1280                         struct drm_atomic_state *state,
1281                         bool async);
1282 int intel_connector_atomic_get_property(struct drm_connector *connector,
1283                                         const struct drm_connector_state *state,
1284                                         struct drm_property *property,
1285                                         uint64_t *val);
1286 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1287 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1288                                struct drm_crtc_state *state);
1289
1290 /* intel_atomic_plane.c */
1291 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1292 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1293 void intel_plane_destroy_state(struct drm_plane *plane,
1294                                struct drm_plane_state *state);
1295 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1296
1297 #endif /* __INTEL_DRV_H__ */