2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
32 #include "drm_crtc_helper.h"
33 #include "drm_fb_helper.h"
35 #define _wait_for(COND, MS, W) ({ \
36 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
39 if (time_after(jiffies, timeout__)) { \
43 if (W && drm_can_sleep()) msleep(W); \
48 #define wait_for_atomic_us(COND, US) ({ \
49 int i, ret__ = -ETIMEDOUT; \
50 for (i = 0; i < (US); i++) { \
60 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
61 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
63 #define KHz(x) (1000*x)
64 #define MHz(x) KHz(1000*x)
67 * Display related stuff
70 /* store information about an Ixxx DVO */
71 /* The i830->i865 use multiple DVOs with multiple i2cs */
72 /* the i915, i945 have a single sDVO i2c bus - which is different */
74 /* maximum connectors per crtcs in the mode set */
75 #define INTELFB_CONN_LIMIT 4
77 #define INTEL_I2C_BUS_DVO 1
78 #define INTEL_I2C_BUS_SDVO 2
80 /* these are outputs from the chip - integrated only
81 external chips are via DVO or SDVO output */
82 #define INTEL_OUTPUT_UNUSED 0
83 #define INTEL_OUTPUT_ANALOG 1
84 #define INTEL_OUTPUT_DVO 2
85 #define INTEL_OUTPUT_SDVO 3
86 #define INTEL_OUTPUT_LVDS 4
87 #define INTEL_OUTPUT_TVOUT 5
88 #define INTEL_OUTPUT_HDMI 6
89 #define INTEL_OUTPUT_DISPLAYPORT 7
90 #define INTEL_OUTPUT_EDP 8
92 /* Intel Pipe Clone Bit */
93 #define INTEL_HDMIB_CLONE_BIT 1
94 #define INTEL_HDMIC_CLONE_BIT 2
95 #define INTEL_HDMID_CLONE_BIT 3
96 #define INTEL_HDMIE_CLONE_BIT 4
97 #define INTEL_HDMIF_CLONE_BIT 5
98 #define INTEL_SDVO_NON_TV_CLONE_BIT 6
99 #define INTEL_SDVO_TV_CLONE_BIT 7
100 #define INTEL_SDVO_LVDS_CLONE_BIT 8
101 #define INTEL_ANALOG_CLONE_BIT 9
102 #define INTEL_TV_CLONE_BIT 10
103 #define INTEL_DP_B_CLONE_BIT 11
104 #define INTEL_DP_C_CLONE_BIT 12
105 #define INTEL_DP_D_CLONE_BIT 13
106 #define INTEL_LVDS_CLONE_BIT 14
107 #define INTEL_DVO_TMDS_CLONE_BIT 15
108 #define INTEL_DVO_LVDS_CLONE_BIT 16
109 #define INTEL_EDP_CLONE_BIT 17
111 #define INTEL_DVO_CHIP_NONE 0
112 #define INTEL_DVO_CHIP_LVDS 1
113 #define INTEL_DVO_CHIP_TMDS 2
114 #define INTEL_DVO_CHIP_TVOUT 4
116 /* drm_display_mode->private_flags */
117 #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
118 #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
119 #define INTEL_MODE_DP_FORCE_6BPC (0x10)
120 /* This flag must be set by the encoder's mode_fixup if it changes the crtc
121 * timings in the mode to prevent the crtc fixup from overwriting them.
122 * Currently only lvds needs that. */
123 #define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
126 intel_mode_set_pixel_multiplier(struct drm_display_mode
*mode
,
129 mode
->clock
*= multiplier
;
130 mode
->private_flags
|= multiplier
;
134 intel_mode_get_pixel_multiplier(const struct drm_display_mode
*mode
)
136 return (mode
->private_flags
& INTEL_MODE_PIXEL_MULTIPLIER_MASK
) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT
;
139 struct intel_framebuffer
{
140 struct drm_framebuffer base
;
141 struct drm_i915_gem_object
*obj
;
145 struct drm_fb_helper helper
;
146 struct intel_framebuffer ifb
;
147 struct list_head fbdev_list
;
148 struct drm_display_mode
*our_mode
;
151 struct intel_encoder
{
152 struct drm_encoder base
;
155 void (*hot_plug
)(struct intel_encoder
*);
160 struct intel_connector
{
161 struct drm_connector base
;
162 struct intel_encoder
*encoder
;
166 struct drm_crtc base
;
169 u8 lut_r
[256], lut_g
[256], lut_b
[256];
171 bool active
; /* is the crtc on? independent of the dpms mode */
172 bool busy
; /* is scanout buffer being updated frequently? */
173 struct timer_list idle_timer
;
175 struct intel_overlay
*overlay
;
176 struct intel_unpin_work
*unpin_work
;
179 struct drm_i915_gem_object
*cursor_bo
;
180 uint32_t cursor_addr
;
181 int16_t cursor_x
, cursor_y
;
182 int16_t cursor_width
, cursor_height
;
186 /* We can share PLLs across outputs if the timings match */
187 struct intel_pch_pll
*pch_pll
;
191 struct drm_plane base
;
193 struct drm_i915_gem_object
*obj
;
194 bool primary_disabled
;
196 u32 lut_r
[1024], lut_g
[1024], lut_b
[1024];
197 void (*update_plane
)(struct drm_plane
*plane
,
198 struct drm_framebuffer
*fb
,
199 struct drm_i915_gem_object
*obj
,
200 int crtc_x
, int crtc_y
,
201 unsigned int crtc_w
, unsigned int crtc_h
,
202 uint32_t x
, uint32_t y
,
203 uint32_t src_w
, uint32_t src_h
);
204 void (*disable_plane
)(struct drm_plane
*plane
);
205 int (*update_colorkey
)(struct drm_plane
*plane
,
206 struct drm_intel_sprite_colorkey
*key
);
207 void (*get_colorkey
)(struct drm_plane
*plane
,
208 struct drm_intel_sprite_colorkey
*key
);
211 struct intel_watermark_params
{
212 unsigned long fifo_size
;
213 unsigned long max_wm
;
214 unsigned long default_wm
;
215 unsigned long guard_size
;
216 unsigned long cacheline_size
;
219 struct cxsr_latency
{
222 unsigned long fsb_freq
;
223 unsigned long mem_freq
;
224 unsigned long display_sr
;
225 unsigned long display_hpll_disable
;
226 unsigned long cursor_sr
;
227 unsigned long cursor_hpll_disable
;
230 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
231 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
232 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
233 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
234 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
236 #define DIP_HEADER_SIZE 5
238 #define DIP_TYPE_AVI 0x82
239 #define DIP_VERSION_AVI 0x2
240 #define DIP_LEN_AVI 13
241 #define DIP_AVI_PR_1 0
242 #define DIP_AVI_PR_2 1
244 #define DIP_TYPE_SPD 0x83
245 #define DIP_VERSION_SPD 0x1
246 #define DIP_LEN_SPD 25
247 #define DIP_SPD_UNKNOWN 0
248 #define DIP_SPD_DSTB 0x1
249 #define DIP_SPD_DVDP 0x2
250 #define DIP_SPD_DVHS 0x3
251 #define DIP_SPD_HDDVR 0x4
252 #define DIP_SPD_DVC 0x5
253 #define DIP_SPD_DSC 0x6
254 #define DIP_SPD_VCD 0x7
255 #define DIP_SPD_GAME 0x8
256 #define DIP_SPD_PC 0x9
257 #define DIP_SPD_BD 0xa
258 #define DIP_SPD_SCD 0xb
260 struct dip_infoframe
{
261 uint8_t type
; /* HB0 */
262 uint8_t ver
; /* HB1 */
263 uint8_t len
; /* HB2 - body len, not including checksum */
264 uint8_t ecc
; /* Header ECC */
265 uint8_t checksum
; /* PB0 */
268 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
270 /* PB2 - C 7:6, M 5:4, R 3:0 */
272 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
276 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
279 uint16_t top_bar_end
;
280 uint16_t bottom_bar_start
;
281 uint16_t left_bar_end
;
282 uint16_t right_bar_start
;
290 } __attribute__ ((packed
)) body
;
291 } __attribute__((packed
));
293 static inline struct drm_crtc
*
294 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
297 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
300 static inline struct drm_crtc
*
301 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
304 return dev_priv
->plane_to_crtc_mapping
[plane
];
307 struct intel_unpin_work
{
308 struct work_struct work
;
309 struct drm_device
*dev
;
310 struct drm_i915_gem_object
*old_fb_obj
;
311 struct drm_i915_gem_object
*pending_flip_obj
;
312 struct drm_pending_vblank_event
*event
;
314 bool enable_stall_check
;
317 struct intel_fbc_work
{
318 struct delayed_work work
;
319 struct drm_crtc
*crtc
;
320 struct drm_framebuffer
*fb
;
324 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
325 extern bool intel_ddc_probe(struct intel_encoder
*intel_encoder
, int ddc_bus
);
327 extern void intel_attach_force_audio_property(struct drm_connector
*connector
);
328 extern void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
330 extern void intel_crt_init(struct drm_device
*dev
);
331 extern void intel_hdmi_init(struct drm_device
*dev
, int sdvox_reg
);
332 void intel_dip_infoframe_csum(struct dip_infoframe
*avi_if
);
333 extern bool intel_sdvo_init(struct drm_device
*dev
, uint32_t sdvo_reg
,
335 extern void intel_dvo_init(struct drm_device
*dev
);
336 extern void intel_tv_init(struct drm_device
*dev
);
337 extern void intel_mark_busy(struct drm_device
*dev
,
338 struct drm_i915_gem_object
*obj
);
339 extern bool intel_lvds_init(struct drm_device
*dev
);
340 extern void intel_dp_init(struct drm_device
*dev
, int dp_reg
);
342 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
343 struct drm_display_mode
*adjusted_mode
);
344 extern bool intel_dpd_is_edp(struct drm_device
*dev
);
345 extern void intel_edp_link_config(struct intel_encoder
*, int *, int *);
346 extern bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
);
347 extern int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
);
348 extern void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
351 void intel_sanitize_pm(struct drm_device
*dev
);
354 extern void intel_fixed_panel_mode(struct drm_display_mode
*fixed_mode
,
355 struct drm_display_mode
*adjusted_mode
);
356 extern void intel_pch_panel_fitting(struct drm_device
*dev
,
358 struct drm_display_mode
*mode
,
359 struct drm_display_mode
*adjusted_mode
);
360 extern u32
intel_panel_get_max_backlight(struct drm_device
*dev
);
361 extern u32
intel_panel_get_backlight(struct drm_device
*dev
);
362 extern void intel_panel_set_backlight(struct drm_device
*dev
, u32 level
);
363 extern int intel_panel_setup_backlight(struct drm_device
*dev
);
364 extern void intel_panel_enable_backlight(struct drm_device
*dev
);
365 extern void intel_panel_disable_backlight(struct drm_device
*dev
);
366 extern void intel_panel_destroy_backlight(struct drm_device
*dev
);
367 extern enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
369 extern void intel_crtc_load_lut(struct drm_crtc
*crtc
);
370 extern void intel_encoder_prepare(struct drm_encoder
*encoder
);
371 extern void intel_encoder_commit(struct drm_encoder
*encoder
);
372 extern void intel_encoder_destroy(struct drm_encoder
*encoder
);
374 static inline struct intel_encoder
*intel_attached_encoder(struct drm_connector
*connector
)
376 return to_intel_connector(connector
)->encoder
;
379 extern void intel_connector_attach_encoder(struct intel_connector
*connector
,
380 struct intel_encoder
*encoder
);
381 extern struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
383 extern struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
384 struct drm_crtc
*crtc
);
385 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
386 struct drm_file
*file_priv
);
387 extern void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
);
388 extern void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
);
390 struct intel_load_detect_pipe
{
391 struct drm_framebuffer
*release_fb
;
392 bool load_detect_temp
;
395 extern bool intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
396 struct drm_connector
*connector
,
397 struct drm_display_mode
*mode
,
398 struct intel_load_detect_pipe
*old
);
399 extern void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
400 struct drm_connector
*connector
,
401 struct intel_load_detect_pipe
*old
);
403 extern void intelfb_restore(void);
404 extern void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
405 u16 blue
, int regno
);
406 extern void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
407 u16
*blue
, int regno
);
408 extern void intel_enable_clock_gating(struct drm_device
*dev
);
409 extern void ironlake_disable_rc6(struct drm_device
*dev
);
410 extern void ironlake_enable_drps(struct drm_device
*dev
);
411 extern void ironlake_disable_drps(struct drm_device
*dev
);
413 extern int intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
414 struct drm_i915_gem_object
*obj
,
415 struct intel_ring_buffer
*pipelined
);
416 extern void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
);
418 extern int intel_framebuffer_init(struct drm_device
*dev
,
419 struct intel_framebuffer
*ifb
,
420 struct drm_mode_fb_cmd2
*mode_cmd
,
421 struct drm_i915_gem_object
*obj
);
422 extern int intel_fbdev_init(struct drm_device
*dev
);
423 extern void intel_fbdev_fini(struct drm_device
*dev
);
424 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
);
425 extern void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
426 extern void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
427 extern void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
429 extern void intel_setup_overlay(struct drm_device
*dev
);
430 extern void intel_cleanup_overlay(struct drm_device
*dev
);
431 extern int intel_overlay_switch_off(struct intel_overlay
*overlay
);
432 extern int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
433 struct drm_file
*file_priv
);
434 extern int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
435 struct drm_file
*file_priv
);
437 extern void intel_fb_output_poll_changed(struct drm_device
*dev
);
438 extern void intel_fb_restore_mode(struct drm_device
*dev
);
440 extern void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
442 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
443 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
445 extern void intel_init_clock_gating(struct drm_device
*dev
);
446 extern void intel_write_eld(struct drm_encoder
*encoder
,
447 struct drm_display_mode
*mode
);
448 extern void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
);
449 extern void intel_prepare_ddi(struct drm_device
*dev
);
450 extern void hsw_fdi_link_train(struct drm_crtc
*crtc
);
452 /* For use by IVB LP watermark workaround in intel_sprite.c */
453 extern void intel_update_watermarks(struct drm_device
*dev
);
454 extern void intel_update_sprite_watermarks(struct drm_device
*dev
, int pipe
,
455 uint32_t sprite_width
,
458 extern int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
459 struct drm_file
*file_priv
);
460 extern int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
461 struct drm_file
*file_priv
);
463 extern u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
);
465 /* Power-related functions, located in intel_pm.c */
466 extern void intel_init_pm(struct drm_device
*dev
);
468 extern bool intel_fbc_enabled(struct drm_device
*dev
);
469 extern void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
);
470 extern void intel_update_fbc(struct drm_device
*dev
);
472 extern void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
473 extern void intel_gpu_ips_teardown(void);
475 extern void gen6_enable_rps(struct drm_i915_private
*dev_priv
);
476 extern void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
);
477 extern void gen6_disable_rps(struct drm_device
*dev
);
478 extern void intel_init_emon(struct drm_device
*dev
);
480 #endif /* __INTEL_DRV_H__ */