drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000*x)
  69 #define MHz(x) KHz(1000*x)
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80 #define INTELFB_CONN_LIMIT 4
  81
  82 #define INTEL_I2C_BUS_DVO 1
  83 #define INTEL_I2C_BUS_SDVO 2
  84
  85 /* these are outputs from the chip - integrated only
  86    external chips are via DVO or SDVO output */
  87 #define INTEL_OUTPUT_UNUSED 0
  88 #define INTEL_OUTPUT_ANALOG 1
  89 #define INTEL_OUTPUT_DVO 2
  90 #define INTEL_OUTPUT_SDVO 3
  91 #define INTEL_OUTPUT_LVDS 4
  92 #define INTEL_OUTPUT_TVOUT 5
  93 #define INTEL_OUTPUT_HDMI 6
  94 #define INTEL_OUTPUT_DISPLAYPORT 7
  95 #define INTEL_OUTPUT_EDP 8
  96 #define INTEL_OUTPUT_UNKNOWN 9
  97
  98 #define INTEL_DVO_CHIP_NONE 0
  99 #define INTEL_DVO_CHIP_LVDS 1
 100 #define INTEL_DVO_CHIP_TMDS 2
 101 #define INTEL_DVO_CHIP_TVOUT 4
 102
 103 struct intel_framebuffer {
 104         struct drm_framebuffer base;
 105         struct drm_i915_gem_object *obj;
 106 };
 107
 108 struct intel_fbdev {
 109         struct drm_fb_helper helper;
 110         struct intel_framebuffer ifb;
 111         struct list_head fbdev_list;
 112         struct drm_display_mode *our_mode;
 113 };
 114
 115 struct intel_encoder {
 116         struct drm_encoder base;
 117         /*
 118          * The new crtc this encoder will be driven from. Only differs from
 119          * base->crtc while a modeset is in progress.
 120          */
 121         struct intel_crtc *new_crtc;
 122
 123         int type;
 124         /*
 125          * Intel hw has only one MUX where encoders could be clone, hence a
 126          * simple flag is enough to compute the possible_clones mask.
 127          */
 128         bool cloneable;
 129         bool connectors_active;
 130         void (*hot_plug)(struct intel_encoder *);
 131         bool (*compute_config)(struct intel_encoder *,
 132                                struct intel_crtc_config *);
 133         void (*pre_pll_enable)(struct intel_encoder *);
 134         void (*pre_enable)(struct intel_encoder *);
 135         void (*enable)(struct intel_encoder *);
 136         void (*mode_set)(struct intel_encoder *intel_encoder);
 137         void (*disable)(struct intel_encoder *);
 138         void (*post_disable)(struct intel_encoder *);
 139         /* Read out the current hw state of this connector, returning true if
 140          * the encoder is active. If the encoder is enabled it also set the pipe
 141          * it is connected to in the pipe parameter. */
 142         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 143         /* Reconstructs the equivalent mode flags for the current hardware
 144          * state. This must be called _after_ display->get_pipe_config has
 145          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 146          * be set correctly before calling this function. */
 147         void (*get_config)(struct intel_encoder *,
 148                            struct intel_crtc_config *pipe_config);
 149         int crtc_mask;
 150         enum hpd_pin hpd_pin;
 151 };
 152
 153 struct intel_panel {
 154         struct drm_display_mode *fixed_mode;
 155         int fitting_mode;
 156 };
 157
 158 struct intel_connector {
 159         struct drm_connector base;
 160         /*
 161          * The fixed encoder this connector is connected to.
 162          */
 163         struct intel_encoder *encoder;
 164
 165         /*
 166          * The new encoder this connector will be driven. Only differs from
 167          * encoder while a modeset is in progress.
 168          */
 169         struct intel_encoder *new_encoder;
 170
 171         /* Reads out the current hw, returning true if the connector is enabled
 172          * and active (i.e. dpms ON state). */
 173         bool (*get_hw_state)(struct intel_connector *);
 174
 175         /* Panel info for eDP and LVDS */
 176         struct intel_panel panel;
 177
 178         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 179         struct edid *edid;
 180
 181         /* since POLL and HPD connectors may use the same HPD line keep the native
 182            state of connector->polled in case hotplug storm detection changes it */
 183         u8 polled;
 184 };
 185
 186 typedef struct dpll {
 187         /* given values */
 188         int n;
 189         int m1, m2;
 190         int p1, p2;
 191         /* derived values */
 192         int     dot;
 193         int     vco;
 194         int     m;
 195         int     p;
 196 } intel_clock_t;
 197
 198 struct intel_crtc_config {
 199         /**
 200          * quirks - bitfield with hw state readout quirks
 201          *
 202          * For various reasons the hw state readout code might not be able to
 203          * completely faithfully read out the current state. These cases are
 204          * tracked with quirk flags so that fastboot and state checker can act
 205          * accordingly.
 206          */
 207 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
 208         unsigned long quirks;
 209
 210         struct drm_display_mode requested_mode;
 211         struct drm_display_mode adjusted_mode;
 212         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 213          * between pch encoders and cpu encoders. */
 214         bool has_pch_encoder;
 215
 216         /* CPU Transcoder for the pipe. Currently this can only differ from the
 217          * pipe on Haswell (where we have a special eDP transcoder). */
 218         enum transcoder cpu_transcoder;
 219
 220         /*
 221          * Use reduced/limited/broadcast rbg range, compressing from the full
 222          * range fed into the crtcs.
 223          */
 224         bool limited_color_range;
 225
 226         /* DP has a bunch of special case unfortunately, so mark the pipe
 227          * accordingly. */
 228         bool has_dp_encoder;
 229
 230         /*
 231          * Enable dithering, used when the selected pipe bpp doesn't match the
 232          * plane bpp.
 233          */
 234         bool dither;
 235
 236         /* Controls for the clock computation, to override various stages. */
 237         bool clock_set;
 238
 239         /* SDVO TV has a bunch of special case. To make multifunction encoders
 240          * work correctly, we need to track this at runtime.*/
 241         bool sdvo_tv_clock;
 242
 243         /*
 244          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 245          * required. This is set in the 2nd loop of calling encoder's
 246          * ->compute_config if the first pick doesn't work out.
 247          */
 248         bool bw_constrained;
 249
 250         /* Settings for the intel dpll used on pretty much everything but
 251          * haswell. */
 252         struct dpll dpll;
 253
 254         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 255         enum intel_dpll_id shared_dpll;
 256
 257         /* Actual register state of the dpll, for shared dpll cross-checking. */
 258         struct intel_dpll_hw_state dpll_hw_state;
 259
 260         int pipe_bpp;
 261         struct intel_link_m_n dp_m_n;
 262
 263         /*
 264          * Frequence the dpll for the port should run at. Differs from the
 265          * adjusted dotclock e.g. for DP or 12bpc hdmi mode.
 266          */
 267         int port_clock;
 268
 269         /* Used by SDVO (and if we ever fix it, HDMI). */
 270         unsigned pixel_multiplier;
 271
 272         /* Panel fitter controls for gen2-gen4 + VLV */
 273         struct {
 274                 u32 control;
 275                 u32 pgm_ratios;
 276                 u32 lvds_border_bits;
 277         } gmch_pfit;
 278
 279         /* Panel fitter placement and size for Ironlake+ */
 280         struct {
 281                 u32 pos;
 282                 u32 size;
 283         } pch_pfit;
 284
 285         /* FDI configuration, only valid if has_pch_encoder is set. */
 286         int fdi_lanes;
 287         struct intel_link_m_n fdi_m_n;
 288
 289         bool ips_enabled;
 290 };
 291
 292 struct intel_crtc {
 293         struct drm_crtc base;
 294         enum pipe pipe;
 295         enum plane plane;
 296         u8 lut_r[256], lut_g[256], lut_b[256];
 297         /*
 298          * Whether the crtc and the connected output pipeline is active. Implies
 299          * that crtc->enabled is set, i.e. the current mode configuration has
 300          * some outputs connected to this crtc.
 301          */
 302         bool active;
 303         bool eld_vld;
 304         bool primary_disabled; /* is the crtc obscured by a plane? */
 305         bool lowfreq_avail;
 306         struct intel_overlay *overlay;
 307         struct intel_unpin_work *unpin_work;
 308
 309         atomic_t unpin_work_count;
 310
 311         /* Display surface base address adjustement for pageflips. Note that on
 312          * gen4+ this only adjusts up to a tile, offsets within a tile are
 313          * handled in the hw itself (with the TILEOFF register). */
 314         unsigned long dspaddr_offset;
 315
 316         struct drm_i915_gem_object *cursor_bo;
 317         uint32_t cursor_addr;
 318         int16_t cursor_x, cursor_y;
 319         int16_t cursor_width, cursor_height;
 320         bool cursor_visible;
 321
 322         struct intel_crtc_config config;
 323
 324         uint32_t ddi_pll_sel;
 325
 326         /* reset counter value when the last flip was submitted */
 327         unsigned int reset_counter;
 328
 329         /* Access to these should be protected by dev_priv->irq_lock. */
 330         bool cpu_fifo_underrun_disabled;
 331         bool pch_fifo_underrun_disabled;
 332 };
 333
 334 struct intel_plane_wm_parameters {
 335         uint32_t horiz_pixels;
 336         uint8_t bytes_per_pixel;
 337         bool enabled;
 338         bool scaled;
 339 };
 340
 341 struct intel_plane {
 342         struct drm_plane base;
 343         int plane;
 344         enum pipe pipe;
 345         struct drm_i915_gem_object *obj;
 346         bool can_scale;
 347         int max_downscale;
 348         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 349         int crtc_x, crtc_y;
 350         unsigned int crtc_w, crtc_h;
 351         uint32_t src_x, src_y;
 352         uint32_t src_w, src_h;
 353
 354         /* Since we need to change the watermarks before/after
 355          * enabling/disabling the planes, we need to store the parameters here
 356          * as the other pieces of the struct may not reflect the values we want
 357          * for the watermark calculations. Currently only Haswell uses this.
 358          */
 359         struct intel_plane_wm_parameters wm;
 360
 361         void (*update_plane)(struct drm_plane *plane,
 362                              struct drm_crtc *crtc,
 363                              struct drm_framebuffer *fb,
 364                              struct drm_i915_gem_object *obj,
 365                              int crtc_x, int crtc_y,
 366                              unsigned int crtc_w, unsigned int crtc_h,
 367                              uint32_t x, uint32_t y,
 368                              uint32_t src_w, uint32_t src_h);
 369         void (*disable_plane)(struct drm_plane *plane,
 370                               struct drm_crtc *crtc);
 371         int (*update_colorkey)(struct drm_plane *plane,
 372                                struct drm_intel_sprite_colorkey *key);
 373         void (*get_colorkey)(struct drm_plane *plane,
 374                              struct drm_intel_sprite_colorkey *key);
 375 };
 376
 377 struct intel_watermark_params {
 378         unsigned long fifo_size;
 379         unsigned long max_wm;
 380         unsigned long default_wm;
 381         unsigned long guard_size;
 382         unsigned long cacheline_size;
 383 };
 384
 385 struct cxsr_latency {
 386         int is_desktop;
 387         int is_ddr3;
 388         unsigned long fsb_freq;
 389         unsigned long mem_freq;
 390         unsigned long display_sr;
 391         unsigned long display_hpll_disable;
 392         unsigned long cursor_sr;
 393         unsigned long cursor_hpll_disable;
 394 };
 395
 396 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 397 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 398 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 399 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 400 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 401
 402 struct intel_hdmi {
 403         u32 hdmi_reg;
 404         int ddc_bus;
 405         uint32_t color_range;
 406         bool color_range_auto;
 407         bool has_hdmi_sink;
 408         bool has_audio;
 409         enum hdmi_force_audio force_audio;
 410         bool rgb_quant_range_selectable;
 411         void (*write_infoframe)(struct drm_encoder *encoder,
 412                                 enum hdmi_infoframe_type type,
 413                                 const uint8_t *frame, ssize_t len);
 414         void (*set_infoframes)(struct drm_encoder *encoder,
 415                                struct drm_display_mode *adjusted_mode);
 416 };
 417
 418 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 419 #define DP_LINK_CONFIGURATION_SIZE      9
 420
 421 struct intel_dp {
 422         uint32_t output_reg;
 423         uint32_t aux_ch_ctl_reg;
 424         uint32_t DP;
 425         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
 426         bool has_audio;
 427         enum hdmi_force_audio force_audio;
 428         uint32_t color_range;
 429         bool color_range_auto;
 430         uint8_t link_bw;
 431         uint8_t lane_count;
 432         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 433         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 434         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 435         struct i2c_adapter adapter;
 436         struct i2c_algo_dp_aux_data algo;
 437         uint8_t train_set[4];
 438         int panel_power_up_delay;
 439         int panel_power_down_delay;
 440         int panel_power_cycle_delay;
 441         int backlight_on_delay;
 442         int backlight_off_delay;
 443         struct delayed_work panel_vdd_work;
 444         bool want_panel_vdd;
 445         bool psr_setup_done;
 446         struct intel_connector *attached_connector;
 447 };
 448
 449 struct intel_digital_port {
 450         struct intel_encoder base;
 451         enum port port;
 452         u32 saved_port_bits;
 453         struct intel_dp dp;
 454         struct intel_hdmi hdmi;
 455 };
 456
 457 static inline int
 458 vlv_dport_to_channel(struct intel_digital_port *dport)
 459 {
 460         switch (dport->port) {
 461         case PORT_B:
 462                 return 0;
 463         case PORT_C:
 464                 return 1;
 465         default:
 466                 BUG();
 467         }
 468 }
 469
 470 static inline struct drm_crtc *
 471 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 472 {
 473         struct drm_i915_private *dev_priv = dev->dev_private;
 474         return dev_priv->pipe_to_crtc_mapping[pipe];
 475 }
 476
 477 static inline struct drm_crtc *
 478 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 479 {
 480         struct drm_i915_private *dev_priv = dev->dev_private;
 481         return dev_priv->plane_to_crtc_mapping[plane];
 482 }
 483
 484 struct intel_unpin_work {
 485         struct work_struct work;
 486         struct drm_crtc *crtc;
 487         struct drm_i915_gem_object *old_fb_obj;
 488         struct drm_i915_gem_object *pending_flip_obj;
 489         struct drm_pending_vblank_event *event;
 490         atomic_t pending;
 491 #define INTEL_FLIP_INACTIVE     0
 492 #define INTEL_FLIP_PENDING      1
 493 #define INTEL_FLIP_COMPLETE     2
 494         bool enable_stall_check;
 495 };
 496
 497 int intel_pch_rawclk(struct drm_device *dev);
 498
 499 int intel_connector_update_modes(struct drm_connector *connector,
 500                                 struct edid *edid);
 501 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 502
 503 extern void intel_attach_force_audio_property(struct drm_connector *connector);
 504 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 505
 506 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
 507 extern void intel_crt_init(struct drm_device *dev);
 508 extern void intel_hdmi_init(struct drm_device *dev,
 509                             int hdmi_reg, enum port port);
 510 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 511                                       struct intel_connector *intel_connector);
 512 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 513 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 514                                       struct intel_crtc_config *pipe_config);
 515 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
 516                             bool is_sdvob);
 517 extern void intel_dvo_init(struct drm_device *dev);
 518 extern void intel_tv_init(struct drm_device *dev);
 519 extern void intel_mark_busy(struct drm_device *dev);
 520 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 521                                struct intel_ring_buffer *ring);
 522 extern void intel_mark_idle(struct drm_device *dev);
 523 extern void intel_lvds_init(struct drm_device *dev);
 524 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
 525 extern void intel_dp_init(struct drm_device *dev, int output_reg,
 526                           enum port port);
 527 extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 528                                     struct intel_connector *intel_connector);
 529 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
 530 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
 531 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 532 extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 533 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 534 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 535 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
 536 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
 537                                     struct intel_crtc_config *pipe_config);
 538 extern bool intel_dpd_is_edp(struct drm_device *dev);
 539 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
 540 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
 541 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
 542 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
 543 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 544 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 545 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 546 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
 547                                       enum plane plane);
 548
 549 /* intel_panel.c */
 550 extern int intel_panel_init(struct intel_panel *panel,
 551                             struct drm_display_mode *fixed_mode);
 552 extern void intel_panel_fini(struct intel_panel *panel);
 553
 554 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
 555                                    struct drm_display_mode *adjusted_mode);
 556 extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
 557                                     struct intel_crtc_config *pipe_config,
 558                                     int fitting_mode);
 559 extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 560                                      struct intel_crtc_config *pipe_config,
 561                                      int fitting_mode);
 562 extern void intel_panel_set_backlight(struct drm_device *dev,
 563                                       u32 level, u32 max);
 564 extern int intel_panel_setup_backlight(struct drm_connector *connector);
 565 extern void intel_panel_enable_backlight(struct drm_device *dev,
 566                                          enum pipe pipe);
 567 extern void intel_panel_disable_backlight(struct drm_device *dev);
 568 extern void intel_panel_destroy_backlight(struct drm_device *dev);
 569 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 570
 571 struct intel_set_config {
 572         struct drm_encoder **save_connector_encoders;
 573         struct drm_crtc **save_encoder_crtcs;
 574
 575         bool fb_changed;
 576         bool mode_changed;
 577 };
 578
 579 extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
 580                           int x, int y, struct drm_framebuffer *old_fb);
 581 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
 582 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
 583 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
 584 extern void intel_encoder_destroy(struct drm_encoder *encoder);
 585 extern void intel_connector_dpms(struct drm_connector *, int mode);
 586 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
 587 extern void intel_modeset_check_state(struct drm_device *dev);
 588 extern void intel_plane_restore(struct drm_plane *plane);
 589 extern void intel_plane_disable(struct drm_plane *plane);
 590
 591
 592 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
 593 {
 594         return to_intel_connector(connector)->encoder;
 595 }
 596
 597 static inline struct intel_digital_port *
 598 enc_to_dig_port(struct drm_encoder *encoder)
 599 {
 600         return container_of(encoder, struct intel_digital_port, base.base);
 601 }
 602
 603 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 604 {
 605         return &enc_to_dig_port(encoder)->dp;
 606 }
 607
 608 static inline struct intel_digital_port *
 609 dp_to_dig_port(struct intel_dp *intel_dp)
 610 {
 611         return container_of(intel_dp, struct intel_digital_port, dp);
 612 }
 613
 614 static inline struct intel_digital_port *
 615 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 616 {
 617         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 618 }
 619
 620 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 621                                 struct intel_digital_port *port);
 622
 623 extern void intel_connector_attach_encoder(struct intel_connector *connector,
 624                                            struct intel_encoder *encoder);
 625 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 626
 627 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 628                                                     struct drm_crtc *crtc);
 629 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 630                                 struct drm_file *file_priv);
 631 extern enum transcoder
 632 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 633                              enum pipe pipe);
 634 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 635 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 636 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 637 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
 638
 639 struct intel_load_detect_pipe {
 640         struct drm_framebuffer *release_fb;
 641         bool load_detect_temp;
 642         int dpms_mode;
 643 };
 644 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
 645                                        struct drm_display_mode *mode,
 646                                        struct intel_load_detect_pipe *old);
 647 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
 648                                            struct intel_load_detect_pipe *old);
 649
 650 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 651                                     u16 blue, int regno);
 652 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 653                                     u16 *blue, int regno);
 654
 655 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 656                                       struct drm_i915_gem_object *obj,
 657                                       struct intel_ring_buffer *pipelined);
 658 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 659
 660 extern int intel_framebuffer_init(struct drm_device *dev,
 661                                   struct intel_framebuffer *ifb,
 662                                   struct drm_mode_fb_cmd2 *mode_cmd,
 663                                   struct drm_i915_gem_object *obj);
 664 extern void intel_framebuffer_fini(struct intel_framebuffer *fb);
 665 extern int intel_fbdev_init(struct drm_device *dev);
 666 extern void intel_fbdev_initial_config(struct drm_device *dev);
 667 extern void intel_fbdev_fini(struct drm_device *dev);
 668 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 669 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
 670 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
 671 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 672
 673 extern void intel_setup_overlay(struct drm_device *dev);
 674 extern void intel_cleanup_overlay(struct drm_device *dev);
 675 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
 676 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
 677                                    struct drm_file *file_priv);
 678 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
 679                                struct drm_file *file_priv);
 680
 681 extern void intel_fb_output_poll_changed(struct drm_device *dev);
 682 extern void intel_fb_restore_mode(struct drm_device *dev);
 683
 684 struct intel_shared_dpll *
 685 intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 686
 687 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 688                         struct intel_shared_dpll *pll,
 689                         bool state);
 690 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 691 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 692 void assert_pll(struct drm_i915_private *dev_priv,
 693                 enum pipe pipe, bool state);
 694 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 695 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 696 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 697                        enum pipe pipe, bool state);
 698 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 699 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 700 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 701                         bool state);
 702 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 703 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 704
 705 extern void intel_init_clock_gating(struct drm_device *dev);
 706 extern void intel_suspend_hw(struct drm_device *dev);
 707 extern void intel_write_eld(struct drm_encoder *encoder,
 708                             struct drm_display_mode *mode);
 709 extern void intel_prepare_ddi(struct drm_device *dev);
 710 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
 711 extern void intel_ddi_init(struct drm_device *dev, enum port port);
 712
 713 /* For use by IVB LP watermark workaround in intel_sprite.c */
 714 extern void intel_update_watermarks(struct drm_device *dev);
 715 extern void intel_update_sprite_watermarks(struct drm_plane *plane,
 716                                            struct drm_crtc *crtc,
 717                                            uint32_t sprite_width, int pixel_size,
 718                                            bool enabled, bool scaled);
 719
 720 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 721                                                     unsigned int tiling_mode,
 722                                                     unsigned int bpp,
 723                                                     unsigned int pitch);
 724
 725 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 726                                      struct drm_file *file_priv);
 727 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 728                                      struct drm_file *file_priv);
 729
 730 /* Power-related functions, located in intel_pm.c */
 731 extern void intel_init_pm(struct drm_device *dev);
 732 /* FBC */
 733 extern bool intel_fbc_enabled(struct drm_device *dev);
 734 extern void intel_update_fbc(struct drm_device *dev);
 735 /* IPS */
 736 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 737 extern void intel_gpu_ips_teardown(void);
 738
 739 /* Power well */
 740 extern int i915_init_power_well(struct drm_device *dev);
 741 extern void i915_remove_power_well(struct drm_device *dev);
 742
 743 extern bool intel_display_power_enabled(struct drm_device *dev,
 744                                         enum intel_display_power_domain domain);
 745 extern void intel_init_power_well(struct drm_device *dev);
 746 extern void intel_set_power_well(struct drm_device *dev, bool enable);
 747 extern void intel_enable_gt_powersave(struct drm_device *dev);
 748 extern void intel_disable_gt_powersave(struct drm_device *dev);
 749 extern void ironlake_teardown_rc6(struct drm_device *dev);
 750
 751 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 752                                    enum pipe *pipe);
 753 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 754 extern void intel_ddi_pll_init(struct drm_device *dev);
 755 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 756 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 757                                               enum transcoder cpu_transcoder);
 758 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 759 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 760 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 761 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
 762 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 763 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 764 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 765 extern bool
 766 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 767 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 768
 769 extern void intel_display_handle_reset(struct drm_device *dev);
 770 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 771                                                   enum pipe pipe,
 772                                                   bool enable);
 773 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 774                                                  enum transcoder pch_transcoder,
 775                                                  bool enable);
 776
 777 extern void intel_edp_psr_enable(struct intel_dp *intel_dp);
 778 extern void intel_edp_psr_disable(struct intel_dp *intel_dp);
 779 extern void intel_edp_psr_update(struct drm_device *dev);
 780 extern void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
 781                               bool switch_to_fclk, bool allow_power_down);
 782 extern void hsw_restore_lcpll(struct drm_i915_private *dev_priv);
 783
 784 #endif /* __INTEL_DRV_H__ */