drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38
  39 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  40 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  41
  42 /**
  43  * _wait_for - magic (register) wait macro
  44  *
  45  * Does the right thing for modeset paths when run under kdgb or similar atomic
  46  * contexts. Note that it's important that we check the condition again after
  47  * having timed out, since the timeout could be due to preemption or similar and
  48  * we've never had a chance to check the condition before the timeout.
  49  */
  50 #define _wait_for(COND, MS, W) ({ \
  51         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  52         int ret__ = 0;                                                  \
  53         while (!(COND)) {                                               \
  54                 if (time_after(jiffies, timeout__)) {                   \
  55                         if (!(COND))                                    \
  56                                 ret__ = -ETIMEDOUT;                     \
  57                         break;                                          \
  58                 }                                                       \
  59                 if (W && drm_can_sleep())  {                            \
  60                         msleep(W);                                      \
  61                 } else {                                                \
  62                         cpu_relax();                                    \
  63                 }                                                       \
  64         }                                                               \
  65         ret__;                                                          \
  66 })
  67
  68 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  69 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  70 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  71                                                DIV_ROUND_UP((US), 1000), 0)
  72
  73 #define KHz(x) (1000 * (x))
  74 #define MHz(x) KHz(1000 * (x))
  75
  76 /*
  77  * Display related stuff
  78  */
  79
  80 /* store information about an Ixxx DVO */
  81 /* The i830->i865 use multiple DVOs with multiple i2cs */
  82 /* the i915, i945 have a single sDVO i2c bus - which is different */
  83 #define MAX_OUTPUTS 6
  84 /* maximum connectors per crtcs in the mode set */
  85
  86 /* Maximum cursor sizes */
  87 #define GEN2_CURSOR_WIDTH 64
  88 #define GEN2_CURSOR_HEIGHT 64
  89 #define MAX_CURSOR_WIDTH 256
  90 #define MAX_CURSOR_HEIGHT 256
  91
  92 #define INTEL_I2C_BUS_DVO 1
  93 #define INTEL_I2C_BUS_SDVO 2
  94
  95 /* these are outputs from the chip - integrated only
  96    external chips are via DVO or SDVO output */
  97 enum intel_output_type {
  98         INTEL_OUTPUT_UNUSED = 0,
  99         INTEL_OUTPUT_ANALOG = 1,
 100         INTEL_OUTPUT_DVO = 2,
 101         INTEL_OUTPUT_SDVO = 3,
 102         INTEL_OUTPUT_LVDS = 4,
 103         INTEL_OUTPUT_TVOUT = 5,
 104         INTEL_OUTPUT_HDMI = 6,
 105         INTEL_OUTPUT_DISPLAYPORT = 7,
 106         INTEL_OUTPUT_EDP = 8,
 107         INTEL_OUTPUT_DSI = 9,
 108         INTEL_OUTPUT_UNKNOWN = 10,
 109         INTEL_OUTPUT_DP_MST = 11,
 110 };
 111
 112 #define INTEL_DVO_CHIP_NONE 0
 113 #define INTEL_DVO_CHIP_LVDS 1
 114 #define INTEL_DVO_CHIP_TMDS 2
 115 #define INTEL_DVO_CHIP_TVOUT 4
 116
 117 #define INTEL_DSI_VIDEO_MODE    0
 118 #define INTEL_DSI_COMMAND_MODE  1
 119
 120 struct intel_framebuffer {
 121         struct drm_framebuffer base;
 122         struct drm_i915_gem_object *obj;
 123 };
 124
 125 struct intel_fbdev {
 126         struct drm_fb_helper helper;
 127         struct intel_framebuffer *fb;
 128         struct list_head fbdev_list;
 129         struct drm_display_mode *our_mode;
 130         int preferred_bpp;
 131 };
 132
 133 struct intel_encoder {
 134         struct drm_encoder base;
 135         /*
 136          * The new crtc this encoder will be driven from. Only differs from
 137          * base->crtc while a modeset is in progress.
 138          */
 139         struct intel_crtc *new_crtc;
 140
 141         enum intel_output_type type;
 142         unsigned int cloneable;
 143         bool connectors_active;
 144         void (*hot_plug)(struct intel_encoder *);
 145         bool (*compute_config)(struct intel_encoder *,
 146                                struct intel_crtc_state *);
 147         void (*pre_pll_enable)(struct intel_encoder *);
 148         void (*pre_enable)(struct intel_encoder *);
 149         void (*enable)(struct intel_encoder *);
 150         void (*mode_set)(struct intel_encoder *intel_encoder);
 151         void (*disable)(struct intel_encoder *);
 152         void (*post_disable)(struct intel_encoder *);
 153         /* Read out the current hw state of this connector, returning true if
 154          * the encoder is active. If the encoder is enabled it also set the pipe
 155          * it is connected to in the pipe parameter. */
 156         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 157         /* Reconstructs the equivalent mode flags for the current hardware
 158          * state. This must be called _after_ display->get_pipe_config has
 159          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 160          * be set correctly before calling this function. */
 161         void (*get_config)(struct intel_encoder *,
 162                            struct intel_crtc_state *pipe_config);
 163         /*
 164          * Called during system suspend after all pending requests for the
 165          * encoder are flushed (for example for DP AUX transactions) and
 166          * device interrupts are disabled.
 167          */
 168         void (*suspend)(struct intel_encoder *);
 169         int crtc_mask;
 170         enum hpd_pin hpd_pin;
 171 };
 172
 173 struct intel_panel {
 174         struct drm_display_mode *fixed_mode;
 175         struct drm_display_mode *downclock_mode;
 176         int fitting_mode;
 177
 178         /* backlight */
 179         struct {
 180                 bool present;
 181                 u32 level;
 182                 u32 min;
 183                 u32 max;
 184                 bool enabled;
 185                 bool combination_mode;  /* gen 2/4 only */
 186                 bool active_low_pwm;
 187                 struct backlight_device *device;
 188         } backlight;
 189
 190         void (*backlight_power)(struct intel_connector *, bool enable);
 191 };
 192
 193 struct intel_connector {
 194         struct drm_connector base;
 195         /*
 196          * The fixed encoder this connector is connected to.
 197          */
 198         struct intel_encoder *encoder;
 199
 200         /*
 201          * The new encoder this connector will be driven. Only differs from
 202          * encoder while a modeset is in progress.
 203          */
 204         struct intel_encoder *new_encoder;
 205
 206         /* Reads out the current hw, returning true if the connector is enabled
 207          * and active (i.e. dpms ON state). */
 208         bool (*get_hw_state)(struct intel_connector *);
 209
 210         /*
 211          * Removes all interfaces through which the connector is accessible
 212          * - like sysfs, debugfs entries -, so that no new operations can be
 213          * started on the connector. Also makes sure all currently pending
 214          * operations finish before returing.
 215          */
 216         void (*unregister)(struct intel_connector *);
 217
 218         /* Panel info for eDP and LVDS */
 219         struct intel_panel panel;
 220
 221         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 222         struct edid *edid;
 223         struct edid *detect_edid;
 224
 225         /* since POLL and HPD connectors may use the same HPD line keep the native
 226            state of connector->polled in case hotplug storm detection changes it */
 227         u8 polled;
 228
 229         void *port; /* store this opaque as its illegal to dereference it */
 230
 231         struct intel_dp *mst_port;
 232 };
 233
 234 typedef struct dpll {
 235         /* given values */
 236         int n;
 237         int m1, m2;
 238         int p1, p2;
 239         /* derived values */
 240         int     dot;
 241         int     vco;
 242         int     m;
 243         int     p;
 244 } intel_clock_t;
 245
 246 struct intel_plane_state {
 247         struct drm_plane_state base;
 248         struct drm_rect src;
 249         struct drm_rect dst;
 250         struct drm_rect clip;
 251         bool visible;
 252
 253         /*
 254          * used only for sprite planes to determine when to implicitly
 255          * enable/disable the primary plane
 256          */
 257         bool hides_primary;
 258 };
 259
 260 struct intel_initial_plane_config {
 261         unsigned int tiling;
 262         int size;
 263         u32 base;
 264 };
 265
 266 struct intel_crtc_state {
 267         struct drm_crtc_state base;
 268
 269         /**
 270          * quirks - bitfield with hw state readout quirks
 271          *
 272          * For various reasons the hw state readout code might not be able to
 273          * completely faithfully read out the current state. These cases are
 274          * tracked with quirk flags so that fastboot and state checker can act
 275          * accordingly.
 276          */
 277 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 278 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 279         unsigned long quirks;
 280
 281         /* Pipe source size (ie. panel fitter input size)
 282          * All planes will be positioned inside this space,
 283          * and get clipped at the edges. */
 284         int pipe_src_w, pipe_src_h;
 285
 286         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 287          * between pch encoders and cpu encoders. */
 288         bool has_pch_encoder;
 289
 290         /* Are we sending infoframes on the attached port */
 291         bool has_infoframe;
 292
 293         /* CPU Transcoder for the pipe. Currently this can only differ from the
 294          * pipe on Haswell (where we have a special eDP transcoder). */
 295         enum transcoder cpu_transcoder;
 296
 297         /*
 298          * Use reduced/limited/broadcast rbg range, compressing from the full
 299          * range fed into the crtcs.
 300          */
 301         bool limited_color_range;
 302
 303         /* DP has a bunch of special case unfortunately, so mark the pipe
 304          * accordingly. */
 305         bool has_dp_encoder;
 306
 307         /* Whether we should send NULL infoframes. Required for audio. */
 308         bool has_hdmi_sink;
 309
 310         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 311          * has_dp_encoder is set. */
 312         bool has_audio;
 313
 314         /*
 315          * Enable dithering, used when the selected pipe bpp doesn't match the
 316          * plane bpp.
 317          */
 318         bool dither;
 319
 320         /* Controls for the clock computation, to override various stages. */
 321         bool clock_set;
 322
 323         /* SDVO TV has a bunch of special case. To make multifunction encoders
 324          * work correctly, we need to track this at runtime.*/
 325         bool sdvo_tv_clock;
 326
 327         /*
 328          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 329          * required. This is set in the 2nd loop of calling encoder's
 330          * ->compute_config if the first pick doesn't work out.
 331          */
 332         bool bw_constrained;
 333
 334         /* Settings for the intel dpll used on pretty much everything but
 335          * haswell. */
 336         struct dpll dpll;
 337
 338         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 339         enum intel_dpll_id shared_dpll;
 340
 341         /*
 342          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 343          * - enum skl_dpll on SKL
 344          */
 345         uint32_t ddi_pll_sel;
 346
 347         /* Actual register state of the dpll, for shared dpll cross-checking. */
 348         struct intel_dpll_hw_state dpll_hw_state;
 349
 350         int pipe_bpp;
 351         struct intel_link_m_n dp_m_n;
 352
 353         /* m2_n2 for eDP downclock */
 354         struct intel_link_m_n dp_m2_n2;
 355         bool has_drrs;
 356
 357         /*
 358          * Frequence the dpll for the port should run at. Differs from the
 359          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 360          * already multiplied by pixel_multiplier.
 361          */
 362         int port_clock;
 363
 364         /* Used by SDVO (and if we ever fix it, HDMI). */
 365         unsigned pixel_multiplier;
 366
 367         /* Panel fitter controls for gen2-gen4 + VLV */
 368         struct {
 369                 u32 control;
 370                 u32 pgm_ratios;
 371                 u32 lvds_border_bits;
 372         } gmch_pfit;
 373
 374         /* Panel fitter placement and size for Ironlake+ */
 375         struct {
 376                 u32 pos;
 377                 u32 size;
 378                 bool enabled;
 379                 bool force_thru;
 380         } pch_pfit;
 381
 382         /* FDI configuration, only valid if has_pch_encoder is set. */
 383         int fdi_lanes;
 384         struct intel_link_m_n fdi_m_n;
 385
 386         bool ips_enabled;
 387
 388         bool double_wide;
 389
 390         bool dp_encoder_is_mst;
 391         int pbn;
 392 };
 393
 394 struct intel_pipe_wm {
 395         struct intel_wm_level wm[5];
 396         uint32_t linetime;
 397         bool fbc_wm_enabled;
 398         bool pipe_enabled;
 399         bool sprites_enabled;
 400         bool sprites_scaled;
 401 };
 402
 403 struct intel_mmio_flip {
 404         struct drm_i915_gem_request *req;
 405         struct work_struct work;
 406 };
 407
 408 struct skl_pipe_wm {
 409         struct skl_wm_level wm[8];
 410         struct skl_wm_level trans_wm;
 411         uint32_t linetime;
 412 };
 413
 414 /*
 415  * Tracking of operations that need to be performed at the beginning/end of an
 416  * atomic commit, outside the atomic section where interrupts are disabled.
 417  * These are generally operations that grab mutexes or might otherwise sleep
 418  * and thus can't be run with interrupts disabled.
 419  */
 420 struct intel_crtc_atomic_commit {
 421         /* vblank evasion */
 422         bool evade;
 423         unsigned start_vbl_count;
 424
 425         /* Sleepable operations to perform before commit */
 426         bool wait_for_flips;
 427         bool disable_fbc;
 428         bool pre_disable_primary;
 429         bool update_wm;
 430         unsigned disabled_planes;
 431
 432         /* Sleepable operations to perform after commit */
 433         unsigned fb_bits;
 434         bool wait_vblank;
 435         bool update_fbc;
 436         bool post_enable_primary;
 437         unsigned update_sprite_watermarks;
 438 };
 439
 440 struct intel_crtc {
 441         struct drm_crtc base;
 442         enum pipe pipe;
 443         enum plane plane;
 444         u8 lut_r[256], lut_g[256], lut_b[256];
 445         /*
 446          * Whether the crtc and the connected output pipeline is active. Implies
 447          * that crtc->enabled is set, i.e. the current mode configuration has
 448          * some outputs connected to this crtc.
 449          */
 450         bool active;
 451         unsigned long enabled_power_domains;
 452         bool primary_enabled; /* is the primary plane (partially) visible? */
 453         bool lowfreq_avail;
 454         struct intel_overlay *overlay;
 455         struct intel_unpin_work *unpin_work;
 456
 457         atomic_t unpin_work_count;
 458
 459         /* Display surface base address adjustement for pageflips. Note that on
 460          * gen4+ this only adjusts up to a tile, offsets within a tile are
 461          * handled in the hw itself (with the TILEOFF register). */
 462         unsigned long dspaddr_offset;
 463
 464         struct drm_i915_gem_object *cursor_bo;
 465         uint32_t cursor_addr;
 466         int16_t cursor_width, cursor_height;
 467         uint32_t cursor_cntl;
 468         uint32_t cursor_size;
 469         uint32_t cursor_base;
 470
 471         struct intel_initial_plane_config plane_config;
 472         struct intel_crtc_state *config;
 473         struct intel_crtc_state *new_config;
 474         bool new_enabled;
 475
 476         /* reset counter value when the last flip was submitted */
 477         unsigned int reset_counter;
 478
 479         /* Access to these should be protected by dev_priv->irq_lock. */
 480         bool cpu_fifo_underrun_disabled;
 481         bool pch_fifo_underrun_disabled;
 482
 483         /* per-pipe watermark state */
 484         struct {
 485                 /* watermarks currently being used  */
 486                 struct intel_pipe_wm active;
 487                 /* SKL wm values currently in use */
 488                 struct skl_pipe_wm skl_active;
 489         } wm;
 490
 491         int scanline_offset;
 492         struct intel_mmio_flip mmio_flip;
 493
 494         struct intel_crtc_atomic_commit atomic;
 495 };
 496
 497 struct intel_plane_wm_parameters {
 498         uint32_t horiz_pixels;
 499         uint32_t vert_pixels;
 500         uint8_t bytes_per_pixel;
 501         bool enabled;
 502         bool scaled;
 503 };
 504
 505 struct intel_plane {
 506         struct drm_plane base;
 507         int plane;
 508         enum pipe pipe;
 509         struct drm_i915_gem_object *obj;
 510         bool can_scale;
 511         int max_downscale;
 512
 513         /* Since we need to change the watermarks before/after
 514          * enabling/disabling the planes, we need to store the parameters here
 515          * as the other pieces of the struct may not reflect the values we want
 516          * for the watermark calculations. Currently only Haswell uses this.
 517          */
 518         struct intel_plane_wm_parameters wm;
 519
 520         /*
 521          * NOTE: Do not place new plane state fields here (e.g., when adding
 522          * new plane properties).  New runtime state should now be placed in
 523          * the intel_plane_state structure and accessed via drm_plane->state.
 524          */
 525
 526         void (*update_plane)(struct drm_plane *plane,
 527                              struct drm_crtc *crtc,
 528                              struct drm_framebuffer *fb,
 529                              struct drm_i915_gem_object *obj,
 530                              int crtc_x, int crtc_y,
 531                              unsigned int crtc_w, unsigned int crtc_h,
 532                              uint32_t x, uint32_t y,
 533                              uint32_t src_w, uint32_t src_h);
 534         void (*disable_plane)(struct drm_plane *plane,
 535                               struct drm_crtc *crtc);
 536         int (*check_plane)(struct drm_plane *plane,
 537                            struct intel_plane_state *state);
 538         void (*commit_plane)(struct drm_plane *plane,
 539                              struct intel_plane_state *state);
 540         int (*update_colorkey)(struct drm_plane *plane,
 541                                struct drm_intel_sprite_colorkey *key);
 542         void (*get_colorkey)(struct drm_plane *plane,
 543                              struct drm_intel_sprite_colorkey *key);
 544 };
 545
 546 struct intel_watermark_params {
 547         unsigned long fifo_size;
 548         unsigned long max_wm;
 549         unsigned long default_wm;
 550         unsigned long guard_size;
 551         unsigned long cacheline_size;
 552 };
 553
 554 struct cxsr_latency {
 555         int is_desktop;
 556         int is_ddr3;
 557         unsigned long fsb_freq;
 558         unsigned long mem_freq;
 559         unsigned long display_sr;
 560         unsigned long display_hpll_disable;
 561         unsigned long cursor_sr;
 562         unsigned long cursor_hpll_disable;
 563 };
 564
 565 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 566 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 567 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 568 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 569 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 570 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 571 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 572
 573 struct intel_hdmi {
 574         u32 hdmi_reg;
 575         int ddc_bus;
 576         uint32_t color_range;
 577         bool color_range_auto;
 578         bool has_hdmi_sink;
 579         bool has_audio;
 580         enum hdmi_force_audio force_audio;
 581         bool rgb_quant_range_selectable;
 582         enum hdmi_picture_aspect aspect_ratio;
 583         void (*write_infoframe)(struct drm_encoder *encoder,
 584                                 enum hdmi_infoframe_type type,
 585                                 const void *frame, ssize_t len);
 586         void (*set_infoframes)(struct drm_encoder *encoder,
 587                                bool enable,
 588                                struct drm_display_mode *adjusted_mode);
 589         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 590 };
 591
 592 struct intel_dp_mst_encoder;
 593 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 594
 595 struct intel_dp {
 596         uint32_t output_reg;
 597         uint32_t aux_ch_ctl_reg;
 598         uint32_t DP;
 599         bool has_audio;
 600         enum hdmi_force_audio force_audio;
 601         uint32_t color_range;
 602         bool color_range_auto;
 603         uint8_t link_bw;
 604         uint8_t lane_count;
 605         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 606         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 607         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 608         struct drm_dp_aux aux;
 609         uint8_t train_set[4];
 610         int panel_power_up_delay;
 611         int panel_power_down_delay;
 612         int panel_power_cycle_delay;
 613         int backlight_on_delay;
 614         int backlight_off_delay;
 615         struct delayed_work panel_vdd_work;
 616         bool want_panel_vdd;
 617         unsigned long last_power_cycle;
 618         unsigned long last_power_on;
 619         unsigned long last_backlight_off;
 620
 621         struct notifier_block edp_notifier;
 622
 623         /*
 624          * Pipe whose power sequencer is currently locked into
 625          * this port. Only relevant on VLV/CHV.
 626          */
 627         enum pipe pps_pipe;
 628         struct edp_power_seq pps_delays;
 629
 630         bool use_tps3;
 631         bool can_mst; /* this port supports mst */
 632         bool is_mst;
 633         int active_mst_links;
 634         /* connector directly attached - won't be use for modeset in mst world */
 635         struct intel_connector *attached_connector;
 636
 637         /* mst connector list */
 638         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 639         struct drm_dp_mst_topology_mgr mst_mgr;
 640
 641         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 642         /*
 643          * This function returns the value we have to program the AUX_CTL
 644          * register with to kick off an AUX transaction.
 645          */
 646         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 647                                      bool has_aux_irq,
 648                                      int send_bytes,
 649                                      uint32_t aux_clock_divider);
 650 };
 651
 652 struct intel_digital_port {
 653         struct intel_encoder base;
 654         enum port port;
 655         u32 saved_port_bits;
 656         struct intel_dp dp;
 657         struct intel_hdmi hdmi;
 658         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 659 };
 660
 661 struct intel_dp_mst_encoder {
 662         struct intel_encoder base;
 663         enum pipe pipe;
 664         struct intel_digital_port *primary;
 665         void *port; /* store this opaque as its illegal to dereference it */
 666 };
 667
 668 static inline int
 669 vlv_dport_to_channel(struct intel_digital_port *dport)
 670 {
 671         switch (dport->port) {
 672         case PORT_B:
 673         case PORT_D:
 674                 return DPIO_CH0;
 675         case PORT_C:
 676                 return DPIO_CH1;
 677         default:
 678                 BUG();
 679         }
 680 }
 681
 682 static inline int
 683 vlv_pipe_to_channel(enum pipe pipe)
 684 {
 685         switch (pipe) {
 686         case PIPE_A:
 687         case PIPE_C:
 688                 return DPIO_CH0;
 689         case PIPE_B:
 690                 return DPIO_CH1;
 691         default:
 692                 BUG();
 693         }
 694 }
 695
 696 static inline struct drm_crtc *
 697 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 698 {
 699         struct drm_i915_private *dev_priv = dev->dev_private;
 700         return dev_priv->pipe_to_crtc_mapping[pipe];
 701 }
 702
 703 static inline struct drm_crtc *
 704 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 705 {
 706         struct drm_i915_private *dev_priv = dev->dev_private;
 707         return dev_priv->plane_to_crtc_mapping[plane];
 708 }
 709
 710 struct intel_unpin_work {
 711         struct work_struct work;
 712         struct drm_crtc *crtc;
 713         struct drm_i915_gem_object *old_fb_obj;
 714         struct drm_i915_gem_object *pending_flip_obj;
 715         struct drm_pending_vblank_event *event;
 716         atomic_t pending;
 717 #define INTEL_FLIP_INACTIVE     0
 718 #define INTEL_FLIP_PENDING      1
 719 #define INTEL_FLIP_COMPLETE     2
 720         u32 flip_count;
 721         u32 gtt_offset;
 722         struct drm_i915_gem_request *flip_queued_req;
 723         int flip_queued_vblank;
 724         int flip_ready_vblank;
 725         bool enable_stall_check;
 726 };
 727
 728 struct intel_set_config {
 729         struct drm_encoder **save_connector_encoders;
 730         struct drm_crtc **save_encoder_crtcs;
 731         bool *save_crtc_enabled;
 732
 733         bool fb_changed;
 734         bool mode_changed;
 735 };
 736
 737 struct intel_load_detect_pipe {
 738         struct drm_framebuffer *release_fb;
 739         bool load_detect_temp;
 740         int dpms_mode;
 741 };
 742
 743 static inline struct intel_encoder *
 744 intel_attached_encoder(struct drm_connector *connector)
 745 {
 746         return to_intel_connector(connector)->encoder;
 747 }
 748
 749 static inline struct intel_digital_port *
 750 enc_to_dig_port(struct drm_encoder *encoder)
 751 {
 752         return container_of(encoder, struct intel_digital_port, base.base);
 753 }
 754
 755 static inline struct intel_dp_mst_encoder *
 756 enc_to_mst(struct drm_encoder *encoder)
 757 {
 758         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 759 }
 760
 761 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 762 {
 763         return &enc_to_dig_port(encoder)->dp;
 764 }
 765
 766 static inline struct intel_digital_port *
 767 dp_to_dig_port(struct intel_dp *intel_dp)
 768 {
 769         return container_of(intel_dp, struct intel_digital_port, dp);
 770 }
 771
 772 static inline struct intel_digital_port *
 773 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 774 {
 775         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 776 }
 777
 778 /*
 779  * Returns the number of planes for this pipe, ie the number of sprites + 1
 780  * (primary plane). This doesn't count the cursor plane then.
 781  */
 782 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 783 {
 784         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 785 }
 786
 787 /* intel_fifo_underrun.c */
 788 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 789                                            enum pipe pipe, bool enable);
 790 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 791                                            enum transcoder pch_transcoder,
 792                                            bool enable);
 793 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 794                                          enum pipe pipe);
 795 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 796                                          enum transcoder pch_transcoder);
 797 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 798
 799 /* i915_irq.c */
 800 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 801 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 802 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 803 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 804 void gen6_reset_rps_interrupts(struct drm_device *dev);
 805 void gen6_enable_rps_interrupts(struct drm_device *dev);
 806 void gen6_disable_rps_interrupts(struct drm_device *dev);
 807 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 808 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 809 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 810 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 811 {
 812         /*
 813          * We only use drm_irq_uninstall() at unload and VT switch, so
 814          * this is the only thing we need to check.
 815          */
 816         return dev_priv->pm.irqs_enabled;
 817 }
 818
 819 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 820 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
 821
 822 /* intel_crt.c */
 823 void intel_crt_init(struct drm_device *dev);
 824
 825
 826 /* intel_ddi.c */
 827 void intel_prepare_ddi(struct drm_device *dev);
 828 void hsw_fdi_link_train(struct drm_crtc *crtc);
 829 void intel_ddi_init(struct drm_device *dev, enum port port);
 830 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 831 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 832 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 833 void intel_ddi_pll_init(struct drm_device *dev);
 834 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 835 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 836                                        enum transcoder cpu_transcoder);
 837 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 838 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 839 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 840                           struct intel_crtc_state *crtc_state);
 841 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 842 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 843 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 844 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 845 void intel_ddi_get_config(struct intel_encoder *encoder,
 846                           struct intel_crtc_state *pipe_config);
 847
 848 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 849 void intel_ddi_clock_get(struct intel_encoder *encoder,
 850                          struct intel_crtc_state *pipe_config);
 851 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 852
 853 /* intel_frontbuffer.c */
 854 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 855                              struct intel_engine_cs *ring);
 856 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 857                                     unsigned frontbuffer_bits);
 858 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 859                                      unsigned frontbuffer_bits);
 860 void intel_frontbuffer_flush(struct drm_device *dev,
 861                              unsigned frontbuffer_bits);
 862 /**
 863  * intel_frontbuffer_flip - synchronous frontbuffer flip
 864  * @dev: DRM device
 865  * @frontbuffer_bits: frontbuffer plane tracking bits
 866  *
 867  * This function gets called after scheduling a flip on @obj. This is for
 868  * synchronous plane updates which will happen on the next vblank and which will
 869  * not get delayed by pending gpu rendering.
 870  *
 871  * Can be called without any locks held.
 872  */
 873 static inline
 874 void intel_frontbuffer_flip(struct drm_device *dev,
 875                             unsigned frontbuffer_bits)
 876 {
 877         intel_frontbuffer_flush(dev, frontbuffer_bits);
 878 }
 879
 880 int intel_fb_align_height(struct drm_device *dev, int height,
 881                           unsigned int tiling);
 882 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 883
 884
 885 /* intel_audio.c */
 886 void intel_init_audio(struct drm_device *dev);
 887 void intel_audio_codec_enable(struct intel_encoder *encoder);
 888 void intel_audio_codec_disable(struct intel_encoder *encoder);
 889 void i915_audio_component_init(struct drm_i915_private *dev_priv);
 890 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
 891
 892 /* intel_display.c */
 893 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 894 int intel_pch_rawclk(struct drm_device *dev);
 895 void intel_mark_busy(struct drm_device *dev);
 896 void intel_mark_idle(struct drm_device *dev);
 897 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 898 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
 899 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 900 void intel_encoder_destroy(struct drm_encoder *encoder);
 901 void intel_connector_dpms(struct drm_connector *, int mode);
 902 bool intel_connector_get_hw_state(struct intel_connector *connector);
 903 void intel_modeset_check_state(struct drm_device *dev);
 904 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 905                                 struct intel_digital_port *port);
 906 void intel_connector_attach_encoder(struct intel_connector *connector,
 907                                     struct intel_encoder *encoder);
 908 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 909 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 910                                              struct drm_crtc *crtc);
 911 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 912 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 913                                 struct drm_file *file_priv);
 914 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 915                                              enum pipe pipe);
 916 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
 917 static inline void
 918 intel_wait_for_vblank(struct drm_device *dev, int pipe)
 919 {
 920         drm_wait_one_vblank(dev, pipe);
 921 }
 922 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 923 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 924                          struct intel_digital_port *dport);
 925 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 926                                 struct drm_display_mode *mode,
 927                                 struct intel_load_detect_pipe *old,
 928                                 struct drm_modeset_acquire_ctx *ctx);
 929 void intel_release_load_detect_pipe(struct drm_connector *connector,
 930                                     struct intel_load_detect_pipe *old);
 931 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 932                                struct drm_framebuffer *fb,
 933                                struct intel_engine_cs *pipelined);
 934 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 935 struct drm_framebuffer *
 936 __intel_framebuffer_create(struct drm_device *dev,
 937                            struct drm_mode_fb_cmd2 *mode_cmd,
 938                            struct drm_i915_gem_object *obj);
 939 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 940 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 941 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 942 void intel_check_page_flip(struct drm_device *dev, int pipe);
 943 int intel_prepare_plane_fb(struct drm_plane *plane,
 944                            struct drm_framebuffer *fb);
 945 void intel_cleanup_plane_fb(struct drm_plane *plane,
 946                             struct drm_framebuffer *fb);
 947
 948 /* shared dpll functions */
 949 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 950 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 951                         struct intel_shared_dpll *pll,
 952                         bool state);
 953 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 954 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 955 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 956                                                 struct intel_crtc_state *state);
 957 void intel_put_shared_dpll(struct intel_crtc *crtc);
 958
 959 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
 960                       const struct dpll *dpll);
 961 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
 962
 963 /* modesetting asserts */
 964 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 965                            enum pipe pipe);
 966 void assert_pll(struct drm_i915_private *dev_priv,
 967                 enum pipe pipe, bool state);
 968 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 969 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 970 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 971                        enum pipe pipe, bool state);
 972 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 973 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 974 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 975 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 976 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 977 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 978                                              unsigned int tiling_mode,
 979                                              unsigned int bpp,
 980                                              unsigned int pitch);
 981 void intel_prepare_reset(struct drm_device *dev);
 982 void intel_finish_reset(struct drm_device *dev);
 983 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 984 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 985 void intel_dp_get_m_n(struct intel_crtc *crtc,
 986                       struct intel_crtc_state *pipe_config);
 987 void intel_dp_set_m_n(struct intel_crtc *crtc);
 988 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 989 void
 990 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
 991                                 int dotclock);
 992 bool intel_crtc_active(struct drm_crtc *crtc);
 993 void hsw_enable_ips(struct intel_crtc *crtc);
 994 void hsw_disable_ips(struct intel_crtc *crtc);
 995 enum intel_display_power_domain
 996 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 997 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 998                                  struct intel_crtc_state *pipe_config);
 999 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1000 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1001
1002 /* intel_dp.c */
1003 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1004 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1005                              struct intel_connector *intel_connector);
1006 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1007 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1008 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1009 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1010 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1011 void intel_dp_check_link_status(struct intel_dp *intel_dp);
1012 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1013 bool intel_dp_compute_config(struct intel_encoder *encoder,
1014                              struct intel_crtc_state *pipe_config);
1015 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1016 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1017                                   bool long_hpd);
1018 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1019 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1020 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1021 void intel_edp_panel_on(struct intel_dp *intel_dp);
1022 void intel_edp_panel_off(struct intel_dp *intel_dp);
1023 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1024 void intel_dp_mst_suspend(struct drm_device *dev);
1025 void intel_dp_mst_resume(struct drm_device *dev);
1026 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
1027 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1028 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1029 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1030 void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes);
1031 int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
1032                        struct drm_framebuffer *fb, int crtc_x, int crtc_y,
1033                        unsigned int crtc_w, unsigned int crtc_h,
1034                        uint32_t src_x, uint32_t src_y,
1035                        uint32_t src_w, uint32_t src_h);
1036 int intel_disable_plane(struct drm_plane *plane);
1037 void intel_plane_destroy(struct drm_plane *plane);
1038 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1039 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1040 void intel_edp_drrs_invalidate(struct drm_device *dev,
1041                 unsigned frontbuffer_bits);
1042 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1043
1044 /* intel_dp_mst.c */
1045 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1046 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1047 /* intel_dsi.c */
1048 void intel_dsi_init(struct drm_device *dev);
1049
1050
1051 /* intel_dvo.c */
1052 void intel_dvo_init(struct drm_device *dev);
1053
1054
1055 /* legacy fbdev emulation in intel_fbdev.c */
1056 #ifdef CONFIG_DRM_I915_FBDEV
1057 extern int intel_fbdev_init(struct drm_device *dev);
1058 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1059 extern void intel_fbdev_fini(struct drm_device *dev);
1060 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1061 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1062 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1063 #else
1064 static inline int intel_fbdev_init(struct drm_device *dev)
1065 {
1066         return 0;
1067 }
1068
1069 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1070 {
1071 }
1072
1073 static inline void intel_fbdev_fini(struct drm_device *dev)
1074 {
1075 }
1076
1077 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1078 {
1079 }
1080
1081 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1082 {
1083 }
1084 #endif
1085
1086 /* intel_fbc.c */
1087 bool intel_fbc_enabled(struct drm_device *dev);
1088 void intel_fbc_update(struct drm_device *dev);
1089 void intel_fbc_init(struct drm_i915_private *dev_priv);
1090 void intel_fbc_disable(struct drm_device *dev);
1091 void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
1092
1093 /* intel_hdmi.c */
1094 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1095 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1096                                struct intel_connector *intel_connector);
1097 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1098 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1099                                struct intel_crtc_state *pipe_config);
1100
1101
1102 /* intel_lvds.c */
1103 void intel_lvds_init(struct drm_device *dev);
1104 bool intel_is_dual_link_lvds(struct drm_device *dev);
1105
1106
1107 /* intel_modes.c */
1108 int intel_connector_update_modes(struct drm_connector *connector,
1109                                  struct edid *edid);
1110 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1111 void intel_attach_force_audio_property(struct drm_connector *connector);
1112 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1113
1114
1115 /* intel_overlay.c */
1116 void intel_setup_overlay(struct drm_device *dev);
1117 void intel_cleanup_overlay(struct drm_device *dev);
1118 int intel_overlay_switch_off(struct intel_overlay *overlay);
1119 int intel_overlay_put_image(struct drm_device *dev, void *data,
1120                             struct drm_file *file_priv);
1121 int intel_overlay_attrs(struct drm_device *dev, void *data,
1122                         struct drm_file *file_priv);
1123 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1124
1125
1126 /* intel_panel.c */
1127 int intel_panel_init(struct intel_panel *panel,
1128                      struct drm_display_mode *fixed_mode,
1129                      struct drm_display_mode *downclock_mode);
1130 void intel_panel_fini(struct intel_panel *panel);
1131 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1132                             struct drm_display_mode *adjusted_mode);
1133 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1134                              struct intel_crtc_state *pipe_config,
1135                              int fitting_mode);
1136 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1137                               struct intel_crtc_state *pipe_config,
1138                               int fitting_mode);
1139 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1140                                     u32 level, u32 max);
1141 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1142 void intel_panel_enable_backlight(struct intel_connector *connector);
1143 void intel_panel_disable_backlight(struct intel_connector *connector);
1144 void intel_panel_destroy_backlight(struct drm_connector *connector);
1145 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1146 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1147 extern struct drm_display_mode *intel_find_panel_downclock(
1148                                 struct drm_device *dev,
1149                                 struct drm_display_mode *fixed_mode,
1150                                 struct drm_connector *connector);
1151 void intel_backlight_register(struct drm_device *dev);
1152 void intel_backlight_unregister(struct drm_device *dev);
1153
1154
1155 /* intel_psr.c */
1156 void intel_psr_enable(struct intel_dp *intel_dp);
1157 void intel_psr_disable(struct intel_dp *intel_dp);
1158 void intel_psr_invalidate(struct drm_device *dev,
1159                               unsigned frontbuffer_bits);
1160 void intel_psr_flush(struct drm_device *dev,
1161                          unsigned frontbuffer_bits);
1162 void intel_psr_init(struct drm_device *dev);
1163
1164 /* intel_runtime_pm.c */
1165 int intel_power_domains_init(struct drm_i915_private *);
1166 void intel_power_domains_fini(struct drm_i915_private *);
1167 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1168 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1169
1170 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1171                                     enum intel_display_power_domain domain);
1172 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1173                                       enum intel_display_power_domain domain);
1174 void intel_display_power_get(struct drm_i915_private *dev_priv,
1175                              enum intel_display_power_domain domain);
1176 void intel_display_power_put(struct drm_i915_private *dev_priv,
1177                              enum intel_display_power_domain domain);
1178 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1179 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1180 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1181 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1182 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1183
1184 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1185
1186 /* intel_pm.c */
1187 void intel_init_clock_gating(struct drm_device *dev);
1188 void intel_suspend_hw(struct drm_device *dev);
1189 int ilk_wm_max_level(const struct drm_device *dev);
1190 void intel_update_watermarks(struct drm_crtc *crtc);
1191 void intel_update_sprite_watermarks(struct drm_plane *plane,
1192                                     struct drm_crtc *crtc,
1193                                     uint32_t sprite_width,
1194                                     uint32_t sprite_height,
1195                                     int pixel_size,
1196                                     bool enabled, bool scaled);
1197 void intel_init_pm(struct drm_device *dev);
1198 void intel_pm_setup(struct drm_device *dev);
1199 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1200 void intel_gpu_ips_teardown(void);
1201 void intel_init_gt_powersave(struct drm_device *dev);
1202 void intel_cleanup_gt_powersave(struct drm_device *dev);
1203 void intel_enable_gt_powersave(struct drm_device *dev);
1204 void intel_disable_gt_powersave(struct drm_device *dev);
1205 void intel_suspend_gt_powersave(struct drm_device *dev);
1206 void intel_reset_gt_powersave(struct drm_device *dev);
1207 void ironlake_teardown_rc6(struct drm_device *dev);
1208 void gen6_update_ring_freq(struct drm_device *dev);
1209 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1210 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1211 void ilk_wm_get_hw_state(struct drm_device *dev);
1212 void skl_wm_get_hw_state(struct drm_device *dev);
1213 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1214                           struct skl_ddb_allocation *ddb /* out */);
1215
1216
1217 /* intel_sdvo.c */
1218 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1219
1220
1221 /* intel_sprite.c */
1222 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1223 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1224                                enum plane plane);
1225 int intel_plane_set_property(struct drm_plane *plane,
1226                              struct drm_property *prop,
1227                              uint64_t val);
1228 int intel_plane_restore(struct drm_plane *plane);
1229 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1230                               struct drm_file *file_priv);
1231 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1232                               struct drm_file *file_priv);
1233 bool intel_pipe_update_start(struct intel_crtc *crtc,
1234                              uint32_t *start_vbl_count);
1235 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1236 void intel_post_enable_primary(struct drm_crtc *crtc);
1237 void intel_pre_disable_primary(struct drm_crtc *crtc);
1238
1239 /* intel_tv.c */
1240 void intel_tv_init(struct drm_device *dev);
1241
1242 /* intel_atomic.c */
1243 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1244 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1245 void intel_plane_destroy_state(struct drm_plane *plane,
1246                                struct drm_plane_state *state);
1247 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1248
1249 #endif /* __INTEL_DRV_H__ */