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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
32 #include "i915_drv.h"
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38
39 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
40 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
41
42 /**
43 * _wait_for - magic (register) wait macro
44 *
45 * Does the right thing for modeset paths when run under kdgb or similar atomic
46 * contexts. Note that it's important that we check the condition again after
47 * having timed out, since the timeout could be due to preemption or similar and
48 * we've never had a chance to check the condition before the timeout.
49 */
50 #define _wait_for(COND, MS, W) ({ \
51 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
52 int ret__ = 0; \
53 while (!(COND)) { \
54 if (time_after(jiffies, timeout__)) { \
55 if (!(COND)) \
56 ret__ = -ETIMEDOUT; \
57 break; \
58 } \
59 if (W && drm_can_sleep()) { \
60 msleep(W); \
61 } else { \
62 cpu_relax(); \
63 } \
64 } \
65 ret__; \
66 })
67
68 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
69 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
70 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
71 DIV_ROUND_UP((US), 1000), 0)
72
73 #define KHz(x) (1000 * (x))
74 #define MHz(x) KHz(1000 * (x))
75
76 /*
77 * Display related stuff
78 */
79
80 /* store information about an Ixxx DVO */
81 /* The i830->i865 use multiple DVOs with multiple i2cs */
82 /* the i915, i945 have a single sDVO i2c bus - which is different */
83 #define MAX_OUTPUTS 6
84 /* maximum connectors per crtcs in the mode set */
85
86 /* Maximum cursor sizes */
87 #define GEN2_CURSOR_WIDTH 64
88 #define GEN2_CURSOR_HEIGHT 64
89 #define MAX_CURSOR_WIDTH 256
90 #define MAX_CURSOR_HEIGHT 256
91
92 #define INTEL_I2C_BUS_DVO 1
93 #define INTEL_I2C_BUS_SDVO 2
94
95 /* these are outputs from the chip - integrated only
96 external chips are via DVO or SDVO output */
97 enum intel_output_type {
98 INTEL_OUTPUT_UNUSED = 0,
99 INTEL_OUTPUT_ANALOG = 1,
100 INTEL_OUTPUT_DVO = 2,
101 INTEL_OUTPUT_SDVO = 3,
102 INTEL_OUTPUT_LVDS = 4,
103 INTEL_OUTPUT_TVOUT = 5,
104 INTEL_OUTPUT_HDMI = 6,
105 INTEL_OUTPUT_DISPLAYPORT = 7,
106 INTEL_OUTPUT_EDP = 8,
107 INTEL_OUTPUT_DSI = 9,
108 INTEL_OUTPUT_UNKNOWN = 10,
109 INTEL_OUTPUT_DP_MST = 11,
110 };
111
112 #define INTEL_DVO_CHIP_NONE 0
113 #define INTEL_DVO_CHIP_LVDS 1
114 #define INTEL_DVO_CHIP_TMDS 2
115 #define INTEL_DVO_CHIP_TVOUT 4
116
117 #define INTEL_DSI_VIDEO_MODE 0
118 #define INTEL_DSI_COMMAND_MODE 1
119
120 struct intel_framebuffer {
121 struct drm_framebuffer base;
122 struct drm_i915_gem_object *obj;
123 };
124
125 struct intel_fbdev {
126 struct drm_fb_helper helper;
127 struct intel_framebuffer *fb;
128 struct list_head fbdev_list;
129 struct drm_display_mode *our_mode;
130 int preferred_bpp;
131 };
132
133 struct intel_encoder {
134 struct drm_encoder base;
135 /*
136 * The new crtc this encoder will be driven from. Only differs from
137 * base->crtc while a modeset is in progress.
138 */
139 struct intel_crtc *new_crtc;
140
141 enum intel_output_type type;
142 unsigned int cloneable;
143 bool connectors_active;
144 void (*hot_plug)(struct intel_encoder *);
145 bool (*compute_config)(struct intel_encoder *,
146 struct intel_crtc_state *);
147 void (*pre_pll_enable)(struct intel_encoder *);
148 void (*pre_enable)(struct intel_encoder *);
149 void (*enable)(struct intel_encoder *);
150 void (*mode_set)(struct intel_encoder *intel_encoder);
151 void (*disable)(struct intel_encoder *);
152 void (*post_disable)(struct intel_encoder *);
153 /* Read out the current hw state of this connector, returning true if
154 * the encoder is active. If the encoder is enabled it also set the pipe
155 * it is connected to in the pipe parameter. */
156 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
157 /* Reconstructs the equivalent mode flags for the current hardware
158 * state. This must be called _after_ display->get_pipe_config has
159 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
160 * be set correctly before calling this function. */
161 void (*get_config)(struct intel_encoder *,
162 struct intel_crtc_state *pipe_config);
163 /*
164 * Called during system suspend after all pending requests for the
165 * encoder are flushed (for example for DP AUX transactions) and
166 * device interrupts are disabled.
167 */
168 void (*suspend)(struct intel_encoder *);
169 int crtc_mask;
170 enum hpd_pin hpd_pin;
171 };
172
173 struct intel_panel {
174 struct drm_display_mode *fixed_mode;
175 struct drm_display_mode *downclock_mode;
176 int fitting_mode;
177
178 /* backlight */
179 struct {
180 bool present;
181 u32 level;
182 u32 min;
183 u32 max;
184 bool enabled;
185 bool combination_mode; /* gen 2/4 only */
186 bool active_low_pwm;
187 struct backlight_device *device;
188 } backlight;
189
190 void (*backlight_power)(struct intel_connector *, bool enable);
191 };
192
193 struct intel_connector {
194 struct drm_connector base;
195 /*
196 * The fixed encoder this connector is connected to.
197 */
198 struct intel_encoder *encoder;
199
200 /*
201 * The new encoder this connector will be driven. Only differs from
202 * encoder while a modeset is in progress.
203 */
204 struct intel_encoder *new_encoder;
205
206 /* Reads out the current hw, returning true if the connector is enabled
207 * and active (i.e. dpms ON state). */
208 bool (*get_hw_state)(struct intel_connector *);
209
210 /*
211 * Removes all interfaces through which the connector is accessible
212 * - like sysfs, debugfs entries -, so that no new operations can be
213 * started on the connector. Also makes sure all currently pending
214 * operations finish before returing.
215 */
216 void (*unregister)(struct intel_connector *);
217
218 /* Panel info for eDP and LVDS */
219 struct intel_panel panel;
220
221 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
222 struct edid *edid;
223 struct edid *detect_edid;
224
225 /* since POLL and HPD connectors may use the same HPD line keep the native
226 state of connector->polled in case hotplug storm detection changes it */
227 u8 polled;
228
229 void *port; /* store this opaque as its illegal to dereference it */
230
231 struct intel_dp *mst_port;
232 };
233
234 typedef struct dpll {
235 /* given values */
236 int n;
237 int m1, m2;
238 int p1, p2;
239 /* derived values */
240 int dot;
241 int vco;
242 int m;
243 int p;
244 } intel_clock_t;
245
246 struct intel_plane_state {
247 struct drm_plane_state base;
248 struct drm_rect src;
249 struct drm_rect dst;
250 struct drm_rect clip;
251 bool visible;
252
253 /*
254 * used only for sprite planes to determine when to implicitly
255 * enable/disable the primary plane
256 */
257 bool hides_primary;
258 };
259
260 struct intel_initial_plane_config {
261 struct intel_framebuffer *fb;
262 unsigned int tiling;
263 int size;
264 u32 base;
265 };
266
267 struct intel_crtc_state {
268 struct drm_crtc_state base;
269
270 /**
271 * quirks - bitfield with hw state readout quirks
272 *
273 * For various reasons the hw state readout code might not be able to
274 * completely faithfully read out the current state. These cases are
275 * tracked with quirk flags so that fastboot and state checker can act
276 * accordingly.
277 */
278 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
279 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
280 unsigned long quirks;
281
282 /* Pipe source size (ie. panel fitter input size)
283 * All planes will be positioned inside this space,
284 * and get clipped at the edges. */
285 int pipe_src_w, pipe_src_h;
286
287 /* Whether to set up the PCH/FDI. Note that we never allow sharing
288 * between pch encoders and cpu encoders. */
289 bool has_pch_encoder;
290
291 /* Are we sending infoframes on the attached port */
292 bool has_infoframe;
293
294 /* CPU Transcoder for the pipe. Currently this can only differ from the
295 * pipe on Haswell (where we have a special eDP transcoder). */
296 enum transcoder cpu_transcoder;
297
298 /*
299 * Use reduced/limited/broadcast rbg range, compressing from the full
300 * range fed into the crtcs.
301 */
302 bool limited_color_range;
303
304 /* DP has a bunch of special case unfortunately, so mark the pipe
305 * accordingly. */
306 bool has_dp_encoder;
307
308 /* Whether we should send NULL infoframes. Required for audio. */
309 bool has_hdmi_sink;
310
311 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
312 * has_dp_encoder is set. */
313 bool has_audio;
314
315 /*
316 * Enable dithering, used when the selected pipe bpp doesn't match the
317 * plane bpp.
318 */
319 bool dither;
320
321 /* Controls for the clock computation, to override various stages. */
322 bool clock_set;
323
324 /* SDVO TV has a bunch of special case. To make multifunction encoders
325 * work correctly, we need to track this at runtime.*/
326 bool sdvo_tv_clock;
327
328 /*
329 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
330 * required. This is set in the 2nd loop of calling encoder's
331 * ->compute_config if the first pick doesn't work out.
332 */
333 bool bw_constrained;
334
335 /* Settings for the intel dpll used on pretty much everything but
336 * haswell. */
337 struct dpll dpll;
338
339 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
340 enum intel_dpll_id shared_dpll;
341
342 /*
343 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
344 * - enum skl_dpll on SKL
345 */
346 uint32_t ddi_pll_sel;
347
348 /* Actual register state of the dpll, for shared dpll cross-checking. */
349 struct intel_dpll_hw_state dpll_hw_state;
350
351 int pipe_bpp;
352 struct intel_link_m_n dp_m_n;
353
354 /* m2_n2 for eDP downclock */
355 struct intel_link_m_n dp_m2_n2;
356 bool has_drrs;
357
358 /*
359 * Frequence the dpll for the port should run at. Differs from the
360 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
361 * already multiplied by pixel_multiplier.
362 */
363 int port_clock;
364
365 /* Used by SDVO (and if we ever fix it, HDMI). */
366 unsigned pixel_multiplier;
367
368 /* Panel fitter controls for gen2-gen4 + VLV */
369 struct {
370 u32 control;
371 u32 pgm_ratios;
372 u32 lvds_border_bits;
373 } gmch_pfit;
374
375 /* Panel fitter placement and size for Ironlake+ */
376 struct {
377 u32 pos;
378 u32 size;
379 bool enabled;
380 bool force_thru;
381 } pch_pfit;
382
383 /* FDI configuration, only valid if has_pch_encoder is set. */
384 int fdi_lanes;
385 struct intel_link_m_n fdi_m_n;
386
387 bool ips_enabled;
388
389 bool double_wide;
390
391 bool dp_encoder_is_mst;
392 int pbn;
393 };
394
395 struct intel_pipe_wm {
396 struct intel_wm_level wm[5];
397 uint32_t linetime;
398 bool fbc_wm_enabled;
399 bool pipe_enabled;
400 bool sprites_enabled;
401 bool sprites_scaled;
402 };
403
404 struct intel_mmio_flip {
405 struct drm_i915_gem_request *req;
406 struct work_struct work;
407 };
408
409 struct skl_pipe_wm {
410 struct skl_wm_level wm[8];
411 struct skl_wm_level trans_wm;
412 uint32_t linetime;
413 };
414
415 /*
416 * Tracking of operations that need to be performed at the beginning/end of an
417 * atomic commit, outside the atomic section where interrupts are disabled.
418 * These are generally operations that grab mutexes or might otherwise sleep
419 * and thus can't be run with interrupts disabled.
420 */
421 struct intel_crtc_atomic_commit {
422 /* vblank evasion */
423 bool evade;
424 unsigned start_vbl_count;
425
426 /* Sleepable operations to perform before commit */
427 bool wait_for_flips;
428 bool disable_fbc;
429 bool pre_disable_primary;
430 bool update_wm;
431 unsigned disabled_planes;
432
433 /* Sleepable operations to perform after commit */
434 unsigned fb_bits;
435 bool wait_vblank;
436 bool update_fbc;
437 bool post_enable_primary;
438 unsigned update_sprite_watermarks;
439 };
440
441 struct intel_crtc {
442 struct drm_crtc base;
443 enum pipe pipe;
444 enum plane plane;
445 u8 lut_r[256], lut_g[256], lut_b[256];
446 /*
447 * Whether the crtc and the connected output pipeline is active. Implies
448 * that crtc->enabled is set, i.e. the current mode configuration has
449 * some outputs connected to this crtc.
450 */
451 bool active;
452 unsigned long enabled_power_domains;
453 bool primary_enabled; /* is the primary plane (partially) visible? */
454 bool lowfreq_avail;
455 struct intel_overlay *overlay;
456 struct intel_unpin_work *unpin_work;
457
458 atomic_t unpin_work_count;
459
460 /* Display surface base address adjustement for pageflips. Note that on
461 * gen4+ this only adjusts up to a tile, offsets within a tile are
462 * handled in the hw itself (with the TILEOFF register). */
463 unsigned long dspaddr_offset;
464
465 struct drm_i915_gem_object *cursor_bo;
466 uint32_t cursor_addr;
467 uint32_t cursor_cntl;
468 uint32_t cursor_size;
469 uint32_t cursor_base;
470
471 struct intel_initial_plane_config plane_config;
472 struct intel_crtc_state *config;
473 struct intel_crtc_state *new_config;
474 bool new_enabled;
475
476 /* reset counter value when the last flip was submitted */
477 unsigned int reset_counter;
478
479 /* Access to these should be protected by dev_priv->irq_lock. */
480 bool cpu_fifo_underrun_disabled;
481 bool pch_fifo_underrun_disabled;
482
483 /* per-pipe watermark state */
484 struct {
485 /* watermarks currently being used */
486 struct intel_pipe_wm active;
487 /* SKL wm values currently in use */
488 struct skl_pipe_wm skl_active;
489 } wm;
490
491 int scanline_offset;
492 struct intel_mmio_flip mmio_flip;
493
494 struct intel_crtc_atomic_commit atomic;
495 };
496
497 struct intel_plane_wm_parameters {
498 uint32_t horiz_pixels;
499 uint32_t vert_pixels;
500 uint8_t bytes_per_pixel;
501 bool enabled;
502 bool scaled;
503 u64 tiling;
504 };
505
506 struct intel_plane {
507 struct drm_plane base;
508 int plane;
509 enum pipe pipe;
510 struct drm_i915_gem_object *obj;
511 bool can_scale;
512 int max_downscale;
513
514 /* Since we need to change the watermarks before/after
515 * enabling/disabling the planes, we need to store the parameters here
516 * as the other pieces of the struct may not reflect the values we want
517 * for the watermark calculations. Currently only Haswell uses this.
518 */
519 struct intel_plane_wm_parameters wm;
520
521 /*
522 * NOTE: Do not place new plane state fields here (e.g., when adding
523 * new plane properties). New runtime state should now be placed in
524 * the intel_plane_state structure and accessed via drm_plane->state.
525 */
526
527 void (*update_plane)(struct drm_plane *plane,
528 struct drm_crtc *crtc,
529 struct drm_framebuffer *fb,
530 struct drm_i915_gem_object *obj,
531 int crtc_x, int crtc_y,
532 unsigned int crtc_w, unsigned int crtc_h,
533 uint32_t x, uint32_t y,
534 uint32_t src_w, uint32_t src_h);
535 void (*disable_plane)(struct drm_plane *plane,
536 struct drm_crtc *crtc);
537 int (*check_plane)(struct drm_plane *plane,
538 struct intel_plane_state *state);
539 void (*commit_plane)(struct drm_plane *plane,
540 struct intel_plane_state *state);
541 int (*update_colorkey)(struct drm_plane *plane,
542 struct drm_intel_sprite_colorkey *key);
543 void (*get_colorkey)(struct drm_plane *plane,
544 struct drm_intel_sprite_colorkey *key);
545 };
546
547 struct intel_watermark_params {
548 unsigned long fifo_size;
549 unsigned long max_wm;
550 unsigned long default_wm;
551 unsigned long guard_size;
552 unsigned long cacheline_size;
553 };
554
555 struct cxsr_latency {
556 int is_desktop;
557 int is_ddr3;
558 unsigned long fsb_freq;
559 unsigned long mem_freq;
560 unsigned long display_sr;
561 unsigned long display_hpll_disable;
562 unsigned long cursor_sr;
563 unsigned long cursor_hpll_disable;
564 };
565
566 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
567 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
568 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
569 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
570 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
571 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
572 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
573
574 struct intel_hdmi {
575 u32 hdmi_reg;
576 int ddc_bus;
577 uint32_t color_range;
578 bool color_range_auto;
579 bool has_hdmi_sink;
580 bool has_audio;
581 enum hdmi_force_audio force_audio;
582 bool rgb_quant_range_selectable;
583 enum hdmi_picture_aspect aspect_ratio;
584 void (*write_infoframe)(struct drm_encoder *encoder,
585 enum hdmi_infoframe_type type,
586 const void *frame, ssize_t len);
587 void (*set_infoframes)(struct drm_encoder *encoder,
588 bool enable,
589 struct drm_display_mode *adjusted_mode);
590 bool (*infoframe_enabled)(struct drm_encoder *encoder);
591 };
592
593 struct intel_dp_mst_encoder;
594 #define DP_MAX_DOWNSTREAM_PORTS 0x10
595
596 /*
597 * enum link_m_n_set:
598 * When platform provides two set of M_N registers for dp, we can
599 * program them and switch between them incase of DRRS.
600 * But When only one such register is provided, we have to program the
601 * required divider value on that registers itself based on the DRRS state.
602 *
603 * M1_N1 : Program dp_m_n on M1_N1 registers
604 * dp_m2_n2 on M2_N2 registers (If supported)
605 *
606 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
607 * M2_N2 registers are not supported
608 */
609
610 enum link_m_n_set {
611 /* Sets the m1_n1 and m2_n2 */
612 M1_N1 = 0,
613 M2_N2
614 };
615
616 struct intel_dp {
617 uint32_t output_reg;
618 uint32_t aux_ch_ctl_reg;
619 uint32_t DP;
620 bool has_audio;
621 enum hdmi_force_audio force_audio;
622 uint32_t color_range;
623 bool color_range_auto;
624 uint8_t link_bw;
625 uint8_t rate_select;
626 uint8_t lane_count;
627 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
628 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
629 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
630 uint8_t num_supported_rates;
631 int supported_rates[DP_MAX_SUPPORTED_RATES];
632 struct drm_dp_aux aux;
633 uint8_t train_set[4];
634 int panel_power_up_delay;
635 int panel_power_down_delay;
636 int panel_power_cycle_delay;
637 int backlight_on_delay;
638 int backlight_off_delay;
639 struct delayed_work panel_vdd_work;
640 bool want_panel_vdd;
641 unsigned long last_power_cycle;
642 unsigned long last_power_on;
643 unsigned long last_backlight_off;
644
645 struct notifier_block edp_notifier;
646
647 /*
648 * Pipe whose power sequencer is currently locked into
649 * this port. Only relevant on VLV/CHV.
650 */
651 enum pipe pps_pipe;
652 struct edp_power_seq pps_delays;
653
654 bool use_tps3;
655 bool can_mst; /* this port supports mst */
656 bool is_mst;
657 int active_mst_links;
658 /* connector directly attached - won't be use for modeset in mst world */
659 struct intel_connector *attached_connector;
660
661 /* mst connector list */
662 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
663 struct drm_dp_mst_topology_mgr mst_mgr;
664
665 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
666 /*
667 * This function returns the value we have to program the AUX_CTL
668 * register with to kick off an AUX transaction.
669 */
670 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
671 bool has_aux_irq,
672 int send_bytes,
673 uint32_t aux_clock_divider);
674 };
675
676 struct intel_digital_port {
677 struct intel_encoder base;
678 enum port port;
679 u32 saved_port_bits;
680 struct intel_dp dp;
681 struct intel_hdmi hdmi;
682 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
683 };
684
685 struct intel_dp_mst_encoder {
686 struct intel_encoder base;
687 enum pipe pipe;
688 struct intel_digital_port *primary;
689 void *port; /* store this opaque as its illegal to dereference it */
690 };
691
692 static inline int
693 vlv_dport_to_channel(struct intel_digital_port *dport)
694 {
695 switch (dport->port) {
696 case PORT_B:
697 case PORT_D:
698 return DPIO_CH0;
699 case PORT_C:
700 return DPIO_CH1;
701 default:
702 BUG();
703 }
704 }
705
706 static inline int
707 vlv_pipe_to_channel(enum pipe pipe)
708 {
709 switch (pipe) {
710 case PIPE_A:
711 case PIPE_C:
712 return DPIO_CH0;
713 case PIPE_B:
714 return DPIO_CH1;
715 default:
716 BUG();
717 }
718 }
719
720 static inline struct drm_crtc *
721 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
722 {
723 struct drm_i915_private *dev_priv = dev->dev_private;
724 return dev_priv->pipe_to_crtc_mapping[pipe];
725 }
726
727 static inline struct drm_crtc *
728 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
729 {
730 struct drm_i915_private *dev_priv = dev->dev_private;
731 return dev_priv->plane_to_crtc_mapping[plane];
732 }
733
734 struct intel_unpin_work {
735 struct work_struct work;
736 struct drm_crtc *crtc;
737 struct drm_framebuffer *old_fb;
738 struct drm_i915_gem_object *pending_flip_obj;
739 struct drm_pending_vblank_event *event;
740 atomic_t pending;
741 #define INTEL_FLIP_INACTIVE 0
742 #define INTEL_FLIP_PENDING 1
743 #define INTEL_FLIP_COMPLETE 2
744 u32 flip_count;
745 u32 gtt_offset;
746 struct drm_i915_gem_request *flip_queued_req;
747 int flip_queued_vblank;
748 int flip_ready_vblank;
749 bool enable_stall_check;
750 };
751
752 struct intel_set_config {
753 struct drm_encoder **save_connector_encoders;
754 struct drm_crtc **save_encoder_crtcs;
755 bool *save_crtc_enabled;
756
757 bool fb_changed;
758 bool mode_changed;
759 };
760
761 struct intel_load_detect_pipe {
762 struct drm_framebuffer *release_fb;
763 bool load_detect_temp;
764 int dpms_mode;
765 };
766
767 static inline struct intel_encoder *
768 intel_attached_encoder(struct drm_connector *connector)
769 {
770 return to_intel_connector(connector)->encoder;
771 }
772
773 static inline struct intel_digital_port *
774 enc_to_dig_port(struct drm_encoder *encoder)
775 {
776 return container_of(encoder, struct intel_digital_port, base.base);
777 }
778
779 static inline struct intel_dp_mst_encoder *
780 enc_to_mst(struct drm_encoder *encoder)
781 {
782 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
783 }
784
785 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
786 {
787 return &enc_to_dig_port(encoder)->dp;
788 }
789
790 static inline struct intel_digital_port *
791 dp_to_dig_port(struct intel_dp *intel_dp)
792 {
793 return container_of(intel_dp, struct intel_digital_port, dp);
794 }
795
796 static inline struct intel_digital_port *
797 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
798 {
799 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
800 }
801
802 /*
803 * Returns the number of planes for this pipe, ie the number of sprites + 1
804 * (primary plane). This doesn't count the cursor plane then.
805 */
806 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
807 {
808 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
809 }
810
811 /* intel_fifo_underrun.c */
812 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
813 enum pipe pipe, bool enable);
814 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
815 enum transcoder pch_transcoder,
816 bool enable);
817 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
818 enum pipe pipe);
819 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
820 enum transcoder pch_transcoder);
821 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
822
823 /* i915_irq.c */
824 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
825 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
826 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
827 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
828 void gen6_reset_rps_interrupts(struct drm_device *dev);
829 void gen6_enable_rps_interrupts(struct drm_device *dev);
830 void gen6_disable_rps_interrupts(struct drm_device *dev);
831 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
832 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
833 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
834 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
835 {
836 /*
837 * We only use drm_irq_uninstall() at unload and VT switch, so
838 * this is the only thing we need to check.
839 */
840 return dev_priv->pm.irqs_enabled;
841 }
842
843 int intel_get_crtc_scanline(struct intel_crtc *crtc);
844 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
845 unsigned int pipe_mask);
846
847 /* intel_crt.c */
848 void intel_crt_init(struct drm_device *dev);
849
850
851 /* intel_ddi.c */
852 void intel_prepare_ddi(struct drm_device *dev);
853 void hsw_fdi_link_train(struct drm_crtc *crtc);
854 void intel_ddi_init(struct drm_device *dev, enum port port);
855 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
856 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
857 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
858 void intel_ddi_pll_init(struct drm_device *dev);
859 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
860 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
861 enum transcoder cpu_transcoder);
862 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
863 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
864 bool intel_ddi_pll_select(struct intel_crtc *crtc,
865 struct intel_crtc_state *crtc_state);
866 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
867 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
868 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
869 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
870 void intel_ddi_get_config(struct intel_encoder *encoder,
871 struct intel_crtc_state *pipe_config);
872
873 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
874 void intel_ddi_clock_get(struct intel_encoder *encoder,
875 struct intel_crtc_state *pipe_config);
876 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
877
878 /* intel_frontbuffer.c */
879 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
880 struct intel_engine_cs *ring,
881 enum fb_op_origin origin);
882 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
883 unsigned frontbuffer_bits);
884 void intel_frontbuffer_flip_complete(struct drm_device *dev,
885 unsigned frontbuffer_bits);
886 void intel_frontbuffer_flush(struct drm_device *dev,
887 unsigned frontbuffer_bits);
888 /**
889 * intel_frontbuffer_flip - synchronous frontbuffer flip
890 * @dev: DRM device
891 * @frontbuffer_bits: frontbuffer plane tracking bits
892 *
893 * This function gets called after scheduling a flip on @obj. This is for
894 * synchronous plane updates which will happen on the next vblank and which will
895 * not get delayed by pending gpu rendering.
896 *
897 * Can be called without any locks held.
898 */
899 static inline
900 void intel_frontbuffer_flip(struct drm_device *dev,
901 unsigned frontbuffer_bits)
902 {
903 intel_frontbuffer_flush(dev, frontbuffer_bits);
904 }
905
906 int intel_fb_align_height(struct drm_device *dev, int height,
907 uint32_t pixel_format,
908 uint64_t fb_format_modifier);
909 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
910
911 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
912 uint32_t pixel_format);
913
914 /* intel_audio.c */
915 void intel_init_audio(struct drm_device *dev);
916 void intel_audio_codec_enable(struct intel_encoder *encoder);
917 void intel_audio_codec_disable(struct intel_encoder *encoder);
918 void i915_audio_component_init(struct drm_i915_private *dev_priv);
919 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
920
921 /* intel_display.c */
922 extern const struct drm_plane_funcs intel_plane_funcs;
923 bool intel_has_pending_fb_unpin(struct drm_device *dev);
924 int intel_pch_rawclk(struct drm_device *dev);
925 void intel_mark_busy(struct drm_device *dev);
926 void intel_mark_idle(struct drm_device *dev);
927 void intel_crtc_restore_mode(struct drm_crtc *crtc);
928 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
929 void intel_crtc_update_dpms(struct drm_crtc *crtc);
930 void intel_encoder_destroy(struct drm_encoder *encoder);
931 void intel_connector_dpms(struct drm_connector *, int mode);
932 bool intel_connector_get_hw_state(struct intel_connector *connector);
933 void intel_modeset_check_state(struct drm_device *dev);
934 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
935 struct intel_digital_port *port);
936 void intel_connector_attach_encoder(struct intel_connector *connector,
937 struct intel_encoder *encoder);
938 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
939 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
940 struct drm_crtc *crtc);
941 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
942 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
943 struct drm_file *file_priv);
944 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
945 enum pipe pipe);
946 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
947 static inline void
948 intel_wait_for_vblank(struct drm_device *dev, int pipe)
949 {
950 drm_wait_one_vblank(dev, pipe);
951 }
952 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
953 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
954 struct intel_digital_port *dport);
955 bool intel_get_load_detect_pipe(struct drm_connector *connector,
956 struct drm_display_mode *mode,
957 struct intel_load_detect_pipe *old,
958 struct drm_modeset_acquire_ctx *ctx);
959 void intel_release_load_detect_pipe(struct drm_connector *connector,
960 struct intel_load_detect_pipe *old);
961 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
962 struct drm_framebuffer *fb,
963 struct intel_engine_cs *pipelined);
964 struct drm_framebuffer *
965 __intel_framebuffer_create(struct drm_device *dev,
966 struct drm_mode_fb_cmd2 *mode_cmd,
967 struct drm_i915_gem_object *obj);
968 void intel_prepare_page_flip(struct drm_device *dev, int plane);
969 void intel_finish_page_flip(struct drm_device *dev, int pipe);
970 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
971 void intel_check_page_flip(struct drm_device *dev, int pipe);
972 int intel_prepare_plane_fb(struct drm_plane *plane,
973 struct drm_framebuffer *fb,
974 const struct drm_plane_state *new_state);
975 void intel_cleanup_plane_fb(struct drm_plane *plane,
976 struct drm_framebuffer *fb,
977 const struct drm_plane_state *old_state);
978 int intel_plane_atomic_get_property(struct drm_plane *plane,
979 const struct drm_plane_state *state,
980 struct drm_property *property,
981 uint64_t *val);
982 int intel_plane_atomic_set_property(struct drm_plane *plane,
983 struct drm_plane_state *state,
984 struct drm_property *property,
985 uint64_t val);
986
987 /* shared dpll functions */
988 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
989 void assert_shared_dpll(struct drm_i915_private *dev_priv,
990 struct intel_shared_dpll *pll,
991 bool state);
992 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
993 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
994 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
995 struct intel_crtc_state *state);
996 void intel_put_shared_dpll(struct intel_crtc *crtc);
997
998 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
999 const struct dpll *dpll);
1000 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1001
1002 /* modesetting asserts */
1003 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1004 enum pipe pipe);
1005 void assert_pll(struct drm_i915_private *dev_priv,
1006 enum pipe pipe, bool state);
1007 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1008 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1009 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state);
1011 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1012 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1013 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1014 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1015 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1016 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1017 unsigned int tiling_mode,
1018 unsigned int bpp,
1019 unsigned int pitch);
1020 void intel_prepare_reset(struct drm_device *dev);
1021 void intel_finish_reset(struct drm_device *dev);
1022 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1023 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1024 void intel_dp_get_m_n(struct intel_crtc *crtc,
1025 struct intel_crtc_state *pipe_config);
1026 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1027 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1028 void
1029 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1030 int dotclock);
1031 bool intel_crtc_active(struct drm_crtc *crtc);
1032 void hsw_enable_ips(struct intel_crtc *crtc);
1033 void hsw_disable_ips(struct intel_crtc *crtc);
1034 enum intel_display_power_domain
1035 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1036 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1037 struct intel_crtc_state *pipe_config);
1038 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1039 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1040
1041 /* intel_dp.c */
1042 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1043 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1044 struct intel_connector *intel_connector);
1045 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1046 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1047 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1048 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1049 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1050 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1051 bool intel_dp_compute_config(struct intel_encoder *encoder,
1052 struct intel_crtc_state *pipe_config);
1053 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1054 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1055 bool long_hpd);
1056 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1057 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1058 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1059 void intel_edp_panel_on(struct intel_dp *intel_dp);
1060 void intel_edp_panel_off(struct intel_dp *intel_dp);
1061 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1062 void intel_dp_mst_suspend(struct drm_device *dev);
1063 void intel_dp_mst_resume(struct drm_device *dev);
1064 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
1065 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1066 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1067 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1068 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1069 void intel_plane_destroy(struct drm_plane *plane);
1070 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1071 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1072 void intel_edp_drrs_invalidate(struct drm_device *dev,
1073 unsigned frontbuffer_bits);
1074 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1075
1076 /* intel_dp_mst.c */
1077 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1078 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1079 /* intel_dsi.c */
1080 void intel_dsi_init(struct drm_device *dev);
1081
1082
1083 /* intel_dvo.c */
1084 void intel_dvo_init(struct drm_device *dev);
1085
1086
1087 /* legacy fbdev emulation in intel_fbdev.c */
1088 #ifdef CONFIG_DRM_I915_FBDEV
1089 extern int intel_fbdev_init(struct drm_device *dev);
1090 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1091 extern void intel_fbdev_fini(struct drm_device *dev);
1092 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1093 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1094 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1095 #else
1096 static inline int intel_fbdev_init(struct drm_device *dev)
1097 {
1098 return 0;
1099 }
1100
1101 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1102 {
1103 }
1104
1105 static inline void intel_fbdev_fini(struct drm_device *dev)
1106 {
1107 }
1108
1109 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1110 {
1111 }
1112
1113 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1114 {
1115 }
1116 #endif
1117
1118 /* intel_fbc.c */
1119 bool intel_fbc_enabled(struct drm_device *dev);
1120 void intel_fbc_update(struct drm_device *dev);
1121 void intel_fbc_init(struct drm_i915_private *dev_priv);
1122 void intel_fbc_disable(struct drm_device *dev);
1123 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1124 unsigned int frontbuffer_bits,
1125 enum fb_op_origin origin);
1126 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1127 unsigned int frontbuffer_bits);
1128
1129 /* intel_hdmi.c */
1130 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1131 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1132 struct intel_connector *intel_connector);
1133 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1134 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1135 struct intel_crtc_state *pipe_config);
1136
1137
1138 /* intel_lvds.c */
1139 void intel_lvds_init(struct drm_device *dev);
1140 bool intel_is_dual_link_lvds(struct drm_device *dev);
1141
1142
1143 /* intel_modes.c */
1144 int intel_connector_update_modes(struct drm_connector *connector,
1145 struct edid *edid);
1146 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1147 void intel_attach_force_audio_property(struct drm_connector *connector);
1148 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1149
1150
1151 /* intel_overlay.c */
1152 void intel_setup_overlay(struct drm_device *dev);
1153 void intel_cleanup_overlay(struct drm_device *dev);
1154 int intel_overlay_switch_off(struct intel_overlay *overlay);
1155 int intel_overlay_put_image(struct drm_device *dev, void *data,
1156 struct drm_file *file_priv);
1157 int intel_overlay_attrs(struct drm_device *dev, void *data,
1158 struct drm_file *file_priv);
1159 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1160
1161
1162 /* intel_panel.c */
1163 int intel_panel_init(struct intel_panel *panel,
1164 struct drm_display_mode *fixed_mode,
1165 struct drm_display_mode *downclock_mode);
1166 void intel_panel_fini(struct intel_panel *panel);
1167 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1168 struct drm_display_mode *adjusted_mode);
1169 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1170 struct intel_crtc_state *pipe_config,
1171 int fitting_mode);
1172 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1173 struct intel_crtc_state *pipe_config,
1174 int fitting_mode);
1175 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1176 u32 level, u32 max);
1177 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1178 void intel_panel_enable_backlight(struct intel_connector *connector);
1179 void intel_panel_disable_backlight(struct intel_connector *connector);
1180 void intel_panel_destroy_backlight(struct drm_connector *connector);
1181 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1182 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1183 extern struct drm_display_mode *intel_find_panel_downclock(
1184 struct drm_device *dev,
1185 struct drm_display_mode *fixed_mode,
1186 struct drm_connector *connector);
1187 void intel_backlight_register(struct drm_device *dev);
1188 void intel_backlight_unregister(struct drm_device *dev);
1189
1190
1191 /* intel_psr.c */
1192 void intel_psr_enable(struct intel_dp *intel_dp);
1193 void intel_psr_disable(struct intel_dp *intel_dp);
1194 void intel_psr_invalidate(struct drm_device *dev,
1195 unsigned frontbuffer_bits);
1196 void intel_psr_flush(struct drm_device *dev,
1197 unsigned frontbuffer_bits);
1198 void intel_psr_init(struct drm_device *dev);
1199
1200 /* intel_runtime_pm.c */
1201 int intel_power_domains_init(struct drm_i915_private *);
1202 void intel_power_domains_fini(struct drm_i915_private *);
1203 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1204 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1205
1206 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1207 enum intel_display_power_domain domain);
1208 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1209 enum intel_display_power_domain domain);
1210 void intel_display_power_get(struct drm_i915_private *dev_priv,
1211 enum intel_display_power_domain domain);
1212 void intel_display_power_put(struct drm_i915_private *dev_priv,
1213 enum intel_display_power_domain domain);
1214 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1215 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1216 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1217 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1218 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1219
1220 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1221
1222 /* intel_pm.c */
1223 void intel_init_clock_gating(struct drm_device *dev);
1224 void intel_suspend_hw(struct drm_device *dev);
1225 int ilk_wm_max_level(const struct drm_device *dev);
1226 void intel_update_watermarks(struct drm_crtc *crtc);
1227 void intel_update_sprite_watermarks(struct drm_plane *plane,
1228 struct drm_crtc *crtc,
1229 uint32_t sprite_width,
1230 uint32_t sprite_height,
1231 int pixel_size,
1232 bool enabled, bool scaled);
1233 void intel_init_pm(struct drm_device *dev);
1234 void intel_pm_setup(struct drm_device *dev);
1235 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1236 void intel_gpu_ips_teardown(void);
1237 void intel_init_gt_powersave(struct drm_device *dev);
1238 void intel_cleanup_gt_powersave(struct drm_device *dev);
1239 void intel_enable_gt_powersave(struct drm_device *dev);
1240 void intel_disable_gt_powersave(struct drm_device *dev);
1241 void intel_suspend_gt_powersave(struct drm_device *dev);
1242 void intel_reset_gt_powersave(struct drm_device *dev);
1243 void gen6_update_ring_freq(struct drm_device *dev);
1244 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1245 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1246 void ilk_wm_get_hw_state(struct drm_device *dev);
1247 void skl_wm_get_hw_state(struct drm_device *dev);
1248 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1249 struct skl_ddb_allocation *ddb /* out */);
1250
1251
1252 /* intel_sdvo.c */
1253 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1254
1255
1256 /* intel_sprite.c */
1257 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1258 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1259 enum plane plane);
1260 int intel_plane_restore(struct drm_plane *plane);
1261 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1262 struct drm_file *file_priv);
1263 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1264 struct drm_file *file_priv);
1265 bool intel_pipe_update_start(struct intel_crtc *crtc,
1266 uint32_t *start_vbl_count);
1267 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1268 void intel_post_enable_primary(struct drm_crtc *crtc);
1269 void intel_pre_disable_primary(struct drm_crtc *crtc);
1270
1271 /* intel_tv.c */
1272 void intel_tv_init(struct drm_device *dev);
1273
1274 /* intel_atomic.c */
1275 int intel_atomic_check(struct drm_device *dev,
1276 struct drm_atomic_state *state);
1277 int intel_atomic_commit(struct drm_device *dev,
1278 struct drm_atomic_state *state,
1279 bool async);
1280 int intel_connector_atomic_get_property(struct drm_connector *connector,
1281 const struct drm_connector_state *state,
1282 struct drm_property *property,
1283 uint64_t *val);
1284 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1285 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1286 struct drm_crtc_state *state);
1287
1288 /* intel_atomic_plane.c */
1289 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1290 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1291 void intel_plane_destroy_state(struct drm_plane *plane,
1292 struct drm_plane_state *state);
1293 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1294
1295 #endif /* __INTEL_DRV_H__ */
Linux kernel - Deliverables
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