drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000 * (x))
  69 #define MHz(x) KHz(1000 * (x))
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80
  81 /* Maximum cursor sizes */
  82 #define GEN2_CURSOR_WIDTH 64
  83 #define GEN2_CURSOR_HEIGHT 64
  84 #define MAX_CURSOR_WIDTH 256
  85 #define MAX_CURSOR_HEIGHT 256
  86
  87 #define INTEL_I2C_BUS_DVO 1
  88 #define INTEL_I2C_BUS_SDVO 2
  89
  90 /* these are outputs from the chip - integrated only
  91    external chips are via DVO or SDVO output */
  92 #define INTEL_OUTPUT_UNUSED 0
  93 #define INTEL_OUTPUT_ANALOG 1
  94 #define INTEL_OUTPUT_DVO 2
  95 #define INTEL_OUTPUT_SDVO 3
  96 #define INTEL_OUTPUT_LVDS 4
  97 #define INTEL_OUTPUT_TVOUT 5
  98 #define INTEL_OUTPUT_HDMI 6
  99 #define INTEL_OUTPUT_DISPLAYPORT 7
 100 #define INTEL_OUTPUT_EDP 8
 101 #define INTEL_OUTPUT_DSI 9
 102 #define INTEL_OUTPUT_UNKNOWN 10
 103
 104 #define INTEL_DVO_CHIP_NONE 0
 105 #define INTEL_DVO_CHIP_LVDS 1
 106 #define INTEL_DVO_CHIP_TMDS 2
 107 #define INTEL_DVO_CHIP_TVOUT 4
 108
 109 #define INTEL_DSI_VIDEO_MODE    0
 110 #define INTEL_DSI_COMMAND_MODE  1
 111
 112 struct intel_framebuffer {
 113         struct drm_framebuffer base;
 114         struct drm_i915_gem_object *obj;
 115 };
 116
 117 struct intel_fbdev {
 118         struct drm_fb_helper helper;
 119         struct intel_framebuffer *fb;
 120         struct list_head fbdev_list;
 121         struct drm_display_mode *our_mode;
 122         int preferred_bpp;
 123 };
 124
 125 struct intel_encoder {
 126         struct drm_encoder base;
 127         /*
 128          * The new crtc this encoder will be driven from. Only differs from
 129          * base->crtc while a modeset is in progress.
 130          */
 131         struct intel_crtc *new_crtc;
 132
 133         int type;
 134         unsigned int cloneable;
 135         bool connectors_active;
 136         void (*hot_plug)(struct intel_encoder *);
 137         bool (*compute_config)(struct intel_encoder *,
 138                                struct intel_crtc_config *);
 139         void (*pre_pll_enable)(struct intel_encoder *);
 140         void (*pre_enable)(struct intel_encoder *);
 141         void (*enable)(struct intel_encoder *);
 142         void (*mode_set)(struct intel_encoder *intel_encoder);
 143         void (*disable)(struct intel_encoder *);
 144         void (*post_disable)(struct intel_encoder *);
 145         /* Read out the current hw state of this connector, returning true if
 146          * the encoder is active. If the encoder is enabled it also set the pipe
 147          * it is connected to in the pipe parameter. */
 148         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 149         /* Reconstructs the equivalent mode flags for the current hardware
 150          * state. This must be called _after_ display->get_pipe_config has
 151          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 152          * be set correctly before calling this function. */
 153         void (*get_config)(struct intel_encoder *,
 154                            struct intel_crtc_config *pipe_config);
 155         int crtc_mask;
 156         enum hpd_pin hpd_pin;
 157 };
 158
 159 struct intel_panel {
 160         struct drm_display_mode *fixed_mode;
 161         struct drm_display_mode *downclock_mode;
 162         int fitting_mode;
 163
 164         /* backlight */
 165         struct {
 166                 bool present;
 167                 u32 level;
 168                 u32 max;
 169                 bool enabled;
 170                 bool combination_mode;  /* gen 2/4 only */
 171                 bool active_low_pwm;
 172                 struct backlight_device *device;
 173         } backlight;
 174 };
 175
 176 struct intel_connector {
 177         struct drm_connector base;
 178         /*
 179          * The fixed encoder this connector is connected to.
 180          */
 181         struct intel_encoder *encoder;
 182
 183         /*
 184          * The new encoder this connector will be driven. Only differs from
 185          * encoder while a modeset is in progress.
 186          */
 187         struct intel_encoder *new_encoder;
 188
 189         /* Reads out the current hw, returning true if the connector is enabled
 190          * and active (i.e. dpms ON state). */
 191         bool (*get_hw_state)(struct intel_connector *);
 192
 193         /*
 194          * Removes all interfaces through which the connector is accessible
 195          * - like sysfs, debugfs entries -, so that no new operations can be
 196          * started on the connector. Also makes sure all currently pending
 197          * operations finish before returing.
 198          */
 199         void (*unregister)(struct intel_connector *);
 200
 201         /* Panel info for eDP and LVDS */
 202         struct intel_panel panel;
 203
 204         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 205         struct edid *edid;
 206
 207         /* since POLL and HPD connectors may use the same HPD line keep the native
 208            state of connector->polled in case hotplug storm detection changes it */
 209         u8 polled;
 210 };
 211
 212 typedef struct dpll {
 213         /* given values */
 214         int n;
 215         int m1, m2;
 216         int p1, p2;
 217         /* derived values */
 218         int     dot;
 219         int     vco;
 220         int     m;
 221         int     p;
 222 } intel_clock_t;
 223
 224 struct intel_plane_config {
 225         bool tiled;
 226         int size;
 227         u32 base;
 228 };
 229
 230 struct intel_crtc_config {
 231         /**
 232          * quirks - bitfield with hw state readout quirks
 233          *
 234          * For various reasons the hw state readout code might not be able to
 235          * completely faithfully read out the current state. These cases are
 236          * tracked with quirk flags so that fastboot and state checker can act
 237          * accordingly.
 238          */
 239 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 240 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 241         unsigned long quirks;
 242
 243         /* User requested mode, only valid as a starting point to
 244          * compute adjusted_mode, except in the case of (S)DVO where
 245          * it's also for the output timings of the (S)DVO chip.
 246          * adjusted_mode will then correspond to the S(DVO) chip's
 247          * preferred input timings. */
 248         struct drm_display_mode requested_mode;
 249         /* Actual pipe timings ie. what we program into the pipe timing
 250          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 251         struct drm_display_mode adjusted_mode;
 252
 253         /* Pipe source size (ie. panel fitter input size)
 254          * All planes will be positioned inside this space,
 255          * and get clipped at the edges. */
 256         int pipe_src_w, pipe_src_h;
 257
 258         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 259          * between pch encoders and cpu encoders. */
 260         bool has_pch_encoder;
 261
 262         /* CPU Transcoder for the pipe. Currently this can only differ from the
 263          * pipe on Haswell (where we have a special eDP transcoder). */
 264         enum transcoder cpu_transcoder;
 265
 266         /*
 267          * Use reduced/limited/broadcast rbg range, compressing from the full
 268          * range fed into the crtcs.
 269          */
 270         bool limited_color_range;
 271
 272         /* DP has a bunch of special case unfortunately, so mark the pipe
 273          * accordingly. */
 274         bool has_dp_encoder;
 275
 276         /* Whether we should send NULL infoframes. Required for audio. */
 277         bool has_hdmi_sink;
 278
 279         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 280          * has_dp_encoder is set. */
 281         bool has_audio;
 282
 283         /*
 284          * Enable dithering, used when the selected pipe bpp doesn't match the
 285          * plane bpp.
 286          */
 287         bool dither;
 288
 289         /* Controls for the clock computation, to override various stages. */
 290         bool clock_set;
 291
 292         /* SDVO TV has a bunch of special case. To make multifunction encoders
 293          * work correctly, we need to track this at runtime.*/
 294         bool sdvo_tv_clock;
 295
 296         /*
 297          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 298          * required. This is set in the 2nd loop of calling encoder's
 299          * ->compute_config if the first pick doesn't work out.
 300          */
 301         bool bw_constrained;
 302
 303         /* Settings for the intel dpll used on pretty much everything but
 304          * haswell. */
 305         struct dpll dpll;
 306
 307         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 308         enum intel_dpll_id shared_dpll;
 309
 310         /* Actual register state of the dpll, for shared dpll cross-checking. */
 311         struct intel_dpll_hw_state dpll_hw_state;
 312
 313         int pipe_bpp;
 314         struct intel_link_m_n dp_m_n;
 315
 316         /* m2_n2 for eDP downclock */
 317         struct intel_link_m_n dp_m2_n2;
 318
 319         /*
 320          * Frequence the dpll for the port should run at. Differs from the
 321          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 322          * already multiplied by pixel_multiplier.
 323          */
 324         int port_clock;
 325
 326         /* Used by SDVO (and if we ever fix it, HDMI). */
 327         unsigned pixel_multiplier;
 328
 329         /* Panel fitter controls for gen2-gen4 + VLV */
 330         struct {
 331                 u32 control;
 332                 u32 pgm_ratios;
 333                 u32 lvds_border_bits;
 334         } gmch_pfit;
 335
 336         /* Panel fitter placement and size for Ironlake+ */
 337         struct {
 338                 u32 pos;
 339                 u32 size;
 340                 bool enabled;
 341         } pch_pfit;
 342
 343         /* FDI configuration, only valid if has_pch_encoder is set. */
 344         int fdi_lanes;
 345         struct intel_link_m_n fdi_m_n;
 346
 347         bool ips_enabled;
 348
 349         bool double_wide;
 350 };
 351
 352 struct intel_pipe_wm {
 353         struct intel_wm_level wm[5];
 354         uint32_t linetime;
 355         bool fbc_wm_enabled;
 356         bool pipe_enabled;
 357         bool sprites_enabled;
 358         bool sprites_scaled;
 359 };
 360
 361 struct intel_crtc {
 362         struct drm_crtc base;
 363         enum pipe pipe;
 364         enum plane plane;
 365         u8 lut_r[256], lut_g[256], lut_b[256];
 366         /*
 367          * Whether the crtc and the connected output pipeline is active. Implies
 368          * that crtc->enabled is set, i.e. the current mode configuration has
 369          * some outputs connected to this crtc.
 370          */
 371         bool active;
 372         unsigned long enabled_power_domains;
 373         bool primary_enabled; /* is the primary plane (partially) visible? */
 374         bool lowfreq_avail;
 375         struct intel_overlay *overlay;
 376         struct intel_unpin_work *unpin_work;
 377
 378         atomic_t unpin_work_count;
 379
 380         /* Display surface base address adjustement for pageflips. Note that on
 381          * gen4+ this only adjusts up to a tile, offsets within a tile are
 382          * handled in the hw itself (with the TILEOFF register). */
 383         unsigned long dspaddr_offset;
 384
 385         struct drm_i915_gem_object *cursor_bo;
 386         uint32_t cursor_addr;
 387         int16_t cursor_x, cursor_y;
 388         int16_t cursor_width, cursor_height;
 389         uint32_t cursor_cntl;
 390         uint32_t cursor_base;
 391
 392         struct intel_plane_config plane_config;
 393         struct intel_crtc_config config;
 394         struct intel_crtc_config *new_config;
 395         bool new_enabled;
 396
 397         uint32_t ddi_pll_sel;
 398
 399         /* reset counter value when the last flip was submitted */
 400         unsigned int reset_counter;
 401
 402         /* Access to these should be protected by dev_priv->irq_lock. */
 403         bool cpu_fifo_underrun_disabled;
 404         bool pch_fifo_underrun_disabled;
 405
 406         /* per-pipe watermark state */
 407         struct {
 408                 /* watermarks currently being used  */
 409                 struct intel_pipe_wm active;
 410         } wm;
 411
 412         wait_queue_head_t vbl_wait;
 413
 414         int scanline_offset;
 415 };
 416
 417 struct intel_plane_wm_parameters {
 418         uint32_t horiz_pixels;
 419         uint8_t bytes_per_pixel;
 420         bool enabled;
 421         bool scaled;
 422 };
 423
 424 struct intel_plane {
 425         struct drm_plane base;
 426         int plane;
 427         enum pipe pipe;
 428         struct drm_i915_gem_object *obj;
 429         bool can_scale;
 430         int max_downscale;
 431         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 432         int crtc_x, crtc_y;
 433         unsigned int crtc_w, crtc_h;
 434         uint32_t src_x, src_y;
 435         uint32_t src_w, src_h;
 436
 437         /* Since we need to change the watermarks before/after
 438          * enabling/disabling the planes, we need to store the parameters here
 439          * as the other pieces of the struct may not reflect the values we want
 440          * for the watermark calculations. Currently only Haswell uses this.
 441          */
 442         struct intel_plane_wm_parameters wm;
 443
 444         void (*update_plane)(struct drm_plane *plane,
 445                              struct drm_crtc *crtc,
 446                              struct drm_framebuffer *fb,
 447                              struct drm_i915_gem_object *obj,
 448                              int crtc_x, int crtc_y,
 449                              unsigned int crtc_w, unsigned int crtc_h,
 450                              uint32_t x, uint32_t y,
 451                              uint32_t src_w, uint32_t src_h);
 452         void (*disable_plane)(struct drm_plane *plane,
 453                               struct drm_crtc *crtc);
 454         int (*update_colorkey)(struct drm_plane *plane,
 455                                struct drm_intel_sprite_colorkey *key);
 456         void (*get_colorkey)(struct drm_plane *plane,
 457                              struct drm_intel_sprite_colorkey *key);
 458 };
 459
 460 struct intel_watermark_params {
 461         unsigned long fifo_size;
 462         unsigned long max_wm;
 463         unsigned long default_wm;
 464         unsigned long guard_size;
 465         unsigned long cacheline_size;
 466 };
 467
 468 struct cxsr_latency {
 469         int is_desktop;
 470         int is_ddr3;
 471         unsigned long fsb_freq;
 472         unsigned long mem_freq;
 473         unsigned long display_sr;
 474         unsigned long display_hpll_disable;
 475         unsigned long cursor_sr;
 476         unsigned long cursor_hpll_disable;
 477 };
 478
 479 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 480 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 481 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 482 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 483 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 484
 485 struct intel_hdmi {
 486         u32 hdmi_reg;
 487         int ddc_bus;
 488         uint32_t color_range;
 489         bool color_range_auto;
 490         bool has_hdmi_sink;
 491         bool has_audio;
 492         enum hdmi_force_audio force_audio;
 493         bool rgb_quant_range_selectable;
 494         void (*write_infoframe)(struct drm_encoder *encoder,
 495                                 enum hdmi_infoframe_type type,
 496                                 const void *frame, ssize_t len);
 497         void (*set_infoframes)(struct drm_encoder *encoder,
 498                                bool enable,
 499                                struct drm_display_mode *adjusted_mode);
 500 };
 501
 502 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 503
 504 /**
 505  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 506  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 507  * parsing for same resolution.
 508  */
 509 enum edp_drrs_refresh_rate_type {
 510         DRRS_HIGH_RR,
 511         DRRS_LOW_RR,
 512         DRRS_MAX_RR, /* RR count */
 513 };
 514
 515 struct intel_dp {
 516         uint32_t output_reg;
 517         uint32_t aux_ch_ctl_reg;
 518         uint32_t DP;
 519         bool has_audio;
 520         enum hdmi_force_audio force_audio;
 521         uint32_t color_range;
 522         bool color_range_auto;
 523         uint8_t link_bw;
 524         uint8_t lane_count;
 525         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 526         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 527         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 528         struct drm_dp_aux aux;
 529         uint8_t train_set[4];
 530         int panel_power_up_delay;
 531         int panel_power_down_delay;
 532         int panel_power_cycle_delay;
 533         int backlight_on_delay;
 534         int backlight_off_delay;
 535         struct delayed_work panel_vdd_work;
 536         bool want_panel_vdd;
 537         unsigned long last_power_cycle;
 538         unsigned long last_power_on;
 539         unsigned long last_backlight_off;
 540         bool use_tps3;
 541         struct intel_connector *attached_connector;
 542
 543         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 544         /*
 545          * This function returns the value we have to program the AUX_CTL
 546          * register with to kick off an AUX transaction.
 547          */
 548         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 549                                      bool has_aux_irq,
 550                                      int send_bytes,
 551                                      uint32_t aux_clock_divider);
 552         struct {
 553                 enum drrs_support_type type;
 554                 enum edp_drrs_refresh_rate_type refresh_rate_type;
 555                 struct mutex mutex;
 556         } drrs_state;
 557
 558 };
 559
 560 struct intel_digital_port {
 561         struct intel_encoder base;
 562         enum port port;
 563         u32 saved_port_bits;
 564         struct intel_dp dp;
 565         struct intel_hdmi hdmi;
 566 };
 567
 568 static inline int
 569 vlv_dport_to_channel(struct intel_digital_port *dport)
 570 {
 571         switch (dport->port) {
 572         case PORT_B:
 573         case PORT_D:
 574                 return DPIO_CH0;
 575         case PORT_C:
 576                 return DPIO_CH1;
 577         default:
 578                 BUG();
 579         }
 580 }
 581
 582 static inline int
 583 vlv_pipe_to_channel(enum pipe pipe)
 584 {
 585         switch (pipe) {
 586         case PIPE_A:
 587         case PIPE_C:
 588                 return DPIO_CH0;
 589         case PIPE_B:
 590                 return DPIO_CH1;
 591         default:
 592                 BUG();
 593         }
 594 }
 595
 596 static inline struct drm_crtc *
 597 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 598 {
 599         struct drm_i915_private *dev_priv = dev->dev_private;
 600         return dev_priv->pipe_to_crtc_mapping[pipe];
 601 }
 602
 603 static inline struct drm_crtc *
 604 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 605 {
 606         struct drm_i915_private *dev_priv = dev->dev_private;
 607         return dev_priv->plane_to_crtc_mapping[plane];
 608 }
 609
 610 struct intel_unpin_work {
 611         struct work_struct work;
 612         struct drm_crtc *crtc;
 613         struct drm_i915_gem_object *old_fb_obj;
 614         struct drm_i915_gem_object *pending_flip_obj;
 615         struct drm_pending_vblank_event *event;
 616         atomic_t pending;
 617 #define INTEL_FLIP_INACTIVE     0
 618 #define INTEL_FLIP_PENDING      1
 619 #define INTEL_FLIP_COMPLETE     2
 620         u32 flip_count;
 621         u32 gtt_offset;
 622         bool enable_stall_check;
 623 };
 624
 625 struct intel_set_config {
 626         struct drm_encoder **save_connector_encoders;
 627         struct drm_crtc **save_encoder_crtcs;
 628         bool *save_crtc_enabled;
 629
 630         bool fb_changed;
 631         bool mode_changed;
 632 };
 633
 634 struct intel_load_detect_pipe {
 635         struct drm_framebuffer *release_fb;
 636         bool load_detect_temp;
 637         int dpms_mode;
 638 };
 639
 640 static inline struct intel_encoder *
 641 intel_attached_encoder(struct drm_connector *connector)
 642 {
 643         return to_intel_connector(connector)->encoder;
 644 }
 645
 646 static inline struct intel_digital_port *
 647 enc_to_dig_port(struct drm_encoder *encoder)
 648 {
 649         return container_of(encoder, struct intel_digital_port, base.base);
 650 }
 651
 652 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 653 {
 654         return &enc_to_dig_port(encoder)->dp;
 655 }
 656
 657 static inline struct intel_digital_port *
 658 dp_to_dig_port(struct intel_dp *intel_dp)
 659 {
 660         return container_of(intel_dp, struct intel_digital_port, dp);
 661 }
 662
 663 static inline struct intel_digital_port *
 664 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 665 {
 666         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 667 }
 668
 669
 670 /* i915_irq.c */
 671 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 672                                            enum pipe pipe, bool enable);
 673 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 674                                            enum transcoder pch_transcoder,
 675                                            bool enable);
 676 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 677 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 678 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 679 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 680 void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 681 void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 682 void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
 683 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
 684 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 685 void i9xx_check_fifo_underruns(struct drm_device *dev);
 686
 687
 688 /* intel_crt.c */
 689 void intel_crt_init(struct drm_device *dev);
 690
 691
 692 /* intel_ddi.c */
 693 void intel_prepare_ddi(struct drm_device *dev);
 694 void hsw_fdi_link_train(struct drm_crtc *crtc);
 695 void intel_ddi_init(struct drm_device *dev, enum port port);
 696 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 697 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 698 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 699 void intel_ddi_pll_init(struct drm_device *dev);
 700 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 701 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 702                                        enum transcoder cpu_transcoder);
 703 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 704 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 705 void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 706 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 707 void intel_ddi_pll_enable(struct intel_crtc *crtc);
 708 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 709 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 710 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 711 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 712 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 713 void intel_ddi_get_config(struct intel_encoder *encoder,
 714                           struct intel_crtc_config *pipe_config);
 715
 716
 717 /* intel_display.c */
 718 const char *intel_output_name(int output);
 719 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 720 int intel_pch_rawclk(struct drm_device *dev);
 721 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv);
 722 void intel_mark_busy(struct drm_device *dev);
 723 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 724                         struct intel_engine_cs *ring);
 725 void intel_mark_idle(struct drm_device *dev);
 726 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 727 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 728 void intel_encoder_destroy(struct drm_encoder *encoder);
 729 void intel_connector_dpms(struct drm_connector *, int mode);
 730 bool intel_connector_get_hw_state(struct intel_connector *connector);
 731 void intel_modeset_check_state(struct drm_device *dev);
 732 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 733                                 struct intel_digital_port *port);
 734 void intel_connector_attach_encoder(struct intel_connector *connector,
 735                                     struct intel_encoder *encoder);
 736 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 737 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 738                                              struct drm_crtc *crtc);
 739 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 740 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 741                                 struct drm_file *file_priv);
 742 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 743                                              enum pipe pipe);
 744 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 745 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 746 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 748                          struct intel_digital_port *dport);
 749 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 750                                 struct drm_display_mode *mode,
 751                                 struct intel_load_detect_pipe *old,
 752                                 struct drm_modeset_acquire_ctx *ctx);
 753 void intel_release_load_detect_pipe(struct drm_connector *connector,
 754                                     struct intel_load_detect_pipe *old,
 755                                     struct drm_modeset_acquire_ctx *ctx);
 756 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 757                                struct drm_i915_gem_object *obj,
 758                                struct intel_engine_cs *pipelined);
 759 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 760 struct drm_framebuffer *
 761 __intel_framebuffer_create(struct drm_device *dev,
 762                            struct drm_mode_fb_cmd2 *mode_cmd,
 763                            struct drm_i915_gem_object *obj);
 764 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 765 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 766 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 767 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 768 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 769                         struct intel_shared_dpll *pll,
 770                         bool state);
 771 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 772 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 773 void assert_pll(struct drm_i915_private *dev_priv,
 774                 enum pipe pipe, bool state);
 775 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 776 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 777 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 778                        enum pipe pipe, bool state);
 779 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 780 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 781 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 782 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 783 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 784 void intel_write_eld(struct drm_encoder *encoder,
 785                      struct drm_display_mode *mode);
 786 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 787                                              unsigned int tiling_mode,
 788                                              unsigned int bpp,
 789                                              unsigned int pitch);
 790 void intel_display_handle_reset(struct drm_device *dev);
 791 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 792 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 793 void intel_dp_get_m_n(struct intel_crtc *crtc,
 794                       struct intel_crtc_config *pipe_config);
 795 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 796 void
 797 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 798                                 int dotclock);
 799 bool intel_crtc_active(struct drm_crtc *crtc);
 800 void hsw_enable_ips(struct intel_crtc *crtc);
 801 void hsw_disable_ips(struct intel_crtc *crtc);
 802 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
 803 enum intel_display_power_domain
 804 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 805 int valleyview_get_vco(struct drm_i915_private *dev_priv);
 806 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 807                                  struct intel_crtc_config *pipe_config);
 808 int intel_format_to_fourcc(int format);
 809 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 810
 811
 812 /* intel_dp.c */
 813 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 814 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 815                              struct intel_connector *intel_connector);
 816 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 817 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 818 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 819 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 820 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 821 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 822 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 823 bool intel_dp_compute_config(struct intel_encoder *encoder,
 824                              struct intel_crtc_config *pipe_config);
 825 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 826 void intel_edp_backlight_on(struct intel_dp *intel_dp);
 827 void intel_edp_backlight_off(struct intel_dp *intel_dp);
 828 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 829 void intel_edp_panel_on(struct intel_dp *intel_dp);
 830 void intel_edp_panel_off(struct intel_dp *intel_dp);
 831 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 832 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 833 void intel_edp_psr_update(struct drm_device *dev);
 834 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
 835
 836 /* intel_dsi.c */
 837 bool intel_dsi_init(struct drm_device *dev);
 838
 839
 840 /* intel_dvo.c */
 841 void intel_dvo_init(struct drm_device *dev);
 842
 843
 844 /* legacy fbdev emulation in intel_fbdev.c */
 845 #ifdef CONFIG_DRM_I915_FBDEV
 846 extern int intel_fbdev_init(struct drm_device *dev);
 847 extern void intel_fbdev_initial_config(struct drm_device *dev);
 848 extern void intel_fbdev_fini(struct drm_device *dev);
 849 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 850 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 851 extern void intel_fbdev_restore_mode(struct drm_device *dev);
 852 #else
 853 static inline int intel_fbdev_init(struct drm_device *dev)
 854 {
 855         return 0;
 856 }
 857
 858 static inline void intel_fbdev_initial_config(struct drm_device *dev)
 859 {
 860 }
 861
 862 static inline void intel_fbdev_fini(struct drm_device *dev)
 863 {
 864 }
 865
 866 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
 867 {
 868 }
 869
 870 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 871 {
 872 }
 873 #endif
 874
 875 /* intel_hdmi.c */
 876 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 877 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 878                                struct intel_connector *intel_connector);
 879 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 880 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 881                                struct intel_crtc_config *pipe_config);
 882
 883
 884 /* intel_lvds.c */
 885 void intel_lvds_init(struct drm_device *dev);
 886 bool intel_is_dual_link_lvds(struct drm_device *dev);
 887
 888
 889 /* intel_modes.c */
 890 int intel_connector_update_modes(struct drm_connector *connector,
 891                                  struct edid *edid);
 892 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 893 void intel_attach_force_audio_property(struct drm_connector *connector);
 894 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 895
 896
 897 /* intel_overlay.c */
 898 void intel_setup_overlay(struct drm_device *dev);
 899 void intel_cleanup_overlay(struct drm_device *dev);
 900 int intel_overlay_switch_off(struct intel_overlay *overlay);
 901 int intel_overlay_put_image(struct drm_device *dev, void *data,
 902                             struct drm_file *file_priv);
 903 int intel_overlay_attrs(struct drm_device *dev, void *data,
 904                         struct drm_file *file_priv);
 905
 906
 907 /* intel_panel.c */
 908 int intel_panel_init(struct intel_panel *panel,
 909                      struct drm_display_mode *fixed_mode,
 910                      struct drm_display_mode *downclock_mode);
 911 void intel_panel_fini(struct intel_panel *panel);
 912 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
 913                             struct drm_display_mode *adjusted_mode);
 914 void intel_pch_panel_fitting(struct intel_crtc *crtc,
 915                              struct intel_crtc_config *pipe_config,
 916                              int fitting_mode);
 917 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 918                               struct intel_crtc_config *pipe_config,
 919                               int fitting_mode);
 920 void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
 921                                u32 max);
 922 int intel_panel_setup_backlight(struct drm_connector *connector);
 923 void intel_panel_enable_backlight(struct intel_connector *connector);
 924 void intel_panel_disable_backlight(struct intel_connector *connector);
 925 void intel_panel_destroy_backlight(struct drm_connector *connector);
 926 void intel_panel_init_backlight_funcs(struct drm_device *dev);
 927 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 928 extern struct drm_display_mode *intel_find_panel_downclock(
 929                                 struct drm_device *dev,
 930                                 struct drm_display_mode *fixed_mode,
 931                                 struct drm_connector *connector);
 932
 933 /* intel_pm.c */
 934 void intel_init_clock_gating(struct drm_device *dev);
 935 void intel_suspend_hw(struct drm_device *dev);
 936 int ilk_wm_max_level(const struct drm_device *dev);
 937 void intel_update_watermarks(struct drm_crtc *crtc);
 938 void intel_update_sprite_watermarks(struct drm_plane *plane,
 939                                     struct drm_crtc *crtc,
 940                                     uint32_t sprite_width, int pixel_size,
 941                                     bool enabled, bool scaled);
 942 void intel_init_pm(struct drm_device *dev);
 943 void intel_pm_setup(struct drm_device *dev);
 944 bool intel_fbc_enabled(struct drm_device *dev);
 945 void intel_update_fbc(struct drm_device *dev);
 946 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 947 void intel_gpu_ips_teardown(void);
 948 int intel_power_domains_init(struct drm_i915_private *);
 949 void intel_power_domains_remove(struct drm_i915_private *);
 950 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
 951                                  enum intel_display_power_domain domain);
 952 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
 953                                     enum intel_display_power_domain domain);
 954 void intel_display_power_get(struct drm_i915_private *dev_priv,
 955                              enum intel_display_power_domain domain);
 956 void intel_display_power_put(struct drm_i915_private *dev_priv,
 957                              enum intel_display_power_domain domain);
 958 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
 959 void intel_init_gt_powersave(struct drm_device *dev);
 960 void intel_cleanup_gt_powersave(struct drm_device *dev);
 961 void intel_enable_gt_powersave(struct drm_device *dev);
 962 void intel_disable_gt_powersave(struct drm_device *dev);
 963 void intel_reset_gt_powersave(struct drm_device *dev);
 964 void ironlake_teardown_rc6(struct drm_device *dev);
 965 void gen6_update_ring_freq(struct drm_device *dev);
 966 void gen6_rps_idle(struct drm_i915_private *dev_priv);
 967 void gen6_rps_boost(struct drm_i915_private *dev_priv);
 968 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
 969 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 970 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
 971 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
 972 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
 973 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
 974 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
 975 void ilk_wm_get_hw_state(struct drm_device *dev);
 976 void __vlv_set_power_well(struct drm_i915_private *dev_priv,
 977                           enum punit_power_well power_well_id, bool enable);
 978
 979 /* intel_sdvo.c */
 980 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
 981
 982
 983 /* intel_sprite.c */
 984 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 985 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 986                                enum plane plane);
 987 void intel_plane_restore(struct drm_plane *plane);
 988 void intel_plane_disable(struct drm_plane *plane);
 989 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 990                               struct drm_file *file_priv);
 991 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 992                               struct drm_file *file_priv);
 993
 994
 995 /* intel_tv.c */
 996 void intel_tv_init(struct drm_device *dev);
 997
 998 #endif /* __INTEL_DRV_H__ */