drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include <drm/drm_crtc.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include <drm/drm_dp_helper.h>
  35
  36 /**
  37  * _wait_for - magic (register) wait macro
  38  *
  39  * Does the right thing for modeset paths when run under kdgb or similar atomic
  40  * contexts. Note that it's important that we check the condition again after
  41  * having timed out, since the timeout could be due to preemption or similar and
  42  * we've never had a chance to check the condition before the timeout.
  43  */
  44 #define _wait_for(COND, MS, W) ({ \
  45         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  46         int ret__ = 0;                                                  \
  47         while (!(COND)) {                                               \
  48                 if (time_after(jiffies, timeout__)) {                   \
  49                         if (!(COND))                                    \
  50                                 ret__ = -ETIMEDOUT;                     \
  51                         break;                                          \
  52                 }                                                       \
  53                 if (W && drm_can_sleep())  {                            \
  54                         msleep(W);                                      \
  55                 } else {                                                \
  56                         cpu_relax();                                    \
  57                 }                                                       \
  58         }                                                               \
  59         ret__;                                                          \
  60 })
  61
  62 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  63 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  64 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  65                                                DIV_ROUND_UP((US), 1000), 0)
  66
  67 #define KHz(x) (1000*x)
  68 #define MHz(x) KHz(1000*x)
  69
  70 /*
  71  * Display related stuff
  72  */
  73
  74 /* store information about an Ixxx DVO */
  75 /* The i830->i865 use multiple DVOs with multiple i2cs */
  76 /* the i915, i945 have a single sDVO i2c bus - which is different */
  77 #define MAX_OUTPUTS 6
  78 /* maximum connectors per crtcs in the mode set */
  79 #define INTELFB_CONN_LIMIT 4
  80
  81 #define INTEL_I2C_BUS_DVO 1
  82 #define INTEL_I2C_BUS_SDVO 2
  83
  84 /* these are outputs from the chip - integrated only
  85    external chips are via DVO or SDVO output */
  86 #define INTEL_OUTPUT_UNUSED 0
  87 #define INTEL_OUTPUT_ANALOG 1
  88 #define INTEL_OUTPUT_DVO 2
  89 #define INTEL_OUTPUT_SDVO 3
  90 #define INTEL_OUTPUT_LVDS 4
  91 #define INTEL_OUTPUT_TVOUT 5
  92 #define INTEL_OUTPUT_HDMI 6
  93 #define INTEL_OUTPUT_DISPLAYPORT 7
  94 #define INTEL_OUTPUT_EDP 8
  95 #define INTEL_OUTPUT_UNKNOWN 9
  96
  97 #define INTEL_DVO_CHIP_NONE 0
  98 #define INTEL_DVO_CHIP_LVDS 1
  99 #define INTEL_DVO_CHIP_TMDS 2
 100 #define INTEL_DVO_CHIP_TVOUT 4
 101
 102 struct intel_framebuffer {
 103         struct drm_framebuffer base;
 104         struct drm_i915_gem_object *obj;
 105 };
 106
 107 struct intel_fbdev {
 108         struct drm_fb_helper helper;
 109         struct intel_framebuffer ifb;
 110         struct list_head fbdev_list;
 111         struct drm_display_mode *our_mode;
 112 };
 113
 114 struct intel_encoder {
 115         struct drm_encoder base;
 116         /*
 117          * The new crtc this encoder will be driven from. Only differs from
 118          * base->crtc while a modeset is in progress.
 119          */
 120         struct intel_crtc *new_crtc;
 121
 122         int type;
 123         /*
 124          * Intel hw has only one MUX where encoders could be clone, hence a
 125          * simple flag is enough to compute the possible_clones mask.
 126          */
 127         bool cloneable;
 128         bool connectors_active;
 129         void (*hot_plug)(struct intel_encoder *);
 130         bool (*compute_config)(struct intel_encoder *,
 131                                struct intel_crtc_config *);
 132         void (*pre_pll_enable)(struct intel_encoder *);
 133         void (*pre_enable)(struct intel_encoder *);
 134         void (*enable)(struct intel_encoder *);
 135         void (*mode_set)(struct intel_encoder *intel_encoder);
 136         void (*disable)(struct intel_encoder *);
 137         void (*post_disable)(struct intel_encoder *);
 138         /* Read out the current hw state of this connector, returning true if
 139          * the encoder is active. If the encoder is enabled it also set the pipe
 140          * it is connected to in the pipe parameter. */
 141         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 142         /* Reconstructs the equivalent mode flags for the current hardware
 143          * state. */
 144         void (*get_config)(struct intel_encoder *,
 145                            struct intel_crtc_config *pipe_config);
 146         int crtc_mask;
 147         enum hpd_pin hpd_pin;
 148 };
 149
 150 struct intel_panel {
 151         struct drm_display_mode *fixed_mode;
 152         int fitting_mode;
 153 };
 154
 155 struct intel_connector {
 156         struct drm_connector base;
 157         /*
 158          * The fixed encoder this connector is connected to.
 159          */
 160         struct intel_encoder *encoder;
 161
 162         /*
 163          * The new encoder this connector will be driven. Only differs from
 164          * encoder while a modeset is in progress.
 165          */
 166         struct intel_encoder *new_encoder;
 167
 168         /* Reads out the current hw, returning true if the connector is enabled
 169          * and active (i.e. dpms ON state). */
 170         bool (*get_hw_state)(struct intel_connector *);
 171
 172         /* Panel info for eDP and LVDS */
 173         struct intel_panel panel;
 174
 175         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 176         struct edid *edid;
 177
 178         /* since POLL and HPD connectors may use the same HPD line keep the native
 179            state of connector->polled in case hotplug storm detection changes it */
 180         u8 polled;
 181 };
 182
 183 typedef struct dpll {
 184         /* given values */
 185         int n;
 186         int m1, m2;
 187         int p1, p2;
 188         /* derived values */
 189         int     dot;
 190         int     vco;
 191         int     m;
 192         int     p;
 193 } intel_clock_t;
 194
 195 struct intel_crtc_config {
 196         struct drm_display_mode requested_mode;
 197         struct drm_display_mode adjusted_mode;
 198         /* This flag must be set by the encoder's compute_config callback if it
 199          * changes the crtc timings in the mode to prevent the crtc fixup from
 200          * overwriting them.  Currently only lvds needs that. */
 201         bool timings_set;
 202         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 203          * between pch encoders and cpu encoders. */
 204         bool has_pch_encoder;
 205
 206         /* CPU Transcoder for the pipe. Currently this can only differ from the
 207          * pipe on Haswell (where we have a special eDP transcoder). */
 208         enum transcoder cpu_transcoder;
 209
 210         /*
 211          * Use reduced/limited/broadcast rbg range, compressing from the full
 212          * range fed into the crtcs.
 213          */
 214         bool limited_color_range;
 215
 216         /* DP has a bunch of special case unfortunately, so mark the pipe
 217          * accordingly. */
 218         bool has_dp_encoder;
 219
 220         /*
 221          * Enable dithering, used when the selected pipe bpp doesn't match the
 222          * plane bpp.
 223          */
 224         bool dither;
 225
 226         /* Controls for the clock computation, to override various stages. */
 227         bool clock_set;
 228
 229         /* SDVO TV has a bunch of special case. To make multifunction encoders
 230          * work correctly, we need to track this at runtime.*/
 231         bool sdvo_tv_clock;
 232
 233         /*
 234          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 235          * required. This is set in the 2nd loop of calling encoder's
 236          * ->compute_config if the first pick doesn't work out.
 237          */
 238         bool bw_constrained;
 239
 240         /* Settings for the intel dpll used on pretty much everything but
 241          * haswell. */
 242         struct dpll dpll;
 243
 244         int pipe_bpp;
 245         struct intel_link_m_n dp_m_n;
 246         /**
 247          * This is currently used by DP and HDMI encoders since those can have a
 248          * target pixel clock != the port link clock (which is currently stored
 249          * in adjusted_mode->clock).
 250          */
 251         int pixel_target_clock;
 252         /* Used by SDVO (and if we ever fix it, HDMI). */
 253         unsigned pixel_multiplier;
 254
 255         /* Panel fitter controls for gen2-gen4 + VLV */
 256         struct {
 257                 u32 control;
 258                 u32 pgm_ratios;
 259                 u32 lvds_border_bits;
 260         } gmch_pfit;
 261
 262         /* Panel fitter placement and size for Ironlake+ */
 263         struct {
 264                 u32 pos;
 265                 u32 size;
 266         } pch_pfit;
 267
 268         /* FDI configuration, only valid if has_pch_encoder is set. */
 269         int fdi_lanes;
 270         struct intel_link_m_n fdi_m_n;
 271
 272         bool ips_enabled;
 273 };
 274
 275 struct intel_crtc {
 276         struct drm_crtc base;
 277         enum pipe pipe;
 278         enum plane plane;
 279         u8 lut_r[256], lut_g[256], lut_b[256];
 280         /*
 281          * Whether the crtc and the connected output pipeline is active. Implies
 282          * that crtc->enabled is set, i.e. the current mode configuration has
 283          * some outputs connected to this crtc.
 284          */
 285         bool active;
 286         bool eld_vld;
 287         bool primary_disabled; /* is the crtc obscured by a plane? */
 288         bool lowfreq_avail;
 289         struct intel_overlay *overlay;
 290         struct intel_unpin_work *unpin_work;
 291
 292         atomic_t unpin_work_count;
 293
 294         /* Display surface base address adjustement for pageflips. Note that on
 295          * gen4+ this only adjusts up to a tile, offsets within a tile are
 296          * handled in the hw itself (with the TILEOFF register). */
 297         unsigned long dspaddr_offset;
 298
 299         struct drm_i915_gem_object *cursor_bo;
 300         uint32_t cursor_addr;
 301         int16_t cursor_x, cursor_y;
 302         int16_t cursor_width, cursor_height;
 303         bool cursor_visible;
 304
 305         struct intel_crtc_config config;
 306
 307         /* We can share PLLs across outputs if the timings match */
 308         struct intel_pch_pll *pch_pll;
 309         uint32_t ddi_pll_sel;
 310
 311         /* reset counter value when the last flip was submitted */
 312         unsigned int reset_counter;
 313
 314         /* Access to these should be protected by dev_priv->irq_lock. */
 315         bool cpu_fifo_underrun_disabled;
 316         bool pch_fifo_underrun_disabled;
 317 };
 318
 319 struct intel_plane {
 320         struct drm_plane base;
 321         int plane;
 322         enum pipe pipe;
 323         struct drm_i915_gem_object *obj;
 324         bool can_scale;
 325         int max_downscale;
 326         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 327         int crtc_x, crtc_y;
 328         unsigned int crtc_w, crtc_h;
 329         uint32_t src_x, src_y;
 330         uint32_t src_w, src_h;
 331
 332         /* Since we need to change the watermarks before/after
 333          * enabling/disabling the planes, we need to store the parameters here
 334          * as the other pieces of the struct may not reflect the values we want
 335          * for the watermark calculations. Currently only Haswell uses this.
 336          */
 337         struct {
 338                 bool enable;
 339                 uint8_t bytes_per_pixel;
 340                 uint32_t horiz_pixels;
 341         } wm;
 342
 343         void (*update_plane)(struct drm_plane *plane,
 344                              struct drm_framebuffer *fb,
 345                              struct drm_i915_gem_object *obj,
 346                              int crtc_x, int crtc_y,
 347                              unsigned int crtc_w, unsigned int crtc_h,
 348                              uint32_t x, uint32_t y,
 349                              uint32_t src_w, uint32_t src_h);
 350         void (*disable_plane)(struct drm_plane *plane);
 351         int (*update_colorkey)(struct drm_plane *plane,
 352                                struct drm_intel_sprite_colorkey *key);
 353         void (*get_colorkey)(struct drm_plane *plane,
 354                              struct drm_intel_sprite_colorkey *key);
 355 };
 356
 357 struct intel_watermark_params {
 358         unsigned long fifo_size;
 359         unsigned long max_wm;
 360         unsigned long default_wm;
 361         unsigned long guard_size;
 362         unsigned long cacheline_size;
 363 };
 364
 365 struct cxsr_latency {
 366         int is_desktop;
 367         int is_ddr3;
 368         unsigned long fsb_freq;
 369         unsigned long mem_freq;
 370         unsigned long display_sr;
 371         unsigned long display_hpll_disable;
 372         unsigned long cursor_sr;
 373         unsigned long cursor_hpll_disable;
 374 };
 375
 376 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 377 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 378 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 379 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 380 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 381
 382 #define DIP_HEADER_SIZE 5
 383
 384 #define DIP_TYPE_AVI    0x82
 385 #define DIP_VERSION_AVI 0x2
 386 #define DIP_LEN_AVI     13
 387 #define DIP_AVI_PR_1    0
 388 #define DIP_AVI_PR_2    1
 389 #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
 390 #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
 391 #define DIP_AVI_RGB_QUANT_RANGE_FULL    (2 << 2)
 392
 393 #define DIP_TYPE_SPD    0x83
 394 #define DIP_VERSION_SPD 0x1
 395 #define DIP_LEN_SPD     25
 396 #define DIP_SPD_UNKNOWN 0
 397 #define DIP_SPD_DSTB    0x1
 398 #define DIP_SPD_DVDP    0x2
 399 #define DIP_SPD_DVHS    0x3
 400 #define DIP_SPD_HDDVR   0x4
 401 #define DIP_SPD_DVC     0x5
 402 #define DIP_SPD_DSC     0x6
 403 #define DIP_SPD_VCD     0x7
 404 #define DIP_SPD_GAME    0x8
 405 #define DIP_SPD_PC      0x9
 406 #define DIP_SPD_BD      0xa
 407 #define DIP_SPD_SCD     0xb
 408
 409 struct dip_infoframe {
 410         uint8_t type;           /* HB0 */
 411         uint8_t ver;            /* HB1 */
 412         uint8_t len;            /* HB2 - body len, not including checksum */
 413         uint8_t ecc;            /* Header ECC */
 414         uint8_t checksum;       /* PB0 */
 415         union {
 416                 struct {
 417                         /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
 418                         uint8_t Y_A_B_S;
 419                         /* PB2 - C 7:6, M 5:4, R 3:0 */
 420                         uint8_t C_M_R;
 421                         /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
 422                         uint8_t ITC_EC_Q_SC;
 423                         /* PB4 - VIC 6:0 */
 424                         uint8_t VIC;
 425                         /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
 426                         uint8_t YQ_CN_PR;
 427                         /* PB6 to PB13 */
 428                         uint16_t top_bar_end;
 429                         uint16_t bottom_bar_start;
 430                         uint16_t left_bar_end;
 431                         uint16_t right_bar_start;
 432                 } __attribute__ ((packed)) avi;
 433                 struct {
 434                         uint8_t vn[8];
 435                         uint8_t pd[16];
 436                         uint8_t sdi;
 437                 } __attribute__ ((packed)) spd;
 438                 uint8_t payload[27];
 439         } __attribute__ ((packed)) body;
 440 } __attribute__((packed));
 441
 442 struct intel_hdmi {
 443         u32 hdmi_reg;
 444         int ddc_bus;
 445         uint32_t color_range;
 446         bool color_range_auto;
 447         bool has_hdmi_sink;
 448         bool has_audio;
 449         enum hdmi_force_audio force_audio;
 450         bool rgb_quant_range_selectable;
 451         void (*write_infoframe)(struct drm_encoder *encoder,
 452                                 struct dip_infoframe *frame);
 453         void (*set_infoframes)(struct drm_encoder *encoder,
 454                                struct drm_display_mode *adjusted_mode);
 455 };
 456
 457 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 458 #define DP_LINK_CONFIGURATION_SIZE      9
 459
 460 struct intel_dp {
 461         uint32_t output_reg;
 462         uint32_t aux_ch_ctl_reg;
 463         uint32_t DP;
 464         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
 465         bool has_audio;
 466         enum hdmi_force_audio force_audio;
 467         uint32_t color_range;
 468         bool color_range_auto;
 469         uint8_t link_bw;
 470         uint8_t lane_count;
 471         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 472         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 473         struct i2c_adapter adapter;
 474         struct i2c_algo_dp_aux_data algo;
 475         uint8_t train_set[4];
 476         int panel_power_up_delay;
 477         int panel_power_down_delay;
 478         int panel_power_cycle_delay;
 479         int backlight_on_delay;
 480         int backlight_off_delay;
 481         struct delayed_work panel_vdd_work;
 482         bool want_panel_vdd;
 483         struct intel_connector *attached_connector;
 484 };
 485
 486 struct intel_digital_port {
 487         struct intel_encoder base;
 488         enum port port;
 489         u32 port_reversal;
 490         struct intel_dp dp;
 491         struct intel_hdmi hdmi;
 492 };
 493
 494 static inline int
 495 vlv_dport_to_channel(struct intel_digital_port *dport)
 496 {
 497         switch (dport->port) {
 498         case PORT_B:
 499                 return 0;
 500         case PORT_C:
 501                 return 1;
 502         default:
 503                 BUG();
 504         }
 505 }
 506
 507 static inline struct drm_crtc *
 508 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 509 {
 510         struct drm_i915_private *dev_priv = dev->dev_private;
 511         return dev_priv->pipe_to_crtc_mapping[pipe];
 512 }
 513
 514 static inline struct drm_crtc *
 515 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 516 {
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         return dev_priv->plane_to_crtc_mapping[plane];
 519 }
 520
 521 struct intel_unpin_work {
 522         struct work_struct work;
 523         struct drm_crtc *crtc;
 524         struct drm_i915_gem_object *old_fb_obj;
 525         struct drm_i915_gem_object *pending_flip_obj;
 526         struct drm_pending_vblank_event *event;
 527         atomic_t pending;
 528 #define INTEL_FLIP_INACTIVE     0
 529 #define INTEL_FLIP_PENDING      1
 530 #define INTEL_FLIP_COMPLETE     2
 531         bool enable_stall_check;
 532 };
 533
 534 struct intel_fbc_work {
 535         struct delayed_work work;
 536         struct drm_crtc *crtc;
 537         struct drm_framebuffer *fb;
 538         int interval;
 539 };
 540
 541 int intel_pch_rawclk(struct drm_device *dev);
 542
 543 int intel_connector_update_modes(struct drm_connector *connector,
 544                                 struct edid *edid);
 545 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 546
 547 extern void intel_attach_force_audio_property(struct drm_connector *connector);
 548 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 549
 550 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
 551 extern void intel_crt_init(struct drm_device *dev);
 552 extern void intel_hdmi_init(struct drm_device *dev,
 553                             int hdmi_reg, enum port port);
 554 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 555                                       struct intel_connector *intel_connector);
 556 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 557 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 558                                       struct intel_crtc_config *pipe_config);
 559 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
 560 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
 561                             bool is_sdvob);
 562 extern void intel_dvo_init(struct drm_device *dev);
 563 extern void intel_tv_init(struct drm_device *dev);
 564 extern void intel_mark_busy(struct drm_device *dev);
 565 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
 566 extern void intel_mark_idle(struct drm_device *dev);
 567 extern bool intel_lvds_init(struct drm_device *dev);
 568 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
 569 extern void intel_dp_init(struct drm_device *dev, int output_reg,
 570                           enum port port);
 571 extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 572                                     struct intel_connector *intel_connector);
 573 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
 574 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
 575 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 576 extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 577 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 578 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 579 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
 580 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
 581                                     struct intel_crtc_config *pipe_config);
 582 extern bool intel_dpd_is_edp(struct drm_device *dev);
 583 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
 584 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
 585 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
 586 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
 587 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 588 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 589 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 590 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
 591                                       enum plane plane);
 592
 593 /* intel_panel.c */
 594 extern int intel_panel_init(struct intel_panel *panel,
 595                             struct drm_display_mode *fixed_mode);
 596 extern void intel_panel_fini(struct intel_panel *panel);
 597
 598 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
 599                                    struct drm_display_mode *adjusted_mode);
 600 extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
 601                                     struct intel_crtc_config *pipe_config,
 602                                     int fitting_mode);
 603 extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 604                                      struct intel_crtc_config *pipe_config,
 605                                      int fitting_mode);
 606 extern void intel_panel_set_backlight(struct drm_device *dev,
 607                                       u32 level, u32 max);
 608 extern int intel_panel_setup_backlight(struct drm_connector *connector);
 609 extern void intel_panel_enable_backlight(struct drm_device *dev,
 610                                          enum pipe pipe);
 611 extern void intel_panel_disable_backlight(struct drm_device *dev);
 612 extern void intel_panel_destroy_backlight(struct drm_device *dev);
 613 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 614
 615 struct intel_set_config {
 616         struct drm_encoder **save_connector_encoders;
 617         struct drm_crtc **save_encoder_crtcs;
 618
 619         bool fb_changed;
 620         bool mode_changed;
 621 };
 622
 623 extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
 624                           int x, int y, struct drm_framebuffer *old_fb);
 625 extern void intel_modeset_disable(struct drm_device *dev);
 626 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
 627 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
 628 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
 629 extern void intel_encoder_destroy(struct drm_encoder *encoder);
 630 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
 631 extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
 632 extern void intel_connector_dpms(struct drm_connector *, int mode);
 633 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
 634 extern void intel_modeset_check_state(struct drm_device *dev);
 635 extern void intel_plane_restore(struct drm_plane *plane);
 636
 637
 638 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
 639 {
 640         return to_intel_connector(connector)->encoder;
 641 }
 642
 643 static inline struct intel_digital_port *
 644 enc_to_dig_port(struct drm_encoder *encoder)
 645 {
 646         return container_of(encoder, struct intel_digital_port, base.base);
 647 }
 648
 649 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 650 {
 651         return &enc_to_dig_port(encoder)->dp;
 652 }
 653
 654 static inline struct intel_digital_port *
 655 dp_to_dig_port(struct intel_dp *intel_dp)
 656 {
 657         return container_of(intel_dp, struct intel_digital_port, dp);
 658 }
 659
 660 static inline struct intel_digital_port *
 661 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 662 {
 663         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 664 }
 665
 666 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 667                                 struct intel_digital_port *port);
 668
 669 extern void intel_connector_attach_encoder(struct intel_connector *connector,
 670                                            struct intel_encoder *encoder);
 671 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 672
 673 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 674                                                     struct drm_crtc *crtc);
 675 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 676                                 struct drm_file *file_priv);
 677 extern enum transcoder
 678 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 679                              enum pipe pipe);
 680 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 681 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 682 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 683 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
 684
 685 struct intel_load_detect_pipe {
 686         struct drm_framebuffer *release_fb;
 687         bool load_detect_temp;
 688         int dpms_mode;
 689 };
 690 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
 691                                        struct drm_display_mode *mode,
 692                                        struct intel_load_detect_pipe *old);
 693 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
 694                                            struct intel_load_detect_pipe *old);
 695
 696 extern void intelfb_restore(void);
 697 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 698                                     u16 blue, int regno);
 699 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 700                                     u16 *blue, int regno);
 701 extern void intel_enable_clock_gating(struct drm_device *dev);
 702
 703 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 704                                       struct drm_i915_gem_object *obj,
 705                                       struct intel_ring_buffer *pipelined);
 706 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 707
 708 extern int intel_framebuffer_init(struct drm_device *dev,
 709                                   struct intel_framebuffer *ifb,
 710                                   struct drm_mode_fb_cmd2 *mode_cmd,
 711                                   struct drm_i915_gem_object *obj);
 712 extern int intel_fbdev_init(struct drm_device *dev);
 713 extern void intel_fbdev_initial_config(struct drm_device *dev);
 714 extern void intel_fbdev_fini(struct drm_device *dev);
 715 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 716 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
 717 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
 718 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 719
 720 extern void intel_setup_overlay(struct drm_device *dev);
 721 extern void intel_cleanup_overlay(struct drm_device *dev);
 722 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
 723 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
 724                                    struct drm_file *file_priv);
 725 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
 726                                struct drm_file *file_priv);
 727
 728 extern void intel_fb_output_poll_changed(struct drm_device *dev);
 729 extern void intel_fb_restore_mode(struct drm_device *dev);
 730
 731 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 732                         bool state);
 733 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 734 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 735
 736 extern void intel_init_clock_gating(struct drm_device *dev);
 737 extern void intel_suspend_hw(struct drm_device *dev);
 738 extern void intel_write_eld(struct drm_encoder *encoder,
 739                             struct drm_display_mode *mode);
 740 extern void intel_prepare_ddi(struct drm_device *dev);
 741 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
 742 extern void intel_ddi_init(struct drm_device *dev, enum port port);
 743
 744 /* For use by IVB LP watermark workaround in intel_sprite.c */
 745 extern void intel_update_watermarks(struct drm_device *dev);
 746 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
 747                                            uint32_t sprite_width,
 748                                            int pixel_size, bool enable);
 749
 750 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 751                                                     unsigned int tiling_mode,
 752                                                     unsigned int bpp,
 753                                                     unsigned int pitch);
 754
 755 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 756                                      struct drm_file *file_priv);
 757 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 758                                      struct drm_file *file_priv);
 759
 760 /* Power-related functions, located in intel_pm.c */
 761 extern void intel_init_pm(struct drm_device *dev);
 762 /* FBC */
 763 extern bool intel_fbc_enabled(struct drm_device *dev);
 764 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
 765 extern void intel_update_fbc(struct drm_device *dev);
 766 /* IPS */
 767 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 768 extern void intel_gpu_ips_teardown(void);
 769
 770 extern bool intel_display_power_enabled(struct drm_device *dev,
 771                                         enum intel_display_power_domain domain);
 772 extern void intel_init_power_well(struct drm_device *dev);
 773 extern void intel_set_power_well(struct drm_device *dev, bool enable);
 774 extern void intel_enable_gt_powersave(struct drm_device *dev);
 775 extern void intel_disable_gt_powersave(struct drm_device *dev);
 776 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
 777 extern void ironlake_teardown_rc6(struct drm_device *dev);
 778
 779 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 780                                    enum pipe *pipe);
 781 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 782 extern void intel_ddi_pll_init(struct drm_device *dev);
 783 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 784 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 785                                               enum transcoder cpu_transcoder);
 786 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 787 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 788 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 789 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
 790 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 791 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 792 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 793 extern bool
 794 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 795 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 796
 797 extern void intel_display_handle_reset(struct drm_device *dev);
 798 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 799                                                   enum pipe pipe,
 800                                                   bool enable);
 801 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 802                                                  enum transcoder pch_transcoder,
 803                                                  bool enable);
 804
 805 #endif /* __INTEL_DRV_H__ */