2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
39 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
40 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
43 * _wait_for - magic (register) wait macro
45 * Does the right thing for modeset paths when run under kdgb or similar atomic
46 * contexts. Note that it's important that we check the condition again after
47 * having timed out, since the timeout could be due to preemption or similar and
48 * we've never had a chance to check the condition before the timeout.
50 #define _wait_for(COND, MS, W) ({ \
51 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
54 if (time_after(jiffies, timeout__)) { \
59 if (W && drm_can_sleep()) { \
68 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
69 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
70 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
71 DIV_ROUND_UP((US), 1000), 0)
73 #define KHz(x) (1000 * (x))
74 #define MHz(x) KHz(1000 * (x))
77 * Display related stuff
80 /* store information about an Ixxx DVO */
81 /* The i830->i865 use multiple DVOs with multiple i2cs */
82 /* the i915, i945 have a single sDVO i2c bus - which is different */
84 /* maximum connectors per crtcs in the mode set */
86 /* Maximum cursor sizes */
87 #define GEN2_CURSOR_WIDTH 64
88 #define GEN2_CURSOR_HEIGHT 64
89 #define MAX_CURSOR_WIDTH 256
90 #define MAX_CURSOR_HEIGHT 256
92 #define INTEL_I2C_BUS_DVO 1
93 #define INTEL_I2C_BUS_SDVO 2
95 /* these are outputs from the chip - integrated only
96 external chips are via DVO or SDVO output */
97 #define INTEL_OUTPUT_UNUSED 0
98 #define INTEL_OUTPUT_ANALOG 1
99 #define INTEL_OUTPUT_DVO 2
100 #define INTEL_OUTPUT_SDVO 3
101 #define INTEL_OUTPUT_LVDS 4
102 #define INTEL_OUTPUT_TVOUT 5
103 #define INTEL_OUTPUT_HDMI 6
104 #define INTEL_OUTPUT_DISPLAYPORT 7
105 #define INTEL_OUTPUT_EDP 8
106 #define INTEL_OUTPUT_DSI 9
107 #define INTEL_OUTPUT_UNKNOWN 10
108 #define INTEL_OUTPUT_DP_MST 11
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
118 struct intel_framebuffer
{
119 struct drm_framebuffer base
;
120 struct drm_i915_gem_object
*obj
;
124 struct drm_fb_helper helper
;
125 struct intel_framebuffer
*fb
;
126 struct list_head fbdev_list
;
127 struct drm_display_mode
*our_mode
;
131 struct intel_encoder
{
132 struct drm_encoder base
;
134 * The new crtc this encoder will be driven from. Only differs from
135 * base->crtc while a modeset is in progress.
137 struct intel_crtc
*new_crtc
;
140 unsigned int cloneable
;
141 bool connectors_active
;
142 void (*hot_plug
)(struct intel_encoder
*);
143 bool (*compute_config
)(struct intel_encoder
*,
144 struct intel_crtc_config
*);
145 void (*pre_pll_enable
)(struct intel_encoder
*);
146 void (*pre_enable
)(struct intel_encoder
*);
147 void (*enable
)(struct intel_encoder
*);
148 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
149 void (*disable
)(struct intel_encoder
*);
150 void (*post_disable
)(struct intel_encoder
*);
151 /* Read out the current hw state of this connector, returning true if
152 * the encoder is active. If the encoder is enabled it also set the pipe
153 * it is connected to in the pipe parameter. */
154 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
155 /* Reconstructs the equivalent mode flags for the current hardware
156 * state. This must be called _after_ display->get_pipe_config has
157 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
158 * be set correctly before calling this function. */
159 void (*get_config
)(struct intel_encoder
*,
160 struct intel_crtc_config
*pipe_config
);
162 * Called during system suspend after all pending requests for the
163 * encoder are flushed (for example for DP AUX transactions) and
164 * device interrupts are disabled.
166 void (*suspend
)(struct intel_encoder
*);
168 enum hpd_pin hpd_pin
;
172 struct drm_display_mode
*fixed_mode
;
173 struct drm_display_mode
*downclock_mode
;
183 bool combination_mode
; /* gen 2/4 only */
185 struct backlight_device
*device
;
188 void (*backlight_power
)(struct intel_connector
*, bool enable
);
191 struct intel_connector
{
192 struct drm_connector base
;
194 * The fixed encoder this connector is connected to.
196 struct intel_encoder
*encoder
;
199 * The new encoder this connector will be driven. Only differs from
200 * encoder while a modeset is in progress.
202 struct intel_encoder
*new_encoder
;
204 /* Reads out the current hw, returning true if the connector is enabled
205 * and active (i.e. dpms ON state). */
206 bool (*get_hw_state
)(struct intel_connector
*);
209 * Removes all interfaces through which the connector is accessible
210 * - like sysfs, debugfs entries -, so that no new operations can be
211 * started on the connector. Also makes sure all currently pending
212 * operations finish before returing.
214 void (*unregister
)(struct intel_connector
*);
216 /* Panel info for eDP and LVDS */
217 struct intel_panel panel
;
219 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
221 struct edid
*detect_edid
;
223 /* since POLL and HPD connectors may use the same HPD line keep the native
224 state of connector->polled in case hotplug storm detection changes it */
227 void *port
; /* store this opaque as its illegal to dereference it */
229 struct intel_dp
*mst_port
;
232 typedef struct dpll
{
244 struct intel_plane_state
{
245 struct drm_crtc
*crtc
;
246 struct drm_framebuffer
*fb
;
249 struct drm_rect clip
;
250 struct drm_rect orig_src
;
251 struct drm_rect orig_dst
;
255 struct intel_plane_config
{
261 struct intel_crtc_config
{
263 * quirks - bitfield with hw state readout quirks
265 * For various reasons the hw state readout code might not be able to
266 * completely faithfully read out the current state. These cases are
267 * tracked with quirk flags so that fastboot and state checker can act
270 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
271 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
272 unsigned long quirks
;
274 /* User requested mode, only valid as a starting point to
275 * compute adjusted_mode, except in the case of (S)DVO where
276 * it's also for the output timings of the (S)DVO chip.
277 * adjusted_mode will then correspond to the S(DVO) chip's
278 * preferred input timings. */
279 struct drm_display_mode requested_mode
;
280 /* Actual pipe timings ie. what we program into the pipe timing
281 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
282 struct drm_display_mode adjusted_mode
;
284 /* Pipe source size (ie. panel fitter input size)
285 * All planes will be positioned inside this space,
286 * and get clipped at the edges. */
287 int pipe_src_w
, pipe_src_h
;
289 /* Whether to set up the PCH/FDI. Note that we never allow sharing
290 * between pch encoders and cpu encoders. */
291 bool has_pch_encoder
;
293 /* CPU Transcoder for the pipe. Currently this can only differ from the
294 * pipe on Haswell (where we have a special eDP transcoder). */
295 enum transcoder cpu_transcoder
;
298 * Use reduced/limited/broadcast rbg range, compressing from the full
299 * range fed into the crtcs.
301 bool limited_color_range
;
303 /* DP has a bunch of special case unfortunately, so mark the pipe
307 /* Whether we should send NULL infoframes. Required for audio. */
310 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
311 * has_dp_encoder is set. */
315 * Enable dithering, used when the selected pipe bpp doesn't match the
320 /* Controls for the clock computation, to override various stages. */
323 /* SDVO TV has a bunch of special case. To make multifunction encoders
324 * work correctly, we need to track this at runtime.*/
328 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
329 * required. This is set in the 2nd loop of calling encoder's
330 * ->compute_config if the first pick doesn't work out.
334 /* Settings for the intel dpll used on pretty much everything but
338 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
339 enum intel_dpll_id shared_dpll
;
341 /* PORT_CLK_SEL for DDI ports. */
342 uint32_t ddi_pll_sel
;
344 /* Actual register state of the dpll, for shared dpll cross-checking. */
345 struct intel_dpll_hw_state dpll_hw_state
;
348 struct intel_link_m_n dp_m_n
;
350 /* m2_n2 for eDP downclock */
351 struct intel_link_m_n dp_m2_n2
;
355 * Frequence the dpll for the port should run at. Differs from the
356 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
357 * already multiplied by pixel_multiplier.
361 /* Used by SDVO (and if we ever fix it, HDMI). */
362 unsigned pixel_multiplier
;
364 /* Panel fitter controls for gen2-gen4 + VLV */
368 u32 lvds_border_bits
;
371 /* Panel fitter placement and size for Ironlake+ */
379 /* FDI configuration, only valid if has_pch_encoder is set. */
381 struct intel_link_m_n fdi_m_n
;
387 bool dp_encoder_is_mst
;
391 struct intel_pipe_wm
{
392 struct intel_wm_level wm
[5];
396 bool sprites_enabled
;
400 struct intel_mmio_flip
{
406 struct drm_crtc base
;
409 u8 lut_r
[256], lut_g
[256], lut_b
[256];
411 * Whether the crtc and the connected output pipeline is active. Implies
412 * that crtc->enabled is set, i.e. the current mode configuration has
413 * some outputs connected to this crtc.
416 unsigned long enabled_power_domains
;
417 bool primary_enabled
; /* is the primary plane (partially) visible? */
419 struct intel_overlay
*overlay
;
420 struct intel_unpin_work
*unpin_work
;
422 atomic_t unpin_work_count
;
424 /* Display surface base address adjustement for pageflips. Note that on
425 * gen4+ this only adjusts up to a tile, offsets within a tile are
426 * handled in the hw itself (with the TILEOFF register). */
427 unsigned long dspaddr_offset
;
429 struct drm_i915_gem_object
*cursor_bo
;
430 uint32_t cursor_addr
;
431 int16_t cursor_width
, cursor_height
;
432 uint32_t cursor_cntl
;
433 uint32_t cursor_size
;
434 uint32_t cursor_base
;
436 struct intel_plane_config plane_config
;
437 struct intel_crtc_config config
;
438 struct intel_crtc_config
*new_config
;
441 /* reset counter value when the last flip was submitted */
442 unsigned int reset_counter
;
444 /* Access to these should be protected by dev_priv->irq_lock. */
445 bool cpu_fifo_underrun_disabled
;
446 bool pch_fifo_underrun_disabled
;
448 /* per-pipe watermark state */
450 /* watermarks currently being used */
451 struct intel_pipe_wm active
;
455 struct intel_mmio_flip mmio_flip
;
458 struct intel_plane_wm_parameters
{
459 uint32_t horiz_pixels
;
460 uint32_t vert_pixels
;
461 uint8_t bytes_per_pixel
;
467 struct drm_plane base
;
470 struct drm_i915_gem_object
*obj
;
474 unsigned int crtc_w
, crtc_h
;
475 uint32_t src_x
, src_y
;
476 uint32_t src_w
, src_h
;
477 unsigned int rotation
;
479 /* Since we need to change the watermarks before/after
480 * enabling/disabling the planes, we need to store the parameters here
481 * as the other pieces of the struct may not reflect the values we want
482 * for the watermark calculations. Currently only Haswell uses this.
484 struct intel_plane_wm_parameters wm
;
486 void (*update_plane
)(struct drm_plane
*plane
,
487 struct drm_crtc
*crtc
,
488 struct drm_framebuffer
*fb
,
489 struct drm_i915_gem_object
*obj
,
490 int crtc_x
, int crtc_y
,
491 unsigned int crtc_w
, unsigned int crtc_h
,
492 uint32_t x
, uint32_t y
,
493 uint32_t src_w
, uint32_t src_h
);
494 void (*disable_plane
)(struct drm_plane
*plane
,
495 struct drm_crtc
*crtc
);
496 int (*update_colorkey
)(struct drm_plane
*plane
,
497 struct drm_intel_sprite_colorkey
*key
);
498 void (*get_colorkey
)(struct drm_plane
*plane
,
499 struct drm_intel_sprite_colorkey
*key
);
502 struct intel_watermark_params
{
503 unsigned long fifo_size
;
504 unsigned long max_wm
;
505 unsigned long default_wm
;
506 unsigned long guard_size
;
507 unsigned long cacheline_size
;
510 struct cxsr_latency
{
513 unsigned long fsb_freq
;
514 unsigned long mem_freq
;
515 unsigned long display_sr
;
516 unsigned long display_hpll_disable
;
517 unsigned long cursor_sr
;
518 unsigned long cursor_hpll_disable
;
521 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
522 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
523 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
524 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
525 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
526 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
531 uint32_t color_range
;
532 bool color_range_auto
;
535 enum hdmi_force_audio force_audio
;
536 bool rgb_quant_range_selectable
;
537 enum hdmi_picture_aspect aspect_ratio
;
538 void (*write_infoframe
)(struct drm_encoder
*encoder
,
539 enum hdmi_infoframe_type type
,
540 const void *frame
, ssize_t len
);
541 void (*set_infoframes
)(struct drm_encoder
*encoder
,
543 struct drm_display_mode
*adjusted_mode
);
546 struct intel_dp_mst_encoder
;
547 #define DP_MAX_DOWNSTREAM_PORTS 0x10
550 * HIGH_RR is the highest eDP panel refresh rate read from EDID
551 * LOW_RR is the lowest eDP panel refresh rate found from EDID
552 * parsing for same resolution.
554 enum edp_drrs_refresh_rate_type
{
557 DRRS_MAX_RR
, /* RR count */
562 uint32_t aux_ch_ctl_reg
;
565 enum hdmi_force_audio force_audio
;
566 uint32_t color_range
;
567 bool color_range_auto
;
570 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
571 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
572 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
573 struct drm_dp_aux aux
;
574 uint8_t train_set
[4];
575 int panel_power_up_delay
;
576 int panel_power_down_delay
;
577 int panel_power_cycle_delay
;
578 int backlight_on_delay
;
579 int backlight_off_delay
;
580 struct delayed_work panel_vdd_work
;
582 unsigned long last_power_cycle
;
583 unsigned long last_power_on
;
584 unsigned long last_backlight_off
;
586 struct notifier_block edp_notifier
;
589 * Pipe whose power sequencer is currently locked into
590 * this port. Only relevant on VLV/CHV.
595 bool can_mst
; /* this port supports mst */
597 int active_mst_links
;
598 /* connector directly attached - won't be use for modeset in mst world */
599 struct intel_connector
*attached_connector
;
601 /* mst connector list */
602 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
603 struct drm_dp_mst_topology_mgr mst_mgr
;
605 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
607 * This function returns the value we have to program the AUX_CTL
608 * register with to kick off an AUX transaction.
610 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
613 uint32_t aux_clock_divider
);
615 enum drrs_support_type type
;
616 enum edp_drrs_refresh_rate_type refresh_rate_type
;
622 struct intel_digital_port
{
623 struct intel_encoder base
;
627 struct intel_hdmi hdmi
;
628 bool (*hpd_pulse
)(struct intel_digital_port
*, bool);
631 struct intel_dp_mst_encoder
{
632 struct intel_encoder base
;
634 struct intel_digital_port
*primary
;
635 void *port
; /* store this opaque as its illegal to dereference it */
639 vlv_dport_to_channel(struct intel_digital_port
*dport
)
641 switch (dport
->port
) {
653 vlv_pipe_to_channel(enum pipe pipe
)
666 static inline struct drm_crtc
*
667 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
670 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
673 static inline struct drm_crtc
*
674 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
677 return dev_priv
->plane_to_crtc_mapping
[plane
];
680 struct intel_unpin_work
{
681 struct work_struct work
;
682 struct drm_crtc
*crtc
;
683 struct drm_i915_gem_object
*old_fb_obj
;
684 struct drm_i915_gem_object
*pending_flip_obj
;
685 struct drm_pending_vblank_event
*event
;
687 #define INTEL_FLIP_INACTIVE 0
688 #define INTEL_FLIP_PENDING 1
689 #define INTEL_FLIP_COMPLETE 2
692 struct intel_engine_cs
*flip_queued_ring
;
693 u32 flip_queued_seqno
;
694 int flip_queued_vblank
;
695 int flip_ready_vblank
;
696 bool enable_stall_check
;
699 struct intel_set_config
{
700 struct drm_encoder
**save_connector_encoders
;
701 struct drm_crtc
**save_encoder_crtcs
;
702 bool *save_crtc_enabled
;
708 struct intel_load_detect_pipe
{
709 struct drm_framebuffer
*release_fb
;
710 bool load_detect_temp
;
714 static inline struct intel_encoder
*
715 intel_attached_encoder(struct drm_connector
*connector
)
717 return to_intel_connector(connector
)->encoder
;
720 static inline struct intel_digital_port
*
721 enc_to_dig_port(struct drm_encoder
*encoder
)
723 return container_of(encoder
, struct intel_digital_port
, base
.base
);
726 static inline struct intel_dp_mst_encoder
*
727 enc_to_mst(struct drm_encoder
*encoder
)
729 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
732 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
734 return &enc_to_dig_port(encoder
)->dp
;
737 static inline struct intel_digital_port
*
738 dp_to_dig_port(struct intel_dp
*intel_dp
)
740 return container_of(intel_dp
, struct intel_digital_port
, dp
);
743 static inline struct intel_digital_port
*
744 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
746 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
750 * Returns the number of planes for this pipe, ie the number of sprites + 1
751 * (primary plane). This doesn't count the cursor plane then.
753 static inline unsigned int intel_num_planes(struct intel_crtc
*crtc
)
755 return INTEL_INFO(crtc
->base
.dev
)->num_sprites
[crtc
->pipe
] + 1;
758 /* intel_fifo_underrun.c */
759 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
760 enum pipe pipe
, bool enable
);
761 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
762 enum transcoder pch_transcoder
,
764 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
766 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
767 enum transcoder pch_transcoder
);
768 void i9xx_check_fifo_underruns(struct drm_i915_private
*dev_priv
);
769 bool __cpu_fifo_underrun_reporting_enabled(struct drm_i915_private
*dev_priv
,
773 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
774 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
775 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
776 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
777 void gen8_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
778 void gen8_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
779 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
780 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
781 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
784 * We only use drm_irq_uninstall() at unload and VT switch, so
785 * this is the only thing we need to check.
787 return dev_priv
->pm
.irqs_enabled
;
790 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
791 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
);
794 void intel_crt_init(struct drm_device
*dev
);
798 void intel_prepare_ddi(struct drm_device
*dev
);
799 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
800 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
801 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
802 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
803 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
);
804 void intel_ddi_pll_init(struct drm_device
*dev
);
805 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
806 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
807 enum transcoder cpu_transcoder
);
808 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
809 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
810 bool intel_ddi_pll_select(struct intel_crtc
*crtc
);
811 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
812 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
);
813 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
814 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
815 void intel_ddi_get_config(struct intel_encoder
*encoder
,
816 struct intel_crtc_config
*pipe_config
);
818 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
819 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
820 struct intel_crtc_config
*pipe_config
);
821 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
823 /* intel_frontbuffer.c */
824 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
825 struct intel_engine_cs
*ring
);
826 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
827 unsigned frontbuffer_bits
);
828 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
829 unsigned frontbuffer_bits
);
830 void intel_frontbuffer_flush(struct drm_device
*dev
,
831 unsigned frontbuffer_bits
);
833 * intel_frontbuffer_flip - synchronous frontbuffer flip
835 * @frontbuffer_bits: frontbuffer plane tracking bits
837 * This function gets called after scheduling a flip on @obj. This is for
838 * synchronous plane updates which will happen on the next vblank and which will
839 * not get delayed by pending gpu rendering.
841 * Can be called without any locks held.
844 void intel_frontbuffer_flip(struct drm_device
*dev
,
845 unsigned frontbuffer_bits
)
847 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
850 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
, bool retire
);
853 /* intel_display.c */
854 const char *intel_output_name(int output
);
855 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
856 int intel_pch_rawclk(struct drm_device
*dev
);
857 void intel_mark_busy(struct drm_device
*dev
);
858 void intel_mark_idle(struct drm_device
*dev
);
859 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
860 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
);
861 void intel_crtc_update_dpms(struct drm_crtc
*crtc
);
862 void intel_encoder_destroy(struct drm_encoder
*encoder
);
863 void intel_connector_dpms(struct drm_connector
*, int mode
);
864 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
865 void intel_modeset_check_state(struct drm_device
*dev
);
866 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
867 struct intel_digital_port
*port
);
868 void intel_connector_attach_encoder(struct intel_connector
*connector
,
869 struct intel_encoder
*encoder
);
870 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
871 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
872 struct drm_crtc
*crtc
);
873 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
874 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
875 struct drm_file
*file_priv
);
876 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
879 intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
881 drm_wait_one_vblank(dev
, pipe
);
883 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
884 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
885 struct intel_digital_port
*dport
);
886 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
887 struct drm_display_mode
*mode
,
888 struct intel_load_detect_pipe
*old
,
889 struct drm_modeset_acquire_ctx
*ctx
);
890 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
891 struct intel_load_detect_pipe
*old
);
892 int intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
893 struct drm_i915_gem_object
*obj
,
894 struct intel_engine_cs
*pipelined
);
895 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
);
896 struct drm_framebuffer
*
897 __intel_framebuffer_create(struct drm_device
*dev
,
898 struct drm_mode_fb_cmd2
*mode_cmd
,
899 struct drm_i915_gem_object
*obj
);
900 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
901 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
902 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
903 void intel_check_page_flip(struct drm_device
*dev
, int pipe
);
905 /* shared dpll functions */
906 struct intel_shared_dpll
*intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
);
907 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
908 struct intel_shared_dpll
*pll
,
910 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
911 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
912 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
);
913 void intel_put_shared_dpll(struct intel_crtc
*crtc
);
915 /* modesetting asserts */
916 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
918 void assert_pll(struct drm_i915_private
*dev_priv
,
919 enum pipe pipe
, bool state
);
920 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
921 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
922 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
923 enum pipe pipe
, bool state
);
924 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
925 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
926 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
927 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
928 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
929 void intel_write_eld(struct drm_encoder
*encoder
,
930 struct drm_display_mode
*mode
);
931 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
932 unsigned int tiling_mode
,
935 void intel_display_handle_reset(struct drm_device
*dev
);
936 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
937 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
938 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
939 struct intel_crtc_config
*pipe_config
);
940 void intel_dp_set_m_n(struct intel_crtc
*crtc
);
941 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
943 ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
945 bool intel_crtc_active(struct drm_crtc
*crtc
);
946 void hsw_enable_ips(struct intel_crtc
*crtc
);
947 void hsw_disable_ips(struct intel_crtc
*crtc
);
948 enum intel_display_power_domain
949 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
950 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
951 struct intel_crtc_config
*pipe_config
);
952 int intel_format_to_fourcc(int format
);
953 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
);
954 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
);
957 void intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
);
958 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
959 struct intel_connector
*intel_connector
);
960 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
961 void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
962 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
963 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
964 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
965 void intel_dp_check_link_status(struct intel_dp
*intel_dp
);
966 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
967 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
968 struct intel_crtc_config
*pipe_config
);
969 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
970 bool intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
972 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
973 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
974 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
975 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
);
976 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
977 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
978 void intel_edp_psr_enable(struct intel_dp
*intel_dp
);
979 void intel_edp_psr_disable(struct intel_dp
*intel_dp
);
980 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
);
981 void intel_edp_psr_invalidate(struct drm_device
*dev
,
982 unsigned frontbuffer_bits
);
983 void intel_edp_psr_flush(struct drm_device
*dev
,
984 unsigned frontbuffer_bits
);
985 void intel_edp_psr_init(struct drm_device
*dev
);
987 int intel_dp_handle_hpd_irq(struct intel_digital_port
*digport
, bool long_hpd
);
988 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
989 void intel_dp_mst_suspend(struct drm_device
*dev
);
990 void intel_dp_mst_resume(struct drm_device
*dev
);
991 int intel_dp_max_link_bw(struct intel_dp
*intel_dp
);
992 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
993 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
995 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
996 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
998 void intel_dsi_init(struct drm_device
*dev
);
1002 void intel_dvo_init(struct drm_device
*dev
);
1005 /* legacy fbdev emulation in intel_fbdev.c */
1006 #ifdef CONFIG_DRM_I915_FBDEV
1007 extern int intel_fbdev_init(struct drm_device
*dev
);
1008 extern void intel_fbdev_initial_config(void *data
, async_cookie_t cookie
);
1009 extern void intel_fbdev_fini(struct drm_device
*dev
);
1010 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1011 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1012 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1014 static inline int intel_fbdev_init(struct drm_device
*dev
)
1019 static inline void intel_fbdev_initial_config(void *data
, async_cookie_t cookie
)
1023 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1027 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1031 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1037 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
);
1038 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1039 struct intel_connector
*intel_connector
);
1040 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1041 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1042 struct intel_crtc_config
*pipe_config
);
1046 void intel_lvds_init(struct drm_device
*dev
);
1047 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1051 int intel_connector_update_modes(struct drm_connector
*connector
,
1053 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1054 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1055 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1058 /* intel_overlay.c */
1059 void intel_setup_overlay(struct drm_device
*dev
);
1060 void intel_cleanup_overlay(struct drm_device
*dev
);
1061 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1062 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1063 struct drm_file
*file_priv
);
1064 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1065 struct drm_file
*file_priv
);
1069 int intel_panel_init(struct intel_panel
*panel
,
1070 struct drm_display_mode
*fixed_mode
,
1071 struct drm_display_mode
*downclock_mode
);
1072 void intel_panel_fini(struct intel_panel
*panel
);
1073 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1074 struct drm_display_mode
*adjusted_mode
);
1075 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1076 struct intel_crtc_config
*pipe_config
,
1078 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1079 struct intel_crtc_config
*pipe_config
,
1081 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1082 u32 level
, u32 max
);
1083 int intel_panel_setup_backlight(struct drm_connector
*connector
);
1084 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1085 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1086 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1087 void intel_panel_init_backlight_funcs(struct drm_device
*dev
);
1088 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1089 extern struct drm_display_mode
*intel_find_panel_downclock(
1090 struct drm_device
*dev
,
1091 struct drm_display_mode
*fixed_mode
,
1092 struct drm_connector
*connector
);
1094 /* intel_runtime_pm.c */
1095 int intel_power_domains_init(struct drm_i915_private
*);
1096 void intel_power_domains_fini(struct drm_i915_private
*);
1097 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
);
1098 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1100 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1101 enum intel_display_power_domain domain
);
1102 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1103 enum intel_display_power_domain domain
);
1104 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1105 enum intel_display_power_domain domain
);
1106 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1107 enum intel_display_power_domain domain
);
1108 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
);
1109 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
);
1110 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1111 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1112 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1114 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1117 void intel_init_clock_gating(struct drm_device
*dev
);
1118 void intel_suspend_hw(struct drm_device
*dev
);
1119 int ilk_wm_max_level(const struct drm_device
*dev
);
1120 void intel_update_watermarks(struct drm_crtc
*crtc
);
1121 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
1122 struct drm_crtc
*crtc
,
1123 uint32_t sprite_width
,
1124 uint32_t sprite_height
,
1126 bool enabled
, bool scaled
);
1127 void intel_init_pm(struct drm_device
*dev
);
1128 void intel_pm_setup(struct drm_device
*dev
);
1129 bool intel_fbc_enabled(struct drm_device
*dev
);
1130 void intel_update_fbc(struct drm_device
*dev
);
1131 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1132 void intel_gpu_ips_teardown(void);
1133 void intel_init_gt_powersave(struct drm_device
*dev
);
1134 void intel_cleanup_gt_powersave(struct drm_device
*dev
);
1135 void intel_enable_gt_powersave(struct drm_device
*dev
);
1136 void intel_disable_gt_powersave(struct drm_device
*dev
);
1137 void intel_suspend_gt_powersave(struct drm_device
*dev
);
1138 void intel_reset_gt_powersave(struct drm_device
*dev
);
1139 void ironlake_teardown_rc6(struct drm_device
*dev
);
1140 void gen6_update_ring_freq(struct drm_device
*dev
);
1141 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1142 void gen6_rps_boost(struct drm_i915_private
*dev_priv
);
1143 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1147 bool intel_sdvo_init(struct drm_device
*dev
, uint32_t sdvo_reg
, bool is_sdvob
);
1150 /* intel_sprite.c */
1151 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
1152 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
1154 int intel_plane_set_property(struct drm_plane
*plane
,
1155 struct drm_property
*prop
,
1157 int intel_plane_restore(struct drm_plane
*plane
);
1158 void intel_plane_disable(struct drm_plane
*plane
);
1159 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1160 struct drm_file
*file_priv
);
1161 int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
1162 struct drm_file
*file_priv
);
1166 void intel_tv_init(struct drm_device
*dev
);
1168 #endif /* __INTEL_DRV_H__ */