2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <linux/hdmi.h>
30 #include <drm/i915_drm.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_dp_helper.h>
38 * _wait_for - magic (register) wait macro
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
45 #define _wait_for(COND, MS, W) ({ \
46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
49 if (time_after(jiffies, timeout__)) { \
54 if (W && drm_can_sleep()) { \
63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
68 #define KHz(x) (1000 * (x))
69 #define MHz(x) KHz(1000 * (x))
72 * Display related stuff
75 /* store information about an Ixxx DVO */
76 /* The i830->i865 use multiple DVOs with multiple i2cs */
77 /* the i915, i945 have a single sDVO i2c bus - which is different */
79 /* maximum connectors per crtcs in the mode set */
81 #define INTEL_I2C_BUS_DVO 1
82 #define INTEL_I2C_BUS_SDVO 2
84 /* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86 #define INTEL_OUTPUT_UNUSED 0
87 #define INTEL_OUTPUT_ANALOG 1
88 #define INTEL_OUTPUT_DVO 2
89 #define INTEL_OUTPUT_SDVO 3
90 #define INTEL_OUTPUT_LVDS 4
91 #define INTEL_OUTPUT_TVOUT 5
92 #define INTEL_OUTPUT_HDMI 6
93 #define INTEL_OUTPUT_DISPLAYPORT 7
94 #define INTEL_OUTPUT_EDP 8
95 #define INTEL_OUTPUT_DSI 9
96 #define INTEL_OUTPUT_UNKNOWN 10
98 #define INTEL_DVO_CHIP_NONE 0
99 #define INTEL_DVO_CHIP_LVDS 1
100 #define INTEL_DVO_CHIP_TMDS 2
101 #define INTEL_DVO_CHIP_TVOUT 4
103 #define INTEL_DSI_COMMAND_MODE 0
104 #define INTEL_DSI_VIDEO_MODE 1
106 struct intel_framebuffer
{
107 struct drm_framebuffer base
;
108 struct drm_i915_gem_object
*obj
;
112 struct drm_fb_helper helper
;
113 struct intel_framebuffer
*fb
;
114 struct list_head fbdev_list
;
115 struct drm_display_mode
*our_mode
;
118 struct intel_encoder
{
119 struct drm_encoder base
;
121 * The new crtc this encoder will be driven from. Only differs from
122 * base->crtc while a modeset is in progress.
124 struct intel_crtc
*new_crtc
;
128 * Intel hw has only one MUX where encoders could be clone, hence a
129 * simple flag is enough to compute the possible_clones mask.
132 bool connectors_active
;
133 void (*hot_plug
)(struct intel_encoder
*);
134 bool (*compute_config
)(struct intel_encoder
*,
135 struct intel_crtc_config
*);
136 void (*pre_pll_enable
)(struct intel_encoder
*);
137 void (*pre_enable
)(struct intel_encoder
*);
138 void (*enable
)(struct intel_encoder
*);
139 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
140 void (*disable
)(struct intel_encoder
*);
141 void (*post_disable
)(struct intel_encoder
*);
142 /* Read out the current hw state of this connector, returning true if
143 * the encoder is active. If the encoder is enabled it also set the pipe
144 * it is connected to in the pipe parameter. */
145 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
146 /* Reconstructs the equivalent mode flags for the current hardware
147 * state. This must be called _after_ display->get_pipe_config has
148 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
149 * be set correctly before calling this function. */
150 void (*get_config
)(struct intel_encoder
*,
151 struct intel_crtc_config
*pipe_config
);
153 enum hpd_pin hpd_pin
;
157 struct drm_display_mode
*fixed_mode
;
158 struct drm_display_mode
*downclock_mode
;
167 bool combination_mode
; /* gen 2/4 only */
169 struct backlight_device
*device
;
173 struct intel_connector
{
174 struct drm_connector base
;
176 * The fixed encoder this connector is connected to.
178 struct intel_encoder
*encoder
;
181 * The new encoder this connector will be driven. Only differs from
182 * encoder while a modeset is in progress.
184 struct intel_encoder
*new_encoder
;
186 /* Reads out the current hw, returning true if the connector is enabled
187 * and active (i.e. dpms ON state). */
188 bool (*get_hw_state
)(struct intel_connector
*);
191 * Removes all interfaces through which the connector is accessible
192 * - like sysfs, debugfs entries -, so that no new operations can be
193 * started on the connector. Also makes sure all currently pending
194 * operations finish before returing.
196 void (*unregister
)(struct intel_connector
*);
198 /* Panel info for eDP and LVDS */
199 struct intel_panel panel
;
201 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
204 /* since POLL and HPD connectors may use the same HPD line keep the native
205 state of connector->polled in case hotplug storm detection changes it */
209 typedef struct dpll
{
221 struct intel_crtc_config
{
223 * quirks - bitfield with hw state readout quirks
225 * For various reasons the hw state readout code might not be able to
226 * completely faithfully read out the current state. These cases are
227 * tracked with quirk flags so that fastboot and state checker can act
230 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
231 unsigned long quirks
;
233 /* User requested mode, only valid as a starting point to
234 * compute adjusted_mode, except in the case of (S)DVO where
235 * it's also for the output timings of the (S)DVO chip.
236 * adjusted_mode will then correspond to the S(DVO) chip's
237 * preferred input timings. */
238 struct drm_display_mode requested_mode
;
239 /* Actual pipe timings ie. what we program into the pipe timing
240 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
241 struct drm_display_mode adjusted_mode
;
243 /* Pipe source size (ie. panel fitter input size)
244 * All planes will be positioned inside this space,
245 * and get clipped at the edges. */
246 int pipe_src_w
, pipe_src_h
;
248 /* Whether to set up the PCH/FDI. Note that we never allow sharing
249 * between pch encoders and cpu encoders. */
250 bool has_pch_encoder
;
252 /* CPU Transcoder for the pipe. Currently this can only differ from the
253 * pipe on Haswell (where we have a special eDP transcoder). */
254 enum transcoder cpu_transcoder
;
257 * Use reduced/limited/broadcast rbg range, compressing from the full
258 * range fed into the crtcs.
260 bool limited_color_range
;
262 /* DP has a bunch of special case unfortunately, so mark the pipe
267 * Enable dithering, used when the selected pipe bpp doesn't match the
272 /* Controls for the clock computation, to override various stages. */
275 /* SDVO TV has a bunch of special case. To make multifunction encoders
276 * work correctly, we need to track this at runtime.*/
280 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
281 * required. This is set in the 2nd loop of calling encoder's
282 * ->compute_config if the first pick doesn't work out.
286 /* Settings for the intel dpll used on pretty much everything but
290 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
291 enum intel_dpll_id shared_dpll
;
293 /* Actual register state of the dpll, for shared dpll cross-checking. */
294 struct intel_dpll_hw_state dpll_hw_state
;
297 struct intel_link_m_n dp_m_n
;
300 * Frequence the dpll for the port should run at. Differs from the
301 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
302 * already multiplied by pixel_multiplier.
306 /* Used by SDVO (and if we ever fix it, HDMI). */
307 unsigned pixel_multiplier
;
309 /* Panel fitter controls for gen2-gen4 + VLV */
313 u32 lvds_border_bits
;
316 /* Panel fitter placement and size for Ironlake+ */
323 /* FDI configuration, only valid if has_pch_encoder is set. */
325 struct intel_link_m_n fdi_m_n
;
332 struct intel_pipe_wm
{
333 struct intel_wm_level wm
[5];
339 struct drm_crtc base
;
342 u8 lut_r
[256], lut_g
[256], lut_b
[256];
344 * Whether the crtc and the connected output pipeline is active. Implies
345 * that crtc->enabled is set, i.e. the current mode configuration has
346 * some outputs connected to this crtc.
349 unsigned long enabled_power_domains
;
351 bool primary_enabled
; /* is the primary plane (partially) visible? */
353 struct intel_overlay
*overlay
;
354 struct intel_unpin_work
*unpin_work
;
356 atomic_t unpin_work_count
;
358 /* Display surface base address adjustement for pageflips. Note that on
359 * gen4+ this only adjusts up to a tile, offsets within a tile are
360 * handled in the hw itself (with the TILEOFF register). */
361 unsigned long dspaddr_offset
;
363 struct drm_i915_gem_object
*cursor_bo
;
364 uint32_t cursor_addr
;
365 int16_t cursor_x
, cursor_y
;
366 int16_t cursor_width
, cursor_height
;
369 struct intel_crtc_config config
;
370 struct intel_crtc_config
*new_config
;
373 uint32_t ddi_pll_sel
;
375 /* reset counter value when the last flip was submitted */
376 unsigned int reset_counter
;
378 /* Access to these should be protected by dev_priv->irq_lock. */
379 bool cpu_fifo_underrun_disabled
;
380 bool pch_fifo_underrun_disabled
;
382 /* per-pipe watermark state */
384 /* watermarks currently being used */
385 struct intel_pipe_wm active
;
389 struct intel_plane_wm_parameters
{
390 uint32_t horiz_pixels
;
391 uint8_t bytes_per_pixel
;
397 struct drm_plane base
;
400 struct drm_i915_gem_object
*obj
;
403 u32 lut_r
[1024], lut_g
[1024], lut_b
[1024];
405 unsigned int crtc_w
, crtc_h
;
406 uint32_t src_x
, src_y
;
407 uint32_t src_w
, src_h
;
409 /* Since we need to change the watermarks before/after
410 * enabling/disabling the planes, we need to store the parameters here
411 * as the other pieces of the struct may not reflect the values we want
412 * for the watermark calculations. Currently only Haswell uses this.
414 struct intel_plane_wm_parameters wm
;
416 void (*update_plane
)(struct drm_plane
*plane
,
417 struct drm_crtc
*crtc
,
418 struct drm_framebuffer
*fb
,
419 struct drm_i915_gem_object
*obj
,
420 int crtc_x
, int crtc_y
,
421 unsigned int crtc_w
, unsigned int crtc_h
,
422 uint32_t x
, uint32_t y
,
423 uint32_t src_w
, uint32_t src_h
);
424 void (*disable_plane
)(struct drm_plane
*plane
,
425 struct drm_crtc
*crtc
);
426 int (*update_colorkey
)(struct drm_plane
*plane
,
427 struct drm_intel_sprite_colorkey
*key
);
428 void (*get_colorkey
)(struct drm_plane
*plane
,
429 struct drm_intel_sprite_colorkey
*key
);
432 struct intel_watermark_params
{
433 unsigned long fifo_size
;
434 unsigned long max_wm
;
435 unsigned long default_wm
;
436 unsigned long guard_size
;
437 unsigned long cacheline_size
;
440 struct cxsr_latency
{
443 unsigned long fsb_freq
;
444 unsigned long mem_freq
;
445 unsigned long display_sr
;
446 unsigned long display_hpll_disable
;
447 unsigned long cursor_sr
;
448 unsigned long cursor_hpll_disable
;
451 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
452 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
453 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
454 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
455 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
460 uint32_t color_range
;
461 bool color_range_auto
;
464 enum hdmi_force_audio force_audio
;
465 bool rgb_quant_range_selectable
;
466 void (*write_infoframe
)(struct drm_encoder
*encoder
,
467 enum hdmi_infoframe_type type
,
468 const void *frame
, ssize_t len
);
469 void (*set_infoframes
)(struct drm_encoder
*encoder
,
470 struct drm_display_mode
*adjusted_mode
);
473 #define DP_MAX_DOWNSTREAM_PORTS 0x10
477 uint32_t aux_ch_ctl_reg
;
480 enum hdmi_force_audio force_audio
;
481 uint32_t color_range
;
482 bool color_range_auto
;
485 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
486 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
487 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
488 struct i2c_adapter adapter
;
489 struct i2c_algo_dp_aux_data algo
;
490 uint8_t train_set
[4];
491 int panel_power_up_delay
;
492 int panel_power_down_delay
;
493 int panel_power_cycle_delay
;
494 int backlight_on_delay
;
495 int backlight_off_delay
;
496 struct delayed_work panel_vdd_work
;
498 unsigned long last_power_cycle
;
499 unsigned long last_power_on
;
500 unsigned long last_backlight_off
;
503 struct intel_connector
*attached_connector
;
505 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
507 * This function returns the value we have to program the AUX_CTL
508 * register with to kick off an AUX transaction.
510 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
513 uint32_t aux_clock_divider
);
516 struct intel_digital_port
{
517 struct intel_encoder base
;
521 struct intel_hdmi hdmi
;
525 vlv_dport_to_channel(struct intel_digital_port
*dport
)
527 switch (dport
->port
) {
537 static inline struct drm_crtc
*
538 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
541 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
544 static inline struct drm_crtc
*
545 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
548 return dev_priv
->plane_to_crtc_mapping
[plane
];
551 struct intel_unpin_work
{
552 struct work_struct work
;
553 struct drm_crtc
*crtc
;
554 struct drm_i915_gem_object
*old_fb_obj
;
555 struct drm_i915_gem_object
*pending_flip_obj
;
556 struct drm_pending_vblank_event
*event
;
558 #define INTEL_FLIP_INACTIVE 0
559 #define INTEL_FLIP_PENDING 1
560 #define INTEL_FLIP_COMPLETE 2
561 bool enable_stall_check
;
564 struct intel_set_config
{
565 struct drm_encoder
**save_connector_encoders
;
566 struct drm_crtc
**save_encoder_crtcs
;
567 bool *save_crtc_enabled
;
573 struct intel_load_detect_pipe
{
574 struct drm_framebuffer
*release_fb
;
575 bool load_detect_temp
;
579 static inline struct intel_encoder
*
580 intel_attached_encoder(struct drm_connector
*connector
)
582 return to_intel_connector(connector
)->encoder
;
585 static inline struct intel_digital_port
*
586 enc_to_dig_port(struct drm_encoder
*encoder
)
588 return container_of(encoder
, struct intel_digital_port
, base
.base
);
591 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
593 return &enc_to_dig_port(encoder
)->dp
;
596 static inline struct intel_digital_port
*
597 dp_to_dig_port(struct intel_dp
*intel_dp
)
599 return container_of(intel_dp
, struct intel_digital_port
, dp
);
602 static inline struct intel_digital_port
*
603 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
605 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
610 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
611 enum pipe pipe
, bool enable
);
612 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
613 enum transcoder pch_transcoder
,
615 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
616 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
617 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
618 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
619 void hsw_pc8_disable_interrupts(struct drm_device
*dev
);
620 void hsw_pc8_restore_interrupts(struct drm_device
*dev
);
624 void intel_crt_init(struct drm_device
*dev
);
628 void intel_prepare_ddi(struct drm_device
*dev
);
629 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
630 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
631 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
632 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
633 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
);
634 void intel_ddi_pll_init(struct drm_device
*dev
);
635 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
636 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
637 enum transcoder cpu_transcoder
);
638 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
639 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
640 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
);
641 bool intel_ddi_pll_select(struct intel_crtc
*crtc
);
642 void intel_ddi_pll_enable(struct intel_crtc
*crtc
);
643 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
);
644 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
645 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
);
646 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
647 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
648 void intel_ddi_get_config(struct intel_encoder
*encoder
,
649 struct intel_crtc_config
*pipe_config
);
652 /* intel_display.c */
653 const char *intel_output_name(int output
);
654 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
655 int intel_pch_rawclk(struct drm_device
*dev
);
656 void intel_mark_busy(struct drm_device
*dev
);
657 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
658 struct intel_ring_buffer
*ring
);
659 void intel_mark_idle(struct drm_device
*dev
);
660 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
661 void intel_crtc_update_dpms(struct drm_crtc
*crtc
);
662 void intel_encoder_destroy(struct drm_encoder
*encoder
);
663 void intel_connector_dpms(struct drm_connector
*, int mode
);
664 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
665 void intel_modeset_check_state(struct drm_device
*dev
);
666 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
667 struct intel_digital_port
*port
);
668 void intel_connector_attach_encoder(struct intel_connector
*connector
,
669 struct intel_encoder
*encoder
);
670 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
671 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
672 struct drm_crtc
*crtc
);
673 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
674 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
675 struct drm_file
*file_priv
);
676 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
678 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
);
679 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
);
680 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
681 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
682 struct intel_digital_port
*dport
);
683 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
684 struct drm_display_mode
*mode
,
685 struct intel_load_detect_pipe
*old
);
686 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
687 struct intel_load_detect_pipe
*old
);
688 int intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
689 struct drm_i915_gem_object
*obj
,
690 struct intel_ring_buffer
*pipelined
);
691 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
);
692 struct drm_framebuffer
*
693 __intel_framebuffer_create(struct drm_device
*dev
,
694 struct drm_mode_fb_cmd2
*mode_cmd
,
695 struct drm_i915_gem_object
*obj
);
696 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
697 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
698 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
699 struct intel_shared_dpll
*intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
);
700 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
701 struct intel_shared_dpll
*pll
,
703 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
704 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
705 void assert_pll(struct drm_i915_private
*dev_priv
,
706 enum pipe pipe
, bool state
);
707 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
708 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
709 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
710 enum pipe pipe
, bool state
);
711 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
712 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
713 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
714 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
715 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
716 void intel_write_eld(struct drm_encoder
*encoder
,
717 struct drm_display_mode
*mode
);
718 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
719 unsigned int tiling_mode
,
722 void intel_display_handle_reset(struct drm_device
*dev
);
723 void hsw_enable_pc8_work(struct work_struct
*__work
);
724 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
);
725 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
);
726 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
727 struct intel_crtc_config
*pipe_config
);
728 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
730 ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
732 bool intel_crtc_active(struct drm_crtc
*crtc
);
733 void hsw_enable_ips(struct intel_crtc
*crtc
);
734 void hsw_disable_ips(struct intel_crtc
*crtc
);
735 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
736 enum intel_display_power_domain
737 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
738 int valleyview_get_vco(struct drm_i915_private
*dev_priv
);
739 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
740 struct intel_crtc_config
*pipe_config
);
743 void intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
);
744 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
745 struct intel_connector
*intel_connector
);
746 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
747 void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
748 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
749 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
750 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
751 void intel_dp_check_link_status(struct intel_dp
*intel_dp
);
752 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
753 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
754 struct intel_crtc_config
*pipe_config
);
755 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
756 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
757 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
758 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
759 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
760 void intel_edp_psr_enable(struct intel_dp
*intel_dp
);
761 void intel_edp_psr_disable(struct intel_dp
*intel_dp
);
762 void intel_edp_psr_update(struct drm_device
*dev
);
766 bool intel_dsi_init(struct drm_device
*dev
);
770 void intel_dvo_init(struct drm_device
*dev
);
773 /* legacy fbdev emulation in intel_fbdev.c */
774 #ifdef CONFIG_DRM_I915_FBDEV
775 extern int intel_fbdev_init(struct drm_device
*dev
);
776 extern void intel_fbdev_initial_config(struct drm_device
*dev
);
777 extern void intel_fbdev_fini(struct drm_device
*dev
);
778 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
);
779 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
780 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
782 static inline int intel_fbdev_init(struct drm_device
*dev
)
787 static inline void intel_fbdev_initial_config(struct drm_device
*dev
)
791 static inline void intel_fbdev_fini(struct drm_device
*dev
)
795 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
)
799 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
805 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
);
806 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
807 struct intel_connector
*intel_connector
);
808 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
809 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
810 struct intel_crtc_config
*pipe_config
);
814 void intel_lvds_init(struct drm_device
*dev
);
815 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
819 int intel_connector_update_modes(struct drm_connector
*connector
,
821 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
822 void intel_attach_force_audio_property(struct drm_connector
*connector
);
823 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
826 /* intel_overlay.c */
827 void intel_setup_overlay(struct drm_device
*dev
);
828 void intel_cleanup_overlay(struct drm_device
*dev
);
829 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
830 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
831 struct drm_file
*file_priv
);
832 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
833 struct drm_file
*file_priv
);
837 int intel_panel_init(struct intel_panel
*panel
,
838 struct drm_display_mode
*fixed_mode
,
839 struct drm_display_mode
*downclock_mode
);
840 void intel_panel_fini(struct intel_panel
*panel
);
841 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
842 struct drm_display_mode
*adjusted_mode
);
843 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
844 struct intel_crtc_config
*pipe_config
,
846 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
847 struct intel_crtc_config
*pipe_config
,
849 void intel_panel_set_backlight(struct intel_connector
*connector
, u32 level
,
851 int intel_panel_setup_backlight(struct drm_connector
*connector
);
852 void intel_panel_enable_backlight(struct intel_connector
*connector
);
853 void intel_panel_disable_backlight(struct intel_connector
*connector
);
854 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
855 void intel_panel_init_backlight_funcs(struct drm_device
*dev
);
856 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
857 extern struct drm_display_mode
*intel_find_panel_downclock(
858 struct drm_device
*dev
,
859 struct drm_display_mode
*fixed_mode
,
860 struct drm_connector
*connector
);
863 void intel_init_clock_gating(struct drm_device
*dev
);
864 void intel_suspend_hw(struct drm_device
*dev
);
865 void intel_update_watermarks(struct drm_crtc
*crtc
);
866 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
867 struct drm_crtc
*crtc
,
868 uint32_t sprite_width
, int pixel_size
,
869 bool enabled
, bool scaled
);
870 void intel_init_pm(struct drm_device
*dev
);
871 void intel_pm_setup(struct drm_device
*dev
);
872 bool intel_fbc_enabled(struct drm_device
*dev
);
873 void intel_update_fbc(struct drm_device
*dev
);
874 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
875 void intel_gpu_ips_teardown(void);
876 int intel_power_domains_init(struct drm_i915_private
*);
877 void intel_power_domains_remove(struct drm_i915_private
*);
878 bool intel_display_power_enabled(struct drm_i915_private
*dev_priv
,
879 enum intel_display_power_domain domain
);
880 bool intel_display_power_enabled_sw(struct drm_i915_private
*dev_priv
,
881 enum intel_display_power_domain domain
);
882 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
883 enum intel_display_power_domain domain
);
884 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
885 enum intel_display_power_domain domain
);
886 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
);
887 void intel_enable_gt_powersave(struct drm_device
*dev
);
888 void intel_disable_gt_powersave(struct drm_device
*dev
);
889 void ironlake_teardown_rc6(struct drm_device
*dev
);
890 void gen6_update_ring_freq(struct drm_device
*dev
);
891 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
892 void gen6_rps_boost(struct drm_i915_private
*dev_priv
);
893 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
);
894 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
);
895 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
896 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
897 void intel_init_runtime_pm(struct drm_i915_private
*dev_priv
);
898 void intel_fini_runtime_pm(struct drm_i915_private
*dev_priv
);
899 void ilk_wm_get_hw_state(struct drm_device
*dev
);
903 bool intel_sdvo_init(struct drm_device
*dev
, uint32_t sdvo_reg
, bool is_sdvob
);
907 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
908 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
910 void intel_plane_restore(struct drm_plane
*plane
);
911 void intel_plane_disable(struct drm_plane
*plane
);
912 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
913 struct drm_file
*file_priv
);
914 int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
915 struct drm_file
*file_priv
);
919 void intel_tv_init(struct drm_device
*dev
);
921 #endif /* __INTEL_DRV_H__ */