drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38
  39 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  40 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  41
  42 /**
  43  * _wait_for - magic (register) wait macro
  44  *
  45  * Does the right thing for modeset paths when run under kdgb or similar atomic
  46  * contexts. Note that it's important that we check the condition again after
  47  * having timed out, since the timeout could be due to preemption or similar and
  48  * we've never had a chance to check the condition before the timeout.
  49  */
  50 #define _wait_for(COND, MS, W) ({ \
  51         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  52         int ret__ = 0;                                                  \
  53         while (!(COND)) {                                               \
  54                 if (time_after(jiffies, timeout__)) {                   \
  55                         if (!(COND))                                    \
  56                                 ret__ = -ETIMEDOUT;                     \
  57                         break;                                          \
  58                 }                                                       \
  59                 if (W && drm_can_sleep())  {                            \
  60                         msleep(W);                                      \
  61                 } else {                                                \
  62                         cpu_relax();                                    \
  63                 }                                                       \
  64         }                                                               \
  65         ret__;                                                          \
  66 })
  67
  68 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  69 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  70 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  71                                                DIV_ROUND_UP((US), 1000), 0)
  72
  73 #define KHz(x) (1000 * (x))
  74 #define MHz(x) KHz(1000 * (x))
  75
  76 /*
  77  * Display related stuff
  78  */
  79
  80 /* store information about an Ixxx DVO */
  81 /* The i830->i865 use multiple DVOs with multiple i2cs */
  82 /* the i915, i945 have a single sDVO i2c bus - which is different */
  83 #define MAX_OUTPUTS 6
  84 /* maximum connectors per crtcs in the mode set */
  85
  86 /* Maximum cursor sizes */
  87 #define GEN2_CURSOR_WIDTH 64
  88 #define GEN2_CURSOR_HEIGHT 64
  89 #define MAX_CURSOR_WIDTH 256
  90 #define MAX_CURSOR_HEIGHT 256
  91
  92 #define INTEL_I2C_BUS_DVO 1
  93 #define INTEL_I2C_BUS_SDVO 2
  94
  95 /* these are outputs from the chip - integrated only
  96    external chips are via DVO or SDVO output */
  97 enum intel_output_type {
  98         INTEL_OUTPUT_UNUSED = 0,
  99         INTEL_OUTPUT_ANALOG = 1,
 100         INTEL_OUTPUT_DVO = 2,
 101         INTEL_OUTPUT_SDVO = 3,
 102         INTEL_OUTPUT_LVDS = 4,
 103         INTEL_OUTPUT_TVOUT = 5,
 104         INTEL_OUTPUT_HDMI = 6,
 105         INTEL_OUTPUT_DISPLAYPORT = 7,
 106         INTEL_OUTPUT_EDP = 8,
 107         INTEL_OUTPUT_DSI = 9,
 108         INTEL_OUTPUT_UNKNOWN = 10,
 109         INTEL_OUTPUT_DP_MST = 11,
 110 };
 111
 112 #define INTEL_DVO_CHIP_NONE 0
 113 #define INTEL_DVO_CHIP_LVDS 1
 114 #define INTEL_DVO_CHIP_TMDS 2
 115 #define INTEL_DVO_CHIP_TVOUT 4
 116
 117 #define INTEL_DSI_VIDEO_MODE    0
 118 #define INTEL_DSI_COMMAND_MODE  1
 119
 120 struct intel_framebuffer {
 121         struct drm_framebuffer base;
 122         struct drm_i915_gem_object *obj;
 123 };
 124
 125 struct intel_fbdev {
 126         struct drm_fb_helper helper;
 127         struct intel_framebuffer *fb;
 128         struct list_head fbdev_list;
 129         struct drm_display_mode *our_mode;
 130         int preferred_bpp;
 131 };
 132
 133 struct intel_encoder {
 134         struct drm_encoder base;
 135         /*
 136          * The new crtc this encoder will be driven from. Only differs from
 137          * base->crtc while a modeset is in progress.
 138          */
 139         struct intel_crtc *new_crtc;
 140
 141         enum intel_output_type type;
 142         unsigned int cloneable;
 143         bool connectors_active;
 144         void (*hot_plug)(struct intel_encoder *);
 145         bool (*compute_config)(struct intel_encoder *,
 146                                struct intel_crtc_config *);
 147         void (*pre_pll_enable)(struct intel_encoder *);
 148         void (*pre_enable)(struct intel_encoder *);
 149         void (*enable)(struct intel_encoder *);
 150         void (*mode_set)(struct intel_encoder *intel_encoder);
 151         void (*disable)(struct intel_encoder *);
 152         void (*post_disable)(struct intel_encoder *);
 153         /* Read out the current hw state of this connector, returning true if
 154          * the encoder is active. If the encoder is enabled it also set the pipe
 155          * it is connected to in the pipe parameter. */
 156         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 157         /* Reconstructs the equivalent mode flags for the current hardware
 158          * state. This must be called _after_ display->get_pipe_config has
 159          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 160          * be set correctly before calling this function. */
 161         void (*get_config)(struct intel_encoder *,
 162                            struct intel_crtc_config *pipe_config);
 163         /*
 164          * Called during system suspend after all pending requests for the
 165          * encoder are flushed (for example for DP AUX transactions) and
 166          * device interrupts are disabled.
 167          */
 168         void (*suspend)(struct intel_encoder *);
 169         int crtc_mask;
 170         enum hpd_pin hpd_pin;
 171 };
 172
 173 struct intel_panel {
 174         struct drm_display_mode *fixed_mode;
 175         struct drm_display_mode *downclock_mode;
 176         int fitting_mode;
 177
 178         /* backlight */
 179         struct {
 180                 bool present;
 181                 u32 level;
 182                 u32 min;
 183                 u32 max;
 184                 bool enabled;
 185                 bool combination_mode;  /* gen 2/4 only */
 186                 bool active_low_pwm;
 187                 struct backlight_device *device;
 188         } backlight;
 189
 190         void (*backlight_power)(struct intel_connector *, bool enable);
 191 };
 192
 193 struct intel_connector {
 194         struct drm_connector base;
 195         /*
 196          * The fixed encoder this connector is connected to.
 197          */
 198         struct intel_encoder *encoder;
 199
 200         /*
 201          * The new encoder this connector will be driven. Only differs from
 202          * encoder while a modeset is in progress.
 203          */
 204         struct intel_encoder *new_encoder;
 205
 206         /* Reads out the current hw, returning true if the connector is enabled
 207          * and active (i.e. dpms ON state). */
 208         bool (*get_hw_state)(struct intel_connector *);
 209
 210         /*
 211          * Removes all interfaces through which the connector is accessible
 212          * - like sysfs, debugfs entries -, so that no new operations can be
 213          * started on the connector. Also makes sure all currently pending
 214          * operations finish before returing.
 215          */
 216         void (*unregister)(struct intel_connector *);
 217
 218         /* Panel info for eDP and LVDS */
 219         struct intel_panel panel;
 220
 221         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 222         struct edid *edid;
 223         struct edid *detect_edid;
 224
 225         /* since POLL and HPD connectors may use the same HPD line keep the native
 226            state of connector->polled in case hotplug storm detection changes it */
 227         u8 polled;
 228
 229         void *port; /* store this opaque as its illegal to dereference it */
 230
 231         struct intel_dp *mst_port;
 232 };
 233
 234 typedef struct dpll {
 235         /* given values */
 236         int n;
 237         int m1, m2;
 238         int p1, p2;
 239         /* derived values */
 240         int     dot;
 241         int     vco;
 242         int     m;
 243         int     p;
 244 } intel_clock_t;
 245
 246 struct intel_plane_state {
 247         struct drm_crtc *crtc;
 248         struct drm_framebuffer *fb;
 249         struct drm_rect src;
 250         struct drm_rect dst;
 251         struct drm_rect clip;
 252         struct drm_rect orig_src;
 253         struct drm_rect orig_dst;
 254         bool visible;
 255 };
 256
 257 struct intel_plane_config {
 258         bool tiled;
 259         int size;
 260         u32 base;
 261 };
 262
 263 struct intel_crtc_config {
 264         /**
 265          * quirks - bitfield with hw state readout quirks
 266          *
 267          * For various reasons the hw state readout code might not be able to
 268          * completely faithfully read out the current state. These cases are
 269          * tracked with quirk flags so that fastboot and state checker can act
 270          * accordingly.
 271          */
 272 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 273 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 274         unsigned long quirks;
 275
 276         /* User requested mode, only valid as a starting point to
 277          * compute adjusted_mode, except in the case of (S)DVO where
 278          * it's also for the output timings of the (S)DVO chip.
 279          * adjusted_mode will then correspond to the S(DVO) chip's
 280          * preferred input timings. */
 281         struct drm_display_mode requested_mode;
 282         /* Actual pipe timings ie. what we program into the pipe timing
 283          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 284         struct drm_display_mode adjusted_mode;
 285
 286         /* Pipe source size (ie. panel fitter input size)
 287          * All planes will be positioned inside this space,
 288          * and get clipped at the edges. */
 289         int pipe_src_w, pipe_src_h;
 290
 291         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 292          * between pch encoders and cpu encoders. */
 293         bool has_pch_encoder;
 294
 295         /* CPU Transcoder for the pipe. Currently this can only differ from the
 296          * pipe on Haswell (where we have a special eDP transcoder). */
 297         enum transcoder cpu_transcoder;
 298
 299         /*
 300          * Use reduced/limited/broadcast rbg range, compressing from the full
 301          * range fed into the crtcs.
 302          */
 303         bool limited_color_range;
 304
 305         /* DP has a bunch of special case unfortunately, so mark the pipe
 306          * accordingly. */
 307         bool has_dp_encoder;
 308
 309         /* Whether we should send NULL infoframes. Required for audio. */
 310         bool has_hdmi_sink;
 311
 312         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 313          * has_dp_encoder is set. */
 314         bool has_audio;
 315
 316         /*
 317          * Enable dithering, used when the selected pipe bpp doesn't match the
 318          * plane bpp.
 319          */
 320         bool dither;
 321
 322         /* Controls for the clock computation, to override various stages. */
 323         bool clock_set;
 324
 325         /* SDVO TV has a bunch of special case. To make multifunction encoders
 326          * work correctly, we need to track this at runtime.*/
 327         bool sdvo_tv_clock;
 328
 329         /*
 330          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 331          * required. This is set in the 2nd loop of calling encoder's
 332          * ->compute_config if the first pick doesn't work out.
 333          */
 334         bool bw_constrained;
 335
 336         /* Settings for the intel dpll used on pretty much everything but
 337          * haswell. */
 338         struct dpll dpll;
 339
 340         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 341         enum intel_dpll_id shared_dpll;
 342
 343         /* PORT_CLK_SEL for DDI ports. */
 344         uint32_t ddi_pll_sel;
 345
 346         /* Actual register state of the dpll, for shared dpll cross-checking. */
 347         struct intel_dpll_hw_state dpll_hw_state;
 348
 349         int pipe_bpp;
 350         struct intel_link_m_n dp_m_n;
 351
 352         /* m2_n2 for eDP downclock */
 353         struct intel_link_m_n dp_m2_n2;
 354         bool has_drrs;
 355
 356         /*
 357          * Frequence the dpll for the port should run at. Differs from the
 358          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 359          * already multiplied by pixel_multiplier.
 360          */
 361         int port_clock;
 362
 363         /* Used by SDVO (and if we ever fix it, HDMI). */
 364         unsigned pixel_multiplier;
 365
 366         /* Panel fitter controls for gen2-gen4 + VLV */
 367         struct {
 368                 u32 control;
 369                 u32 pgm_ratios;
 370                 u32 lvds_border_bits;
 371         } gmch_pfit;
 372
 373         /* Panel fitter placement and size for Ironlake+ */
 374         struct {
 375                 u32 pos;
 376                 u32 size;
 377                 bool enabled;
 378                 bool force_thru;
 379         } pch_pfit;
 380
 381         /* FDI configuration, only valid if has_pch_encoder is set. */
 382         int fdi_lanes;
 383         struct intel_link_m_n fdi_m_n;
 384
 385         bool ips_enabled;
 386
 387         bool double_wide;
 388
 389         bool dp_encoder_is_mst;
 390         int pbn;
 391 };
 392
 393 struct intel_pipe_wm {
 394         struct intel_wm_level wm[5];
 395         uint32_t linetime;
 396         bool fbc_wm_enabled;
 397         bool pipe_enabled;
 398         bool sprites_enabled;
 399         bool sprites_scaled;
 400 };
 401
 402 struct intel_mmio_flip {
 403         u32 seqno;
 404         struct intel_engine_cs *ring;
 405         struct work_struct work;
 406 };
 407
 408 struct skl_pipe_wm {
 409         struct skl_wm_level wm[8];
 410         struct skl_wm_level trans_wm;
 411         uint32_t linetime;
 412 };
 413
 414 struct intel_crtc {
 415         struct drm_crtc base;
 416         enum pipe pipe;
 417         enum plane plane;
 418         u8 lut_r[256], lut_g[256], lut_b[256];
 419         /*
 420          * Whether the crtc and the connected output pipeline is active. Implies
 421          * that crtc->enabled is set, i.e. the current mode configuration has
 422          * some outputs connected to this crtc.
 423          */
 424         bool active;
 425         unsigned long enabled_power_domains;
 426         bool primary_enabled; /* is the primary plane (partially) visible? */
 427         bool lowfreq_avail;
 428         struct intel_overlay *overlay;
 429         struct intel_unpin_work *unpin_work;
 430
 431         atomic_t unpin_work_count;
 432
 433         /* Display surface base address adjustement for pageflips. Note that on
 434          * gen4+ this only adjusts up to a tile, offsets within a tile are
 435          * handled in the hw itself (with the TILEOFF register). */
 436         unsigned long dspaddr_offset;
 437
 438         struct drm_i915_gem_object *cursor_bo;
 439         uint32_t cursor_addr;
 440         int16_t cursor_width, cursor_height;
 441         uint32_t cursor_cntl;
 442         uint32_t cursor_size;
 443         uint32_t cursor_base;
 444
 445         struct intel_plane_config plane_config;
 446         struct intel_crtc_config config;
 447         struct intel_crtc_config *new_config;
 448         bool new_enabled;
 449
 450         /* reset counter value when the last flip was submitted */
 451         unsigned int reset_counter;
 452
 453         /* Access to these should be protected by dev_priv->irq_lock. */
 454         bool cpu_fifo_underrun_disabled;
 455         bool pch_fifo_underrun_disabled;
 456
 457         /* per-pipe watermark state */
 458         struct {
 459                 /* watermarks currently being used  */
 460                 struct intel_pipe_wm active;
 461                 /* SKL wm values currently in use */
 462                 struct skl_pipe_wm skl_active;
 463         } wm;
 464
 465         int scanline_offset;
 466         struct intel_mmio_flip mmio_flip;
 467 };
 468
 469 struct intel_plane_wm_parameters {
 470         uint32_t horiz_pixels;
 471         uint32_t vert_pixels;
 472         uint8_t bytes_per_pixel;
 473         bool enabled;
 474         bool scaled;
 475 };
 476
 477 struct intel_plane {
 478         struct drm_plane base;
 479         int plane;
 480         enum pipe pipe;
 481         struct drm_i915_gem_object *obj;
 482         bool can_scale;
 483         int max_downscale;
 484         int crtc_x, crtc_y;
 485         unsigned int crtc_w, crtc_h;
 486         uint32_t src_x, src_y;
 487         uint32_t src_w, src_h;
 488         unsigned int rotation;
 489
 490         /* Since we need to change the watermarks before/after
 491          * enabling/disabling the planes, we need to store the parameters here
 492          * as the other pieces of the struct may not reflect the values we want
 493          * for the watermark calculations. Currently only Haswell uses this.
 494          */
 495         struct intel_plane_wm_parameters wm;
 496
 497         void (*update_plane)(struct drm_plane *plane,
 498                              struct drm_crtc *crtc,
 499                              struct drm_framebuffer *fb,
 500                              struct drm_i915_gem_object *obj,
 501                              int crtc_x, int crtc_y,
 502                              unsigned int crtc_w, unsigned int crtc_h,
 503                              uint32_t x, uint32_t y,
 504                              uint32_t src_w, uint32_t src_h);
 505         void (*disable_plane)(struct drm_plane *plane,
 506                               struct drm_crtc *crtc);
 507         int (*update_colorkey)(struct drm_plane *plane,
 508                                struct drm_intel_sprite_colorkey *key);
 509         void (*get_colorkey)(struct drm_plane *plane,
 510                              struct drm_intel_sprite_colorkey *key);
 511 };
 512
 513 struct intel_watermark_params {
 514         unsigned long fifo_size;
 515         unsigned long max_wm;
 516         unsigned long default_wm;
 517         unsigned long guard_size;
 518         unsigned long cacheline_size;
 519 };
 520
 521 struct cxsr_latency {
 522         int is_desktop;
 523         int is_ddr3;
 524         unsigned long fsb_freq;
 525         unsigned long mem_freq;
 526         unsigned long display_sr;
 527         unsigned long display_hpll_disable;
 528         unsigned long cursor_sr;
 529         unsigned long cursor_hpll_disable;
 530 };
 531
 532 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 533 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 534 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 535 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 536 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 537 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 538
 539 struct intel_hdmi {
 540         u32 hdmi_reg;
 541         int ddc_bus;
 542         uint32_t color_range;
 543         bool color_range_auto;
 544         bool has_hdmi_sink;
 545         bool has_audio;
 546         enum hdmi_force_audio force_audio;
 547         bool rgb_quant_range_selectable;
 548         enum hdmi_picture_aspect aspect_ratio;
 549         void (*write_infoframe)(struct drm_encoder *encoder,
 550                                 enum hdmi_infoframe_type type,
 551                                 const void *frame, ssize_t len);
 552         void (*set_infoframes)(struct drm_encoder *encoder,
 553                                bool enable,
 554                                struct drm_display_mode *adjusted_mode);
 555 };
 556
 557 struct intel_dp_mst_encoder;
 558 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 559
 560 /**
 561  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 562  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 563  * parsing for same resolution.
 564  */
 565 enum edp_drrs_refresh_rate_type {
 566         DRRS_HIGH_RR,
 567         DRRS_LOW_RR,
 568         DRRS_MAX_RR, /* RR count */
 569 };
 570
 571 struct intel_dp {
 572         uint32_t output_reg;
 573         uint32_t aux_ch_ctl_reg;
 574         uint32_t DP;
 575         bool has_audio;
 576         enum hdmi_force_audio force_audio;
 577         uint32_t color_range;
 578         bool color_range_auto;
 579         uint8_t link_bw;
 580         uint8_t lane_count;
 581         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 582         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 583         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 584         struct drm_dp_aux aux;
 585         uint8_t train_set[4];
 586         int panel_power_up_delay;
 587         int panel_power_down_delay;
 588         int panel_power_cycle_delay;
 589         int backlight_on_delay;
 590         int backlight_off_delay;
 591         struct delayed_work panel_vdd_work;
 592         bool want_panel_vdd;
 593         unsigned long last_power_cycle;
 594         unsigned long last_power_on;
 595         unsigned long last_backlight_off;
 596
 597         struct notifier_block edp_notifier;
 598
 599         /*
 600          * Pipe whose power sequencer is currently locked into
 601          * this port. Only relevant on VLV/CHV.
 602          */
 603         enum pipe pps_pipe;
 604         struct edp_power_seq pps_delays;
 605
 606         bool use_tps3;
 607         bool can_mst; /* this port supports mst */
 608         bool is_mst;
 609         int active_mst_links;
 610         /* connector directly attached - won't be use for modeset in mst world */
 611         struct intel_connector *attached_connector;
 612
 613         /* mst connector list */
 614         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 615         struct drm_dp_mst_topology_mgr mst_mgr;
 616
 617         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 618         /*
 619          * This function returns the value we have to program the AUX_CTL
 620          * register with to kick off an AUX transaction.
 621          */
 622         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 623                                      bool has_aux_irq,
 624                                      int send_bytes,
 625                                      uint32_t aux_clock_divider);
 626         struct {
 627                 enum drrs_support_type type;
 628                 enum edp_drrs_refresh_rate_type refresh_rate_type;
 629                 struct mutex mutex;
 630         } drrs_state;
 631
 632 };
 633
 634 struct intel_digital_port {
 635         struct intel_encoder base;
 636         enum port port;
 637         u32 saved_port_bits;
 638         struct intel_dp dp;
 639         struct intel_hdmi hdmi;
 640         bool (*hpd_pulse)(struct intel_digital_port *, bool);
 641 };
 642
 643 struct intel_dp_mst_encoder {
 644         struct intel_encoder base;
 645         enum pipe pipe;
 646         struct intel_digital_port *primary;
 647         void *port; /* store this opaque as its illegal to dereference it */
 648 };
 649
 650 static inline int
 651 vlv_dport_to_channel(struct intel_digital_port *dport)
 652 {
 653         switch (dport->port) {
 654         case PORT_B:
 655         case PORT_D:
 656                 return DPIO_CH0;
 657         case PORT_C:
 658                 return DPIO_CH1;
 659         default:
 660                 BUG();
 661         }
 662 }
 663
 664 static inline int
 665 vlv_pipe_to_channel(enum pipe pipe)
 666 {
 667         switch (pipe) {
 668         case PIPE_A:
 669         case PIPE_C:
 670                 return DPIO_CH0;
 671         case PIPE_B:
 672                 return DPIO_CH1;
 673         default:
 674                 BUG();
 675         }
 676 }
 677
 678 static inline struct drm_crtc *
 679 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 680 {
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         return dev_priv->pipe_to_crtc_mapping[pipe];
 683 }
 684
 685 static inline struct drm_crtc *
 686 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 687 {
 688         struct drm_i915_private *dev_priv = dev->dev_private;
 689         return dev_priv->plane_to_crtc_mapping[plane];
 690 }
 691
 692 struct intel_unpin_work {
 693         struct work_struct work;
 694         struct drm_crtc *crtc;
 695         struct drm_i915_gem_object *old_fb_obj;
 696         struct drm_i915_gem_object *pending_flip_obj;
 697         struct drm_pending_vblank_event *event;
 698         atomic_t pending;
 699 #define INTEL_FLIP_INACTIVE     0
 700 #define INTEL_FLIP_PENDING      1
 701 #define INTEL_FLIP_COMPLETE     2
 702         u32 flip_count;
 703         u32 gtt_offset;
 704         struct intel_engine_cs *flip_queued_ring;
 705         u32 flip_queued_seqno;
 706         int flip_queued_vblank;
 707         int flip_ready_vblank;
 708         bool enable_stall_check;
 709 };
 710
 711 struct intel_set_config {
 712         struct drm_encoder **save_connector_encoders;
 713         struct drm_crtc **save_encoder_crtcs;
 714         bool *save_crtc_enabled;
 715
 716         bool fb_changed;
 717         bool mode_changed;
 718 };
 719
 720 struct intel_load_detect_pipe {
 721         struct drm_framebuffer *release_fb;
 722         bool load_detect_temp;
 723         int dpms_mode;
 724 };
 725
 726 static inline struct intel_encoder *
 727 intel_attached_encoder(struct drm_connector *connector)
 728 {
 729         return to_intel_connector(connector)->encoder;
 730 }
 731
 732 static inline struct intel_digital_port *
 733 enc_to_dig_port(struct drm_encoder *encoder)
 734 {
 735         return container_of(encoder, struct intel_digital_port, base.base);
 736 }
 737
 738 static inline struct intel_dp_mst_encoder *
 739 enc_to_mst(struct drm_encoder *encoder)
 740 {
 741         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 742 }
 743
 744 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 745 {
 746         return &enc_to_dig_port(encoder)->dp;
 747 }
 748
 749 static inline struct intel_digital_port *
 750 dp_to_dig_port(struct intel_dp *intel_dp)
 751 {
 752         return container_of(intel_dp, struct intel_digital_port, dp);
 753 }
 754
 755 static inline struct intel_digital_port *
 756 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 757 {
 758         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 759 }
 760
 761 /*
 762  * Returns the number of planes for this pipe, ie the number of sprites + 1
 763  * (primary plane). This doesn't count the cursor plane then.
 764  */
 765 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 766 {
 767         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 768 }
 769
 770 /* intel_fifo_underrun.c */
 771 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 772                                            enum pipe pipe, bool enable);
 773 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 774                                            enum transcoder pch_transcoder,
 775                                            bool enable);
 776 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 777                                          enum pipe pipe);
 778 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 779                                          enum transcoder pch_transcoder);
 780 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 781
 782 /* i915_irq.c */
 783 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 784 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 785 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 786 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 787 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 788 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 789 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 790 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 791 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 792 {
 793         /*
 794          * We only use drm_irq_uninstall() at unload and VT switch, so
 795          * this is the only thing we need to check.
 796          */
 797         return dev_priv->pm.irqs_enabled;
 798 }
 799
 800 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 801 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
 802
 803 /* intel_crt.c */
 804 void intel_crt_init(struct drm_device *dev);
 805
 806
 807 /* intel_ddi.c */
 808 void intel_prepare_ddi(struct drm_device *dev);
 809 void hsw_fdi_link_train(struct drm_crtc *crtc);
 810 void intel_ddi_init(struct drm_device *dev, enum port port);
 811 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 812 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 813 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 814 void intel_ddi_pll_init(struct drm_device *dev);
 815 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 816 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 817                                        enum transcoder cpu_transcoder);
 818 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 819 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 820 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 821 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 822 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 823 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 824 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 825 void intel_ddi_get_config(struct intel_encoder *encoder,
 826                           struct intel_crtc_config *pipe_config);
 827
 828 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 829 void intel_ddi_clock_get(struct intel_encoder *encoder,
 830                          struct intel_crtc_config *pipe_config);
 831 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 832
 833 /* intel_frontbuffer.c */
 834 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 835                              struct intel_engine_cs *ring);
 836 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 837                                     unsigned frontbuffer_bits);
 838 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 839                                      unsigned frontbuffer_bits);
 840 void intel_frontbuffer_flush(struct drm_device *dev,
 841                              unsigned frontbuffer_bits);
 842 /**
 843  * intel_frontbuffer_flip - synchronous frontbuffer flip
 844  * @dev: DRM device
 845  * @frontbuffer_bits: frontbuffer plane tracking bits
 846  *
 847  * This function gets called after scheduling a flip on @obj. This is for
 848  * synchronous plane updates which will happen on the next vblank and which will
 849  * not get delayed by pending gpu rendering.
 850  *
 851  * Can be called without any locks held.
 852  */
 853 static inline
 854 void intel_frontbuffer_flip(struct drm_device *dev,
 855                             unsigned frontbuffer_bits)
 856 {
 857         intel_frontbuffer_flush(dev, frontbuffer_bits);
 858 }
 859
 860 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 861
 862
 863 /* intel_audio.c */
 864 void intel_init_audio(struct drm_device *dev);
 865 void intel_audio_codec_enable(struct intel_encoder *encoder);
 866 void intel_audio_codec_disable(struct intel_encoder *encoder);
 867
 868 /* intel_display.c */
 869 const char *intel_output_name(int output);
 870 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 871 int intel_pch_rawclk(struct drm_device *dev);
 872 void intel_mark_busy(struct drm_device *dev);
 873 void intel_mark_idle(struct drm_device *dev);
 874 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 875 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
 876 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 877 void intel_encoder_destroy(struct drm_encoder *encoder);
 878 void intel_connector_dpms(struct drm_connector *, int mode);
 879 bool intel_connector_get_hw_state(struct intel_connector *connector);
 880 void intel_modeset_check_state(struct drm_device *dev);
 881 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 882                                 struct intel_digital_port *port);
 883 void intel_connector_attach_encoder(struct intel_connector *connector,
 884                                     struct intel_encoder *encoder);
 885 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 886 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 887                                              struct drm_crtc *crtc);
 888 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 889 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 890                                 struct drm_file *file_priv);
 891 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 892                                              enum pipe pipe);
 893 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
 894 static inline void
 895 intel_wait_for_vblank(struct drm_device *dev, int pipe)
 896 {
 897         drm_wait_one_vblank(dev, pipe);
 898 }
 899 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 900 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 901                          struct intel_digital_port *dport);
 902 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 903                                 struct drm_display_mode *mode,
 904                                 struct intel_load_detect_pipe *old,
 905                                 struct drm_modeset_acquire_ctx *ctx);
 906 void intel_release_load_detect_pipe(struct drm_connector *connector,
 907                                     struct intel_load_detect_pipe *old);
 908 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 909                                struct drm_framebuffer *fb,
 910                                struct intel_engine_cs *pipelined);
 911 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 912 struct drm_framebuffer *
 913 __intel_framebuffer_create(struct drm_device *dev,
 914                            struct drm_mode_fb_cmd2 *mode_cmd,
 915                            struct drm_i915_gem_object *obj);
 916 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 917 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 918 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 919 void intel_check_page_flip(struct drm_device *dev, int pipe);
 920
 921 /* shared dpll functions */
 922 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 923 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 924                         struct intel_shared_dpll *pll,
 925                         bool state);
 926 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 927 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 928 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
 929 void intel_put_shared_dpll(struct intel_crtc *crtc);
 930
 931 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
 932                       const struct dpll *dpll);
 933 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
 934
 935 /* modesetting asserts */
 936 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 937                            enum pipe pipe);
 938 void assert_pll(struct drm_i915_private *dev_priv,
 939                 enum pipe pipe, bool state);
 940 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 941 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 942 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 943                        enum pipe pipe, bool state);
 944 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 945 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 946 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 947 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 948 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 949 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 950                                              unsigned int tiling_mode,
 951                                              unsigned int bpp,
 952                                              unsigned int pitch);
 953 void intel_display_handle_reset(struct drm_device *dev);
 954 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 955 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 956 void intel_dp_get_m_n(struct intel_crtc *crtc,
 957                       struct intel_crtc_config *pipe_config);
 958 void intel_dp_set_m_n(struct intel_crtc *crtc);
 959 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 960 void
 961 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 962                                 int dotclock);
 963 bool intel_crtc_active(struct drm_crtc *crtc);
 964 void hsw_enable_ips(struct intel_crtc *crtc);
 965 void hsw_disable_ips(struct intel_crtc *crtc);
 966 enum intel_display_power_domain
 967 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 968 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 969                                  struct intel_crtc_config *pipe_config);
 970 int intel_format_to_fourcc(int format);
 971 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 972 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
 973
 974 /* intel_dp.c */
 975 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 976 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 977                              struct intel_connector *intel_connector);
 978 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 979 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 980 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 981 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 982 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 983 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 984 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 985 bool intel_dp_compute_config(struct intel_encoder *encoder,
 986                              struct intel_crtc_config *pipe_config);
 987 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 988 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
 989                         bool long_hpd);
 990 void intel_edp_backlight_on(struct intel_dp *intel_dp);
 991 void intel_edp_backlight_off(struct intel_dp *intel_dp);
 992 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 993 void intel_edp_panel_on(struct intel_dp *intel_dp);
 994 void intel_edp_panel_off(struct intel_dp *intel_dp);
 995 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 996 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 997 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
 998 void intel_edp_psr_invalidate(struct drm_device *dev,
 999                               unsigned frontbuffer_bits);
1000 void intel_edp_psr_flush(struct drm_device *dev,
1001                          unsigned frontbuffer_bits);
1002 void intel_edp_psr_init(struct drm_device *dev);
1003
1004 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1005 void intel_dp_mst_suspend(struct drm_device *dev);
1006 void intel_dp_mst_resume(struct drm_device *dev);
1007 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
1008 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1009 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1010 /* intel_dp_mst.c */
1011 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1012 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1013 /* intel_dsi.c */
1014 void intel_dsi_init(struct drm_device *dev);
1015
1016
1017 /* intel_dvo.c */
1018 void intel_dvo_init(struct drm_device *dev);
1019
1020
1021 /* legacy fbdev emulation in intel_fbdev.c */
1022 #ifdef CONFIG_DRM_I915_FBDEV
1023 extern int intel_fbdev_init(struct drm_device *dev);
1024 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1025 extern void intel_fbdev_fini(struct drm_device *dev);
1026 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1027 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1028 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1029 #else
1030 static inline int intel_fbdev_init(struct drm_device *dev)
1031 {
1032         return 0;
1033 }
1034
1035 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1036 {
1037 }
1038
1039 static inline void intel_fbdev_fini(struct drm_device *dev)
1040 {
1041 }
1042
1043 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1044 {
1045 }
1046
1047 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1048 {
1049 }
1050 #endif
1051
1052 /* intel_hdmi.c */
1053 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1054 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1055                                struct intel_connector *intel_connector);
1056 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1057 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1058                                struct intel_crtc_config *pipe_config);
1059
1060
1061 /* intel_lvds.c */
1062 void intel_lvds_init(struct drm_device *dev);
1063 bool intel_is_dual_link_lvds(struct drm_device *dev);
1064
1065
1066 /* intel_modes.c */
1067 int intel_connector_update_modes(struct drm_connector *connector,
1068                                  struct edid *edid);
1069 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1070 void intel_attach_force_audio_property(struct drm_connector *connector);
1071 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1072
1073
1074 /* intel_overlay.c */
1075 void intel_setup_overlay(struct drm_device *dev);
1076 void intel_cleanup_overlay(struct drm_device *dev);
1077 int intel_overlay_switch_off(struct intel_overlay *overlay);
1078 int intel_overlay_put_image(struct drm_device *dev, void *data,
1079                             struct drm_file *file_priv);
1080 int intel_overlay_attrs(struct drm_device *dev, void *data,
1081                         struct drm_file *file_priv);
1082
1083
1084 /* intel_panel.c */
1085 int intel_panel_init(struct intel_panel *panel,
1086                      struct drm_display_mode *fixed_mode,
1087                      struct drm_display_mode *downclock_mode);
1088 void intel_panel_fini(struct intel_panel *panel);
1089 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1090                             struct drm_display_mode *adjusted_mode);
1091 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1092                              struct intel_crtc_config *pipe_config,
1093                              int fitting_mode);
1094 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1095                               struct intel_crtc_config *pipe_config,
1096                               int fitting_mode);
1097 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1098                                     u32 level, u32 max);
1099 int intel_panel_setup_backlight(struct drm_connector *connector);
1100 void intel_panel_enable_backlight(struct intel_connector *connector);
1101 void intel_panel_disable_backlight(struct intel_connector *connector);
1102 void intel_panel_destroy_backlight(struct drm_connector *connector);
1103 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1104 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1105 extern struct drm_display_mode *intel_find_panel_downclock(
1106                                 struct drm_device *dev,
1107                                 struct drm_display_mode *fixed_mode,
1108                                 struct drm_connector *connector);
1109
1110 /* intel_runtime_pm.c */
1111 int intel_power_domains_init(struct drm_i915_private *);
1112 void intel_power_domains_fini(struct drm_i915_private *);
1113 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1114 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1115
1116 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1117                                     enum intel_display_power_domain domain);
1118 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1119                                       enum intel_display_power_domain domain);
1120 void intel_display_power_get(struct drm_i915_private *dev_priv,
1121                              enum intel_display_power_domain domain);
1122 void intel_display_power_put(struct drm_i915_private *dev_priv,
1123                              enum intel_display_power_domain domain);
1124 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1125 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1126 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1127 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1128 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1129
1130 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1131
1132 /* intel_pm.c */
1133 void intel_init_clock_gating(struct drm_device *dev);
1134 void intel_suspend_hw(struct drm_device *dev);
1135 int ilk_wm_max_level(const struct drm_device *dev);
1136 void intel_update_watermarks(struct drm_crtc *crtc);
1137 void intel_update_sprite_watermarks(struct drm_plane *plane,
1138                                     struct drm_crtc *crtc,
1139                                     uint32_t sprite_width,
1140                                     uint32_t sprite_height,
1141                                     int pixel_size,
1142                                     bool enabled, bool scaled);
1143 void intel_init_pm(struct drm_device *dev);
1144 void intel_pm_setup(struct drm_device *dev);
1145 bool intel_fbc_enabled(struct drm_device *dev);
1146 void intel_update_fbc(struct drm_device *dev);
1147 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1148 void intel_gpu_ips_teardown(void);
1149 void intel_init_gt_powersave(struct drm_device *dev);
1150 void intel_cleanup_gt_powersave(struct drm_device *dev);
1151 void intel_enable_gt_powersave(struct drm_device *dev);
1152 void intel_disable_gt_powersave(struct drm_device *dev);
1153 void intel_suspend_gt_powersave(struct drm_device *dev);
1154 void intel_reset_gt_powersave(struct drm_device *dev);
1155 void ironlake_teardown_rc6(struct drm_device *dev);
1156 void gen6_update_ring_freq(struct drm_device *dev);
1157 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1158 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1159 void ilk_wm_get_hw_state(struct drm_device *dev);
1160 void skl_wm_get_hw_state(struct drm_device *dev);
1161 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1162                           struct skl_ddb_allocation *ddb /* out */);
1163
1164
1165 /* intel_sdvo.c */
1166 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1167
1168
1169 /* intel_sprite.c */
1170 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1171 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1172                                enum plane plane);
1173 int intel_plane_set_property(struct drm_plane *plane,
1174                              struct drm_property *prop,
1175                              uint64_t val);
1176 int intel_plane_restore(struct drm_plane *plane);
1177 void intel_plane_disable(struct drm_plane *plane);
1178 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1179                               struct drm_file *file_priv);
1180 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1181                               struct drm_file *file_priv);
1182 bool intel_pipe_update_start(struct intel_crtc *crtc,
1183                              uint32_t *start_vbl_count);
1184 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1185
1186 /* intel_tv.c */
1187 void intel_tv_init(struct drm_device *dev);
1188
1189 #endif /* __INTEL_DRV_H__ */