2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
52 if (time_after(jiffies, timeout__)) { \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
75 * Display related stuff
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
82 /* maximum connectors per crtcs in the mode set */
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type
{
96 INTEL_OUTPUT_UNUSED
= 0,
97 INTEL_OUTPUT_ANALOG
= 1,
99 INTEL_OUTPUT_SDVO
= 3,
100 INTEL_OUTPUT_LVDS
= 4,
101 INTEL_OUTPUT_TVOUT
= 5,
102 INTEL_OUTPUT_HDMI
= 6,
103 INTEL_OUTPUT_DISPLAYPORT
= 7,
104 INTEL_OUTPUT_EDP
= 8,
105 INTEL_OUTPUT_DSI
= 9,
106 INTEL_OUTPUT_UNKNOWN
= 10,
107 INTEL_OUTPUT_DP_MST
= 11,
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
118 struct intel_framebuffer
{
119 struct drm_framebuffer base
;
120 struct drm_i915_gem_object
*obj
;
124 struct drm_fb_helper helper
;
125 struct intel_framebuffer
*fb
;
126 struct list_head fbdev_list
;
127 struct drm_display_mode
*our_mode
;
131 struct intel_encoder
{
132 struct drm_encoder base
;
134 enum intel_output_type type
;
135 unsigned int cloneable
;
136 bool connectors_active
;
137 void (*hot_plug
)(struct intel_encoder
*);
138 bool (*compute_config
)(struct intel_encoder
*,
139 struct intel_crtc_state
*);
140 void (*pre_pll_enable
)(struct intel_encoder
*);
141 void (*pre_enable
)(struct intel_encoder
*);
142 void (*enable
)(struct intel_encoder
*);
143 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
144 void (*disable
)(struct intel_encoder
*);
145 void (*post_disable
)(struct intel_encoder
*);
146 /* Read out the current hw state of this connector, returning true if
147 * the encoder is active. If the encoder is enabled it also set the pipe
148 * it is connected to in the pipe parameter. */
149 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
150 /* Reconstructs the equivalent mode flags for the current hardware
151 * state. This must be called _after_ display->get_pipe_config has
152 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
153 * be set correctly before calling this function. */
154 void (*get_config
)(struct intel_encoder
*,
155 struct intel_crtc_state
*pipe_config
);
157 * Called during system suspend after all pending requests for the
158 * encoder are flushed (for example for DP AUX transactions) and
159 * device interrupts are disabled.
161 void (*suspend
)(struct intel_encoder
*);
163 enum hpd_pin hpd_pin
;
167 struct drm_display_mode
*fixed_mode
;
168 struct drm_display_mode
*downclock_mode
;
178 bool combination_mode
; /* gen 2/4 only */
180 struct backlight_device
*device
;
183 void (*backlight_power
)(struct intel_connector
*, bool enable
);
186 struct intel_connector
{
187 struct drm_connector base
;
189 * The fixed encoder this connector is connected to.
191 struct intel_encoder
*encoder
;
193 /* Reads out the current hw, returning true if the connector is enabled
194 * and active (i.e. dpms ON state). */
195 bool (*get_hw_state
)(struct intel_connector
*);
198 * Removes all interfaces through which the connector is accessible
199 * - like sysfs, debugfs entries -, so that no new operations can be
200 * started on the connector. Also makes sure all currently pending
201 * operations finish before returing.
203 void (*unregister
)(struct intel_connector
*);
205 /* Panel info for eDP and LVDS */
206 struct intel_panel panel
;
208 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
210 struct edid
*detect_edid
;
212 /* since POLL and HPD connectors may use the same HPD line keep the native
213 state of connector->polled in case hotplug storm detection changes it */
216 void *port
; /* store this opaque as its illegal to dereference it */
218 struct intel_dp
*mst_port
;
221 typedef struct dpll
{
233 struct intel_atomic_state
{
234 struct drm_atomic_state base
;
237 struct intel_shared_dpll_config shared_dpll
[I915_NUM_PLLS
];
240 struct intel_plane_state
{
241 struct drm_plane_state base
;
244 struct drm_rect clip
;
249 * = -1 : not using a scaler
250 * >= 0 : using a scalers
252 * plane requiring a scaler:
253 * - During check_plane, its bit is set in
254 * crtc_state->scaler_state.scaler_users by calling helper function
255 * update_scaler_users.
256 * - scaler_id indicates the scaler it got assigned.
258 * plane doesn't require a scaler:
259 * - this can happen when scaling is no more required or plane simply
261 * - During check_plane, corresponding bit is reset in
262 * crtc_state->scaler_state.scaler_users by calling helper function
263 * update_scaler_users.
268 struct intel_initial_plane_config
{
269 struct intel_framebuffer
*fb
;
275 #define SKL_MIN_SRC_W 8
276 #define SKL_MAX_SRC_W 4096
277 #define SKL_MIN_SRC_H 8
278 #define SKL_MAX_SRC_H 4096
279 #define SKL_MIN_DST_W 8
280 #define SKL_MAX_DST_W 4096
281 #define SKL_MIN_DST_H 8
282 #define SKL_MAX_DST_H 4096
284 struct intel_scaler
{
290 struct intel_crtc_scaler_state
{
291 #define SKL_NUM_SCALERS 2
292 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
295 * scaler_users: keeps track of users requesting scalers on this crtc.
297 * If a bit is set, a user is using a scaler.
298 * Here user can be a plane or crtc as defined below:
299 * bits 0-30 - plane (bit position is index from drm_plane_index)
302 * Instead of creating a new index to cover planes and crtc, using
303 * existing drm_plane_index for planes which is well less than 31
304 * planes and bit 31 for crtc. This should be fine to cover all
307 * intel_atomic_setup_scalers will setup available scalers to users
308 * requesting scalers. It will gracefully fail if request exceeds
311 #define SKL_CRTC_INDEX 31
312 unsigned scaler_users
;
314 /* scaler used by crtc for panel fitting purpose */
318 struct intel_crtc_state
{
319 struct drm_crtc_state base
;
322 * quirks - bitfield with hw state readout quirks
324 * For various reasons the hw state readout code might not be able to
325 * completely faithfully read out the current state. These cases are
326 * tracked with quirk flags so that fastboot and state checker can act
329 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
330 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
331 unsigned long quirks
;
333 /* Pipe source size (ie. panel fitter input size)
334 * All planes will be positioned inside this space,
335 * and get clipped at the edges. */
336 int pipe_src_w
, pipe_src_h
;
338 /* Whether to set up the PCH/FDI. Note that we never allow sharing
339 * between pch encoders and cpu encoders. */
340 bool has_pch_encoder
;
342 /* Are we sending infoframes on the attached port */
345 /* CPU Transcoder for the pipe. Currently this can only differ from the
346 * pipe on Haswell (where we have a special eDP transcoder). */
347 enum transcoder cpu_transcoder
;
350 * Use reduced/limited/broadcast rbg range, compressing from the full
351 * range fed into the crtcs.
353 bool limited_color_range
;
355 /* DP has a bunch of special case unfortunately, so mark the pipe
359 /* Whether we should send NULL infoframes. Required for audio. */
362 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
363 * has_dp_encoder is set. */
367 * Enable dithering, used when the selected pipe bpp doesn't match the
372 /* Controls for the clock computation, to override various stages. */
375 /* SDVO TV has a bunch of special case. To make multifunction encoders
376 * work correctly, we need to track this at runtime.*/
380 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
381 * required. This is set in the 2nd loop of calling encoder's
382 * ->compute_config if the first pick doesn't work out.
386 /* Settings for the intel dpll used on pretty much everything but
390 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
391 enum intel_dpll_id shared_dpll
;
394 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
395 * - enum skl_dpll on SKL
397 uint32_t ddi_pll_sel
;
399 /* Actual register state of the dpll, for shared dpll cross-checking. */
400 struct intel_dpll_hw_state dpll_hw_state
;
403 struct intel_link_m_n dp_m_n
;
405 /* m2_n2 for eDP downclock */
406 struct intel_link_m_n dp_m2_n2
;
410 * Frequence the dpll for the port should run at. Differs from the
411 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
412 * already multiplied by pixel_multiplier.
416 /* Used by SDVO (and if we ever fix it, HDMI). */
417 unsigned pixel_multiplier
;
419 /* Panel fitter controls for gen2-gen4 + VLV */
423 u32 lvds_border_bits
;
426 /* Panel fitter placement and size for Ironlake+ */
434 /* FDI configuration, only valid if has_pch_encoder is set. */
436 struct intel_link_m_n fdi_m_n
;
442 bool dp_encoder_is_mst
;
445 struct intel_crtc_scaler_state scaler_state
;
447 /* w/a for waiting 2 vblanks during crtc enable */
448 enum pipe hsw_workaround_pipe
;
451 struct intel_pipe_wm
{
452 struct intel_wm_level wm
[5];
456 bool sprites_enabled
;
460 struct intel_mmio_flip
{
461 struct work_struct work
;
462 struct drm_i915_private
*i915
;
463 struct drm_i915_gem_request
*req
;
464 struct intel_crtc
*crtc
;
468 struct skl_wm_level wm
[8];
469 struct skl_wm_level trans_wm
;
474 * Tracking of operations that need to be performed at the beginning/end of an
475 * atomic commit, outside the atomic section where interrupts are disabled.
476 * These are generally operations that grab mutexes or might otherwise sleep
477 * and thus can't be run with interrupts disabled.
479 struct intel_crtc_atomic_commit
{
482 unsigned start_vbl_count
;
484 /* Sleepable operations to perform before commit */
487 bool pre_disable_primary
;
489 unsigned disabled_planes
;
491 /* Sleepable operations to perform after commit */
495 bool post_enable_primary
;
496 unsigned update_sprite_watermarks
;
500 struct drm_crtc base
;
503 u8 lut_r
[256], lut_g
[256], lut_b
[256];
505 * Whether the crtc and the connected output pipeline is active. Implies
506 * that crtc->enabled is set, i.e. the current mode configuration has
507 * some outputs connected to this crtc.
510 unsigned long enabled_power_domains
;
512 struct intel_overlay
*overlay
;
513 struct intel_unpin_work
*unpin_work
;
515 atomic_t unpin_work_count
;
517 /* Display surface base address adjustement for pageflips. Note that on
518 * gen4+ this only adjusts up to a tile, offsets within a tile are
519 * handled in the hw itself (with the TILEOFF register). */
520 unsigned long dspaddr_offset
;
522 struct drm_i915_gem_object
*cursor_bo
;
523 uint32_t cursor_addr
;
524 uint32_t cursor_cntl
;
525 uint32_t cursor_size
;
526 uint32_t cursor_base
;
528 struct intel_initial_plane_config plane_config
;
529 struct intel_crtc_state
*config
;
531 /* reset counter value when the last flip was submitted */
532 unsigned int reset_counter
;
534 /* Access to these should be protected by dev_priv->irq_lock. */
535 bool cpu_fifo_underrun_disabled
;
536 bool pch_fifo_underrun_disabled
;
538 /* per-pipe watermark state */
540 /* watermarks currently being used */
541 struct intel_pipe_wm active
;
542 /* SKL wm values currently in use */
543 struct skl_pipe_wm skl_active
;
548 struct intel_crtc_atomic_commit atomic
;
550 /* scalers available on this crtc */
554 struct intel_plane_wm_parameters
{
555 uint32_t horiz_pixels
;
556 uint32_t vert_pixels
;
558 * For packed pixel formats:
559 * bytes_per_pixel - holds bytes per pixel
560 * For planar pixel formats:
561 * bytes_per_pixel - holds bytes per pixel for uv-plane
562 * y_bytes_per_pixel - holds bytes per pixel for y-plane
564 uint8_t bytes_per_pixel
;
565 uint8_t y_bytes_per_pixel
;
569 unsigned int rotation
;
573 struct drm_plane base
;
579 /* FIXME convert to properties */
580 struct drm_intel_sprite_colorkey ckey
;
582 /* Since we need to change the watermarks before/after
583 * enabling/disabling the planes, we need to store the parameters here
584 * as the other pieces of the struct may not reflect the values we want
585 * for the watermark calculations. Currently only Haswell uses this.
587 struct intel_plane_wm_parameters wm
;
590 * NOTE: Do not place new plane state fields here (e.g., when adding
591 * new plane properties). New runtime state should now be placed in
592 * the intel_plane_state structure and accessed via drm_plane->state.
595 void (*update_plane
)(struct drm_plane
*plane
,
596 struct drm_crtc
*crtc
,
597 struct drm_framebuffer
*fb
,
598 int crtc_x
, int crtc_y
,
599 unsigned int crtc_w
, unsigned int crtc_h
,
600 uint32_t x
, uint32_t y
,
601 uint32_t src_w
, uint32_t src_h
);
602 void (*disable_plane
)(struct drm_plane
*plane
,
603 struct drm_crtc
*crtc
, bool force
);
604 int (*check_plane
)(struct drm_plane
*plane
,
605 struct intel_plane_state
*state
);
606 void (*commit_plane
)(struct drm_plane
*plane
,
607 struct intel_plane_state
*state
);
610 struct intel_watermark_params
{
611 unsigned long fifo_size
;
612 unsigned long max_wm
;
613 unsigned long default_wm
;
614 unsigned long guard_size
;
615 unsigned long cacheline_size
;
618 struct cxsr_latency
{
621 unsigned long fsb_freq
;
622 unsigned long mem_freq
;
623 unsigned long display_sr
;
624 unsigned long display_hpll_disable
;
625 unsigned long cursor_sr
;
626 unsigned long cursor_hpll_disable
;
629 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
630 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
631 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
632 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
633 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
634 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
635 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
636 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
637 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
642 uint32_t color_range
;
643 bool color_range_auto
;
646 enum hdmi_force_audio force_audio
;
647 bool rgb_quant_range_selectable
;
648 enum hdmi_picture_aspect aspect_ratio
;
649 void (*write_infoframe
)(struct drm_encoder
*encoder
,
650 enum hdmi_infoframe_type type
,
651 const void *frame
, ssize_t len
);
652 void (*set_infoframes
)(struct drm_encoder
*encoder
,
654 struct drm_display_mode
*adjusted_mode
);
655 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
);
658 struct intel_dp_mst_encoder
;
659 #define DP_MAX_DOWNSTREAM_PORTS 0x10
663 * When platform provides two set of M_N registers for dp, we can
664 * program them and switch between them incase of DRRS.
665 * But When only one such register is provided, we have to program the
666 * required divider value on that registers itself based on the DRRS state.
668 * M1_N1 : Program dp_m_n on M1_N1 registers
669 * dp_m2_n2 on M2_N2 registers (If supported)
671 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
672 * M2_N2 registers are not supported
676 /* Sets the m1_n1 and m2_n2 */
683 uint32_t aux_ch_ctl_reg
;
686 enum hdmi_force_audio force_audio
;
687 uint32_t color_range
;
688 bool color_range_auto
;
692 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
693 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
694 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
695 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
696 uint8_t num_sink_rates
;
697 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
698 struct drm_dp_aux aux
;
699 uint8_t train_set
[4];
700 int panel_power_up_delay
;
701 int panel_power_down_delay
;
702 int panel_power_cycle_delay
;
703 int backlight_on_delay
;
704 int backlight_off_delay
;
705 struct delayed_work panel_vdd_work
;
707 unsigned long last_power_cycle
;
708 unsigned long last_power_on
;
709 unsigned long last_backlight_off
;
711 struct notifier_block edp_notifier
;
714 * Pipe whose power sequencer is currently locked into
715 * this port. Only relevant on VLV/CHV.
718 struct edp_power_seq pps_delays
;
721 bool can_mst
; /* this port supports mst */
723 int active_mst_links
;
724 /* connector directly attached - won't be use for modeset in mst world */
725 struct intel_connector
*attached_connector
;
727 /* mst connector list */
728 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
729 struct drm_dp_mst_topology_mgr mst_mgr
;
731 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
733 * This function returns the value we have to program the AUX_CTL
734 * register with to kick off an AUX transaction.
736 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
739 uint32_t aux_clock_divider
);
740 bool train_set_valid
;
742 /* Displayport compliance testing */
743 unsigned long compliance_test_type
;
744 unsigned long compliance_test_data
;
745 bool compliance_test_active
;
748 struct intel_digital_port
{
749 struct intel_encoder base
;
753 struct intel_hdmi hdmi
;
754 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
757 struct intel_dp_mst_encoder
{
758 struct intel_encoder base
;
760 struct intel_digital_port
*primary
;
761 void *port
; /* store this opaque as its illegal to dereference it */
765 vlv_dport_to_channel(struct intel_digital_port
*dport
)
767 switch (dport
->port
) {
779 vlv_pipe_to_channel(enum pipe pipe
)
792 static inline struct drm_crtc
*
793 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
796 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
799 static inline struct drm_crtc
*
800 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
803 return dev_priv
->plane_to_crtc_mapping
[plane
];
806 struct intel_unpin_work
{
807 struct work_struct work
;
808 struct drm_crtc
*crtc
;
809 struct drm_framebuffer
*old_fb
;
810 struct drm_i915_gem_object
*pending_flip_obj
;
811 struct drm_pending_vblank_event
*event
;
813 #define INTEL_FLIP_INACTIVE 0
814 #define INTEL_FLIP_PENDING 1
815 #define INTEL_FLIP_COMPLETE 2
818 struct drm_i915_gem_request
*flip_queued_req
;
819 int flip_queued_vblank
;
820 int flip_ready_vblank
;
821 bool enable_stall_check
;
824 struct intel_load_detect_pipe
{
825 struct drm_framebuffer
*release_fb
;
826 bool load_detect_temp
;
830 static inline struct intel_encoder
*
831 intel_attached_encoder(struct drm_connector
*connector
)
833 return to_intel_connector(connector
)->encoder
;
836 static inline struct intel_digital_port
*
837 enc_to_dig_port(struct drm_encoder
*encoder
)
839 return container_of(encoder
, struct intel_digital_port
, base
.base
);
842 static inline struct intel_dp_mst_encoder
*
843 enc_to_mst(struct drm_encoder
*encoder
)
845 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
848 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
850 return &enc_to_dig_port(encoder
)->dp
;
853 static inline struct intel_digital_port
*
854 dp_to_dig_port(struct intel_dp
*intel_dp
)
856 return container_of(intel_dp
, struct intel_digital_port
, dp
);
859 static inline struct intel_digital_port
*
860 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
862 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
866 * Returns the number of planes for this pipe, ie the number of sprites + 1
867 * (primary plane). This doesn't count the cursor plane then.
869 static inline unsigned int intel_num_planes(struct intel_crtc
*crtc
)
871 return INTEL_INFO(crtc
->base
.dev
)->num_sprites
[crtc
->pipe
] + 1;
874 /* intel_fifo_underrun.c */
875 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
876 enum pipe pipe
, bool enable
);
877 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
878 enum transcoder pch_transcoder
,
880 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
882 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
883 enum transcoder pch_transcoder
);
884 void i9xx_check_fifo_underruns(struct drm_i915_private
*dev_priv
);
887 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
888 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
889 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
890 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
891 void gen6_reset_rps_interrupts(struct drm_device
*dev
);
892 void gen6_enable_rps_interrupts(struct drm_device
*dev
);
893 void gen6_disable_rps_interrupts(struct drm_device
*dev
);
894 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
);
895 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
896 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
897 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
900 * We only use drm_irq_uninstall() at unload and VT switch, so
901 * this is the only thing we need to check.
903 return dev_priv
->pm
.irqs_enabled
;
906 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
907 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
908 unsigned int pipe_mask
);
911 void intel_crt_init(struct drm_device
*dev
);
915 void intel_prepare_ddi(struct drm_device
*dev
);
916 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
917 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
918 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
919 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
920 void intel_ddi_pll_init(struct drm_device
*dev
);
921 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
922 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
923 enum transcoder cpu_transcoder
);
924 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
925 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
926 bool intel_ddi_pll_select(struct intel_crtc
*crtc
,
927 struct intel_crtc_state
*crtc_state
);
928 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
929 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
);
930 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
931 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
932 void intel_ddi_get_config(struct intel_encoder
*encoder
,
933 struct intel_crtc_state
*pipe_config
);
934 struct intel_encoder
*
935 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
);
937 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
938 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
939 struct intel_crtc_state
*pipe_config
);
940 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
941 void bxt_ddi_vswing_sequence(struct drm_device
*dev
, u32 level
,
942 enum port port
, int type
);
944 /* intel_frontbuffer.c */
945 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
946 struct intel_engine_cs
*ring
,
947 enum fb_op_origin origin
);
948 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
949 unsigned frontbuffer_bits
);
950 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
951 unsigned frontbuffer_bits
);
952 void intel_frontbuffer_flush(struct drm_device
*dev
,
953 unsigned frontbuffer_bits
);
955 * intel_frontbuffer_flip - synchronous frontbuffer flip
957 * @frontbuffer_bits: frontbuffer plane tracking bits
959 * This function gets called after scheduling a flip on @obj. This is for
960 * synchronous plane updates which will happen on the next vblank and which will
961 * not get delayed by pending gpu rendering.
963 * Can be called without any locks held.
966 void intel_frontbuffer_flip(struct drm_device
*dev
,
967 unsigned frontbuffer_bits
)
969 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
972 unsigned int intel_fb_align_height(struct drm_device
*dev
,
974 uint32_t pixel_format
,
975 uint64_t fb_format_modifier
);
976 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
, bool retire
);
978 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
979 uint32_t pixel_format
);
982 void intel_init_audio(struct drm_device
*dev
);
983 void intel_audio_codec_enable(struct intel_encoder
*encoder
);
984 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
985 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
986 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
988 /* intel_display.c */
989 extern const struct drm_plane_funcs intel_plane_funcs
;
990 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
991 int intel_pch_rawclk(struct drm_device
*dev
);
992 void intel_mark_busy(struct drm_device
*dev
);
993 void intel_mark_idle(struct drm_device
*dev
);
994 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
995 int intel_display_suspend(struct drm_device
*dev
);
996 int intel_crtc_control(struct drm_crtc
*crtc
, bool enable
);
997 void intel_crtc_update_dpms(struct drm_crtc
*crtc
);
998 void intel_encoder_destroy(struct drm_encoder
*encoder
);
999 int intel_connector_init(struct intel_connector
*);
1000 struct intel_connector
*intel_connector_alloc(void);
1001 void intel_connector_dpms(struct drm_connector
*, int mode
);
1002 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1003 void intel_modeset_check_state(struct drm_device
*dev
);
1004 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1005 struct intel_digital_port
*port
);
1006 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1007 struct intel_encoder
*encoder
);
1008 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
1009 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1010 struct drm_crtc
*crtc
);
1011 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1012 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1013 struct drm_file
*file_priv
);
1014 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1016 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
);
1018 intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
1020 drm_wait_one_vblank(dev
, pipe
);
1022 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1023 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1024 struct intel_digital_port
*dport
,
1025 unsigned int expected_mask
);
1026 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
1027 struct drm_display_mode
*mode
,
1028 struct intel_load_detect_pipe
*old
,
1029 struct drm_modeset_acquire_ctx
*ctx
);
1030 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1031 struct intel_load_detect_pipe
*old
,
1032 struct drm_modeset_acquire_ctx
*ctx
);
1033 int intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
1034 struct drm_framebuffer
*fb
,
1035 const struct drm_plane_state
*plane_state
,
1036 struct intel_engine_cs
*pipelined
);
1037 struct drm_framebuffer
*
1038 __intel_framebuffer_create(struct drm_device
*dev
,
1039 struct drm_mode_fb_cmd2
*mode_cmd
,
1040 struct drm_i915_gem_object
*obj
);
1041 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
1042 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
1043 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
1044 void intel_check_page_flip(struct drm_device
*dev
, int pipe
);
1045 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1046 struct drm_framebuffer
*fb
,
1047 const struct drm_plane_state
*new_state
);
1048 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1049 struct drm_framebuffer
*fb
,
1050 const struct drm_plane_state
*old_state
);
1051 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1052 const struct drm_plane_state
*state
,
1053 struct drm_property
*property
,
1055 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1056 struct drm_plane_state
*state
,
1057 struct drm_property
*property
,
1061 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
1062 uint64_t fb_format_modifier
);
1065 intel_rotation_90_or_270(unsigned int rotation
)
1067 return rotation
& (BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
));
1070 void intel_create_rotation_property(struct drm_device
*dev
,
1071 struct intel_plane
*plane
);
1073 bool intel_wm_need_update(struct drm_plane
*plane
,
1074 struct drm_plane_state
*state
);
1076 /* shared dpll functions */
1077 struct intel_shared_dpll
*intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
);
1078 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1079 struct intel_shared_dpll
*pll
,
1081 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1082 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1083 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
1084 struct intel_crtc_state
*state
);
1086 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
1087 const struct dpll
*dpll
);
1088 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
);
1090 /* modesetting asserts */
1091 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1093 void assert_pll(struct drm_i915_private
*dev_priv
,
1094 enum pipe pipe
, bool state
);
1095 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1096 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1097 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1098 enum pipe pipe
, bool state
);
1099 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1100 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1101 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1102 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1103 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1104 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1105 unsigned int tiling_mode
,
1107 unsigned int pitch
);
1108 void intel_prepare_reset(struct drm_device
*dev
);
1109 void intel_finish_reset(struct drm_device
*dev
);
1110 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1111 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1112 void broxton_init_cdclk(struct drm_device
*dev
);
1113 void broxton_uninit_cdclk(struct drm_device
*dev
);
1114 void broxton_ddi_phy_init(struct drm_device
*dev
);
1115 void broxton_ddi_phy_uninit(struct drm_device
*dev
);
1116 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1117 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1118 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1119 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1120 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1121 struct intel_crtc_state
*pipe_config
);
1122 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1123 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1125 ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
1127 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1128 intel_clock_t
*best_clock
);
1129 bool intel_crtc_active(struct drm_crtc
*crtc
);
1130 void hsw_enable_ips(struct intel_crtc
*crtc
);
1131 void hsw_disable_ips(struct intel_crtc
*crtc
);
1132 enum intel_display_power_domain
1133 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
1134 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1135 struct intel_crtc_state
*pipe_config
);
1136 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
);
1137 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
);
1138 void skl_detach_scalers(struct intel_crtc
*intel_crtc
);
1139 int skl_update_scaler_users(struct intel_crtc
*intel_crtc
,
1140 struct intel_crtc_state
*crtc_state
, struct intel_plane
*intel_plane
,
1141 struct intel_plane_state
*plane_state
, int force_detach
);
1142 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
);
1144 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
1145 struct drm_i915_gem_object
*obj
);
1146 u32
skl_plane_ctl_format(uint32_t pixel_format
);
1147 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
);
1148 u32
skl_plane_ctl_rotation(unsigned int rotation
);
1151 void intel_csr_ucode_init(struct drm_device
*dev
);
1152 enum csr_state
intel_csr_load_status_get(struct drm_i915_private
*dev_priv
);
1153 void intel_csr_load_status_set(struct drm_i915_private
*dev_priv
,
1154 enum csr_state state
);
1155 void intel_csr_load_program(struct drm_device
*dev
);
1156 void intel_csr_ucode_fini(struct drm_device
*dev
);
1157 void assert_csr_loaded(struct drm_i915_private
*dev_priv
);
1160 void intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
);
1161 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1162 struct intel_connector
*intel_connector
);
1163 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1164 void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
1165 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1166 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1167 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1168 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1169 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1170 struct intel_crtc_state
*pipe_config
);
1171 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
1172 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1174 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
1175 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
1176 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1177 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1178 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1179 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
1180 void intel_dp_mst_suspend(struct drm_device
*dev
);
1181 void intel_dp_mst_resume(struct drm_device
*dev
);
1182 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1183 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1184 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1185 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1186 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1187 void intel_plane_destroy(struct drm_plane
*plane
);
1188 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
);
1189 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
);
1190 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
1191 unsigned frontbuffer_bits
);
1192 void intel_edp_drrs_flush(struct drm_device
*dev
, unsigned frontbuffer_bits
);
1194 /* intel_dp_mst.c */
1195 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1196 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1198 void intel_dsi_init(struct drm_device
*dev
);
1202 void intel_dvo_init(struct drm_device
*dev
);
1205 /* legacy fbdev emulation in intel_fbdev.c */
1206 #ifdef CONFIG_DRM_I915_FBDEV
1207 extern int intel_fbdev_init(struct drm_device
*dev
);
1208 extern void intel_fbdev_initial_config(void *data
, async_cookie_t cookie
);
1209 extern void intel_fbdev_fini(struct drm_device
*dev
);
1210 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1211 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1212 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1214 static inline int intel_fbdev_init(struct drm_device
*dev
)
1219 static inline void intel_fbdev_initial_config(void *data
, async_cookie_t cookie
)
1223 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1227 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1231 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1237 bool intel_fbc_enabled(struct drm_device
*dev
);
1238 void intel_fbc_update(struct drm_device
*dev
);
1239 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1240 void intel_fbc_disable(struct drm_device
*dev
);
1241 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1242 unsigned int frontbuffer_bits
,
1243 enum fb_op_origin origin
);
1244 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1245 unsigned int frontbuffer_bits
);
1248 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
);
1249 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1250 struct intel_connector
*intel_connector
);
1251 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1252 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1253 struct intel_crtc_state
*pipe_config
);
1257 void intel_lvds_init(struct drm_device
*dev
);
1258 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1262 int intel_connector_update_modes(struct drm_connector
*connector
,
1264 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1265 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1266 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1269 /* intel_overlay.c */
1270 void intel_setup_overlay(struct drm_device
*dev
);
1271 void intel_cleanup_overlay(struct drm_device
*dev
);
1272 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1273 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1274 struct drm_file
*file_priv
);
1275 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1276 struct drm_file
*file_priv
);
1277 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1281 int intel_panel_init(struct intel_panel
*panel
,
1282 struct drm_display_mode
*fixed_mode
,
1283 struct drm_display_mode
*downclock_mode
);
1284 void intel_panel_fini(struct intel_panel
*panel
);
1285 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1286 struct drm_display_mode
*adjusted_mode
);
1287 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1288 struct intel_crtc_state
*pipe_config
,
1290 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1291 struct intel_crtc_state
*pipe_config
,
1293 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1294 u32 level
, u32 max
);
1295 int intel_panel_setup_backlight(struct drm_connector
*connector
, enum pipe pipe
);
1296 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1297 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1298 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1299 void intel_panel_init_backlight_funcs(struct drm_device
*dev
);
1300 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1301 extern struct drm_display_mode
*intel_find_panel_downclock(
1302 struct drm_device
*dev
,
1303 struct drm_display_mode
*fixed_mode
,
1304 struct drm_connector
*connector
);
1305 void intel_backlight_register(struct drm_device
*dev
);
1306 void intel_backlight_unregister(struct drm_device
*dev
);
1310 void intel_psr_enable(struct intel_dp
*intel_dp
);
1311 void intel_psr_disable(struct intel_dp
*intel_dp
);
1312 void intel_psr_invalidate(struct drm_device
*dev
,
1313 unsigned frontbuffer_bits
);
1314 void intel_psr_flush(struct drm_device
*dev
,
1315 unsigned frontbuffer_bits
);
1316 void intel_psr_init(struct drm_device
*dev
);
1317 void intel_psr_single_frame_update(struct drm_device
*dev
);
1319 /* intel_runtime_pm.c */
1320 int intel_power_domains_init(struct drm_i915_private
*);
1321 void intel_power_domains_fini(struct drm_i915_private
*);
1322 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
);
1323 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1325 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1326 enum intel_display_power_domain domain
);
1327 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1328 enum intel_display_power_domain domain
);
1329 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1330 enum intel_display_power_domain domain
);
1331 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1332 enum intel_display_power_domain domain
);
1333 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
);
1334 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
);
1335 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1336 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1337 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1339 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1342 void intel_init_clock_gating(struct drm_device
*dev
);
1343 void intel_suspend_hw(struct drm_device
*dev
);
1344 int ilk_wm_max_level(const struct drm_device
*dev
);
1345 void intel_update_watermarks(struct drm_crtc
*crtc
);
1346 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
1347 struct drm_crtc
*crtc
,
1348 uint32_t sprite_width
,
1349 uint32_t sprite_height
,
1351 bool enabled
, bool scaled
);
1352 void intel_init_pm(struct drm_device
*dev
);
1353 void intel_pm_setup(struct drm_device
*dev
);
1354 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1355 void intel_gpu_ips_teardown(void);
1356 void intel_init_gt_powersave(struct drm_device
*dev
);
1357 void intel_cleanup_gt_powersave(struct drm_device
*dev
);
1358 void intel_enable_gt_powersave(struct drm_device
*dev
);
1359 void intel_disable_gt_powersave(struct drm_device
*dev
);
1360 void intel_suspend_gt_powersave(struct drm_device
*dev
);
1361 void intel_reset_gt_powersave(struct drm_device
*dev
);
1362 void gen6_update_ring_freq(struct drm_device
*dev
);
1363 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1364 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1365 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1366 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
1367 struct intel_rps_client
*rps
,
1368 unsigned long submitted
);
1369 void intel_queue_rps_boost_for_request(struct drm_device
*dev
,
1370 struct drm_i915_gem_request
*req
);
1371 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1372 void skl_wm_get_hw_state(struct drm_device
*dev
);
1373 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1374 struct skl_ddb_allocation
*ddb
/* out */);
1375 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
);
1378 bool intel_sdvo_init(struct drm_device
*dev
, uint32_t sdvo_reg
, bool is_sdvob
);
1381 /* intel_sprite.c */
1382 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
1383 int intel_plane_restore(struct drm_plane
*plane
);
1384 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1385 struct drm_file
*file_priv
);
1386 bool intel_pipe_update_start(struct intel_crtc
*crtc
,
1387 uint32_t *start_vbl_count
);
1388 void intel_pipe_update_end(struct intel_crtc
*crtc
, u32 start_vbl_count
);
1391 void intel_tv_init(struct drm_device
*dev
);
1393 /* intel_atomic.c */
1394 int intel_atomic_check(struct drm_device
*dev
,
1395 struct drm_atomic_state
*state
);
1396 int intel_atomic_commit(struct drm_device
*dev
,
1397 struct drm_atomic_state
*state
,
1399 int intel_connector_atomic_get_property(struct drm_connector
*connector
,
1400 const struct drm_connector_state
*state
,
1401 struct drm_property
*property
,
1403 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1404 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1405 struct drm_crtc_state
*state
);
1406 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
1407 void intel_atomic_state_clear(struct drm_atomic_state
*);
1408 struct intel_shared_dpll_config
*
1409 intel_atomic_get_shared_dpll_state(struct drm_atomic_state
*s
);
1410 void intel_atomic_duplicate_dpll_state(struct drm_i915_private
*,
1411 struct intel_shared_dpll_config
*);
1413 static inline struct intel_crtc_state
*
1414 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1415 struct intel_crtc
*crtc
)
1417 struct drm_crtc_state
*crtc_state
;
1418 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1419 if (IS_ERR(crtc_state
))
1420 return ERR_CAST(crtc_state
);
1422 return to_intel_crtc_state(crtc_state
);
1424 int intel_atomic_setup_scalers(struct drm_device
*dev
,
1425 struct intel_crtc
*intel_crtc
,
1426 struct intel_crtc_state
*crtc_state
);
1428 /* intel_atomic_plane.c */
1429 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1430 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1431 void intel_plane_destroy_state(struct drm_plane
*plane
,
1432 struct drm_plane_state
*state
);
1433 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1435 #endif /* __INTEL_DRV_H__ */