drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         struct list_head fbdev_list;
 127         struct drm_display_mode *our_mode;
 128         int preferred_bpp;
 129 };
 130
 131 struct intel_encoder {
 132         struct drm_encoder base;
 133         /*
 134          * The new crtc this encoder will be driven from. Only differs from
 135          * base->crtc while a modeset is in progress.
 136          */
 137         struct intel_crtc *new_crtc;
 138
 139         enum intel_output_type type;
 140         unsigned int cloneable;
 141         bool connectors_active;
 142         void (*hot_plug)(struct intel_encoder *);
 143         bool (*compute_config)(struct intel_encoder *,
 144                                struct intel_crtc_state *);
 145         void (*pre_pll_enable)(struct intel_encoder *);
 146         void (*pre_enable)(struct intel_encoder *);
 147         void (*enable)(struct intel_encoder *);
 148         void (*mode_set)(struct intel_encoder *intel_encoder);
 149         void (*disable)(struct intel_encoder *);
 150         void (*post_disable)(struct intel_encoder *);
 151         /* Read out the current hw state of this connector, returning true if
 152          * the encoder is active. If the encoder is enabled it also set the pipe
 153          * it is connected to in the pipe parameter. */
 154         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 155         /* Reconstructs the equivalent mode flags for the current hardware
 156          * state. This must be called _after_ display->get_pipe_config has
 157          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 158          * be set correctly before calling this function. */
 159         void (*get_config)(struct intel_encoder *,
 160                            struct intel_crtc_state *pipe_config);
 161         /*
 162          * Called during system suspend after all pending requests for the
 163          * encoder are flushed (for example for DP AUX transactions) and
 164          * device interrupts are disabled.
 165          */
 166         void (*suspend)(struct intel_encoder *);
 167         int crtc_mask;
 168         enum hpd_pin hpd_pin;
 169 };
 170
 171 struct intel_panel {
 172         struct drm_display_mode *fixed_mode;
 173         struct drm_display_mode *downclock_mode;
 174         int fitting_mode;
 175
 176         /* backlight */
 177         struct {
 178                 bool present;
 179                 u32 level;
 180                 u32 min;
 181                 u32 max;
 182                 bool enabled;
 183                 bool combination_mode;  /* gen 2/4 only */
 184                 bool active_low_pwm;
 185                 struct backlight_device *device;
 186         } backlight;
 187
 188         void (*backlight_power)(struct intel_connector *, bool enable);
 189 };
 190
 191 struct intel_connector {
 192         struct drm_connector base;
 193         /*
 194          * The fixed encoder this connector is connected to.
 195          */
 196         struct intel_encoder *encoder;
 197
 198         /*
 199          * The new encoder this connector will be driven. Only differs from
 200          * encoder while a modeset is in progress.
 201          */
 202         struct intel_encoder *new_encoder;
 203
 204         /* Reads out the current hw, returning true if the connector is enabled
 205          * and active (i.e. dpms ON state). */
 206         bool (*get_hw_state)(struct intel_connector *);
 207
 208         /*
 209          * Removes all interfaces through which the connector is accessible
 210          * - like sysfs, debugfs entries -, so that no new operations can be
 211          * started on the connector. Also makes sure all currently pending
 212          * operations finish before returing.
 213          */
 214         void (*unregister)(struct intel_connector *);
 215
 216         /* Panel info for eDP and LVDS */
 217         struct intel_panel panel;
 218
 219         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 220         struct edid *edid;
 221         struct edid *detect_edid;
 222
 223         /* since POLL and HPD connectors may use the same HPD line keep the native
 224            state of connector->polled in case hotplug storm detection changes it */
 225         u8 polled;
 226
 227         void *port; /* store this opaque as its illegal to dereference it */
 228
 229         struct intel_dp *mst_port;
 230 };
 231
 232 typedef struct dpll {
 233         /* given values */
 234         int n;
 235         int m1, m2;
 236         int p1, p2;
 237         /* derived values */
 238         int     dot;
 239         int     vco;
 240         int     m;
 241         int     p;
 242 } intel_clock_t;
 243
 244 struct intel_plane_state {
 245         struct drm_plane_state base;
 246         struct drm_rect src;
 247         struct drm_rect dst;
 248         struct drm_rect clip;
 249         bool visible;
 250
 251         /*
 252          * scaler_id
 253          *    = -1 : not using a scaler
 254          *    >=  0 : using a scalers
 255          *
 256          * plane requiring a scaler:
 257          *   - During check_plane, its bit is set in
 258          *     crtc_state->scaler_state.scaler_users by calling helper function
 259          *     update_scaler_users.
 260          *   - scaler_id indicates the scaler it got assigned.
 261          *
 262          * plane doesn't require a scaler:
 263          *   - this can happen when scaling is no more required or plane simply
 264          *     got disabled.
 265          *   - During check_plane, corresponding bit is reset in
 266          *     crtc_state->scaler_state.scaler_users by calling helper function
 267          *     update_scaler_users.
 268          */
 269         int scaler_id;
 270 };
 271
 272 struct intel_initial_plane_config {
 273         struct intel_framebuffer *fb;
 274         unsigned int tiling;
 275         int size;
 276         u32 base;
 277 };
 278
 279 #define SKL_MIN_SRC_W 8
 280 #define SKL_MAX_SRC_W 4096
 281 #define SKL_MIN_SRC_H 8
 282 #define SKL_MAX_SRC_H 4096
 283 #define SKL_MIN_DST_W 8
 284 #define SKL_MAX_DST_W 4096
 285 #define SKL_MIN_DST_H 8
 286 #define SKL_MAX_DST_H 4096
 287
 288 struct intel_scaler {
 289         int id;
 290         int in_use;
 291         uint32_t mode;
 292 };
 293
 294 struct intel_crtc_scaler_state {
 295 #define SKL_NUM_SCALERS 2
 296         struct intel_scaler scalers[SKL_NUM_SCALERS];
 297
 298         /*
 299          * scaler_users: keeps track of users requesting scalers on this crtc.
 300          *
 301          *     If a bit is set, a user is using a scaler.
 302          *     Here user can be a plane or crtc as defined below:
 303          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 304          *       bit 31    - crtc
 305          *
 306          * Instead of creating a new index to cover planes and crtc, using
 307          * existing drm_plane_index for planes which is well less than 31
 308          * planes and bit 31 for crtc. This should be fine to cover all
 309          * our platforms.
 310          *
 311          * intel_atomic_setup_scalers will setup available scalers to users
 312          * requesting scalers. It will gracefully fail if request exceeds
 313          * avilability.
 314          */
 315 #define SKL_CRTC_INDEX 31
 316         unsigned scaler_users;
 317
 318         /* scaler used by crtc for panel fitting purpose */
 319         int scaler_id;
 320 };
 321
 322 struct intel_crtc_state {
 323         struct drm_crtc_state base;
 324
 325         /**
 326          * quirks - bitfield with hw state readout quirks
 327          *
 328          * For various reasons the hw state readout code might not be able to
 329          * completely faithfully read out the current state. These cases are
 330          * tracked with quirk flags so that fastboot and state checker can act
 331          * accordingly.
 332          */
 333 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 334 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 335         unsigned long quirks;
 336
 337         /* Pipe source size (ie. panel fitter input size)
 338          * All planes will be positioned inside this space,
 339          * and get clipped at the edges. */
 340         int pipe_src_w, pipe_src_h;
 341
 342         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 343          * between pch encoders and cpu encoders. */
 344         bool has_pch_encoder;
 345
 346         /* Are we sending infoframes on the attached port */
 347         bool has_infoframe;
 348
 349         /* CPU Transcoder for the pipe. Currently this can only differ from the
 350          * pipe on Haswell (where we have a special eDP transcoder). */
 351         enum transcoder cpu_transcoder;
 352
 353         /*
 354          * Use reduced/limited/broadcast rbg range, compressing from the full
 355          * range fed into the crtcs.
 356          */
 357         bool limited_color_range;
 358
 359         /* DP has a bunch of special case unfortunately, so mark the pipe
 360          * accordingly. */
 361         bool has_dp_encoder;
 362
 363         /* Whether we should send NULL infoframes. Required for audio. */
 364         bool has_hdmi_sink;
 365
 366         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 367          * has_dp_encoder is set. */
 368         bool has_audio;
 369
 370         /*
 371          * Enable dithering, used when the selected pipe bpp doesn't match the
 372          * plane bpp.
 373          */
 374         bool dither;
 375
 376         /* Controls for the clock computation, to override various stages. */
 377         bool clock_set;
 378
 379         /* SDVO TV has a bunch of special case. To make multifunction encoders
 380          * work correctly, we need to track this at runtime.*/
 381         bool sdvo_tv_clock;
 382
 383         /*
 384          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 385          * required. This is set in the 2nd loop of calling encoder's
 386          * ->compute_config if the first pick doesn't work out.
 387          */
 388         bool bw_constrained;
 389
 390         /* Settings for the intel dpll used on pretty much everything but
 391          * haswell. */
 392         struct dpll dpll;
 393
 394         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 395         enum intel_dpll_id shared_dpll;
 396
 397         /*
 398          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 399          * - enum skl_dpll on SKL
 400          */
 401         uint32_t ddi_pll_sel;
 402
 403         /* Actual register state of the dpll, for shared dpll cross-checking. */
 404         struct intel_dpll_hw_state dpll_hw_state;
 405
 406         int pipe_bpp;
 407         struct intel_link_m_n dp_m_n;
 408
 409         /* m2_n2 for eDP downclock */
 410         struct intel_link_m_n dp_m2_n2;
 411         bool has_drrs;
 412
 413         /*
 414          * Frequence the dpll for the port should run at. Differs from the
 415          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 416          * already multiplied by pixel_multiplier.
 417          */
 418         int port_clock;
 419
 420         /* Used by SDVO (and if we ever fix it, HDMI). */
 421         unsigned pixel_multiplier;
 422
 423         /* Panel fitter controls for gen2-gen4 + VLV */
 424         struct {
 425                 u32 control;
 426                 u32 pgm_ratios;
 427                 u32 lvds_border_bits;
 428         } gmch_pfit;
 429
 430         /* Panel fitter placement and size for Ironlake+ */
 431         struct {
 432                 u32 pos;
 433                 u32 size;
 434                 bool enabled;
 435                 bool force_thru;
 436         } pch_pfit;
 437
 438         /* FDI configuration, only valid if has_pch_encoder is set. */
 439         int fdi_lanes;
 440         struct intel_link_m_n fdi_m_n;
 441
 442         bool ips_enabled;
 443
 444         bool double_wide;
 445
 446         bool dp_encoder_is_mst;
 447         int pbn;
 448
 449         struct intel_crtc_scaler_state scaler_state;
 450 };
 451
 452 struct intel_pipe_wm {
 453         struct intel_wm_level wm[5];
 454         uint32_t linetime;
 455         bool fbc_wm_enabled;
 456         bool pipe_enabled;
 457         bool sprites_enabled;
 458         bool sprites_scaled;
 459 };
 460
 461 struct intel_mmio_flip {
 462         struct work_struct work;
 463         struct drm_i915_private *i915;
 464         struct drm_i915_gem_request *req;
 465         struct intel_crtc *crtc;
 466 };
 467
 468 struct skl_pipe_wm {
 469         struct skl_wm_level wm[8];
 470         struct skl_wm_level trans_wm;
 471         uint32_t linetime;
 472 };
 473
 474 /*
 475  * Tracking of operations that need to be performed at the beginning/end of an
 476  * atomic commit, outside the atomic section where interrupts are disabled.
 477  * These are generally operations that grab mutexes or might otherwise sleep
 478  * and thus can't be run with interrupts disabled.
 479  */
 480 struct intel_crtc_atomic_commit {
 481         /* vblank evasion */
 482         bool evade;
 483         unsigned start_vbl_count;
 484
 485         /* Sleepable operations to perform before commit */
 486         bool wait_for_flips;
 487         bool disable_fbc;
 488         bool pre_disable_primary;
 489         bool update_wm;
 490         unsigned disabled_planes;
 491
 492         /* Sleepable operations to perform after commit */
 493         unsigned fb_bits;
 494         bool wait_vblank;
 495         bool update_fbc;
 496         bool post_enable_primary;
 497         unsigned update_sprite_watermarks;
 498 };
 499
 500 struct intel_crtc {
 501         struct drm_crtc base;
 502         enum pipe pipe;
 503         enum plane plane;
 504         u8 lut_r[256], lut_g[256], lut_b[256];
 505         /*
 506          * Whether the crtc and the connected output pipeline is active. Implies
 507          * that crtc->enabled is set, i.e. the current mode configuration has
 508          * some outputs connected to this crtc.
 509          */
 510         bool active;
 511         unsigned long enabled_power_domains;
 512         bool lowfreq_avail;
 513         struct intel_overlay *overlay;
 514         struct intel_unpin_work *unpin_work;
 515
 516         atomic_t unpin_work_count;
 517
 518         /* Display surface base address adjustement for pageflips. Note that on
 519          * gen4+ this only adjusts up to a tile, offsets within a tile are
 520          * handled in the hw itself (with the TILEOFF register). */
 521         unsigned long dspaddr_offset;
 522
 523         struct drm_i915_gem_object *cursor_bo;
 524         uint32_t cursor_addr;
 525         uint32_t cursor_cntl;
 526         uint32_t cursor_size;
 527         uint32_t cursor_base;
 528
 529         struct intel_initial_plane_config plane_config;
 530         struct intel_crtc_state *config;
 531         bool new_enabled;
 532
 533         /* reset counter value when the last flip was submitted */
 534         unsigned int reset_counter;
 535
 536         /* Access to these should be protected by dev_priv->irq_lock. */
 537         bool cpu_fifo_underrun_disabled;
 538         bool pch_fifo_underrun_disabled;
 539
 540         /* per-pipe watermark state */
 541         struct {
 542                 /* watermarks currently being used  */
 543                 struct intel_pipe_wm active;
 544                 /* SKL wm values currently in use */
 545                 struct skl_pipe_wm skl_active;
 546         } wm;
 547
 548         int scanline_offset;
 549
 550         struct intel_crtc_atomic_commit atomic;
 551
 552         /* scalers available on this crtc */
 553         int num_scalers;
 554 };
 555
 556 struct intel_plane_wm_parameters {
 557         uint32_t horiz_pixels;
 558         uint32_t vert_pixels;
 559         /*
 560          *   For packed pixel formats:
 561          *     bytes_per_pixel - holds bytes per pixel
 562          *   For planar pixel formats:
 563          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 564          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 565          */
 566         uint8_t bytes_per_pixel;
 567         uint8_t y_bytes_per_pixel;
 568         bool enabled;
 569         bool scaled;
 570         u64 tiling;
 571         unsigned int rotation;
 572 };
 573
 574 struct intel_plane {
 575         struct drm_plane base;
 576         int plane;
 577         enum pipe pipe;
 578         bool can_scale;
 579         int max_downscale;
 580
 581         /* FIXME convert to properties */
 582         struct drm_intel_sprite_colorkey ckey;
 583
 584         /* Since we need to change the watermarks before/after
 585          * enabling/disabling the planes, we need to store the parameters here
 586          * as the other pieces of the struct may not reflect the values we want
 587          * for the watermark calculations. Currently only Haswell uses this.
 588          */
 589         struct intel_plane_wm_parameters wm;
 590
 591         /*
 592          * NOTE: Do not place new plane state fields here (e.g., when adding
 593          * new plane properties).  New runtime state should now be placed in
 594          * the intel_plane_state structure and accessed via drm_plane->state.
 595          */
 596
 597         void (*update_plane)(struct drm_plane *plane,
 598                              struct drm_crtc *crtc,
 599                              struct drm_framebuffer *fb,
 600                              int crtc_x, int crtc_y,
 601                              unsigned int crtc_w, unsigned int crtc_h,
 602                              uint32_t x, uint32_t y,
 603                              uint32_t src_w, uint32_t src_h);
 604         void (*disable_plane)(struct drm_plane *plane,
 605                               struct drm_crtc *crtc, bool force);
 606         int (*check_plane)(struct drm_plane *plane,
 607                            struct intel_plane_state *state);
 608         void (*commit_plane)(struct drm_plane *plane,
 609                              struct intel_plane_state *state);
 610 };
 611
 612 struct intel_watermark_params {
 613         unsigned long fifo_size;
 614         unsigned long max_wm;
 615         unsigned long default_wm;
 616         unsigned long guard_size;
 617         unsigned long cacheline_size;
 618 };
 619
 620 struct cxsr_latency {
 621         int is_desktop;
 622         int is_ddr3;
 623         unsigned long fsb_freq;
 624         unsigned long mem_freq;
 625         unsigned long display_sr;
 626         unsigned long display_hpll_disable;
 627         unsigned long cursor_sr;
 628         unsigned long cursor_hpll_disable;
 629 };
 630
 631 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 632 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 633 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 634 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 635 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 636 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 637 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 638 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 639
 640 struct intel_hdmi {
 641         u32 hdmi_reg;
 642         int ddc_bus;
 643         uint32_t color_range;
 644         bool color_range_auto;
 645         bool has_hdmi_sink;
 646         bool has_audio;
 647         enum hdmi_force_audio force_audio;
 648         bool rgb_quant_range_selectable;
 649         enum hdmi_picture_aspect aspect_ratio;
 650         void (*write_infoframe)(struct drm_encoder *encoder,
 651                                 enum hdmi_infoframe_type type,
 652                                 const void *frame, ssize_t len);
 653         void (*set_infoframes)(struct drm_encoder *encoder,
 654                                bool enable,
 655                                struct drm_display_mode *adjusted_mode);
 656         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 657 };
 658
 659 struct intel_dp_mst_encoder;
 660 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 661
 662 /*
 663  * enum link_m_n_set:
 664  *      When platform provides two set of M_N registers for dp, we can
 665  *      program them and switch between them incase of DRRS.
 666  *      But When only one such register is provided, we have to program the
 667  *      required divider value on that registers itself based on the DRRS state.
 668  *
 669  * M1_N1        : Program dp_m_n on M1_N1 registers
 670  *                        dp_m2_n2 on M2_N2 registers (If supported)
 671  *
 672  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 673  *                        M2_N2 registers are not supported
 674  */
 675
 676 enum link_m_n_set {
 677         /* Sets the m1_n1 and m2_n2 */
 678         M1_N1 = 0,
 679         M2_N2
 680 };
 681
 682 struct intel_dp {
 683         uint32_t output_reg;
 684         uint32_t aux_ch_ctl_reg;
 685         uint32_t DP;
 686         bool has_audio;
 687         enum hdmi_force_audio force_audio;
 688         uint32_t color_range;
 689         bool color_range_auto;
 690         uint8_t link_bw;
 691         uint8_t rate_select;
 692         uint8_t lane_count;
 693         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 694         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 695         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 696         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 697         uint8_t num_sink_rates;
 698         int sink_rates[DP_MAX_SUPPORTED_RATES];
 699         struct drm_dp_aux aux;
 700         uint8_t train_set[4];
 701         int panel_power_up_delay;
 702         int panel_power_down_delay;
 703         int panel_power_cycle_delay;
 704         int backlight_on_delay;
 705         int backlight_off_delay;
 706         struct delayed_work panel_vdd_work;
 707         bool want_panel_vdd;
 708         unsigned long last_power_cycle;
 709         unsigned long last_power_on;
 710         unsigned long last_backlight_off;
 711
 712         struct notifier_block edp_notifier;
 713
 714         /*
 715          * Pipe whose power sequencer is currently locked into
 716          * this port. Only relevant on VLV/CHV.
 717          */
 718         enum pipe pps_pipe;
 719         struct edp_power_seq pps_delays;
 720
 721         bool use_tps3;
 722         bool can_mst; /* this port supports mst */
 723         bool is_mst;
 724         int active_mst_links;
 725         /* connector directly attached - won't be use for modeset in mst world */
 726         struct intel_connector *attached_connector;
 727
 728         /* mst connector list */
 729         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 730         struct drm_dp_mst_topology_mgr mst_mgr;
 731
 732         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 733         /*
 734          * This function returns the value we have to program the AUX_CTL
 735          * register with to kick off an AUX transaction.
 736          */
 737         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 738                                      bool has_aux_irq,
 739                                      int send_bytes,
 740                                      uint32_t aux_clock_divider);
 741         bool train_set_valid;
 742
 743         /* Displayport compliance testing */
 744         unsigned long compliance_test_type;
 745         unsigned long compliance_test_data;
 746         bool compliance_test_active;
 747 };
 748
 749 struct intel_digital_port {
 750         struct intel_encoder base;
 751         enum port port;
 752         u32 saved_port_bits;
 753         struct intel_dp dp;
 754         struct intel_hdmi hdmi;
 755         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 756 };
 757
 758 struct intel_dp_mst_encoder {
 759         struct intel_encoder base;
 760         enum pipe pipe;
 761         struct intel_digital_port *primary;
 762         void *port; /* store this opaque as its illegal to dereference it */
 763 };
 764
 765 static inline int
 766 vlv_dport_to_channel(struct intel_digital_port *dport)
 767 {
 768         switch (dport->port) {
 769         case PORT_B:
 770         case PORT_D:
 771                 return DPIO_CH0;
 772         case PORT_C:
 773                 return DPIO_CH1;
 774         default:
 775                 BUG();
 776         }
 777 }
 778
 779 static inline int
 780 vlv_pipe_to_channel(enum pipe pipe)
 781 {
 782         switch (pipe) {
 783         case PIPE_A:
 784         case PIPE_C:
 785                 return DPIO_CH0;
 786         case PIPE_B:
 787                 return DPIO_CH1;
 788         default:
 789                 BUG();
 790         }
 791 }
 792
 793 static inline struct drm_crtc *
 794 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 795 {
 796         struct drm_i915_private *dev_priv = dev->dev_private;
 797         return dev_priv->pipe_to_crtc_mapping[pipe];
 798 }
 799
 800 static inline struct drm_crtc *
 801 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 802 {
 803         struct drm_i915_private *dev_priv = dev->dev_private;
 804         return dev_priv->plane_to_crtc_mapping[plane];
 805 }
 806
 807 struct intel_unpin_work {
 808         struct work_struct work;
 809         struct drm_crtc *crtc;
 810         struct drm_framebuffer *old_fb;
 811         struct drm_i915_gem_object *pending_flip_obj;
 812         struct drm_pending_vblank_event *event;
 813         atomic_t pending;
 814 #define INTEL_FLIP_INACTIVE     0
 815 #define INTEL_FLIP_PENDING      1
 816 #define INTEL_FLIP_COMPLETE     2
 817         u32 flip_count;
 818         u32 gtt_offset;
 819         struct drm_i915_gem_request *flip_queued_req;
 820         int flip_queued_vblank;
 821         int flip_ready_vblank;
 822         bool enable_stall_check;
 823 };
 824
 825 struct intel_load_detect_pipe {
 826         struct drm_framebuffer *release_fb;
 827         bool load_detect_temp;
 828         int dpms_mode;
 829 };
 830
 831 static inline struct intel_encoder *
 832 intel_attached_encoder(struct drm_connector *connector)
 833 {
 834         return to_intel_connector(connector)->encoder;
 835 }
 836
 837 static inline struct intel_digital_port *
 838 enc_to_dig_port(struct drm_encoder *encoder)
 839 {
 840         return container_of(encoder, struct intel_digital_port, base.base);
 841 }
 842
 843 static inline struct intel_dp_mst_encoder *
 844 enc_to_mst(struct drm_encoder *encoder)
 845 {
 846         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 847 }
 848
 849 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 850 {
 851         return &enc_to_dig_port(encoder)->dp;
 852 }
 853
 854 static inline struct intel_digital_port *
 855 dp_to_dig_port(struct intel_dp *intel_dp)
 856 {
 857         return container_of(intel_dp, struct intel_digital_port, dp);
 858 }
 859
 860 static inline struct intel_digital_port *
 861 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 862 {
 863         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 864 }
 865
 866 /*
 867  * Returns the number of planes for this pipe, ie the number of sprites + 1
 868  * (primary plane). This doesn't count the cursor plane then.
 869  */
 870 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 871 {
 872         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 873 }
 874
 875 /* intel_fifo_underrun.c */
 876 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 877                                            enum pipe pipe, bool enable);
 878 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 879                                            enum transcoder pch_transcoder,
 880                                            bool enable);
 881 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 882                                          enum pipe pipe);
 883 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 884                                          enum transcoder pch_transcoder);
 885 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 886
 887 /* i915_irq.c */
 888 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 889 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 890 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 891 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 892 void gen6_reset_rps_interrupts(struct drm_device *dev);
 893 void gen6_enable_rps_interrupts(struct drm_device *dev);
 894 void gen6_disable_rps_interrupts(struct drm_device *dev);
 895 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 896 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 897 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 898 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 899 {
 900         /*
 901          * We only use drm_irq_uninstall() at unload and VT switch, so
 902          * this is the only thing we need to check.
 903          */
 904         return dev_priv->pm.irqs_enabled;
 905 }
 906
 907 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 908 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 909                                      unsigned int pipe_mask);
 910
 911 /* intel_crt.c */
 912 void intel_crt_init(struct drm_device *dev);
 913
 914
 915 /* intel_ddi.c */
 916 void intel_prepare_ddi(struct drm_device *dev);
 917 void hsw_fdi_link_train(struct drm_crtc *crtc);
 918 void intel_ddi_init(struct drm_device *dev, enum port port);
 919 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 920 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 921 void intel_ddi_pll_init(struct drm_device *dev);
 922 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 923 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 924                                        enum transcoder cpu_transcoder);
 925 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 926 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 927 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 928                           struct intel_crtc_state *crtc_state);
 929 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 930 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 931 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 932 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 933 void intel_ddi_get_config(struct intel_encoder *encoder,
 934                           struct intel_crtc_state *pipe_config);
 935 struct intel_encoder *
 936 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
 937
 938 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 939 void intel_ddi_clock_get(struct intel_encoder *encoder,
 940                          struct intel_crtc_state *pipe_config);
 941 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 942 void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
 943                                 enum port port, int type);
 944
 945 /* intel_frontbuffer.c */
 946 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 947                              struct intel_engine_cs *ring,
 948                              enum fb_op_origin origin);
 949 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 950                                     unsigned frontbuffer_bits);
 951 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 952                                      unsigned frontbuffer_bits);
 953 void intel_frontbuffer_flush(struct drm_device *dev,
 954                              unsigned frontbuffer_bits);
 955 /**
 956  * intel_frontbuffer_flip - synchronous frontbuffer flip
 957  * @dev: DRM device
 958  * @frontbuffer_bits: frontbuffer plane tracking bits
 959  *
 960  * This function gets called after scheduling a flip on @obj. This is for
 961  * synchronous plane updates which will happen on the next vblank and which will
 962  * not get delayed by pending gpu rendering.
 963  *
 964  * Can be called without any locks held.
 965  */
 966 static inline
 967 void intel_frontbuffer_flip(struct drm_device *dev,
 968                             unsigned frontbuffer_bits)
 969 {
 970         intel_frontbuffer_flush(dev, frontbuffer_bits);
 971 }
 972
 973 unsigned int intel_fb_align_height(struct drm_device *dev,
 974                                    unsigned int height,
 975                                    uint32_t pixel_format,
 976                                    uint64_t fb_format_modifier);
 977 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 978
 979 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
 980                               uint32_t pixel_format);
 981
 982 /* intel_audio.c */
 983 void intel_init_audio(struct drm_device *dev);
 984 void intel_audio_codec_enable(struct intel_encoder *encoder);
 985 void intel_audio_codec_disable(struct intel_encoder *encoder);
 986 void i915_audio_component_init(struct drm_i915_private *dev_priv);
 987 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
 988
 989 /* intel_display.c */
 990 extern const struct drm_plane_funcs intel_plane_funcs;
 991 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 992 int intel_pch_rawclk(struct drm_device *dev);
 993 void intel_mark_busy(struct drm_device *dev);
 994 void intel_mark_idle(struct drm_device *dev);
 995 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 996 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
 997 void intel_crtc_reset(struct intel_crtc *crtc);
 998 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 999 void intel_encoder_destroy(struct drm_encoder *encoder);
1000 int intel_connector_init(struct intel_connector *);
1001 struct intel_connector *intel_connector_alloc(void);
1002 void intel_connector_dpms(struct drm_connector *, int mode);
1003 bool intel_connector_get_hw_state(struct intel_connector *connector);
1004 void intel_modeset_check_state(struct drm_device *dev);
1005 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1006                                 struct intel_digital_port *port);
1007 void intel_connector_attach_encoder(struct intel_connector *connector,
1008                                     struct intel_encoder *encoder);
1009 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1010 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1011                                              struct drm_crtc *crtc);
1012 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1013 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1014                                 struct drm_file *file_priv);
1015 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1016                                              enum pipe pipe);
1017 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1018 static inline void
1019 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1020 {
1021         drm_wait_one_vblank(dev, pipe);
1022 }
1023 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1024 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1025                          struct intel_digital_port *dport,
1026                          unsigned int expected_mask);
1027 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1028                                 struct drm_display_mode *mode,
1029                                 struct intel_load_detect_pipe *old,
1030                                 struct drm_modeset_acquire_ctx *ctx);
1031 void intel_release_load_detect_pipe(struct drm_connector *connector,
1032                                     struct intel_load_detect_pipe *old,
1033                                     struct drm_modeset_acquire_ctx *ctx);
1034 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1035                                struct drm_framebuffer *fb,
1036                                const struct drm_plane_state *plane_state,
1037                                struct intel_engine_cs *pipelined);
1038 struct drm_framebuffer *
1039 __intel_framebuffer_create(struct drm_device *dev,
1040                            struct drm_mode_fb_cmd2 *mode_cmd,
1041                            struct drm_i915_gem_object *obj);
1042 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1043 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1044 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1045 void intel_check_page_flip(struct drm_device *dev, int pipe);
1046 int intel_prepare_plane_fb(struct drm_plane *plane,
1047                            struct drm_framebuffer *fb,
1048                            const struct drm_plane_state *new_state);
1049 void intel_cleanup_plane_fb(struct drm_plane *plane,
1050                             struct drm_framebuffer *fb,
1051                             const struct drm_plane_state *old_state);
1052 int intel_plane_atomic_get_property(struct drm_plane *plane,
1053                                     const struct drm_plane_state *state,
1054                                     struct drm_property *property,
1055                                     uint64_t *val);
1056 int intel_plane_atomic_set_property(struct drm_plane *plane,
1057                                     struct drm_plane_state *state,
1058                                     struct drm_property *property,
1059                                     uint64_t val);
1060
1061 unsigned int
1062 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1063                   uint64_t fb_format_modifier);
1064
1065 static inline bool
1066 intel_rotation_90_or_270(unsigned int rotation)
1067 {
1068         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1069 }
1070
1071 void intel_create_rotation_property(struct drm_device *dev,
1072                                         struct intel_plane *plane);
1073
1074 bool intel_wm_need_update(struct drm_plane *plane,
1075                           struct drm_plane_state *state);
1076
1077 /* shared dpll functions */
1078 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1079 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1080                         struct intel_shared_dpll *pll,
1081                         bool state);
1082 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1083 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1084 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1085                                                 struct intel_crtc_state *state);
1086 void intel_put_shared_dpll(struct intel_crtc *crtc);
1087
1088 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1089                       const struct dpll *dpll);
1090 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1091
1092 /* modesetting asserts */
1093 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1094                            enum pipe pipe);
1095 void assert_pll(struct drm_i915_private *dev_priv,
1096                 enum pipe pipe, bool state);
1097 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1098 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1099 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1100                        enum pipe pipe, bool state);
1101 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1102 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1103 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1104 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1105 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1106 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1107                                              unsigned int tiling_mode,
1108                                              unsigned int bpp,
1109                                              unsigned int pitch);
1110 void intel_prepare_reset(struct drm_device *dev);
1111 void intel_finish_reset(struct drm_device *dev);
1112 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1113 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1114 void broxton_init_cdclk(struct drm_device *dev);
1115 void broxton_uninit_cdclk(struct drm_device *dev);
1116 void broxton_ddi_phy_init(struct drm_device *dev);
1117 void broxton_ddi_phy_uninit(struct drm_device *dev);
1118 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1119 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1120 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1121 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1122 void intel_dp_get_m_n(struct intel_crtc *crtc,
1123                       struct intel_crtc_state *pipe_config);
1124 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1125 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1126 void
1127 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1128                                 int dotclock);
1129 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1130                         intel_clock_t *best_clock);
1131 bool intel_crtc_active(struct drm_crtc *crtc);
1132 void hsw_enable_ips(struct intel_crtc *crtc);
1133 void hsw_disable_ips(struct intel_crtc *crtc);
1134 enum intel_display_power_domain
1135 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1136 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1137                                  struct intel_crtc_state *pipe_config);
1138 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1139 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1140 void skl_detach_scalers(struct intel_crtc *intel_crtc);
1141 int skl_update_scaler_users(struct intel_crtc *intel_crtc,
1142         struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane,
1143         struct intel_plane_state *plane_state, int force_detach);
1144 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1145
1146 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1147                                      struct drm_i915_gem_object *obj);
1148 u32 skl_plane_ctl_format(uint32_t pixel_format);
1149 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1150 u32 skl_plane_ctl_rotation(unsigned int rotation);
1151
1152 /* intel_csr.c */
1153 void intel_csr_ucode_init(struct drm_device *dev);
1154 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1155 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1156                                         enum csr_state state);
1157 void intel_csr_load_program(struct drm_device *dev);
1158 void intel_csr_ucode_fini(struct drm_device *dev);
1159 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1160
1161 /* intel_dp.c */
1162 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1163 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1164                              struct intel_connector *intel_connector);
1165 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1166 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1167 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1168 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1169 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1170 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1171 bool intel_dp_compute_config(struct intel_encoder *encoder,
1172                              struct intel_crtc_state *pipe_config);
1173 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1174 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1175                                   bool long_hpd);
1176 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1177 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1178 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1179 void intel_edp_panel_on(struct intel_dp *intel_dp);
1180 void intel_edp_panel_off(struct intel_dp *intel_dp);
1181 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1182 void intel_dp_mst_suspend(struct drm_device *dev);
1183 void intel_dp_mst_resume(struct drm_device *dev);
1184 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1185 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1186 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1187 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1188 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1189 void intel_plane_destroy(struct drm_plane *plane);
1190 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1191 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1192 void intel_edp_drrs_invalidate(struct drm_device *dev,
1193                 unsigned frontbuffer_bits);
1194 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1195
1196 /* intel_dp_mst.c */
1197 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1198 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1199 /* intel_dsi.c */
1200 void intel_dsi_init(struct drm_device *dev);
1201
1202
1203 /* intel_dvo.c */
1204 void intel_dvo_init(struct drm_device *dev);
1205
1206
1207 /* legacy fbdev emulation in intel_fbdev.c */
1208 #ifdef CONFIG_DRM_I915_FBDEV
1209 extern int intel_fbdev_init(struct drm_device *dev);
1210 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1211 extern void intel_fbdev_fini(struct drm_device *dev);
1212 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1213 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1214 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1215 #else
1216 static inline int intel_fbdev_init(struct drm_device *dev)
1217 {
1218         return 0;
1219 }
1220
1221 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1222 {
1223 }
1224
1225 static inline void intel_fbdev_fini(struct drm_device *dev)
1226 {
1227 }
1228
1229 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1230 {
1231 }
1232
1233 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1234 {
1235 }
1236 #endif
1237
1238 /* intel_fbc.c */
1239 bool intel_fbc_enabled(struct drm_device *dev);
1240 void intel_fbc_update(struct drm_device *dev);
1241 void intel_fbc_init(struct drm_i915_private *dev_priv);
1242 void intel_fbc_disable(struct drm_device *dev);
1243 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1244                           unsigned int frontbuffer_bits,
1245                           enum fb_op_origin origin);
1246 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1247                      unsigned int frontbuffer_bits);
1248
1249 /* intel_hdmi.c */
1250 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1251 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1252                                struct intel_connector *intel_connector);
1253 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1254 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1255                                struct intel_crtc_state *pipe_config);
1256
1257
1258 /* intel_lvds.c */
1259 void intel_lvds_init(struct drm_device *dev);
1260 bool intel_is_dual_link_lvds(struct drm_device *dev);
1261
1262
1263 /* intel_modes.c */
1264 int intel_connector_update_modes(struct drm_connector *connector,
1265                                  struct edid *edid);
1266 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1267 void intel_attach_force_audio_property(struct drm_connector *connector);
1268 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1269
1270
1271 /* intel_overlay.c */
1272 void intel_setup_overlay(struct drm_device *dev);
1273 void intel_cleanup_overlay(struct drm_device *dev);
1274 int intel_overlay_switch_off(struct intel_overlay *overlay);
1275 int intel_overlay_put_image(struct drm_device *dev, void *data,
1276                             struct drm_file *file_priv);
1277 int intel_overlay_attrs(struct drm_device *dev, void *data,
1278                         struct drm_file *file_priv);
1279 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1280
1281
1282 /* intel_panel.c */
1283 int intel_panel_init(struct intel_panel *panel,
1284                      struct drm_display_mode *fixed_mode,
1285                      struct drm_display_mode *downclock_mode);
1286 void intel_panel_fini(struct intel_panel *panel);
1287 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1288                             struct drm_display_mode *adjusted_mode);
1289 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1290                              struct intel_crtc_state *pipe_config,
1291                              int fitting_mode);
1292 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1293                               struct intel_crtc_state *pipe_config,
1294                               int fitting_mode);
1295 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1296                                     u32 level, u32 max);
1297 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1298 void intel_panel_enable_backlight(struct intel_connector *connector);
1299 void intel_panel_disable_backlight(struct intel_connector *connector);
1300 void intel_panel_destroy_backlight(struct drm_connector *connector);
1301 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1302 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1303 extern struct drm_display_mode *intel_find_panel_downclock(
1304                                 struct drm_device *dev,
1305                                 struct drm_display_mode *fixed_mode,
1306                                 struct drm_connector *connector);
1307 void intel_backlight_register(struct drm_device *dev);
1308 void intel_backlight_unregister(struct drm_device *dev);
1309
1310
1311 /* intel_psr.c */
1312 void intel_psr_enable(struct intel_dp *intel_dp);
1313 void intel_psr_disable(struct intel_dp *intel_dp);
1314 void intel_psr_invalidate(struct drm_device *dev,
1315                               unsigned frontbuffer_bits);
1316 void intel_psr_flush(struct drm_device *dev,
1317                          unsigned frontbuffer_bits);
1318 void intel_psr_init(struct drm_device *dev);
1319 void intel_psr_single_frame_update(struct drm_device *dev);
1320
1321 /* intel_runtime_pm.c */
1322 int intel_power_domains_init(struct drm_i915_private *);
1323 void intel_power_domains_fini(struct drm_i915_private *);
1324 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1325 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1326
1327 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1328                                     enum intel_display_power_domain domain);
1329 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1330                                       enum intel_display_power_domain domain);
1331 void intel_display_power_get(struct drm_i915_private *dev_priv,
1332                              enum intel_display_power_domain domain);
1333 void intel_display_power_put(struct drm_i915_private *dev_priv,
1334                              enum intel_display_power_domain domain);
1335 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1336 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1337 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1338 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1339 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1340
1341 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1342
1343 /* intel_pm.c */
1344 void intel_init_clock_gating(struct drm_device *dev);
1345 void intel_suspend_hw(struct drm_device *dev);
1346 int ilk_wm_max_level(const struct drm_device *dev);
1347 void intel_update_watermarks(struct drm_crtc *crtc);
1348 void intel_update_sprite_watermarks(struct drm_plane *plane,
1349                                     struct drm_crtc *crtc,
1350                                     uint32_t sprite_width,
1351                                     uint32_t sprite_height,
1352                                     int pixel_size,
1353                                     bool enabled, bool scaled);
1354 void intel_init_pm(struct drm_device *dev);
1355 void intel_pm_setup(struct drm_device *dev);
1356 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1357 void intel_gpu_ips_teardown(void);
1358 void intel_init_gt_powersave(struct drm_device *dev);
1359 void intel_cleanup_gt_powersave(struct drm_device *dev);
1360 void intel_enable_gt_powersave(struct drm_device *dev);
1361 void intel_disable_gt_powersave(struct drm_device *dev);
1362 void intel_suspend_gt_powersave(struct drm_device *dev);
1363 void intel_reset_gt_powersave(struct drm_device *dev);
1364 void gen6_update_ring_freq(struct drm_device *dev);
1365 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1366 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1367 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1368 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1369                     struct intel_rps_client *rps,
1370                     unsigned long submitted);
1371 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1372                                        struct drm_i915_gem_request *req);
1373 void ilk_wm_get_hw_state(struct drm_device *dev);
1374 void skl_wm_get_hw_state(struct drm_device *dev);
1375 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1376                           struct skl_ddb_allocation *ddb /* out */);
1377 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1378
1379 /* intel_sdvo.c */
1380 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1381
1382
1383 /* intel_sprite.c */
1384 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1385 int intel_plane_restore(struct drm_plane *plane);
1386 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1387                               struct drm_file *file_priv);
1388 bool intel_pipe_update_start(struct intel_crtc *crtc,
1389                              uint32_t *start_vbl_count);
1390 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1391
1392 /* intel_tv.c */
1393 void intel_tv_init(struct drm_device *dev);
1394
1395 /* intel_atomic.c */
1396 int intel_atomic_check(struct drm_device *dev,
1397                        struct drm_atomic_state *state);
1398 int intel_atomic_commit(struct drm_device *dev,
1399                         struct drm_atomic_state *state,
1400                         bool async);
1401 int intel_connector_atomic_get_property(struct drm_connector *connector,
1402                                         const struct drm_connector_state *state,
1403                                         struct drm_property *property,
1404                                         uint64_t *val);
1405 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1406 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1407                                struct drm_crtc_state *state);
1408 static inline struct intel_crtc_state *
1409 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1410                             struct intel_crtc *crtc)
1411 {
1412         struct drm_crtc_state *crtc_state;
1413         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1414         if (IS_ERR(crtc_state))
1415                 return ERR_CAST(crtc_state);
1416
1417         return to_intel_crtc_state(crtc_state);
1418 }
1419 int intel_atomic_setup_scalers(struct drm_device *dev,
1420         struct intel_crtc *intel_crtc,
1421         struct intel_crtc_state *crtc_state);
1422
1423 /* intel_atomic_plane.c */
1424 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1425 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1426 void intel_plane_destroy_state(struct drm_plane *plane,
1427                                struct drm_plane_state *state);
1428 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1429
1430 #endif /* __INTEL_DRV_H__ */