2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
39 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
40 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
43 * _wait_for - magic (register) wait macro
45 * Does the right thing for modeset paths when run under kdgb or similar atomic
46 * contexts. Note that it's important that we check the condition again after
47 * having timed out, since the timeout could be due to preemption or similar and
48 * we've never had a chance to check the condition before the timeout.
50 #define _wait_for(COND, MS, W) ({ \
51 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
54 if (time_after(jiffies, timeout__)) { \
59 if (W && drm_can_sleep()) { \
68 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
69 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
70 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
71 DIV_ROUND_UP((US), 1000), 0)
73 #define KHz(x) (1000 * (x))
74 #define MHz(x) KHz(1000 * (x))
77 * Display related stuff
80 /* store information about an Ixxx DVO */
81 /* The i830->i865 use multiple DVOs with multiple i2cs */
82 /* the i915, i945 have a single sDVO i2c bus - which is different */
84 /* maximum connectors per crtcs in the mode set */
86 /* Maximum cursor sizes */
87 #define GEN2_CURSOR_WIDTH 64
88 #define GEN2_CURSOR_HEIGHT 64
89 #define MAX_CURSOR_WIDTH 256
90 #define MAX_CURSOR_HEIGHT 256
92 #define INTEL_I2C_BUS_DVO 1
93 #define INTEL_I2C_BUS_SDVO 2
95 /* these are outputs from the chip - integrated only
96 external chips are via DVO or SDVO output */
97 enum intel_output_type
{
98 INTEL_OUTPUT_UNUSED
= 0,
99 INTEL_OUTPUT_ANALOG
= 1,
100 INTEL_OUTPUT_DVO
= 2,
101 INTEL_OUTPUT_SDVO
= 3,
102 INTEL_OUTPUT_LVDS
= 4,
103 INTEL_OUTPUT_TVOUT
= 5,
104 INTEL_OUTPUT_HDMI
= 6,
105 INTEL_OUTPUT_DISPLAYPORT
= 7,
106 INTEL_OUTPUT_EDP
= 8,
107 INTEL_OUTPUT_DSI
= 9,
108 INTEL_OUTPUT_UNKNOWN
= 10,
109 INTEL_OUTPUT_DP_MST
= 11,
112 #define INTEL_DVO_CHIP_NONE 0
113 #define INTEL_DVO_CHIP_LVDS 1
114 #define INTEL_DVO_CHIP_TMDS 2
115 #define INTEL_DVO_CHIP_TVOUT 4
117 #define INTEL_DSI_VIDEO_MODE 0
118 #define INTEL_DSI_COMMAND_MODE 1
120 struct intel_framebuffer
{
121 struct drm_framebuffer base
;
122 struct drm_i915_gem_object
*obj
;
126 struct drm_fb_helper helper
;
127 struct intel_framebuffer
*fb
;
128 struct list_head fbdev_list
;
129 struct drm_display_mode
*our_mode
;
133 struct intel_encoder
{
134 struct drm_encoder base
;
136 * The new crtc this encoder will be driven from. Only differs from
137 * base->crtc while a modeset is in progress.
139 struct intel_crtc
*new_crtc
;
141 enum intel_output_type type
;
142 unsigned int cloneable
;
143 bool connectors_active
;
144 void (*hot_plug
)(struct intel_encoder
*);
145 bool (*compute_config
)(struct intel_encoder
*,
146 struct intel_crtc_config
*);
147 void (*pre_pll_enable
)(struct intel_encoder
*);
148 void (*pre_enable
)(struct intel_encoder
*);
149 void (*enable
)(struct intel_encoder
*);
150 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
151 void (*disable
)(struct intel_encoder
*);
152 void (*post_disable
)(struct intel_encoder
*);
153 /* Read out the current hw state of this connector, returning true if
154 * the encoder is active. If the encoder is enabled it also set the pipe
155 * it is connected to in the pipe parameter. */
156 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
157 /* Reconstructs the equivalent mode flags for the current hardware
158 * state. This must be called _after_ display->get_pipe_config has
159 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
160 * be set correctly before calling this function. */
161 void (*get_config
)(struct intel_encoder
*,
162 struct intel_crtc_config
*pipe_config
);
164 * Called during system suspend after all pending requests for the
165 * encoder are flushed (for example for DP AUX transactions) and
166 * device interrupts are disabled.
168 void (*suspend
)(struct intel_encoder
*);
170 enum hpd_pin hpd_pin
;
174 struct drm_display_mode
*fixed_mode
;
175 struct drm_display_mode
*downclock_mode
;
185 bool combination_mode
; /* gen 2/4 only */
187 struct backlight_device
*device
;
190 void (*backlight_power
)(struct intel_connector
*, bool enable
);
193 struct intel_connector
{
194 struct drm_connector base
;
196 * The fixed encoder this connector is connected to.
198 struct intel_encoder
*encoder
;
201 * The new encoder this connector will be driven. Only differs from
202 * encoder while a modeset is in progress.
204 struct intel_encoder
*new_encoder
;
206 /* Reads out the current hw, returning true if the connector is enabled
207 * and active (i.e. dpms ON state). */
208 bool (*get_hw_state
)(struct intel_connector
*);
211 * Removes all interfaces through which the connector is accessible
212 * - like sysfs, debugfs entries -, so that no new operations can be
213 * started on the connector. Also makes sure all currently pending
214 * operations finish before returing.
216 void (*unregister
)(struct intel_connector
*);
218 /* Panel info for eDP and LVDS */
219 struct intel_panel panel
;
221 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
223 struct edid
*detect_edid
;
225 /* since POLL and HPD connectors may use the same HPD line keep the native
226 state of connector->polled in case hotplug storm detection changes it */
229 void *port
; /* store this opaque as its illegal to dereference it */
231 struct intel_dp
*mst_port
;
234 typedef struct dpll
{
246 struct intel_plane_state
{
247 struct drm_crtc
*crtc
;
248 struct drm_framebuffer
*fb
;
251 struct drm_rect clip
;
252 struct drm_rect orig_src
;
253 struct drm_rect orig_dst
;
257 struct intel_plane_config
{
263 struct intel_crtc_config
{
265 * quirks - bitfield with hw state readout quirks
267 * For various reasons the hw state readout code might not be able to
268 * completely faithfully read out the current state. These cases are
269 * tracked with quirk flags so that fastboot and state checker can act
272 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
273 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
274 unsigned long quirks
;
276 /* User requested mode, only valid as a starting point to
277 * compute adjusted_mode, except in the case of (S)DVO where
278 * it's also for the output timings of the (S)DVO chip.
279 * adjusted_mode will then correspond to the S(DVO) chip's
280 * preferred input timings. */
281 struct drm_display_mode requested_mode
;
282 /* Actual pipe timings ie. what we program into the pipe timing
283 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
284 struct drm_display_mode adjusted_mode
;
286 /* Pipe source size (ie. panel fitter input size)
287 * All planes will be positioned inside this space,
288 * and get clipped at the edges. */
289 int pipe_src_w
, pipe_src_h
;
291 /* Whether to set up the PCH/FDI. Note that we never allow sharing
292 * between pch encoders and cpu encoders. */
293 bool has_pch_encoder
;
295 /* CPU Transcoder for the pipe. Currently this can only differ from the
296 * pipe on Haswell (where we have a special eDP transcoder). */
297 enum transcoder cpu_transcoder
;
300 * Use reduced/limited/broadcast rbg range, compressing from the full
301 * range fed into the crtcs.
303 bool limited_color_range
;
305 /* DP has a bunch of special case unfortunately, so mark the pipe
309 /* Whether we should send NULL infoframes. Required for audio. */
312 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
313 * has_dp_encoder is set. */
317 * Enable dithering, used when the selected pipe bpp doesn't match the
322 /* Controls for the clock computation, to override various stages. */
325 /* SDVO TV has a bunch of special case. To make multifunction encoders
326 * work correctly, we need to track this at runtime.*/
330 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
331 * required. This is set in the 2nd loop of calling encoder's
332 * ->compute_config if the first pick doesn't work out.
336 /* Settings for the intel dpll used on pretty much everything but
340 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
341 enum intel_dpll_id shared_dpll
;
343 /* PORT_CLK_SEL for DDI ports. */
344 uint32_t ddi_pll_sel
;
346 /* Actual register state of the dpll, for shared dpll cross-checking. */
347 struct intel_dpll_hw_state dpll_hw_state
;
350 struct intel_link_m_n dp_m_n
;
352 /* m2_n2 for eDP downclock */
353 struct intel_link_m_n dp_m2_n2
;
357 * Frequence the dpll for the port should run at. Differs from the
358 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
359 * already multiplied by pixel_multiplier.
363 /* Used by SDVO (and if we ever fix it, HDMI). */
364 unsigned pixel_multiplier
;
366 /* Panel fitter controls for gen2-gen4 + VLV */
370 u32 lvds_border_bits
;
373 /* Panel fitter placement and size for Ironlake+ */
381 /* FDI configuration, only valid if has_pch_encoder is set. */
383 struct intel_link_m_n fdi_m_n
;
389 bool dp_encoder_is_mst
;
393 struct intel_pipe_wm
{
394 struct intel_wm_level wm
[5];
398 bool sprites_enabled
;
402 struct intel_mmio_flip
{
408 struct drm_crtc base
;
411 u8 lut_r
[256], lut_g
[256], lut_b
[256];
413 * Whether the crtc and the connected output pipeline is active. Implies
414 * that crtc->enabled is set, i.e. the current mode configuration has
415 * some outputs connected to this crtc.
418 unsigned long enabled_power_domains
;
419 bool primary_enabled
; /* is the primary plane (partially) visible? */
421 struct intel_overlay
*overlay
;
422 struct intel_unpin_work
*unpin_work
;
424 atomic_t unpin_work_count
;
426 /* Display surface base address adjustement for pageflips. Note that on
427 * gen4+ this only adjusts up to a tile, offsets within a tile are
428 * handled in the hw itself (with the TILEOFF register). */
429 unsigned long dspaddr_offset
;
431 struct drm_i915_gem_object
*cursor_bo
;
432 uint32_t cursor_addr
;
433 int16_t cursor_width
, cursor_height
;
434 uint32_t cursor_cntl
;
435 uint32_t cursor_size
;
436 uint32_t cursor_base
;
438 struct intel_plane_config plane_config
;
439 struct intel_crtc_config config
;
440 struct intel_crtc_config
*new_config
;
443 /* reset counter value when the last flip was submitted */
444 unsigned int reset_counter
;
446 /* Access to these should be protected by dev_priv->irq_lock. */
447 bool cpu_fifo_underrun_disabled
;
448 bool pch_fifo_underrun_disabled
;
450 /* per-pipe watermark state */
452 /* watermarks currently being used */
453 struct intel_pipe_wm active
;
457 struct intel_mmio_flip mmio_flip
;
460 struct intel_plane_wm_parameters
{
461 uint32_t horiz_pixels
;
462 uint32_t vert_pixels
;
463 uint8_t bytes_per_pixel
;
469 struct drm_plane base
;
472 struct drm_i915_gem_object
*obj
;
476 unsigned int crtc_w
, crtc_h
;
477 uint32_t src_x
, src_y
;
478 uint32_t src_w
, src_h
;
479 unsigned int rotation
;
481 /* Since we need to change the watermarks before/after
482 * enabling/disabling the planes, we need to store the parameters here
483 * as the other pieces of the struct may not reflect the values we want
484 * for the watermark calculations. Currently only Haswell uses this.
486 struct intel_plane_wm_parameters wm
;
488 void (*update_plane
)(struct drm_plane
*plane
,
489 struct drm_crtc
*crtc
,
490 struct drm_framebuffer
*fb
,
491 struct drm_i915_gem_object
*obj
,
492 int crtc_x
, int crtc_y
,
493 unsigned int crtc_w
, unsigned int crtc_h
,
494 uint32_t x
, uint32_t y
,
495 uint32_t src_w
, uint32_t src_h
);
496 void (*disable_plane
)(struct drm_plane
*plane
,
497 struct drm_crtc
*crtc
);
498 int (*update_colorkey
)(struct drm_plane
*plane
,
499 struct drm_intel_sprite_colorkey
*key
);
500 void (*get_colorkey
)(struct drm_plane
*plane
,
501 struct drm_intel_sprite_colorkey
*key
);
504 struct intel_watermark_params
{
505 unsigned long fifo_size
;
506 unsigned long max_wm
;
507 unsigned long default_wm
;
508 unsigned long guard_size
;
509 unsigned long cacheline_size
;
512 struct cxsr_latency
{
515 unsigned long fsb_freq
;
516 unsigned long mem_freq
;
517 unsigned long display_sr
;
518 unsigned long display_hpll_disable
;
519 unsigned long cursor_sr
;
520 unsigned long cursor_hpll_disable
;
523 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
524 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
525 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
526 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
527 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
528 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
533 uint32_t color_range
;
534 bool color_range_auto
;
537 enum hdmi_force_audio force_audio
;
538 bool rgb_quant_range_selectable
;
539 enum hdmi_picture_aspect aspect_ratio
;
540 void (*write_infoframe
)(struct drm_encoder
*encoder
,
541 enum hdmi_infoframe_type type
,
542 const void *frame
, ssize_t len
);
543 void (*set_infoframes
)(struct drm_encoder
*encoder
,
545 struct drm_display_mode
*adjusted_mode
);
548 struct intel_dp_mst_encoder
;
549 #define DP_MAX_DOWNSTREAM_PORTS 0x10
552 * HIGH_RR is the highest eDP panel refresh rate read from EDID
553 * LOW_RR is the lowest eDP panel refresh rate found from EDID
554 * parsing for same resolution.
556 enum edp_drrs_refresh_rate_type
{
559 DRRS_MAX_RR
, /* RR count */
564 uint32_t aux_ch_ctl_reg
;
567 enum hdmi_force_audio force_audio
;
568 uint32_t color_range
;
569 bool color_range_auto
;
572 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
573 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
574 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
575 struct drm_dp_aux aux
;
576 uint8_t train_set
[4];
577 int panel_power_up_delay
;
578 int panel_power_down_delay
;
579 int panel_power_cycle_delay
;
580 int backlight_on_delay
;
581 int backlight_off_delay
;
582 struct delayed_work panel_vdd_work
;
584 unsigned long last_power_cycle
;
585 unsigned long last_power_on
;
586 unsigned long last_backlight_off
;
588 struct notifier_block edp_notifier
;
591 * Pipe whose power sequencer is currently locked into
592 * this port. Only relevant on VLV/CHV.
597 bool can_mst
; /* this port supports mst */
599 int active_mst_links
;
600 /* connector directly attached - won't be use for modeset in mst world */
601 struct intel_connector
*attached_connector
;
603 /* mst connector list */
604 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
605 struct drm_dp_mst_topology_mgr mst_mgr
;
607 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
609 * This function returns the value we have to program the AUX_CTL
610 * register with to kick off an AUX transaction.
612 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
615 uint32_t aux_clock_divider
);
617 enum drrs_support_type type
;
618 enum edp_drrs_refresh_rate_type refresh_rate_type
;
624 struct intel_digital_port
{
625 struct intel_encoder base
;
629 struct intel_hdmi hdmi
;
630 bool (*hpd_pulse
)(struct intel_digital_port
*, bool);
633 struct intel_dp_mst_encoder
{
634 struct intel_encoder base
;
636 struct intel_digital_port
*primary
;
637 void *port
; /* store this opaque as its illegal to dereference it */
641 vlv_dport_to_channel(struct intel_digital_port
*dport
)
643 switch (dport
->port
) {
655 vlv_pipe_to_channel(enum pipe pipe
)
668 static inline struct drm_crtc
*
669 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
672 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
675 static inline struct drm_crtc
*
676 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
679 return dev_priv
->plane_to_crtc_mapping
[plane
];
682 struct intel_unpin_work
{
683 struct work_struct work
;
684 struct drm_crtc
*crtc
;
685 struct drm_i915_gem_object
*old_fb_obj
;
686 struct drm_i915_gem_object
*pending_flip_obj
;
687 struct drm_pending_vblank_event
*event
;
689 #define INTEL_FLIP_INACTIVE 0
690 #define INTEL_FLIP_PENDING 1
691 #define INTEL_FLIP_COMPLETE 2
694 struct intel_engine_cs
*flip_queued_ring
;
695 u32 flip_queued_seqno
;
696 int flip_queued_vblank
;
697 int flip_ready_vblank
;
698 bool enable_stall_check
;
701 struct intel_set_config
{
702 struct drm_encoder
**save_connector_encoders
;
703 struct drm_crtc
**save_encoder_crtcs
;
704 bool *save_crtc_enabled
;
710 struct intel_load_detect_pipe
{
711 struct drm_framebuffer
*release_fb
;
712 bool load_detect_temp
;
716 static inline struct intel_encoder
*
717 intel_attached_encoder(struct drm_connector
*connector
)
719 return to_intel_connector(connector
)->encoder
;
722 static inline struct intel_digital_port
*
723 enc_to_dig_port(struct drm_encoder
*encoder
)
725 return container_of(encoder
, struct intel_digital_port
, base
.base
);
728 static inline struct intel_dp_mst_encoder
*
729 enc_to_mst(struct drm_encoder
*encoder
)
731 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
734 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
736 return &enc_to_dig_port(encoder
)->dp
;
739 static inline struct intel_digital_port
*
740 dp_to_dig_port(struct intel_dp
*intel_dp
)
742 return container_of(intel_dp
, struct intel_digital_port
, dp
);
745 static inline struct intel_digital_port
*
746 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
748 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
752 * Returns the number of planes for this pipe, ie the number of sprites + 1
753 * (primary plane). This doesn't count the cursor plane then.
755 static inline unsigned int intel_num_planes(struct intel_crtc
*crtc
)
757 return INTEL_INFO(crtc
->base
.dev
)->num_sprites
[crtc
->pipe
] + 1;
760 /* intel_fifo_underrun.c */
761 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
762 enum pipe pipe
, bool enable
);
763 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
764 enum transcoder pch_transcoder
,
766 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
768 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
769 enum transcoder pch_transcoder
);
770 void i9xx_check_fifo_underruns(struct drm_i915_private
*dev_priv
);
773 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
774 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
775 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
776 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
777 void gen8_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
778 void gen8_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
779 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
780 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
781 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
784 * We only use drm_irq_uninstall() at unload and VT switch, so
785 * this is the only thing we need to check.
787 return dev_priv
->pm
.irqs_enabled
;
790 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
791 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
);
794 void intel_crt_init(struct drm_device
*dev
);
798 void intel_prepare_ddi(struct drm_device
*dev
);
799 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
800 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
801 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
802 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
803 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
);
804 void intel_ddi_pll_init(struct drm_device
*dev
);
805 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
806 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
807 enum transcoder cpu_transcoder
);
808 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
809 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
810 bool intel_ddi_pll_select(struct intel_crtc
*crtc
);
811 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
812 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
);
813 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
814 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
815 void intel_ddi_get_config(struct intel_encoder
*encoder
,
816 struct intel_crtc_config
*pipe_config
);
818 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
819 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
820 struct intel_crtc_config
*pipe_config
);
821 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
823 /* intel_frontbuffer.c */
824 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
825 struct intel_engine_cs
*ring
);
826 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
827 unsigned frontbuffer_bits
);
828 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
829 unsigned frontbuffer_bits
);
830 void intel_frontbuffer_flush(struct drm_device
*dev
,
831 unsigned frontbuffer_bits
);
833 * intel_frontbuffer_flip - synchronous frontbuffer flip
835 * @frontbuffer_bits: frontbuffer plane tracking bits
837 * This function gets called after scheduling a flip on @obj. This is for
838 * synchronous plane updates which will happen on the next vblank and which will
839 * not get delayed by pending gpu rendering.
841 * Can be called without any locks held.
844 void intel_frontbuffer_flip(struct drm_device
*dev
,
845 unsigned frontbuffer_bits
)
847 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
850 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
, bool retire
);
854 void intel_init_audio(struct drm_device
*dev
);
855 void intel_write_eld(struct intel_encoder
*encoder
);
857 /* intel_display.c */
858 const char *intel_output_name(int output
);
859 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
860 int intel_pch_rawclk(struct drm_device
*dev
);
861 void intel_mark_busy(struct drm_device
*dev
);
862 void intel_mark_idle(struct drm_device
*dev
);
863 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
864 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
);
865 void intel_crtc_update_dpms(struct drm_crtc
*crtc
);
866 void intel_encoder_destroy(struct drm_encoder
*encoder
);
867 void intel_connector_dpms(struct drm_connector
*, int mode
);
868 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
869 void intel_modeset_check_state(struct drm_device
*dev
);
870 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
871 struct intel_digital_port
*port
);
872 void intel_connector_attach_encoder(struct intel_connector
*connector
,
873 struct intel_encoder
*encoder
);
874 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
875 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
876 struct drm_crtc
*crtc
);
877 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
878 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
879 struct drm_file
*file_priv
);
880 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
882 bool intel_pipe_has_type(struct intel_crtc
*crtc
, int type
);
884 intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
886 drm_wait_one_vblank(dev
, pipe
);
888 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
889 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
890 struct intel_digital_port
*dport
);
891 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
892 struct drm_display_mode
*mode
,
893 struct intel_load_detect_pipe
*old
,
894 struct drm_modeset_acquire_ctx
*ctx
);
895 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
896 struct intel_load_detect_pipe
*old
);
897 int intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
898 struct drm_i915_gem_object
*obj
,
899 struct intel_engine_cs
*pipelined
);
900 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
);
901 struct drm_framebuffer
*
902 __intel_framebuffer_create(struct drm_device
*dev
,
903 struct drm_mode_fb_cmd2
*mode_cmd
,
904 struct drm_i915_gem_object
*obj
);
905 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
906 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
907 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
908 void intel_check_page_flip(struct drm_device
*dev
, int pipe
);
910 /* shared dpll functions */
911 struct intel_shared_dpll
*intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
);
912 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
913 struct intel_shared_dpll
*pll
,
915 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
916 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
917 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
);
918 void intel_put_shared_dpll(struct intel_crtc
*crtc
);
920 /* modesetting asserts */
921 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
923 void assert_pll(struct drm_i915_private
*dev_priv
,
924 enum pipe pipe
, bool state
);
925 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
926 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
927 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
928 enum pipe pipe
, bool state
);
929 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
930 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
931 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
932 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
933 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
934 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
935 unsigned int tiling_mode
,
938 void intel_display_handle_reset(struct drm_device
*dev
);
939 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
940 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
941 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
942 struct intel_crtc_config
*pipe_config
);
943 void intel_dp_set_m_n(struct intel_crtc
*crtc
);
944 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
946 ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
948 bool intel_crtc_active(struct drm_crtc
*crtc
);
949 void hsw_enable_ips(struct intel_crtc
*crtc
);
950 void hsw_disable_ips(struct intel_crtc
*crtc
);
951 enum intel_display_power_domain
952 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
953 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
954 struct intel_crtc_config
*pipe_config
);
955 int intel_format_to_fourcc(int format
);
956 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
);
957 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
);
960 void intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
);
961 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
962 struct intel_connector
*intel_connector
);
963 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
964 void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
965 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
966 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
967 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
968 void intel_dp_check_link_status(struct intel_dp
*intel_dp
);
969 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
970 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
971 struct intel_crtc_config
*pipe_config
);
972 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
973 bool intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
975 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
976 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
977 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
978 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
);
979 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
980 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
981 void intel_edp_psr_enable(struct intel_dp
*intel_dp
);
982 void intel_edp_psr_disable(struct intel_dp
*intel_dp
);
983 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
);
984 void intel_edp_psr_invalidate(struct drm_device
*dev
,
985 unsigned frontbuffer_bits
);
986 void intel_edp_psr_flush(struct drm_device
*dev
,
987 unsigned frontbuffer_bits
);
988 void intel_edp_psr_init(struct drm_device
*dev
);
990 int intel_dp_handle_hpd_irq(struct intel_digital_port
*digport
, bool long_hpd
);
991 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
992 void intel_dp_mst_suspend(struct drm_device
*dev
);
993 void intel_dp_mst_resume(struct drm_device
*dev
);
994 int intel_dp_max_link_bw(struct intel_dp
*intel_dp
);
995 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
996 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
998 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
999 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1001 void intel_dsi_init(struct drm_device
*dev
);
1005 void intel_dvo_init(struct drm_device
*dev
);
1008 /* legacy fbdev emulation in intel_fbdev.c */
1009 #ifdef CONFIG_DRM_I915_FBDEV
1010 extern int intel_fbdev_init(struct drm_device
*dev
);
1011 extern void intel_fbdev_initial_config(void *data
, async_cookie_t cookie
);
1012 extern void intel_fbdev_fini(struct drm_device
*dev
);
1013 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1014 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1015 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1017 static inline int intel_fbdev_init(struct drm_device
*dev
)
1022 static inline void intel_fbdev_initial_config(void *data
, async_cookie_t cookie
)
1026 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1030 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1034 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1040 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
);
1041 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1042 struct intel_connector
*intel_connector
);
1043 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1044 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1045 struct intel_crtc_config
*pipe_config
);
1049 void intel_lvds_init(struct drm_device
*dev
);
1050 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1054 int intel_connector_update_modes(struct drm_connector
*connector
,
1056 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1057 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1058 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1061 /* intel_overlay.c */
1062 void intel_setup_overlay(struct drm_device
*dev
);
1063 void intel_cleanup_overlay(struct drm_device
*dev
);
1064 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1065 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1066 struct drm_file
*file_priv
);
1067 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1068 struct drm_file
*file_priv
);
1072 int intel_panel_init(struct intel_panel
*panel
,
1073 struct drm_display_mode
*fixed_mode
,
1074 struct drm_display_mode
*downclock_mode
);
1075 void intel_panel_fini(struct intel_panel
*panel
);
1076 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1077 struct drm_display_mode
*adjusted_mode
);
1078 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1079 struct intel_crtc_config
*pipe_config
,
1081 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1082 struct intel_crtc_config
*pipe_config
,
1084 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1085 u32 level
, u32 max
);
1086 int intel_panel_setup_backlight(struct drm_connector
*connector
);
1087 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1088 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1089 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1090 void intel_panel_init_backlight_funcs(struct drm_device
*dev
);
1091 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1092 extern struct drm_display_mode
*intel_find_panel_downclock(
1093 struct drm_device
*dev
,
1094 struct drm_display_mode
*fixed_mode
,
1095 struct drm_connector
*connector
);
1097 /* intel_runtime_pm.c */
1098 int intel_power_domains_init(struct drm_i915_private
*);
1099 void intel_power_domains_fini(struct drm_i915_private
*);
1100 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
);
1101 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1103 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1104 enum intel_display_power_domain domain
);
1105 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1106 enum intel_display_power_domain domain
);
1107 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1108 enum intel_display_power_domain domain
);
1109 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1110 enum intel_display_power_domain domain
);
1111 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
);
1112 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
);
1113 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1114 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1115 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1117 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1120 void intel_init_clock_gating(struct drm_device
*dev
);
1121 void intel_suspend_hw(struct drm_device
*dev
);
1122 int ilk_wm_max_level(const struct drm_device
*dev
);
1123 void intel_update_watermarks(struct drm_crtc
*crtc
);
1124 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
1125 struct drm_crtc
*crtc
,
1126 uint32_t sprite_width
,
1127 uint32_t sprite_height
,
1129 bool enabled
, bool scaled
);
1130 void intel_init_pm(struct drm_device
*dev
);
1131 void intel_pm_setup(struct drm_device
*dev
);
1132 bool intel_fbc_enabled(struct drm_device
*dev
);
1133 void intel_update_fbc(struct drm_device
*dev
);
1134 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1135 void intel_gpu_ips_teardown(void);
1136 void intel_init_gt_powersave(struct drm_device
*dev
);
1137 void intel_cleanup_gt_powersave(struct drm_device
*dev
);
1138 void intel_enable_gt_powersave(struct drm_device
*dev
);
1139 void intel_disable_gt_powersave(struct drm_device
*dev
);
1140 void intel_suspend_gt_powersave(struct drm_device
*dev
);
1141 void intel_reset_gt_powersave(struct drm_device
*dev
);
1142 void ironlake_teardown_rc6(struct drm_device
*dev
);
1143 void gen6_update_ring_freq(struct drm_device
*dev
);
1144 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1145 void gen6_rps_boost(struct drm_i915_private
*dev_priv
);
1146 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1150 bool intel_sdvo_init(struct drm_device
*dev
, uint32_t sdvo_reg
, bool is_sdvob
);
1153 /* intel_sprite.c */
1154 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
1155 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
1157 int intel_plane_set_property(struct drm_plane
*plane
,
1158 struct drm_property
*prop
,
1160 int intel_plane_restore(struct drm_plane
*plane
);
1161 void intel_plane_disable(struct drm_plane
*plane
);
1162 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1163 struct drm_file
*file_priv
);
1164 int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
1165 struct drm_file
*file_priv
);
1169 void intel_tv_init(struct drm_device
*dev
);
1171 #endif /* __INTEL_DRV_H__ */