drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37
  38 /**
  39  * _wait_for - magic (register) wait macro
  40  *
  41  * Does the right thing for modeset paths when run under kdgb or similar atomic
  42  * contexts. Note that it's important that we check the condition again after
  43  * having timed out, since the timeout could be due to preemption or similar and
  44  * we've never had a chance to check the condition before the timeout.
  45  */
  46 #define _wait_for(COND, MS, W) ({ \
  47         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  48         int ret__ = 0;                                                  \
  49         while (!(COND)) {                                               \
  50                 if (time_after(jiffies, timeout__)) {                   \
  51                         if (!(COND))                                    \
  52                                 ret__ = -ETIMEDOUT;                     \
  53                         break;                                          \
  54                 }                                                       \
  55                 if (W && drm_can_sleep())  {                            \
  56                         msleep(W);                                      \
  57                 } else {                                                \
  58                         cpu_relax();                                    \
  59                 }                                                       \
  60         }                                                               \
  61         ret__;                                                          \
  62 })
  63
  64 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  65 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  66 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  67                                                DIV_ROUND_UP((US), 1000), 0)
  68
  69 #define KHz(x) (1000 * (x))
  70 #define MHz(x) KHz(1000 * (x))
  71
  72 /*
  73  * Display related stuff
  74  */
  75
  76 /* store information about an Ixxx DVO */
  77 /* The i830->i865 use multiple DVOs with multiple i2cs */
  78 /* the i915, i945 have a single sDVO i2c bus - which is different */
  79 #define MAX_OUTPUTS 6
  80 /* maximum connectors per crtcs in the mode set */
  81
  82 /* Maximum cursor sizes */
  83 #define GEN2_CURSOR_WIDTH 64
  84 #define GEN2_CURSOR_HEIGHT 64
  85 #define MAX_CURSOR_WIDTH 256
  86 #define MAX_CURSOR_HEIGHT 256
  87
  88 #define INTEL_I2C_BUS_DVO 1
  89 #define INTEL_I2C_BUS_SDVO 2
  90
  91 /* these are outputs from the chip - integrated only
  92    external chips are via DVO or SDVO output */
  93 #define INTEL_OUTPUT_UNUSED 0
  94 #define INTEL_OUTPUT_ANALOG 1
  95 #define INTEL_OUTPUT_DVO 2
  96 #define INTEL_OUTPUT_SDVO 3
  97 #define INTEL_OUTPUT_LVDS 4
  98 #define INTEL_OUTPUT_TVOUT 5
  99 #define INTEL_OUTPUT_HDMI 6
 100 #define INTEL_OUTPUT_DISPLAYPORT 7
 101 #define INTEL_OUTPUT_EDP 8
 102 #define INTEL_OUTPUT_DSI 9
 103 #define INTEL_OUTPUT_UNKNOWN 10
 104 #define INTEL_OUTPUT_DP_MST 11
 105
 106 #define INTEL_DVO_CHIP_NONE 0
 107 #define INTEL_DVO_CHIP_LVDS 1
 108 #define INTEL_DVO_CHIP_TMDS 2
 109 #define INTEL_DVO_CHIP_TVOUT 4
 110
 111 #define INTEL_DSI_VIDEO_MODE    0
 112 #define INTEL_DSI_COMMAND_MODE  1
 113
 114 struct intel_framebuffer {
 115         struct drm_framebuffer base;
 116         struct drm_i915_gem_object *obj;
 117 };
 118
 119 struct intel_fbdev {
 120         struct drm_fb_helper helper;
 121         struct intel_framebuffer *fb;
 122         struct list_head fbdev_list;
 123         struct drm_display_mode *our_mode;
 124         int preferred_bpp;
 125 };
 126
 127 struct intel_encoder {
 128         struct drm_encoder base;
 129         /*
 130          * The new crtc this encoder will be driven from. Only differs from
 131          * base->crtc while a modeset is in progress.
 132          */
 133         struct intel_crtc *new_crtc;
 134
 135         int type;
 136         unsigned int cloneable;
 137         bool connectors_active;
 138         void (*hot_plug)(struct intel_encoder *);
 139         bool (*compute_config)(struct intel_encoder *,
 140                                struct intel_crtc_config *);
 141         void (*pre_pll_enable)(struct intel_encoder *);
 142         void (*pre_enable)(struct intel_encoder *);
 143         void (*enable)(struct intel_encoder *);
 144         void (*mode_set)(struct intel_encoder *intel_encoder);
 145         void (*disable)(struct intel_encoder *);
 146         void (*post_disable)(struct intel_encoder *);
 147         /* Read out the current hw state of this connector, returning true if
 148          * the encoder is active. If the encoder is enabled it also set the pipe
 149          * it is connected to in the pipe parameter. */
 150         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 151         /* Reconstructs the equivalent mode flags for the current hardware
 152          * state. This must be called _after_ display->get_pipe_config has
 153          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 154          * be set correctly before calling this function. */
 155         void (*get_config)(struct intel_encoder *,
 156                            struct intel_crtc_config *pipe_config);
 157         /*
 158          * Called during system suspend after all pending requests for the
 159          * encoder are flushed (for example for DP AUX transactions) and
 160          * device interrupts are disabled.
 161          */
 162         void (*suspend)(struct intel_encoder *);
 163         int crtc_mask;
 164         enum hpd_pin hpd_pin;
 165 };
 166
 167 struct intel_panel {
 168         struct drm_display_mode *fixed_mode;
 169         struct drm_display_mode *downclock_mode;
 170         int fitting_mode;
 171
 172         /* backlight */
 173         struct {
 174                 bool present;
 175                 u32 level;
 176                 u32 min;
 177                 u32 max;
 178                 bool enabled;
 179                 bool combination_mode;  /* gen 2/4 only */
 180                 bool active_low_pwm;
 181                 struct backlight_device *device;
 182         } backlight;
 183
 184         void (*backlight_power)(struct intel_connector *, bool enable);
 185 };
 186
 187 struct intel_connector {
 188         struct drm_connector base;
 189         /*
 190          * The fixed encoder this connector is connected to.
 191          */
 192         struct intel_encoder *encoder;
 193
 194         /*
 195          * The new encoder this connector will be driven. Only differs from
 196          * encoder while a modeset is in progress.
 197          */
 198         struct intel_encoder *new_encoder;
 199
 200         /* Reads out the current hw, returning true if the connector is enabled
 201          * and active (i.e. dpms ON state). */
 202         bool (*get_hw_state)(struct intel_connector *);
 203
 204         /*
 205          * Removes all interfaces through which the connector is accessible
 206          * - like sysfs, debugfs entries -, so that no new operations can be
 207          * started on the connector. Also makes sure all currently pending
 208          * operations finish before returing.
 209          */
 210         void (*unregister)(struct intel_connector *);
 211
 212         /* Panel info for eDP and LVDS */
 213         struct intel_panel panel;
 214
 215         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 216         struct edid *edid;
 217         struct edid *detect_edid;
 218
 219         /* since POLL and HPD connectors may use the same HPD line keep the native
 220            state of connector->polled in case hotplug storm detection changes it */
 221         u8 polled;
 222
 223         void *port; /* store this opaque as its illegal to dereference it */
 224
 225         struct intel_dp *mst_port;
 226 };
 227
 228 typedef struct dpll {
 229         /* given values */
 230         int n;
 231         int m1, m2;
 232         int p1, p2;
 233         /* derived values */
 234         int     dot;
 235         int     vco;
 236         int     m;
 237         int     p;
 238 } intel_clock_t;
 239
 240 struct intel_plane_config {
 241         bool tiled;
 242         int size;
 243         u32 base;
 244 };
 245
 246 struct intel_crtc_config {
 247         /**
 248          * quirks - bitfield with hw state readout quirks
 249          *
 250          * For various reasons the hw state readout code might not be able to
 251          * completely faithfully read out the current state. These cases are
 252          * tracked with quirk flags so that fastboot and state checker can act
 253          * accordingly.
 254          */
 255 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 256 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 257         unsigned long quirks;
 258
 259         /* User requested mode, only valid as a starting point to
 260          * compute adjusted_mode, except in the case of (S)DVO where
 261          * it's also for the output timings of the (S)DVO chip.
 262          * adjusted_mode will then correspond to the S(DVO) chip's
 263          * preferred input timings. */
 264         struct drm_display_mode requested_mode;
 265         /* Actual pipe timings ie. what we program into the pipe timing
 266          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 267         struct drm_display_mode adjusted_mode;
 268
 269         /* Pipe source size (ie. panel fitter input size)
 270          * All planes will be positioned inside this space,
 271          * and get clipped at the edges. */
 272         int pipe_src_w, pipe_src_h;
 273
 274         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 275          * between pch encoders and cpu encoders. */
 276         bool has_pch_encoder;
 277
 278         /* CPU Transcoder for the pipe. Currently this can only differ from the
 279          * pipe on Haswell (where we have a special eDP transcoder). */
 280         enum transcoder cpu_transcoder;
 281
 282         /*
 283          * Use reduced/limited/broadcast rbg range, compressing from the full
 284          * range fed into the crtcs.
 285          */
 286         bool limited_color_range;
 287
 288         /* DP has a bunch of special case unfortunately, so mark the pipe
 289          * accordingly. */
 290         bool has_dp_encoder;
 291
 292         /* Whether we should send NULL infoframes. Required for audio. */
 293         bool has_hdmi_sink;
 294
 295         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 296          * has_dp_encoder is set. */
 297         bool has_audio;
 298
 299         /*
 300          * Enable dithering, used when the selected pipe bpp doesn't match the
 301          * plane bpp.
 302          */
 303         bool dither;
 304
 305         /* Controls for the clock computation, to override various stages. */
 306         bool clock_set;
 307
 308         /* SDVO TV has a bunch of special case. To make multifunction encoders
 309          * work correctly, we need to track this at runtime.*/
 310         bool sdvo_tv_clock;
 311
 312         /*
 313          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 314          * required. This is set in the 2nd loop of calling encoder's
 315          * ->compute_config if the first pick doesn't work out.
 316          */
 317         bool bw_constrained;
 318
 319         /* Settings for the intel dpll used on pretty much everything but
 320          * haswell. */
 321         struct dpll dpll;
 322
 323         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 324         enum intel_dpll_id shared_dpll;
 325
 326         /* PORT_CLK_SEL for DDI ports. */
 327         uint32_t ddi_pll_sel;
 328
 329         /* Actual register state of the dpll, for shared dpll cross-checking. */
 330         struct intel_dpll_hw_state dpll_hw_state;
 331
 332         int pipe_bpp;
 333         struct intel_link_m_n dp_m_n;
 334
 335         /* m2_n2 for eDP downclock */
 336         struct intel_link_m_n dp_m2_n2;
 337         bool has_drrs;
 338
 339         /*
 340          * Frequence the dpll for the port should run at. Differs from the
 341          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 342          * already multiplied by pixel_multiplier.
 343          */
 344         int port_clock;
 345
 346         /* Used by SDVO (and if we ever fix it, HDMI). */
 347         unsigned pixel_multiplier;
 348
 349         /* Panel fitter controls for gen2-gen4 + VLV */
 350         struct {
 351                 u32 control;
 352                 u32 pgm_ratios;
 353                 u32 lvds_border_bits;
 354         } gmch_pfit;
 355
 356         /* Panel fitter placement and size for Ironlake+ */
 357         struct {
 358                 u32 pos;
 359                 u32 size;
 360                 bool enabled;
 361                 bool force_thru;
 362         } pch_pfit;
 363
 364         /* FDI configuration, only valid if has_pch_encoder is set. */
 365         int fdi_lanes;
 366         struct intel_link_m_n fdi_m_n;
 367
 368         bool ips_enabled;
 369
 370         bool double_wide;
 371
 372         bool dp_encoder_is_mst;
 373         int pbn;
 374 };
 375
 376 struct intel_pipe_wm {
 377         struct intel_wm_level wm[5];
 378         uint32_t linetime;
 379         bool fbc_wm_enabled;
 380         bool pipe_enabled;
 381         bool sprites_enabled;
 382         bool sprites_scaled;
 383 };
 384
 385 struct intel_mmio_flip {
 386         u32 seqno;
 387         u32 ring_id;
 388 };
 389
 390 struct intel_crtc {
 391         struct drm_crtc base;
 392         enum pipe pipe;
 393         enum plane plane;
 394         u8 lut_r[256], lut_g[256], lut_b[256];
 395         /*
 396          * Whether the crtc and the connected output pipeline is active. Implies
 397          * that crtc->enabled is set, i.e. the current mode configuration has
 398          * some outputs connected to this crtc.
 399          */
 400         bool active;
 401         unsigned long enabled_power_domains;
 402         bool primary_enabled; /* is the primary plane (partially) visible? */
 403         bool lowfreq_avail;
 404         struct intel_overlay *overlay;
 405         struct intel_unpin_work *unpin_work;
 406
 407         atomic_t unpin_work_count;
 408
 409         /* Display surface base address adjustement for pageflips. Note that on
 410          * gen4+ this only adjusts up to a tile, offsets within a tile are
 411          * handled in the hw itself (with the TILEOFF register). */
 412         unsigned long dspaddr_offset;
 413
 414         struct drm_i915_gem_object *cursor_bo;
 415         uint32_t cursor_addr;
 416         int16_t cursor_width, cursor_height;
 417         uint32_t cursor_cntl;
 418         uint32_t cursor_size;
 419         uint32_t cursor_base;
 420
 421         struct intel_plane_config plane_config;
 422         struct intel_crtc_config config;
 423         struct intel_crtc_config *new_config;
 424         bool new_enabled;
 425
 426         /* reset counter value when the last flip was submitted */
 427         unsigned int reset_counter;
 428
 429         /* Access to these should be protected by dev_priv->irq_lock. */
 430         bool cpu_fifo_underrun_disabled;
 431         bool pch_fifo_underrun_disabled;
 432
 433         /* per-pipe watermark state */
 434         struct {
 435                 /* watermarks currently being used  */
 436                 struct intel_pipe_wm active;
 437         } wm;
 438
 439         int scanline_offset;
 440         struct intel_mmio_flip mmio_flip;
 441 };
 442
 443 struct intel_plane_wm_parameters {
 444         uint32_t horiz_pixels;
 445         uint32_t vert_pixels;
 446         uint8_t bytes_per_pixel;
 447         bool enabled;
 448         bool scaled;
 449 };
 450
 451 struct intel_plane {
 452         struct drm_plane base;
 453         int plane;
 454         enum pipe pipe;
 455         struct drm_i915_gem_object *obj;
 456         bool can_scale;
 457         int max_downscale;
 458         int crtc_x, crtc_y;
 459         unsigned int crtc_w, crtc_h;
 460         uint32_t src_x, src_y;
 461         uint32_t src_w, src_h;
 462         unsigned int rotation;
 463
 464         /* Since we need to change the watermarks before/after
 465          * enabling/disabling the planes, we need to store the parameters here
 466          * as the other pieces of the struct may not reflect the values we want
 467          * for the watermark calculations. Currently only Haswell uses this.
 468          */
 469         struct intel_plane_wm_parameters wm;
 470
 471         void (*update_plane)(struct drm_plane *plane,
 472                              struct drm_crtc *crtc,
 473                              struct drm_framebuffer *fb,
 474                              struct drm_i915_gem_object *obj,
 475                              int crtc_x, int crtc_y,
 476                              unsigned int crtc_w, unsigned int crtc_h,
 477                              uint32_t x, uint32_t y,
 478                              uint32_t src_w, uint32_t src_h);
 479         void (*disable_plane)(struct drm_plane *plane,
 480                               struct drm_crtc *crtc);
 481         int (*update_colorkey)(struct drm_plane *plane,
 482                                struct drm_intel_sprite_colorkey *key);
 483         void (*get_colorkey)(struct drm_plane *plane,
 484                              struct drm_intel_sprite_colorkey *key);
 485 };
 486
 487 struct intel_watermark_params {
 488         unsigned long fifo_size;
 489         unsigned long max_wm;
 490         unsigned long default_wm;
 491         unsigned long guard_size;
 492         unsigned long cacheline_size;
 493 };
 494
 495 struct cxsr_latency {
 496         int is_desktop;
 497         int is_ddr3;
 498         unsigned long fsb_freq;
 499         unsigned long mem_freq;
 500         unsigned long display_sr;
 501         unsigned long display_hpll_disable;
 502         unsigned long cursor_sr;
 503         unsigned long cursor_hpll_disable;
 504 };
 505
 506 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 507 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 508 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 509 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 510 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 511 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 512
 513 struct intel_hdmi {
 514         u32 hdmi_reg;
 515         int ddc_bus;
 516         uint32_t color_range;
 517         bool color_range_auto;
 518         bool has_hdmi_sink;
 519         bool has_audio;
 520         enum hdmi_force_audio force_audio;
 521         bool rgb_quant_range_selectable;
 522         enum hdmi_picture_aspect aspect_ratio;
 523         void (*write_infoframe)(struct drm_encoder *encoder,
 524                                 enum hdmi_infoframe_type type,
 525                                 const void *frame, ssize_t len);
 526         void (*set_infoframes)(struct drm_encoder *encoder,
 527                                bool enable,
 528                                struct drm_display_mode *adjusted_mode);
 529 };
 530
 531 struct intel_dp_mst_encoder;
 532 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 533
 534 /**
 535  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 536  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 537  * parsing for same resolution.
 538  */
 539 enum edp_drrs_refresh_rate_type {
 540         DRRS_HIGH_RR,
 541         DRRS_LOW_RR,
 542         DRRS_MAX_RR, /* RR count */
 543 };
 544
 545 struct intel_dp {
 546         uint32_t output_reg;
 547         uint32_t aux_ch_ctl_reg;
 548         uint32_t DP;
 549         bool has_audio;
 550         enum hdmi_force_audio force_audio;
 551         uint32_t color_range;
 552         bool color_range_auto;
 553         uint8_t link_bw;
 554         uint8_t lane_count;
 555         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 556         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 557         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 558         struct drm_dp_aux aux;
 559         uint8_t train_set[4];
 560         int panel_power_up_delay;
 561         int panel_power_down_delay;
 562         int panel_power_cycle_delay;
 563         int backlight_on_delay;
 564         int backlight_off_delay;
 565         struct delayed_work panel_vdd_work;
 566         bool want_panel_vdd;
 567         unsigned long last_power_cycle;
 568         unsigned long last_power_on;
 569         unsigned long last_backlight_off;
 570
 571         struct notifier_block edp_notifier;
 572
 573         /*
 574          * Pipe whose power sequencer is currently locked into
 575          * this port. Only relevant on VLV/CHV.
 576          */
 577         enum pipe pps_pipe;
 578
 579         bool use_tps3;
 580         bool can_mst; /* this port supports mst */
 581         bool is_mst;
 582         int active_mst_links;
 583         /* connector directly attached - won't be use for modeset in mst world */
 584         struct intel_connector *attached_connector;
 585
 586         /* mst connector list */
 587         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 588         struct drm_dp_mst_topology_mgr mst_mgr;
 589
 590         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 591         /*
 592          * This function returns the value we have to program the AUX_CTL
 593          * register with to kick off an AUX transaction.
 594          */
 595         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 596                                      bool has_aux_irq,
 597                                      int send_bytes,
 598                                      uint32_t aux_clock_divider);
 599         struct {
 600                 enum drrs_support_type type;
 601                 enum edp_drrs_refresh_rate_type refresh_rate_type;
 602                 struct mutex mutex;
 603         } drrs_state;
 604
 605 };
 606
 607 struct intel_digital_port {
 608         struct intel_encoder base;
 609         enum port port;
 610         u32 saved_port_bits;
 611         struct intel_dp dp;
 612         struct intel_hdmi hdmi;
 613         bool (*hpd_pulse)(struct intel_digital_port *, bool);
 614 };
 615
 616 struct intel_dp_mst_encoder {
 617         struct intel_encoder base;
 618         enum pipe pipe;
 619         struct intel_digital_port *primary;
 620         void *port; /* store this opaque as its illegal to dereference it */
 621 };
 622
 623 static inline int
 624 vlv_dport_to_channel(struct intel_digital_port *dport)
 625 {
 626         switch (dport->port) {
 627         case PORT_B:
 628         case PORT_D:
 629                 return DPIO_CH0;
 630         case PORT_C:
 631                 return DPIO_CH1;
 632         default:
 633                 BUG();
 634         }
 635 }
 636
 637 static inline int
 638 vlv_pipe_to_channel(enum pipe pipe)
 639 {
 640         switch (pipe) {
 641         case PIPE_A:
 642         case PIPE_C:
 643                 return DPIO_CH0;
 644         case PIPE_B:
 645                 return DPIO_CH1;
 646         default:
 647                 BUG();
 648         }
 649 }
 650
 651 static inline struct drm_crtc *
 652 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 653 {
 654         struct drm_i915_private *dev_priv = dev->dev_private;
 655         return dev_priv->pipe_to_crtc_mapping[pipe];
 656 }
 657
 658 static inline struct drm_crtc *
 659 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 660 {
 661         struct drm_i915_private *dev_priv = dev->dev_private;
 662         return dev_priv->plane_to_crtc_mapping[plane];
 663 }
 664
 665 struct intel_unpin_work {
 666         struct work_struct work;
 667         struct drm_crtc *crtc;
 668         struct drm_i915_gem_object *old_fb_obj;
 669         struct drm_i915_gem_object *pending_flip_obj;
 670         struct drm_pending_vblank_event *event;
 671         atomic_t pending;
 672 #define INTEL_FLIP_INACTIVE     0
 673 #define INTEL_FLIP_PENDING      1
 674 #define INTEL_FLIP_COMPLETE     2
 675         u32 flip_count;
 676         u32 gtt_offset;
 677         struct intel_engine_cs *flip_queued_ring;
 678         u32 flip_queued_seqno;
 679         int flip_queued_vblank;
 680         int flip_ready_vblank;
 681         bool enable_stall_check;
 682 };
 683
 684 struct intel_set_config {
 685         struct drm_encoder **save_connector_encoders;
 686         struct drm_crtc **save_encoder_crtcs;
 687         bool *save_crtc_enabled;
 688
 689         bool fb_changed;
 690         bool mode_changed;
 691 };
 692
 693 struct intel_load_detect_pipe {
 694         struct drm_framebuffer *release_fb;
 695         bool load_detect_temp;
 696         int dpms_mode;
 697 };
 698
 699 static inline struct intel_encoder *
 700 intel_attached_encoder(struct drm_connector *connector)
 701 {
 702         return to_intel_connector(connector)->encoder;
 703 }
 704
 705 static inline struct intel_digital_port *
 706 enc_to_dig_port(struct drm_encoder *encoder)
 707 {
 708         return container_of(encoder, struct intel_digital_port, base.base);
 709 }
 710
 711 static inline struct intel_dp_mst_encoder *
 712 enc_to_mst(struct drm_encoder *encoder)
 713 {
 714         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 715 }
 716
 717 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 718 {
 719         return &enc_to_dig_port(encoder)->dp;
 720 }
 721
 722 static inline struct intel_digital_port *
 723 dp_to_dig_port(struct intel_dp *intel_dp)
 724 {
 725         return container_of(intel_dp, struct intel_digital_port, dp);
 726 }
 727
 728 static inline struct intel_digital_port *
 729 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 730 {
 731         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 732 }
 733
 734
 735 /* i915_irq.c */
 736 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 737                                            enum pipe pipe, bool enable);
 738 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 739                                            enum transcoder pch_transcoder,
 740                                            bool enable);
 741 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 742 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 743 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 744 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 745 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 746 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 747 void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
 748 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
 749 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 750 {
 751         /*
 752          * We only use drm_irq_uninstall() at unload and VT switch, so
 753          * this is the only thing we need to check.
 754          */
 755         return !dev_priv->pm._irqs_disabled;
 756 }
 757
 758 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 759 void i9xx_check_fifo_underruns(struct drm_device *dev);
 760 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
 761
 762 /* intel_crt.c */
 763 void intel_crt_init(struct drm_device *dev);
 764
 765
 766 /* intel_ddi.c */
 767 void intel_prepare_ddi(struct drm_device *dev);
 768 void hsw_fdi_link_train(struct drm_crtc *crtc);
 769 void intel_ddi_init(struct drm_device *dev, enum port port);
 770 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 771 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 772 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 773 void intel_ddi_pll_init(struct drm_device *dev);
 774 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 775 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 776                                        enum transcoder cpu_transcoder);
 777 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 778 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 779 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 780 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 781 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 782 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 783 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 784 void intel_ddi_get_config(struct intel_encoder *encoder,
 785                           struct intel_crtc_config *pipe_config);
 786
 787 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 788 void intel_ddi_clock_get(struct intel_encoder *encoder,
 789                          struct intel_crtc_config *pipe_config);
 790 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 791
 792 /* intel_display.c */
 793 const char *intel_output_name(int output);
 794 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 795 int intel_pch_rawclk(struct drm_device *dev);
 796 void intel_mark_busy(struct drm_device *dev);
 797 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 798                              struct intel_engine_cs *ring);
 799 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 800                                     unsigned frontbuffer_bits);
 801 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 802                                      unsigned frontbuffer_bits);
 803 void intel_frontbuffer_flush(struct drm_device *dev,
 804                              unsigned frontbuffer_bits);
 805 /**
 806  * intel_frontbuffer_flip - prepare frontbuffer flip
 807  * @dev: DRM device
 808  * @frontbuffer_bits: frontbuffer plane tracking bits
 809  *
 810  * This function gets called after scheduling a flip on @obj. This is for
 811  * synchronous plane updates which will happen on the next vblank and which will
 812  * not get delayed by pending gpu rendering.
 813  *
 814  * Can be called without any locks held.
 815  */
 816 static inline
 817 void intel_frontbuffer_flip(struct drm_device *dev,
 818                             unsigned frontbuffer_bits)
 819 {
 820         intel_frontbuffer_flush(dev, frontbuffer_bits);
 821 }
 822
 823 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 824 void intel_mark_idle(struct drm_device *dev);
 825 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 826 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
 827 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 828 void intel_encoder_destroy(struct drm_encoder *encoder);
 829 void intel_connector_dpms(struct drm_connector *, int mode);
 830 bool intel_connector_get_hw_state(struct intel_connector *connector);
 831 void intel_modeset_check_state(struct drm_device *dev);
 832 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 833                                 struct intel_digital_port *port);
 834 void intel_connector_attach_encoder(struct intel_connector *connector,
 835                                     struct intel_encoder *encoder);
 836 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 837 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 838                                              struct drm_crtc *crtc);
 839 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 840 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 841                                 struct drm_file *file_priv);
 842 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 843                                              enum pipe pipe);
 844 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 845 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 846 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 847                          struct intel_digital_port *dport);
 848 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 849                                 struct drm_display_mode *mode,
 850                                 struct intel_load_detect_pipe *old,
 851                                 struct drm_modeset_acquire_ctx *ctx);
 852 void intel_release_load_detect_pipe(struct drm_connector *connector,
 853                                     struct intel_load_detect_pipe *old);
 854 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 855                                struct drm_i915_gem_object *obj,
 856                                struct intel_engine_cs *pipelined);
 857 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 858 struct drm_framebuffer *
 859 __intel_framebuffer_create(struct drm_device *dev,
 860                            struct drm_mode_fb_cmd2 *mode_cmd,
 861                            struct drm_i915_gem_object *obj);
 862 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 863 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 864 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 865 void intel_check_page_flip(struct drm_device *dev, int pipe);
 866
 867 /* shared dpll functions */
 868 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 869 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 870                         struct intel_shared_dpll *pll,
 871                         bool state);
 872 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 873 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 874 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
 875 void intel_put_shared_dpll(struct intel_crtc *crtc);
 876
 877 /* modesetting asserts */
 878 void assert_pll(struct drm_i915_private *dev_priv,
 879                 enum pipe pipe, bool state);
 880 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 881 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 882 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 883                        enum pipe pipe, bool state);
 884 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 885 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 886 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 887 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 888 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 889 void intel_write_eld(struct drm_encoder *encoder,
 890                      struct drm_display_mode *mode);
 891 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 892                                              unsigned int tiling_mode,
 893                                              unsigned int bpp,
 894                                              unsigned int pitch);
 895 void intel_display_handle_reset(struct drm_device *dev);
 896 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 897 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 898 void intel_dp_get_m_n(struct intel_crtc *crtc,
 899                       struct intel_crtc_config *pipe_config);
 900 void intel_dp_set_m_n(struct intel_crtc *crtc);
 901 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 902 void
 903 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 904                                 int dotclock);
 905 bool intel_crtc_active(struct drm_crtc *crtc);
 906 void hsw_enable_ips(struct intel_crtc *crtc);
 907 void hsw_disable_ips(struct intel_crtc *crtc);
 908 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
 909 enum intel_display_power_domain
 910 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 911 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 912                                  struct intel_crtc_config *pipe_config);
 913 int intel_format_to_fourcc(int format);
 914 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 915 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
 916
 917 /* intel_dp.c */
 918 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 919 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 920                              struct intel_connector *intel_connector);
 921 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 922 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 923 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 924 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 925 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 926 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 927 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 928 bool intel_dp_compute_config(struct intel_encoder *encoder,
 929                              struct intel_crtc_config *pipe_config);
 930 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 931 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
 932                         bool long_hpd);
 933 void intel_edp_backlight_on(struct intel_dp *intel_dp);
 934 void intel_edp_backlight_off(struct intel_dp *intel_dp);
 935 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 936 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder);
 937 void intel_edp_panel_on(struct intel_dp *intel_dp);
 938 void intel_edp_panel_off(struct intel_dp *intel_dp);
 939 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 940 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 941 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
 942 void intel_edp_psr_invalidate(struct drm_device *dev,
 943                               unsigned frontbuffer_bits);
 944 void intel_edp_psr_flush(struct drm_device *dev,
 945                          unsigned frontbuffer_bits);
 946 void intel_edp_psr_init(struct drm_device *dev);
 947
 948 int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd);
 949 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
 950 void intel_dp_mst_suspend(struct drm_device *dev);
 951 void intel_dp_mst_resume(struct drm_device *dev);
 952 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
 953 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
 954 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
 955 /* intel_dp_mst.c */
 956 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 957 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
 958 /* intel_dsi.c */
 959 void intel_dsi_init(struct drm_device *dev);
 960
 961
 962 /* intel_dvo.c */
 963 void intel_dvo_init(struct drm_device *dev);
 964
 965
 966 /* legacy fbdev emulation in intel_fbdev.c */
 967 #ifdef CONFIG_DRM_I915_FBDEV
 968 extern int intel_fbdev_init(struct drm_device *dev);
 969 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
 970 extern void intel_fbdev_fini(struct drm_device *dev);
 971 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
 972 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 973 extern void intel_fbdev_restore_mode(struct drm_device *dev);
 974 #else
 975 static inline int intel_fbdev_init(struct drm_device *dev)
 976 {
 977         return 0;
 978 }
 979
 980 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
 981 {
 982 }
 983
 984 static inline void intel_fbdev_fini(struct drm_device *dev)
 985 {
 986 }
 987
 988 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
 989 {
 990 }
 991
 992 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 993 {
 994 }
 995 #endif
 996
 997 /* intel_hdmi.c */
 998 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 999 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1000                                struct intel_connector *intel_connector);
1001 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1002 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1003                                struct intel_crtc_config *pipe_config);
1004
1005
1006 /* intel_lvds.c */
1007 void intel_lvds_init(struct drm_device *dev);
1008 bool intel_is_dual_link_lvds(struct drm_device *dev);
1009
1010
1011 /* intel_modes.c */
1012 int intel_connector_update_modes(struct drm_connector *connector,
1013                                  struct edid *edid);
1014 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1015 void intel_attach_force_audio_property(struct drm_connector *connector);
1016 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1017
1018
1019 /* intel_overlay.c */
1020 void intel_setup_overlay(struct drm_device *dev);
1021 void intel_cleanup_overlay(struct drm_device *dev);
1022 int intel_overlay_switch_off(struct intel_overlay *overlay);
1023 int intel_overlay_put_image(struct drm_device *dev, void *data,
1024                             struct drm_file *file_priv);
1025 int intel_overlay_attrs(struct drm_device *dev, void *data,
1026                         struct drm_file *file_priv);
1027
1028
1029 /* intel_panel.c */
1030 int intel_panel_init(struct intel_panel *panel,
1031                      struct drm_display_mode *fixed_mode,
1032                      struct drm_display_mode *downclock_mode);
1033 void intel_panel_fini(struct intel_panel *panel);
1034 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1035                             struct drm_display_mode *adjusted_mode);
1036 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1037                              struct intel_crtc_config *pipe_config,
1038                              int fitting_mode);
1039 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1040                               struct intel_crtc_config *pipe_config,
1041                               int fitting_mode);
1042 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1043                                     u32 level, u32 max);
1044 int intel_panel_setup_backlight(struct drm_connector *connector);
1045 void intel_panel_enable_backlight(struct intel_connector *connector);
1046 void intel_panel_disable_backlight(struct intel_connector *connector);
1047 void intel_panel_destroy_backlight(struct drm_connector *connector);
1048 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1049 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1050 extern struct drm_display_mode *intel_find_panel_downclock(
1051                                 struct drm_device *dev,
1052                                 struct drm_display_mode *fixed_mode,
1053                                 struct drm_connector *connector);
1054
1055 /* intel_pm.c */
1056 void intel_init_clock_gating(struct drm_device *dev);
1057 void intel_suspend_hw(struct drm_device *dev);
1058 int ilk_wm_max_level(const struct drm_device *dev);
1059 void intel_update_watermarks(struct drm_crtc *crtc);
1060 void intel_update_sprite_watermarks(struct drm_plane *plane,
1061                                     struct drm_crtc *crtc,
1062                                     uint32_t sprite_width,
1063                                     uint32_t sprite_height,
1064                                     int pixel_size,
1065                                     bool enabled, bool scaled);
1066 void intel_init_pm(struct drm_device *dev);
1067 void intel_pm_setup(struct drm_device *dev);
1068 bool intel_fbc_enabled(struct drm_device *dev);
1069 void intel_update_fbc(struct drm_device *dev);
1070 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1071 void intel_gpu_ips_teardown(void);
1072 int intel_power_domains_init(struct drm_i915_private *);
1073 void intel_power_domains_remove(struct drm_i915_private *);
1074 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
1075                                  enum intel_display_power_domain domain);
1076 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
1077                                           enum intel_display_power_domain domain);
1078 void intel_display_power_get(struct drm_i915_private *dev_priv,
1079                              enum intel_display_power_domain domain);
1080 void intel_display_power_put(struct drm_i915_private *dev_priv,
1081                              enum intel_display_power_domain domain);
1082 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1083 void intel_init_gt_powersave(struct drm_device *dev);
1084 void intel_cleanup_gt_powersave(struct drm_device *dev);
1085 void intel_enable_gt_powersave(struct drm_device *dev);
1086 void intel_disable_gt_powersave(struct drm_device *dev);
1087 void intel_suspend_gt_powersave(struct drm_device *dev);
1088 void intel_reset_gt_powersave(struct drm_device *dev);
1089 void ironlake_teardown_rc6(struct drm_device *dev);
1090 void gen6_update_ring_freq(struct drm_device *dev);
1091 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1092 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1093 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1094 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1095 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1096 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1097 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1098 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
1099 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
1100 void ilk_wm_get_hw_state(struct drm_device *dev);
1101
1102
1103 /* intel_sdvo.c */
1104 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1105
1106
1107 /* intel_sprite.c */
1108 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1109 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1110                                enum plane plane);
1111 int intel_plane_set_property(struct drm_plane *plane,
1112                              struct drm_property *prop,
1113                              uint64_t val);
1114 int intel_plane_restore(struct drm_plane *plane);
1115 void intel_plane_disable(struct drm_plane *plane);
1116 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1117                               struct drm_file *file_priv);
1118 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1119                               struct drm_file *file_priv);
1120
1121
1122 /* intel_tv.c */
1123 void intel_tv_init(struct drm_device *dev);
1124
1125 #endif /* __INTEL_DRV_H__ */