drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         struct list_head fbdev_list;
 127         struct drm_display_mode *our_mode;
 128         int preferred_bpp;
 129 };
 130
 131 struct intel_encoder {
 132         struct drm_encoder base;
 133
 134         enum intel_output_type type;
 135         unsigned int cloneable;
 136         void (*hot_plug)(struct intel_encoder *);
 137         bool (*compute_config)(struct intel_encoder *,
 138                                struct intel_crtc_state *);
 139         void (*pre_pll_enable)(struct intel_encoder *);
 140         void (*pre_enable)(struct intel_encoder *);
 141         void (*enable)(struct intel_encoder *);
 142         void (*mode_set)(struct intel_encoder *intel_encoder);
 143         void (*disable)(struct intel_encoder *);
 144         void (*post_disable)(struct intel_encoder *);
 145         /* Read out the current hw state of this connector, returning true if
 146          * the encoder is active. If the encoder is enabled it also set the pipe
 147          * it is connected to in the pipe parameter. */
 148         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 149         /* Reconstructs the equivalent mode flags for the current hardware
 150          * state. This must be called _after_ display->get_pipe_config has
 151          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 152          * be set correctly before calling this function. */
 153         void (*get_config)(struct intel_encoder *,
 154                            struct intel_crtc_state *pipe_config);
 155         /*
 156          * Called during system suspend after all pending requests for the
 157          * encoder are flushed (for example for DP AUX transactions) and
 158          * device interrupts are disabled.
 159          */
 160         void (*suspend)(struct intel_encoder *);
 161         int crtc_mask;
 162         enum hpd_pin hpd_pin;
 163 };
 164
 165 struct intel_panel {
 166         struct drm_display_mode *fixed_mode;
 167         struct drm_display_mode *downclock_mode;
 168         int fitting_mode;
 169
 170         /* backlight */
 171         struct {
 172                 bool present;
 173                 u32 level;
 174                 u32 min;
 175                 u32 max;
 176                 bool enabled;
 177                 bool combination_mode;  /* gen 2/4 only */
 178                 bool active_low_pwm;
 179
 180                 /* PWM chip */
 181                 struct pwm_device *pwm;
 182
 183                 struct backlight_device *device;
 184         } backlight;
 185
 186         void (*backlight_power)(struct intel_connector *, bool enable);
 187 };
 188
 189 struct intel_connector {
 190         struct drm_connector base;
 191         /*
 192          * The fixed encoder this connector is connected to.
 193          */
 194         struct intel_encoder *encoder;
 195
 196         /* Reads out the current hw, returning true if the connector is enabled
 197          * and active (i.e. dpms ON state). */
 198         bool (*get_hw_state)(struct intel_connector *);
 199
 200         /*
 201          * Removes all interfaces through which the connector is accessible
 202          * - like sysfs, debugfs entries -, so that no new operations can be
 203          * started on the connector. Also makes sure all currently pending
 204          * operations finish before returing.
 205          */
 206         void (*unregister)(struct intel_connector *);
 207
 208         /* Panel info for eDP and LVDS */
 209         struct intel_panel panel;
 210
 211         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 212         struct edid *edid;
 213         struct edid *detect_edid;
 214
 215         /* since POLL and HPD connectors may use the same HPD line keep the native
 216            state of connector->polled in case hotplug storm detection changes it */
 217         u8 polled;
 218
 219         void *port; /* store this opaque as its illegal to dereference it */
 220
 221         struct intel_dp *mst_port;
 222 };
 223
 224 typedef struct dpll {
 225         /* given values */
 226         int n;
 227         int m1, m2;
 228         int p1, p2;
 229         /* derived values */
 230         int     dot;
 231         int     vco;
 232         int     m;
 233         int     p;
 234 } intel_clock_t;
 235
 236 struct intel_atomic_state {
 237         struct drm_atomic_state base;
 238
 239         unsigned int cdclk;
 240         bool dpll_set;
 241         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 242 };
 243
 244 struct intel_plane_state {
 245         struct drm_plane_state base;
 246         struct drm_rect src;
 247         struct drm_rect dst;
 248         struct drm_rect clip;
 249         bool visible;
 250
 251         /*
 252          * scaler_id
 253          *    = -1 : not using a scaler
 254          *    >=  0 : using a scalers
 255          *
 256          * plane requiring a scaler:
 257          *   - During check_plane, its bit is set in
 258          *     crtc_state->scaler_state.scaler_users by calling helper function
 259          *     update_scaler_plane.
 260          *   - scaler_id indicates the scaler it got assigned.
 261          *
 262          * plane doesn't require a scaler:
 263          *   - this can happen when scaling is no more required or plane simply
 264          *     got disabled.
 265          *   - During check_plane, corresponding bit is reset in
 266          *     crtc_state->scaler_state.scaler_users by calling helper function
 267          *     update_scaler_plane.
 268          */
 269         int scaler_id;
 270
 271         struct drm_intel_sprite_colorkey ckey;
 272 };
 273
 274 struct intel_initial_plane_config {
 275         struct intel_framebuffer *fb;
 276         unsigned int tiling;
 277         int size;
 278         u32 base;
 279 };
 280
 281 #define SKL_MIN_SRC_W 8
 282 #define SKL_MAX_SRC_W 4096
 283 #define SKL_MIN_SRC_H 8
 284 #define SKL_MAX_SRC_H 4096
 285 #define SKL_MIN_DST_W 8
 286 #define SKL_MAX_DST_W 4096
 287 #define SKL_MIN_DST_H 8
 288 #define SKL_MAX_DST_H 4096
 289
 290 struct intel_scaler {
 291         int in_use;
 292         uint32_t mode;
 293 };
 294
 295 struct intel_crtc_scaler_state {
 296 #define SKL_NUM_SCALERS 2
 297         struct intel_scaler scalers[SKL_NUM_SCALERS];
 298
 299         /*
 300          * scaler_users: keeps track of users requesting scalers on this crtc.
 301          *
 302          *     If a bit is set, a user is using a scaler.
 303          *     Here user can be a plane or crtc as defined below:
 304          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 305          *       bit 31    - crtc
 306          *
 307          * Instead of creating a new index to cover planes and crtc, using
 308          * existing drm_plane_index for planes which is well less than 31
 309          * planes and bit 31 for crtc. This should be fine to cover all
 310          * our platforms.
 311          *
 312          * intel_atomic_setup_scalers will setup available scalers to users
 313          * requesting scalers. It will gracefully fail if request exceeds
 314          * avilability.
 315          */
 316 #define SKL_CRTC_INDEX 31
 317         unsigned scaler_users;
 318
 319         /* scaler used by crtc for panel fitting purpose */
 320         int scaler_id;
 321 };
 322
 323 /* drm_mode->private_flags */
 324 #define I915_MODE_FLAG_INHERITED 1
 325
 326 struct intel_crtc_state {
 327         struct drm_crtc_state base;
 328
 329         /**
 330          * quirks - bitfield with hw state readout quirks
 331          *
 332          * For various reasons the hw state readout code might not be able to
 333          * completely faithfully read out the current state. These cases are
 334          * tracked with quirk flags so that fastboot and state checker can act
 335          * accordingly.
 336          */
 337 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 338         unsigned long quirks;
 339
 340         /* Pipe source size (ie. panel fitter input size)
 341          * All planes will be positioned inside this space,
 342          * and get clipped at the edges. */
 343         int pipe_src_w, pipe_src_h;
 344
 345         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 346          * between pch encoders and cpu encoders. */
 347         bool has_pch_encoder;
 348
 349         /* Are we sending infoframes on the attached port */
 350         bool has_infoframe;
 351
 352         /* CPU Transcoder for the pipe. Currently this can only differ from the
 353          * pipe on Haswell (where we have a special eDP transcoder). */
 354         enum transcoder cpu_transcoder;
 355
 356         /*
 357          * Use reduced/limited/broadcast rbg range, compressing from the full
 358          * range fed into the crtcs.
 359          */
 360         bool limited_color_range;
 361
 362         /* DP has a bunch of special case unfortunately, so mark the pipe
 363          * accordingly. */
 364         bool has_dp_encoder;
 365
 366         /* Whether we should send NULL infoframes. Required for audio. */
 367         bool has_hdmi_sink;
 368
 369         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 370          * has_dp_encoder is set. */
 371         bool has_audio;
 372
 373         /*
 374          * Enable dithering, used when the selected pipe bpp doesn't match the
 375          * plane bpp.
 376          */
 377         bool dither;
 378
 379         /* Controls for the clock computation, to override various stages. */
 380         bool clock_set;
 381
 382         /* SDVO TV has a bunch of special case. To make multifunction encoders
 383          * work correctly, we need to track this at runtime.*/
 384         bool sdvo_tv_clock;
 385
 386         /*
 387          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 388          * required. This is set in the 2nd loop of calling encoder's
 389          * ->compute_config if the first pick doesn't work out.
 390          */
 391         bool bw_constrained;
 392
 393         /* Settings for the intel dpll used on pretty much everything but
 394          * haswell. */
 395         struct dpll dpll;
 396
 397         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 398         enum intel_dpll_id shared_dpll;
 399
 400         /*
 401          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 402          * - enum skl_dpll on SKL
 403          */
 404         uint32_t ddi_pll_sel;
 405
 406         /* Actual register state of the dpll, for shared dpll cross-checking. */
 407         struct intel_dpll_hw_state dpll_hw_state;
 408
 409         int pipe_bpp;
 410         struct intel_link_m_n dp_m_n;
 411
 412         /* m2_n2 for eDP downclock */
 413         struct intel_link_m_n dp_m2_n2;
 414         bool has_drrs;
 415
 416         /*
 417          * Frequence the dpll for the port should run at. Differs from the
 418          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 419          * already multiplied by pixel_multiplier.
 420          */
 421         int port_clock;
 422
 423         /* Used by SDVO (and if we ever fix it, HDMI). */
 424         unsigned pixel_multiplier;
 425
 426         uint8_t lane_count;
 427
 428         /* Panel fitter controls for gen2-gen4 + VLV */
 429         struct {
 430                 u32 control;
 431                 u32 pgm_ratios;
 432                 u32 lvds_border_bits;
 433         } gmch_pfit;
 434
 435         /* Panel fitter placement and size for Ironlake+ */
 436         struct {
 437                 u32 pos;
 438                 u32 size;
 439                 bool enabled;
 440                 bool force_thru;
 441         } pch_pfit;
 442
 443         /* FDI configuration, only valid if has_pch_encoder is set. */
 444         int fdi_lanes;
 445         struct intel_link_m_n fdi_m_n;
 446
 447         bool ips_enabled;
 448
 449         bool double_wide;
 450
 451         bool dp_encoder_is_mst;
 452         int pbn;
 453
 454         struct intel_crtc_scaler_state scaler_state;
 455
 456         /* w/a for waiting 2 vblanks during crtc enable */
 457         enum pipe hsw_workaround_pipe;
 458 };
 459
 460 struct vlv_wm_state {
 461         struct vlv_pipe_wm wm[3];
 462         struct vlv_sr_wm sr[3];
 463         uint8_t num_active_planes;
 464         uint8_t num_levels;
 465         uint8_t level;
 466         bool cxsr;
 467 };
 468
 469 struct intel_pipe_wm {
 470         struct intel_wm_level wm[5];
 471         uint32_t linetime;
 472         bool fbc_wm_enabled;
 473         bool pipe_enabled;
 474         bool sprites_enabled;
 475         bool sprites_scaled;
 476 };
 477
 478 struct intel_mmio_flip {
 479         struct work_struct work;
 480         struct drm_i915_private *i915;
 481         struct drm_i915_gem_request *req;
 482         struct intel_crtc *crtc;
 483 };
 484
 485 struct skl_pipe_wm {
 486         struct skl_wm_level wm[8];
 487         struct skl_wm_level trans_wm;
 488         uint32_t linetime;
 489 };
 490
 491 /*
 492  * Tracking of operations that need to be performed at the beginning/end of an
 493  * atomic commit, outside the atomic section where interrupts are disabled.
 494  * These are generally operations that grab mutexes or might otherwise sleep
 495  * and thus can't be run with interrupts disabled.
 496  */
 497 struct intel_crtc_atomic_commit {
 498         /* Sleepable operations to perform before commit */
 499         bool wait_for_flips;
 500         bool disable_fbc;
 501         bool disable_ips;
 502         bool disable_cxsr;
 503         bool pre_disable_primary;
 504         bool update_wm_pre, update_wm_post;
 505         unsigned disabled_planes;
 506
 507         /* Sleepable operations to perform after commit */
 508         unsigned fb_bits;
 509         bool wait_vblank;
 510         bool update_fbc;
 511         bool post_enable_primary;
 512         unsigned update_sprite_watermarks;
 513 };
 514
 515 struct intel_crtc {
 516         struct drm_crtc base;
 517         enum pipe pipe;
 518         enum plane plane;
 519         u8 lut_r[256], lut_g[256], lut_b[256];
 520         /*
 521          * Whether the crtc and the connected output pipeline is active. Implies
 522          * that crtc->enabled is set, i.e. the current mode configuration has
 523          * some outputs connected to this crtc.
 524          */
 525         bool active;
 526         unsigned long enabled_power_domains;
 527         bool lowfreq_avail;
 528         struct intel_overlay *overlay;
 529         struct intel_unpin_work *unpin_work;
 530
 531         atomic_t unpin_work_count;
 532
 533         /* Display surface base address adjustement for pageflips. Note that on
 534          * gen4+ this only adjusts up to a tile, offsets within a tile are
 535          * handled in the hw itself (with the TILEOFF register). */
 536         unsigned long dspaddr_offset;
 537
 538         struct drm_i915_gem_object *cursor_bo;
 539         uint32_t cursor_addr;
 540         uint32_t cursor_cntl;
 541         uint32_t cursor_size;
 542         uint32_t cursor_base;
 543
 544         struct intel_crtc_state *config;
 545
 546         /* reset counter value when the last flip was submitted */
 547         unsigned int reset_counter;
 548
 549         /* Access to these should be protected by dev_priv->irq_lock. */
 550         bool cpu_fifo_underrun_disabled;
 551         bool pch_fifo_underrun_disabled;
 552
 553         /* per-pipe watermark state */
 554         struct {
 555                 /* watermarks currently being used  */
 556                 struct intel_pipe_wm active;
 557                 /* SKL wm values currently in use */
 558                 struct skl_pipe_wm skl_active;
 559                 /* allow CxSR on this pipe */
 560                 bool cxsr_allowed;
 561         } wm;
 562
 563         int scanline_offset;
 564
 565         unsigned start_vbl_count;
 566         struct intel_crtc_atomic_commit atomic;
 567
 568         /* scalers available on this crtc */
 569         int num_scalers;
 570
 571         struct vlv_wm_state wm_state;
 572 };
 573
 574 struct intel_plane_wm_parameters {
 575         uint32_t horiz_pixels;
 576         uint32_t vert_pixels;
 577         /*
 578          *   For packed pixel formats:
 579          *     bytes_per_pixel - holds bytes per pixel
 580          *   For planar pixel formats:
 581          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 582          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 583          */
 584         uint8_t bytes_per_pixel;
 585         uint8_t y_bytes_per_pixel;
 586         bool enabled;
 587         bool scaled;
 588         u64 tiling;
 589         unsigned int rotation;
 590         uint16_t fifo_size;
 591 };
 592
 593 struct intel_plane {
 594         struct drm_plane base;
 595         int plane;
 596         enum pipe pipe;
 597         bool can_scale;
 598         int max_downscale;
 599         uint32_t frontbuffer_bit;
 600
 601         /* Since we need to change the watermarks before/after
 602          * enabling/disabling the planes, we need to store the parameters here
 603          * as the other pieces of the struct may not reflect the values we want
 604          * for the watermark calculations. Currently only Haswell uses this.
 605          */
 606         struct intel_plane_wm_parameters wm;
 607
 608         /*
 609          * NOTE: Do not place new plane state fields here (e.g., when adding
 610          * new plane properties).  New runtime state should now be placed in
 611          * the intel_plane_state structure and accessed via drm_plane->state.
 612          */
 613
 614         void (*update_plane)(struct drm_plane *plane,
 615                              struct drm_crtc *crtc,
 616                              struct drm_framebuffer *fb,
 617                              int crtc_x, int crtc_y,
 618                              unsigned int crtc_w, unsigned int crtc_h,
 619                              uint32_t x, uint32_t y,
 620                              uint32_t src_w, uint32_t src_h);
 621         void (*disable_plane)(struct drm_plane *plane,
 622                               struct drm_crtc *crtc);
 623         int (*check_plane)(struct drm_plane *plane,
 624                            struct intel_crtc_state *crtc_state,
 625                            struct intel_plane_state *state);
 626         void (*commit_plane)(struct drm_plane *plane,
 627                              struct intel_plane_state *state);
 628 };
 629
 630 struct intel_watermark_params {
 631         unsigned long fifo_size;
 632         unsigned long max_wm;
 633         unsigned long default_wm;
 634         unsigned long guard_size;
 635         unsigned long cacheline_size;
 636 };
 637
 638 struct cxsr_latency {
 639         int is_desktop;
 640         int is_ddr3;
 641         unsigned long fsb_freq;
 642         unsigned long mem_freq;
 643         unsigned long display_sr;
 644         unsigned long display_hpll_disable;
 645         unsigned long cursor_sr;
 646         unsigned long cursor_hpll_disable;
 647 };
 648
 649 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 650 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 651 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 652 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 653 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 654 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 655 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 656 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 657 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 658
 659 struct intel_hdmi {
 660         u32 hdmi_reg;
 661         int ddc_bus;
 662         bool limited_color_range;
 663         bool color_range_auto;
 664         bool has_hdmi_sink;
 665         bool has_audio;
 666         enum hdmi_force_audio force_audio;
 667         bool rgb_quant_range_selectable;
 668         enum hdmi_picture_aspect aspect_ratio;
 669         void (*write_infoframe)(struct drm_encoder *encoder,
 670                                 enum hdmi_infoframe_type type,
 671                                 const void *frame, ssize_t len);
 672         void (*set_infoframes)(struct drm_encoder *encoder,
 673                                bool enable,
 674                                struct drm_display_mode *adjusted_mode);
 675         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 676 };
 677
 678 struct intel_dp_mst_encoder;
 679 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 680
 681 /*
 682  * enum link_m_n_set:
 683  *      When platform provides two set of M_N registers for dp, we can
 684  *      program them and switch between them incase of DRRS.
 685  *      But When only one such register is provided, we have to program the
 686  *      required divider value on that registers itself based on the DRRS state.
 687  *
 688  * M1_N1        : Program dp_m_n on M1_N1 registers
 689  *                        dp_m2_n2 on M2_N2 registers (If supported)
 690  *
 691  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 692  *                        M2_N2 registers are not supported
 693  */
 694
 695 enum link_m_n_set {
 696         /* Sets the m1_n1 and m2_n2 */
 697         M1_N1 = 0,
 698         M2_N2
 699 };
 700
 701 struct sink_crc {
 702         bool started;
 703         u8 last_crc[6];
 704         int last_count;
 705 };
 706
 707 struct intel_dp {
 708         uint32_t output_reg;
 709         uint32_t aux_ch_ctl_reg;
 710         uint32_t DP;
 711         int link_rate;
 712         uint8_t lane_count;
 713         bool has_audio;
 714         enum hdmi_force_audio force_audio;
 715         bool limited_color_range;
 716         bool color_range_auto;
 717         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 718         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 719         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 720         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 721         uint8_t num_sink_rates;
 722         int sink_rates[DP_MAX_SUPPORTED_RATES];
 723         struct sink_crc sink_crc;
 724         struct drm_dp_aux aux;
 725         uint8_t train_set[4];
 726         int panel_power_up_delay;
 727         int panel_power_down_delay;
 728         int panel_power_cycle_delay;
 729         int backlight_on_delay;
 730         int backlight_off_delay;
 731         struct delayed_work panel_vdd_work;
 732         bool want_panel_vdd;
 733         unsigned long last_power_cycle;
 734         unsigned long last_power_on;
 735         unsigned long last_backlight_off;
 736
 737         struct notifier_block edp_notifier;
 738
 739         /*
 740          * Pipe whose power sequencer is currently locked into
 741          * this port. Only relevant on VLV/CHV.
 742          */
 743         enum pipe pps_pipe;
 744         struct edp_power_seq pps_delays;
 745
 746         bool use_tps3;
 747         bool can_mst; /* this port supports mst */
 748         bool is_mst;
 749         int active_mst_links;
 750         /* connector directly attached - won't be use for modeset in mst world */
 751         struct intel_connector *attached_connector;
 752
 753         /* mst connector list */
 754         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 755         struct drm_dp_mst_topology_mgr mst_mgr;
 756
 757         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 758         /*
 759          * This function returns the value we have to program the AUX_CTL
 760          * register with to kick off an AUX transaction.
 761          */
 762         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 763                                      bool has_aux_irq,
 764                                      int send_bytes,
 765                                      uint32_t aux_clock_divider);
 766         bool train_set_valid;
 767
 768         /* Displayport compliance testing */
 769         unsigned long compliance_test_type;
 770         unsigned long compliance_test_data;
 771         bool compliance_test_active;
 772 };
 773
 774 struct intel_digital_port {
 775         struct intel_encoder base;
 776         enum port port;
 777         u32 saved_port_bits;
 778         struct intel_dp dp;
 779         struct intel_hdmi hdmi;
 780         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 781 };
 782
 783 struct intel_dp_mst_encoder {
 784         struct intel_encoder base;
 785         enum pipe pipe;
 786         struct intel_digital_port *primary;
 787         void *port; /* store this opaque as its illegal to dereference it */
 788 };
 789
 790 static inline int
 791 vlv_dport_to_channel(struct intel_digital_port *dport)
 792 {
 793         switch (dport->port) {
 794         case PORT_B:
 795         case PORT_D:
 796                 return DPIO_CH0;
 797         case PORT_C:
 798                 return DPIO_CH1;
 799         default:
 800                 BUG();
 801         }
 802 }
 803
 804 static inline int
 805 vlv_pipe_to_channel(enum pipe pipe)
 806 {
 807         switch (pipe) {
 808         case PIPE_A:
 809         case PIPE_C:
 810                 return DPIO_CH0;
 811         case PIPE_B:
 812                 return DPIO_CH1;
 813         default:
 814                 BUG();
 815         }
 816 }
 817
 818 static inline struct drm_crtc *
 819 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 820 {
 821         struct drm_i915_private *dev_priv = dev->dev_private;
 822         return dev_priv->pipe_to_crtc_mapping[pipe];
 823 }
 824
 825 static inline struct drm_crtc *
 826 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 827 {
 828         struct drm_i915_private *dev_priv = dev->dev_private;
 829         return dev_priv->plane_to_crtc_mapping[plane];
 830 }
 831
 832 struct intel_unpin_work {
 833         struct work_struct work;
 834         struct drm_crtc *crtc;
 835         struct drm_framebuffer *old_fb;
 836         struct drm_i915_gem_object *pending_flip_obj;
 837         struct drm_pending_vblank_event *event;
 838         atomic_t pending;
 839 #define INTEL_FLIP_INACTIVE     0
 840 #define INTEL_FLIP_PENDING      1
 841 #define INTEL_FLIP_COMPLETE     2
 842         u32 flip_count;
 843         u32 gtt_offset;
 844         struct drm_i915_gem_request *flip_queued_req;
 845         int flip_queued_vblank;
 846         int flip_ready_vblank;
 847         bool enable_stall_check;
 848 };
 849
 850 struct intel_load_detect_pipe {
 851         struct drm_framebuffer *release_fb;
 852         bool load_detect_temp;
 853         int dpms_mode;
 854 };
 855
 856 static inline struct intel_encoder *
 857 intel_attached_encoder(struct drm_connector *connector)
 858 {
 859         return to_intel_connector(connector)->encoder;
 860 }
 861
 862 static inline struct intel_digital_port *
 863 enc_to_dig_port(struct drm_encoder *encoder)
 864 {
 865         return container_of(encoder, struct intel_digital_port, base.base);
 866 }
 867
 868 static inline struct intel_dp_mst_encoder *
 869 enc_to_mst(struct drm_encoder *encoder)
 870 {
 871         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 872 }
 873
 874 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 875 {
 876         return &enc_to_dig_port(encoder)->dp;
 877 }
 878
 879 static inline struct intel_digital_port *
 880 dp_to_dig_port(struct intel_dp *intel_dp)
 881 {
 882         return container_of(intel_dp, struct intel_digital_port, dp);
 883 }
 884
 885 static inline struct intel_digital_port *
 886 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 887 {
 888         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 889 }
 890
 891 /*
 892  * Returns the number of planes for this pipe, ie the number of sprites + 1
 893  * (primary plane). This doesn't count the cursor plane then.
 894  */
 895 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 896 {
 897         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 898 }
 899
 900 /* intel_fifo_underrun.c */
 901 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 902                                            enum pipe pipe, bool enable);
 903 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 904                                            enum transcoder pch_transcoder,
 905                                            bool enable);
 906 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 907                                          enum pipe pipe);
 908 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 909                                          enum transcoder pch_transcoder);
 910 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 911
 912 /* i915_irq.c */
 913 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 914 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 915 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 916 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 917 void gen6_reset_rps_interrupts(struct drm_device *dev);
 918 void gen6_enable_rps_interrupts(struct drm_device *dev);
 919 void gen6_disable_rps_interrupts(struct drm_device *dev);
 920 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 921 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 922 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 923 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 924 {
 925         /*
 926          * We only use drm_irq_uninstall() at unload and VT switch, so
 927          * this is the only thing we need to check.
 928          */
 929         return dev_priv->pm.irqs_enabled;
 930 }
 931
 932 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 933 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 934                                      unsigned int pipe_mask);
 935
 936 /* intel_crt.c */
 937 void intel_crt_init(struct drm_device *dev);
 938
 939
 940 /* intel_ddi.c */
 941 void intel_prepare_ddi(struct drm_device *dev);
 942 void hsw_fdi_link_train(struct drm_crtc *crtc);
 943 void intel_ddi_init(struct drm_device *dev, enum port port);
 944 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 945 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 946 void intel_ddi_pll_init(struct drm_device *dev);
 947 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 948 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 949                                        enum transcoder cpu_transcoder);
 950 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 951 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 952 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 953                           struct intel_crtc_state *crtc_state);
 954 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 955 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 956 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 957 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 958 void intel_ddi_get_config(struct intel_encoder *encoder,
 959                           struct intel_crtc_state *pipe_config);
 960 struct intel_encoder *
 961 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
 962
 963 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 964 void intel_ddi_clock_get(struct intel_encoder *encoder,
 965                          struct intel_crtc_state *pipe_config);
 966 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 967 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 968
 969 /* intel_frontbuffer.c */
 970 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 971                              enum fb_op_origin origin);
 972 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 973                                     unsigned frontbuffer_bits);
 974 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 975                                      unsigned frontbuffer_bits);
 976 void intel_frontbuffer_flip(struct drm_device *dev,
 977                             unsigned frontbuffer_bits);
 978 unsigned int intel_fb_align_height(struct drm_device *dev,
 979                                    unsigned int height,
 980                                    uint32_t pixel_format,
 981                                    uint64_t fb_format_modifier);
 982 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
 983                         enum fb_op_origin origin);
 984 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
 985                               uint32_t pixel_format);
 986
 987 /* intel_audio.c */
 988 void intel_init_audio(struct drm_device *dev);
 989 void intel_audio_codec_enable(struct intel_encoder *encoder);
 990 void intel_audio_codec_disable(struct intel_encoder *encoder);
 991 void i915_audio_component_init(struct drm_i915_private *dev_priv);
 992 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
 993
 994 /* intel_display.c */
 995 extern const struct drm_plane_funcs intel_plane_funcs;
 996 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 997 int intel_pch_rawclk(struct drm_device *dev);
 998 void intel_mark_busy(struct drm_device *dev);
 999 void intel_mark_idle(struct drm_device *dev);
1000 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1001 int intel_display_suspend(struct drm_device *dev);
1002 void intel_encoder_destroy(struct drm_encoder *encoder);
1003 int intel_connector_init(struct intel_connector *);
1004 struct intel_connector *intel_connector_alloc(void);
1005 bool intel_connector_get_hw_state(struct intel_connector *connector);
1006 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1007                                 struct intel_digital_port *port);
1008 void intel_connector_attach_encoder(struct intel_connector *connector,
1009                                     struct intel_encoder *encoder);
1010 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1011 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1012                                              struct drm_crtc *crtc);
1013 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1014 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1015                                 struct drm_file *file_priv);
1016 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1017                                              enum pipe pipe);
1018 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1019 static inline void
1020 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1021 {
1022         drm_wait_one_vblank(dev, pipe);
1023 }
1024 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1025 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1026                          struct intel_digital_port *dport,
1027                          unsigned int expected_mask);
1028 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1029                                 struct drm_display_mode *mode,
1030                                 struct intel_load_detect_pipe *old,
1031                                 struct drm_modeset_acquire_ctx *ctx);
1032 void intel_release_load_detect_pipe(struct drm_connector *connector,
1033                                     struct intel_load_detect_pipe *old,
1034                                     struct drm_modeset_acquire_ctx *ctx);
1035 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1036                                struct drm_framebuffer *fb,
1037                                const struct drm_plane_state *plane_state,
1038                                struct intel_engine_cs *pipelined,
1039                                struct drm_i915_gem_request **pipelined_request);
1040 struct drm_framebuffer *
1041 __intel_framebuffer_create(struct drm_device *dev,
1042                            struct drm_mode_fb_cmd2 *mode_cmd,
1043                            struct drm_i915_gem_object *obj);
1044 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1045 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1046 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1047 void intel_check_page_flip(struct drm_device *dev, int pipe);
1048 int intel_prepare_plane_fb(struct drm_plane *plane,
1049                            struct drm_framebuffer *fb,
1050                            const struct drm_plane_state *new_state);
1051 void intel_cleanup_plane_fb(struct drm_plane *plane,
1052                             struct drm_framebuffer *fb,
1053                             const struct drm_plane_state *old_state);
1054 int intel_plane_atomic_get_property(struct drm_plane *plane,
1055                                     const struct drm_plane_state *state,
1056                                     struct drm_property *property,
1057                                     uint64_t *val);
1058 int intel_plane_atomic_set_property(struct drm_plane *plane,
1059                                     struct drm_plane_state *state,
1060                                     struct drm_property *property,
1061                                     uint64_t val);
1062 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1063                                     struct drm_plane_state *plane_state);
1064
1065 unsigned int
1066 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1067                   uint64_t fb_format_modifier);
1068
1069 static inline bool
1070 intel_rotation_90_or_270(unsigned int rotation)
1071 {
1072         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1073 }
1074
1075 void intel_create_rotation_property(struct drm_device *dev,
1076                                         struct intel_plane *plane);
1077
1078 /* shared dpll functions */
1079 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1080 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1081                         struct intel_shared_dpll *pll,
1082                         bool state);
1083 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1084 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1085 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1086                                                 struct intel_crtc_state *state);
1087
1088 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1089                       const struct dpll *dpll);
1090 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1091
1092 /* modesetting asserts */
1093 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1094                            enum pipe pipe);
1095 void assert_pll(struct drm_i915_private *dev_priv,
1096                 enum pipe pipe, bool state);
1097 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1098 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1099 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1100                        enum pipe pipe, bool state);
1101 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1102 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1103 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1104 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1105 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1106 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1107                                              int *x, int *y,
1108                                              unsigned int tiling_mode,
1109                                              unsigned int bpp,
1110                                              unsigned int pitch);
1111 void intel_prepare_reset(struct drm_device *dev);
1112 void intel_finish_reset(struct drm_device *dev);
1113 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1114 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1115 void broxton_init_cdclk(struct drm_device *dev);
1116 void broxton_uninit_cdclk(struct drm_device *dev);
1117 void broxton_ddi_phy_init(struct drm_device *dev);
1118 void broxton_ddi_phy_uninit(struct drm_device *dev);
1119 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1120 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1121 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1122 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1123 void intel_dp_get_m_n(struct intel_crtc *crtc,
1124                       struct intel_crtc_state *pipe_config);
1125 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1126 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1127 void
1128 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1129                                 int dotclock);
1130 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1131                         intel_clock_t *best_clock);
1132 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1133
1134 bool intel_crtc_active(struct drm_crtc *crtc);
1135 void hsw_enable_ips(struct intel_crtc *crtc);
1136 void hsw_disable_ips(struct intel_crtc *crtc);
1137 enum intel_display_power_domain
1138 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1139 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1140                                  struct intel_crtc_state *pipe_config);
1141 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1142 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1143
1144 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1145 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1146
1147 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1148                                      struct drm_i915_gem_object *obj);
1149 u32 skl_plane_ctl_format(uint32_t pixel_format);
1150 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1151 u32 skl_plane_ctl_rotation(unsigned int rotation);
1152
1153 /* intel_csr.c */
1154 void intel_csr_ucode_init(struct drm_device *dev);
1155 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1156 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1157                                         enum csr_state state);
1158 void intel_csr_load_program(struct drm_device *dev);
1159 void intel_csr_ucode_fini(struct drm_device *dev);
1160 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1161
1162 /* intel_dp.c */
1163 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1164 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1165                              struct intel_connector *intel_connector);
1166 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1167                               const struct intel_crtc_state *pipe_config);
1168 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1169 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1170 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1171 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1172 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1173 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1174 bool intel_dp_compute_config(struct intel_encoder *encoder,
1175                              struct intel_crtc_state *pipe_config);
1176 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1177 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1178                                   bool long_hpd);
1179 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1180 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1181 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1182 void intel_edp_panel_on(struct intel_dp *intel_dp);
1183 void intel_edp_panel_off(struct intel_dp *intel_dp);
1184 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1185 void intel_dp_mst_suspend(struct drm_device *dev);
1186 void intel_dp_mst_resume(struct drm_device *dev);
1187 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1188 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1189 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1190 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1191 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1192 void intel_plane_destroy(struct drm_plane *plane);
1193 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1194 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1195 void intel_edp_drrs_invalidate(struct drm_device *dev,
1196                 unsigned frontbuffer_bits);
1197 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1198
1199 /* intel_dp_mst.c */
1200 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1201 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1202 /* intel_dsi.c */
1203 void intel_dsi_init(struct drm_device *dev);
1204
1205
1206 /* intel_dvo.c */
1207 void intel_dvo_init(struct drm_device *dev);
1208
1209
1210 /* legacy fbdev emulation in intel_fbdev.c */
1211 #ifdef CONFIG_DRM_I915_FBDEV
1212 extern int intel_fbdev_init(struct drm_device *dev);
1213 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1214 extern void intel_fbdev_fini(struct drm_device *dev);
1215 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1216 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1217 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1218 #else
1219 static inline int intel_fbdev_init(struct drm_device *dev)
1220 {
1221         return 0;
1222 }
1223
1224 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1225 {
1226 }
1227
1228 static inline void intel_fbdev_fini(struct drm_device *dev)
1229 {
1230 }
1231
1232 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1233 {
1234 }
1235
1236 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1237 {
1238 }
1239 #endif
1240
1241 /* intel_fbc.c */
1242 bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
1243 void intel_fbc_update(struct drm_i915_private *dev_priv);
1244 void intel_fbc_init(struct drm_i915_private *dev_priv);
1245 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1246 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1247 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1248                           unsigned int frontbuffer_bits,
1249                           enum fb_op_origin origin);
1250 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1251                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1252 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1253 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1254
1255 /* intel_hdmi.c */
1256 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1257 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1258                                struct intel_connector *intel_connector);
1259 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1260 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1261                                struct intel_crtc_state *pipe_config);
1262
1263
1264 /* intel_lvds.c */
1265 void intel_lvds_init(struct drm_device *dev);
1266 bool intel_is_dual_link_lvds(struct drm_device *dev);
1267
1268
1269 /* intel_modes.c */
1270 int intel_connector_update_modes(struct drm_connector *connector,
1271                                  struct edid *edid);
1272 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1273 void intel_attach_force_audio_property(struct drm_connector *connector);
1274 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1275
1276
1277 /* intel_overlay.c */
1278 void intel_setup_overlay(struct drm_device *dev);
1279 void intel_cleanup_overlay(struct drm_device *dev);
1280 int intel_overlay_switch_off(struct intel_overlay *overlay);
1281 int intel_overlay_put_image(struct drm_device *dev, void *data,
1282                             struct drm_file *file_priv);
1283 int intel_overlay_attrs(struct drm_device *dev, void *data,
1284                         struct drm_file *file_priv);
1285 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1286
1287
1288 /* intel_panel.c */
1289 int intel_panel_init(struct intel_panel *panel,
1290                      struct drm_display_mode *fixed_mode,
1291                      struct drm_display_mode *downclock_mode);
1292 void intel_panel_fini(struct intel_panel *panel);
1293 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1294                             struct drm_display_mode *adjusted_mode);
1295 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1296                              struct intel_crtc_state *pipe_config,
1297                              int fitting_mode);
1298 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1299                               struct intel_crtc_state *pipe_config,
1300                               int fitting_mode);
1301 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1302                                     u32 level, u32 max);
1303 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1304 void intel_panel_enable_backlight(struct intel_connector *connector);
1305 void intel_panel_disable_backlight(struct intel_connector *connector);
1306 void intel_panel_destroy_backlight(struct drm_connector *connector);
1307 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1308 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1309 extern struct drm_display_mode *intel_find_panel_downclock(
1310                                 struct drm_device *dev,
1311                                 struct drm_display_mode *fixed_mode,
1312                                 struct drm_connector *connector);
1313 void intel_backlight_register(struct drm_device *dev);
1314 void intel_backlight_unregister(struct drm_device *dev);
1315
1316
1317 /* intel_psr.c */
1318 void intel_psr_enable(struct intel_dp *intel_dp);
1319 void intel_psr_disable(struct intel_dp *intel_dp);
1320 void intel_psr_invalidate(struct drm_device *dev,
1321                           unsigned frontbuffer_bits);
1322 void intel_psr_flush(struct drm_device *dev,
1323                      unsigned frontbuffer_bits,
1324                      enum fb_op_origin origin);
1325 void intel_psr_init(struct drm_device *dev);
1326 void intel_psr_single_frame_update(struct drm_device *dev,
1327                                    unsigned frontbuffer_bits);
1328
1329 /* intel_runtime_pm.c */
1330 int intel_power_domains_init(struct drm_i915_private *);
1331 void intel_power_domains_fini(struct drm_i915_private *);
1332 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1333 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1334
1335 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1336                                     enum intel_display_power_domain domain);
1337 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1338                                       enum intel_display_power_domain domain);
1339 void intel_display_power_get(struct drm_i915_private *dev_priv,
1340                              enum intel_display_power_domain domain);
1341 void intel_display_power_put(struct drm_i915_private *dev_priv,
1342                              enum intel_display_power_domain domain);
1343 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1344 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1345 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1346 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1347 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1348
1349 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1350
1351 /* intel_pm.c */
1352 void intel_init_clock_gating(struct drm_device *dev);
1353 void intel_suspend_hw(struct drm_device *dev);
1354 int ilk_wm_max_level(const struct drm_device *dev);
1355 void intel_update_watermarks(struct drm_crtc *crtc);
1356 void intel_update_sprite_watermarks(struct drm_plane *plane,
1357                                     struct drm_crtc *crtc,
1358                                     uint32_t sprite_width,
1359                                     uint32_t sprite_height,
1360                                     int pixel_size,
1361                                     bool enabled, bool scaled);
1362 void intel_init_pm(struct drm_device *dev);
1363 void intel_pm_setup(struct drm_device *dev);
1364 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1365 void intel_gpu_ips_teardown(void);
1366 void intel_init_gt_powersave(struct drm_device *dev);
1367 void intel_cleanup_gt_powersave(struct drm_device *dev);
1368 void intel_enable_gt_powersave(struct drm_device *dev);
1369 void intel_disable_gt_powersave(struct drm_device *dev);
1370 void intel_suspend_gt_powersave(struct drm_device *dev);
1371 void intel_reset_gt_powersave(struct drm_device *dev);
1372 void gen6_update_ring_freq(struct drm_device *dev);
1373 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1374 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1375 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1376 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1377                     struct intel_rps_client *rps,
1378                     unsigned long submitted);
1379 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1380                                        struct drm_i915_gem_request *req);
1381 void vlv_wm_get_hw_state(struct drm_device *dev);
1382 void ilk_wm_get_hw_state(struct drm_device *dev);
1383 void skl_wm_get_hw_state(struct drm_device *dev);
1384 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1385                           struct skl_ddb_allocation *ddb /* out */);
1386 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1387
1388 /* intel_sdvo.c */
1389 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1390
1391
1392 /* intel_sprite.c */
1393 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1394 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1395                               struct drm_file *file_priv);
1396 void intel_pipe_update_start(struct intel_crtc *crtc,
1397                              uint32_t *start_vbl_count);
1398 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1399
1400 /* intel_tv.c */
1401 void intel_tv_init(struct drm_device *dev);
1402
1403 /* intel_atomic.c */
1404 int intel_connector_atomic_get_property(struct drm_connector *connector,
1405                                         const struct drm_connector_state *state,
1406                                         struct drm_property *property,
1407                                         uint64_t *val);
1408 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1409 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1410                                struct drm_crtc_state *state);
1411 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1412 void intel_atomic_state_clear(struct drm_atomic_state *);
1413 struct intel_shared_dpll_config *
1414 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1415
1416 static inline struct intel_crtc_state *
1417 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1418                             struct intel_crtc *crtc)
1419 {
1420         struct drm_crtc_state *crtc_state;
1421         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1422         if (IS_ERR(crtc_state))
1423                 return ERR_CAST(crtc_state);
1424
1425         return to_intel_crtc_state(crtc_state);
1426 }
1427 int intel_atomic_setup_scalers(struct drm_device *dev,
1428         struct intel_crtc *intel_crtc,
1429         struct intel_crtc_state *crtc_state);
1430
1431 /* intel_atomic_plane.c */
1432 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1433 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1434 void intel_plane_destroy_state(struct drm_plane *plane,
1435                                struct drm_plane_state *state);
1436 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1437
1438 #endif /* __INTEL_DRV_H__ */