drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         struct list_head fbdev_list;
 127         struct drm_display_mode *our_mode;
 128         int preferred_bpp;
 129 };
 130
 131 struct intel_encoder {
 132         struct drm_encoder base;
 133
 134         enum intel_output_type type;
 135         unsigned int cloneable;
 136         bool connectors_active;
 137         void (*hot_plug)(struct intel_encoder *);
 138         bool (*compute_config)(struct intel_encoder *,
 139                                struct intel_crtc_state *);
 140         void (*pre_pll_enable)(struct intel_encoder *);
 141         void (*pre_enable)(struct intel_encoder *);
 142         void (*enable)(struct intel_encoder *);
 143         void (*mode_set)(struct intel_encoder *intel_encoder);
 144         void (*disable)(struct intel_encoder *);
 145         void (*post_disable)(struct intel_encoder *);
 146         /* Read out the current hw state of this connector, returning true if
 147          * the encoder is active. If the encoder is enabled it also set the pipe
 148          * it is connected to in the pipe parameter. */
 149         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 150         /* Reconstructs the equivalent mode flags for the current hardware
 151          * state. This must be called _after_ display->get_pipe_config has
 152          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 153          * be set correctly before calling this function. */
 154         void (*get_config)(struct intel_encoder *,
 155                            struct intel_crtc_state *pipe_config);
 156         /*
 157          * Called during system suspend after all pending requests for the
 158          * encoder are flushed (for example for DP AUX transactions) and
 159          * device interrupts are disabled.
 160          */
 161         void (*suspend)(struct intel_encoder *);
 162         int crtc_mask;
 163         enum hpd_pin hpd_pin;
 164 };
 165
 166 struct intel_panel {
 167         struct drm_display_mode *fixed_mode;
 168         struct drm_display_mode *downclock_mode;
 169         int fitting_mode;
 170
 171         /* backlight */
 172         struct {
 173                 bool present;
 174                 u32 level;
 175                 u32 min;
 176                 u32 max;
 177                 bool enabled;
 178                 bool combination_mode;  /* gen 2/4 only */
 179                 bool active_low_pwm;
 180                 struct backlight_device *device;
 181         } backlight;
 182
 183         void (*backlight_power)(struct intel_connector *, bool enable);
 184 };
 185
 186 struct intel_connector {
 187         struct drm_connector base;
 188         /*
 189          * The fixed encoder this connector is connected to.
 190          */
 191         struct intel_encoder *encoder;
 192
 193         /* Reads out the current hw, returning true if the connector is enabled
 194          * and active (i.e. dpms ON state). */
 195         bool (*get_hw_state)(struct intel_connector *);
 196
 197         /*
 198          * Removes all interfaces through which the connector is accessible
 199          * - like sysfs, debugfs entries -, so that no new operations can be
 200          * started on the connector. Also makes sure all currently pending
 201          * operations finish before returing.
 202          */
 203         void (*unregister)(struct intel_connector *);
 204
 205         /* Panel info for eDP and LVDS */
 206         struct intel_panel panel;
 207
 208         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 209         struct edid *edid;
 210         struct edid *detect_edid;
 211
 212         /* since POLL and HPD connectors may use the same HPD line keep the native
 213            state of connector->polled in case hotplug storm detection changes it */
 214         u8 polled;
 215
 216         void *port; /* store this opaque as its illegal to dereference it */
 217
 218         struct intel_dp *mst_port;
 219 };
 220
 221 typedef struct dpll {
 222         /* given values */
 223         int n;
 224         int m1, m2;
 225         int p1, p2;
 226         /* derived values */
 227         int     dot;
 228         int     vco;
 229         int     m;
 230         int     p;
 231 } intel_clock_t;
 232
 233 struct intel_atomic_state {
 234         struct drm_atomic_state base;
 235
 236         unsigned int cdclk;
 237         bool dpll_set;
 238         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 239 };
 240
 241 struct intel_plane_state {
 242         struct drm_plane_state base;
 243         struct drm_rect src;
 244         struct drm_rect dst;
 245         struct drm_rect clip;
 246         bool visible;
 247
 248         /*
 249          * scaler_id
 250          *    = -1 : not using a scaler
 251          *    >=  0 : using a scalers
 252          *
 253          * plane requiring a scaler:
 254          *   - During check_plane, its bit is set in
 255          *     crtc_state->scaler_state.scaler_users by calling helper function
 256          *     update_scaler_plane.
 257          *   - scaler_id indicates the scaler it got assigned.
 258          *
 259          * plane doesn't require a scaler:
 260          *   - this can happen when scaling is no more required or plane simply
 261          *     got disabled.
 262          *   - During check_plane, corresponding bit is reset in
 263          *     crtc_state->scaler_state.scaler_users by calling helper function
 264          *     update_scaler_plane.
 265          */
 266         int scaler_id;
 267
 268         struct drm_intel_sprite_colorkey ckey;
 269 };
 270
 271 struct intel_initial_plane_config {
 272         struct intel_framebuffer *fb;
 273         unsigned int tiling;
 274         int size;
 275         u32 base;
 276 };
 277
 278 #define SKL_MIN_SRC_W 8
 279 #define SKL_MAX_SRC_W 4096
 280 #define SKL_MIN_SRC_H 8
 281 #define SKL_MAX_SRC_H 4096
 282 #define SKL_MIN_DST_W 8
 283 #define SKL_MAX_DST_W 4096
 284 #define SKL_MIN_DST_H 8
 285 #define SKL_MAX_DST_H 4096
 286
 287 struct intel_scaler {
 288         int in_use;
 289         uint32_t mode;
 290 };
 291
 292 struct intel_crtc_scaler_state {
 293 #define SKL_NUM_SCALERS 2
 294         struct intel_scaler scalers[SKL_NUM_SCALERS];
 295
 296         /*
 297          * scaler_users: keeps track of users requesting scalers on this crtc.
 298          *
 299          *     If a bit is set, a user is using a scaler.
 300          *     Here user can be a plane or crtc as defined below:
 301          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 302          *       bit 31    - crtc
 303          *
 304          * Instead of creating a new index to cover planes and crtc, using
 305          * existing drm_plane_index for planes which is well less than 31
 306          * planes and bit 31 for crtc. This should be fine to cover all
 307          * our platforms.
 308          *
 309          * intel_atomic_setup_scalers will setup available scalers to users
 310          * requesting scalers. It will gracefully fail if request exceeds
 311          * avilability.
 312          */
 313 #define SKL_CRTC_INDEX 31
 314         unsigned scaler_users;
 315
 316         /* scaler used by crtc for panel fitting purpose */
 317         int scaler_id;
 318 };
 319
 320 struct intel_crtc_state {
 321         struct drm_crtc_state base;
 322
 323         /**
 324          * quirks - bitfield with hw state readout quirks
 325          *
 326          * For various reasons the hw state readout code might not be able to
 327          * completely faithfully read out the current state. These cases are
 328          * tracked with quirk flags so that fastboot and state checker can act
 329          * accordingly.
 330          */
 331 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 332 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 333         unsigned long quirks;
 334
 335         /* Pipe source size (ie. panel fitter input size)
 336          * All planes will be positioned inside this space,
 337          * and get clipped at the edges. */
 338         int pipe_src_w, pipe_src_h;
 339
 340         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 341          * between pch encoders and cpu encoders. */
 342         bool has_pch_encoder;
 343
 344         /* Are we sending infoframes on the attached port */
 345         bool has_infoframe;
 346
 347         /* CPU Transcoder for the pipe. Currently this can only differ from the
 348          * pipe on Haswell (where we have a special eDP transcoder). */
 349         enum transcoder cpu_transcoder;
 350
 351         /*
 352          * Use reduced/limited/broadcast rbg range, compressing from the full
 353          * range fed into the crtcs.
 354          */
 355         bool limited_color_range;
 356
 357         /* DP has a bunch of special case unfortunately, so mark the pipe
 358          * accordingly. */
 359         bool has_dp_encoder;
 360
 361         /* Whether we should send NULL infoframes. Required for audio. */
 362         bool has_hdmi_sink;
 363
 364         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 365          * has_dp_encoder is set. */
 366         bool has_audio;
 367
 368         /*
 369          * Enable dithering, used when the selected pipe bpp doesn't match the
 370          * plane bpp.
 371          */
 372         bool dither;
 373
 374         /* Controls for the clock computation, to override various stages. */
 375         bool clock_set;
 376
 377         /* SDVO TV has a bunch of special case. To make multifunction encoders
 378          * work correctly, we need to track this at runtime.*/
 379         bool sdvo_tv_clock;
 380
 381         /*
 382          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 383          * required. This is set in the 2nd loop of calling encoder's
 384          * ->compute_config if the first pick doesn't work out.
 385          */
 386         bool bw_constrained;
 387
 388         /* Settings for the intel dpll used on pretty much everything but
 389          * haswell. */
 390         struct dpll dpll;
 391
 392         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 393         enum intel_dpll_id shared_dpll;
 394
 395         /*
 396          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 397          * - enum skl_dpll on SKL
 398          */
 399         uint32_t ddi_pll_sel;
 400
 401         /* Actual register state of the dpll, for shared dpll cross-checking. */
 402         struct intel_dpll_hw_state dpll_hw_state;
 403
 404         int pipe_bpp;
 405         struct intel_link_m_n dp_m_n;
 406
 407         /* m2_n2 for eDP downclock */
 408         struct intel_link_m_n dp_m2_n2;
 409         bool has_drrs;
 410
 411         /*
 412          * Frequence the dpll for the port should run at. Differs from the
 413          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 414          * already multiplied by pixel_multiplier.
 415          */
 416         int port_clock;
 417
 418         /* Used by SDVO (and if we ever fix it, HDMI). */
 419         unsigned pixel_multiplier;
 420
 421         /* Panel fitter controls for gen2-gen4 + VLV */
 422         struct {
 423                 u32 control;
 424                 u32 pgm_ratios;
 425                 u32 lvds_border_bits;
 426         } gmch_pfit;
 427
 428         /* Panel fitter placement and size for Ironlake+ */
 429         struct {
 430                 u32 pos;
 431                 u32 size;
 432                 bool enabled;
 433                 bool force_thru;
 434         } pch_pfit;
 435
 436         /* FDI configuration, only valid if has_pch_encoder is set. */
 437         int fdi_lanes;
 438         struct intel_link_m_n fdi_m_n;
 439
 440         bool ips_enabled;
 441
 442         bool double_wide;
 443
 444         bool dp_encoder_is_mst;
 445         int pbn;
 446
 447         struct intel_crtc_scaler_state scaler_state;
 448
 449         /* w/a for waiting 2 vblanks during crtc enable */
 450         enum pipe hsw_workaround_pipe;
 451 };
 452
 453 struct vlv_wm_state {
 454         struct vlv_pipe_wm wm[3];
 455         struct vlv_sr_wm sr[3];
 456         uint8_t num_active_planes;
 457         uint8_t num_levels;
 458         uint8_t level;
 459         bool cxsr;
 460 };
 461
 462 struct intel_pipe_wm {
 463         struct intel_wm_level wm[5];
 464         uint32_t linetime;
 465         bool fbc_wm_enabled;
 466         bool pipe_enabled;
 467         bool sprites_enabled;
 468         bool sprites_scaled;
 469 };
 470
 471 struct intel_mmio_flip {
 472         struct work_struct work;
 473         struct drm_i915_private *i915;
 474         struct drm_i915_gem_request *req;
 475         struct intel_crtc *crtc;
 476 };
 477
 478 struct skl_pipe_wm {
 479         struct skl_wm_level wm[8];
 480         struct skl_wm_level trans_wm;
 481         uint32_t linetime;
 482 };
 483
 484 /*
 485  * Tracking of operations that need to be performed at the beginning/end of an
 486  * atomic commit, outside the atomic section where interrupts are disabled.
 487  * These are generally operations that grab mutexes or might otherwise sleep
 488  * and thus can't be run with interrupts disabled.
 489  */
 490 struct intel_crtc_atomic_commit {
 491         /* vblank evasion */
 492         bool evade;
 493         unsigned start_vbl_count;
 494
 495         /* Sleepable operations to perform before commit */
 496         bool wait_for_flips;
 497         bool disable_fbc;
 498         bool disable_ips;
 499         bool disable_cxsr;
 500         bool pre_disable_primary;
 501         bool update_wm_pre, update_wm_post;
 502         unsigned disabled_planes;
 503
 504         /* Sleepable operations to perform after commit */
 505         unsigned fb_bits;
 506         bool wait_vblank;
 507         bool update_fbc;
 508         bool post_enable_primary;
 509         unsigned update_sprite_watermarks;
 510 };
 511
 512 struct intel_crtc {
 513         struct drm_crtc base;
 514         enum pipe pipe;
 515         enum plane plane;
 516         u8 lut_r[256], lut_g[256], lut_b[256];
 517         /*
 518          * Whether the crtc and the connected output pipeline is active. Implies
 519          * that crtc->enabled is set, i.e. the current mode configuration has
 520          * some outputs connected to this crtc.
 521          */
 522         bool active;
 523         unsigned long enabled_power_domains;
 524         bool lowfreq_avail;
 525         struct intel_overlay *overlay;
 526         struct intel_unpin_work *unpin_work;
 527
 528         atomic_t unpin_work_count;
 529
 530         /* Display surface base address adjustement for pageflips. Note that on
 531          * gen4+ this only adjusts up to a tile, offsets within a tile are
 532          * handled in the hw itself (with the TILEOFF register). */
 533         unsigned long dspaddr_offset;
 534
 535         struct drm_i915_gem_object *cursor_bo;
 536         uint32_t cursor_addr;
 537         uint32_t cursor_cntl;
 538         uint32_t cursor_size;
 539         uint32_t cursor_base;
 540
 541         struct intel_crtc_state *config;
 542
 543         /* reset counter value when the last flip was submitted */
 544         unsigned int reset_counter;
 545
 546         /* Access to these should be protected by dev_priv->irq_lock. */
 547         bool cpu_fifo_underrun_disabled;
 548         bool pch_fifo_underrun_disabled;
 549
 550         /* per-pipe watermark state */
 551         struct {
 552                 /* watermarks currently being used  */
 553                 struct intel_pipe_wm active;
 554                 /* SKL wm values currently in use */
 555                 struct skl_pipe_wm skl_active;
 556                 /* allow CxSR on this pipe */
 557                 bool cxsr_allowed;
 558         } wm;
 559
 560         int scanline_offset;
 561
 562         struct intel_crtc_atomic_commit atomic;
 563
 564         /* scalers available on this crtc */
 565         int num_scalers;
 566
 567         struct vlv_wm_state wm_state;
 568 };
 569
 570 struct intel_plane_wm_parameters {
 571         uint32_t horiz_pixels;
 572         uint32_t vert_pixels;
 573         /*
 574          *   For packed pixel formats:
 575          *     bytes_per_pixel - holds bytes per pixel
 576          *   For planar pixel formats:
 577          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 578          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 579          */
 580         uint8_t bytes_per_pixel;
 581         uint8_t y_bytes_per_pixel;
 582         bool enabled;
 583         bool scaled;
 584         u64 tiling;
 585         unsigned int rotation;
 586         uint16_t fifo_size;
 587 };
 588
 589 struct intel_plane {
 590         struct drm_plane base;
 591         int plane;
 592         enum pipe pipe;
 593         bool can_scale;
 594         int max_downscale;
 595         uint32_t frontbuffer_bit;
 596
 597         /* Since we need to change the watermarks before/after
 598          * enabling/disabling the planes, we need to store the parameters here
 599          * as the other pieces of the struct may not reflect the values we want
 600          * for the watermark calculations. Currently only Haswell uses this.
 601          */
 602         struct intel_plane_wm_parameters wm;
 603
 604         /*
 605          * NOTE: Do not place new plane state fields here (e.g., when adding
 606          * new plane properties).  New runtime state should now be placed in
 607          * the intel_plane_state structure and accessed via drm_plane->state.
 608          */
 609
 610         void (*update_plane)(struct drm_plane *plane,
 611                              struct drm_crtc *crtc,
 612                              struct drm_framebuffer *fb,
 613                              int crtc_x, int crtc_y,
 614                              unsigned int crtc_w, unsigned int crtc_h,
 615                              uint32_t x, uint32_t y,
 616                              uint32_t src_w, uint32_t src_h);
 617         void (*disable_plane)(struct drm_plane *plane,
 618                               struct drm_crtc *crtc);
 619         int (*check_plane)(struct drm_plane *plane,
 620                            struct intel_crtc_state *crtc_state,
 621                            struct intel_plane_state *state);
 622         void (*commit_plane)(struct drm_plane *plane,
 623                              struct intel_plane_state *state);
 624 };
 625
 626 struct intel_watermark_params {
 627         unsigned long fifo_size;
 628         unsigned long max_wm;
 629         unsigned long default_wm;
 630         unsigned long guard_size;
 631         unsigned long cacheline_size;
 632 };
 633
 634 struct cxsr_latency {
 635         int is_desktop;
 636         int is_ddr3;
 637         unsigned long fsb_freq;
 638         unsigned long mem_freq;
 639         unsigned long display_sr;
 640         unsigned long display_hpll_disable;
 641         unsigned long cursor_sr;
 642         unsigned long cursor_hpll_disable;
 643 };
 644
 645 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 646 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 647 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 648 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 649 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 650 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 651 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 652 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 653 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 654
 655 struct intel_hdmi {
 656         u32 hdmi_reg;
 657         int ddc_bus;
 658         uint32_t color_range;
 659         bool color_range_auto;
 660         bool has_hdmi_sink;
 661         bool has_audio;
 662         enum hdmi_force_audio force_audio;
 663         bool rgb_quant_range_selectable;
 664         enum hdmi_picture_aspect aspect_ratio;
 665         void (*write_infoframe)(struct drm_encoder *encoder,
 666                                 enum hdmi_infoframe_type type,
 667                                 const void *frame, ssize_t len);
 668         void (*set_infoframes)(struct drm_encoder *encoder,
 669                                bool enable,
 670                                struct drm_display_mode *adjusted_mode);
 671         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 672 };
 673
 674 struct intel_dp_mst_encoder;
 675 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 676
 677 /*
 678  * enum link_m_n_set:
 679  *      When platform provides two set of M_N registers for dp, we can
 680  *      program them and switch between them incase of DRRS.
 681  *      But When only one such register is provided, we have to program the
 682  *      required divider value on that registers itself based on the DRRS state.
 683  *
 684  * M1_N1        : Program dp_m_n on M1_N1 registers
 685  *                        dp_m2_n2 on M2_N2 registers (If supported)
 686  *
 687  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 688  *                        M2_N2 registers are not supported
 689  */
 690
 691 enum link_m_n_set {
 692         /* Sets the m1_n1 and m2_n2 */
 693         M1_N1 = 0,
 694         M2_N2
 695 };
 696
 697 struct intel_dp {
 698         uint32_t output_reg;
 699         uint32_t aux_ch_ctl_reg;
 700         uint32_t DP;
 701         bool has_audio;
 702         enum hdmi_force_audio force_audio;
 703         uint32_t color_range;
 704         bool color_range_auto;
 705         uint8_t link_bw;
 706         uint8_t rate_select;
 707         uint8_t lane_count;
 708         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 709         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 710         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 711         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 712         uint8_t num_sink_rates;
 713         int sink_rates[DP_MAX_SUPPORTED_RATES];
 714         struct drm_dp_aux aux;
 715         uint8_t train_set[4];
 716         int panel_power_up_delay;
 717         int panel_power_down_delay;
 718         int panel_power_cycle_delay;
 719         int backlight_on_delay;
 720         int backlight_off_delay;
 721         struct delayed_work panel_vdd_work;
 722         bool want_panel_vdd;
 723         unsigned long last_power_cycle;
 724         unsigned long last_power_on;
 725         unsigned long last_backlight_off;
 726
 727         struct notifier_block edp_notifier;
 728
 729         /*
 730          * Pipe whose power sequencer is currently locked into
 731          * this port. Only relevant on VLV/CHV.
 732          */
 733         enum pipe pps_pipe;
 734         struct edp_power_seq pps_delays;
 735
 736         bool use_tps3;
 737         bool can_mst; /* this port supports mst */
 738         bool is_mst;
 739         int active_mst_links;
 740         /* connector directly attached - won't be use for modeset in mst world */
 741         struct intel_connector *attached_connector;
 742
 743         /* mst connector list */
 744         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 745         struct drm_dp_mst_topology_mgr mst_mgr;
 746
 747         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 748         /*
 749          * This function returns the value we have to program the AUX_CTL
 750          * register with to kick off an AUX transaction.
 751          */
 752         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 753                                      bool has_aux_irq,
 754                                      int send_bytes,
 755                                      uint32_t aux_clock_divider);
 756         bool train_set_valid;
 757
 758         /* Displayport compliance testing */
 759         unsigned long compliance_test_type;
 760         unsigned long compliance_test_data;
 761         bool compliance_test_active;
 762 };
 763
 764 struct intel_digital_port {
 765         struct intel_encoder base;
 766         enum port port;
 767         u32 saved_port_bits;
 768         struct intel_dp dp;
 769         struct intel_hdmi hdmi;
 770         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 771 };
 772
 773 struct intel_dp_mst_encoder {
 774         struct intel_encoder base;
 775         enum pipe pipe;
 776         struct intel_digital_port *primary;
 777         void *port; /* store this opaque as its illegal to dereference it */
 778 };
 779
 780 static inline int
 781 vlv_dport_to_channel(struct intel_digital_port *dport)
 782 {
 783         switch (dport->port) {
 784         case PORT_B:
 785         case PORT_D:
 786                 return DPIO_CH0;
 787         case PORT_C:
 788                 return DPIO_CH1;
 789         default:
 790                 BUG();
 791         }
 792 }
 793
 794 static inline int
 795 vlv_pipe_to_channel(enum pipe pipe)
 796 {
 797         switch (pipe) {
 798         case PIPE_A:
 799         case PIPE_C:
 800                 return DPIO_CH0;
 801         case PIPE_B:
 802                 return DPIO_CH1;
 803         default:
 804                 BUG();
 805         }
 806 }
 807
 808 static inline struct drm_crtc *
 809 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         return dev_priv->pipe_to_crtc_mapping[pipe];
 813 }
 814
 815 static inline struct drm_crtc *
 816 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 817 {
 818         struct drm_i915_private *dev_priv = dev->dev_private;
 819         return dev_priv->plane_to_crtc_mapping[plane];
 820 }
 821
 822 struct intel_unpin_work {
 823         struct work_struct work;
 824         struct drm_crtc *crtc;
 825         struct drm_framebuffer *old_fb;
 826         struct drm_i915_gem_object *pending_flip_obj;
 827         struct drm_pending_vblank_event *event;
 828         atomic_t pending;
 829 #define INTEL_FLIP_INACTIVE     0
 830 #define INTEL_FLIP_PENDING      1
 831 #define INTEL_FLIP_COMPLETE     2
 832         u32 flip_count;
 833         u32 gtt_offset;
 834         struct drm_i915_gem_request *flip_queued_req;
 835         int flip_queued_vblank;
 836         int flip_ready_vblank;
 837         bool enable_stall_check;
 838 };
 839
 840 struct intel_load_detect_pipe {
 841         struct drm_framebuffer *release_fb;
 842         bool load_detect_temp;
 843         int dpms_mode;
 844 };
 845
 846 static inline struct intel_encoder *
 847 intel_attached_encoder(struct drm_connector *connector)
 848 {
 849         return to_intel_connector(connector)->encoder;
 850 }
 851
 852 static inline struct intel_digital_port *
 853 enc_to_dig_port(struct drm_encoder *encoder)
 854 {
 855         return container_of(encoder, struct intel_digital_port, base.base);
 856 }
 857
 858 static inline struct intel_dp_mst_encoder *
 859 enc_to_mst(struct drm_encoder *encoder)
 860 {
 861         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 862 }
 863
 864 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 865 {
 866         return &enc_to_dig_port(encoder)->dp;
 867 }
 868
 869 static inline struct intel_digital_port *
 870 dp_to_dig_port(struct intel_dp *intel_dp)
 871 {
 872         return container_of(intel_dp, struct intel_digital_port, dp);
 873 }
 874
 875 static inline struct intel_digital_port *
 876 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 877 {
 878         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 879 }
 880
 881 /*
 882  * Returns the number of planes for this pipe, ie the number of sprites + 1
 883  * (primary plane). This doesn't count the cursor plane then.
 884  */
 885 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 886 {
 887         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 888 }
 889
 890 /* intel_fifo_underrun.c */
 891 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 892                                            enum pipe pipe, bool enable);
 893 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 894                                            enum transcoder pch_transcoder,
 895                                            bool enable);
 896 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 897                                          enum pipe pipe);
 898 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 899                                          enum transcoder pch_transcoder);
 900 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 901
 902 /* i915_irq.c */
 903 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 904 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 905 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 906 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 907 void gen6_reset_rps_interrupts(struct drm_device *dev);
 908 void gen6_enable_rps_interrupts(struct drm_device *dev);
 909 void gen6_disable_rps_interrupts(struct drm_device *dev);
 910 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 911 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 912 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 913 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 914 {
 915         /*
 916          * We only use drm_irq_uninstall() at unload and VT switch, so
 917          * this is the only thing we need to check.
 918          */
 919         return dev_priv->pm.irqs_enabled;
 920 }
 921
 922 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 923 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 924                                      unsigned int pipe_mask);
 925
 926 /* intel_crt.c */
 927 void intel_crt_init(struct drm_device *dev);
 928
 929
 930 /* intel_ddi.c */
 931 void intel_prepare_ddi(struct drm_device *dev);
 932 void hsw_fdi_link_train(struct drm_crtc *crtc);
 933 void intel_ddi_init(struct drm_device *dev, enum port port);
 934 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 935 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 936 void intel_ddi_pll_init(struct drm_device *dev);
 937 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 938 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 939                                        enum transcoder cpu_transcoder);
 940 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 941 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 942 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 943                           struct intel_crtc_state *crtc_state);
 944 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 945 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 946 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 947 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 948 void intel_ddi_get_config(struct intel_encoder *encoder,
 949                           struct intel_crtc_state *pipe_config);
 950 struct intel_encoder *
 951 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
 952
 953 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 954 void intel_ddi_clock_get(struct intel_encoder *encoder,
 955                          struct intel_crtc_state *pipe_config);
 956 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 957 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 958
 959 /* intel_frontbuffer.c */
 960 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 961                              enum fb_op_origin origin);
 962 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 963                                     unsigned frontbuffer_bits);
 964 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 965                                      unsigned frontbuffer_bits);
 966 void intel_frontbuffer_flip(struct drm_device *dev,
 967                             unsigned frontbuffer_bits);
 968 unsigned int intel_fb_align_height(struct drm_device *dev,
 969                                    unsigned int height,
 970                                    uint32_t pixel_format,
 971                                    uint64_t fb_format_modifier);
 972 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
 973                         enum fb_op_origin origin);
 974 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
 975                               uint32_t pixel_format);
 976
 977 /* intel_audio.c */
 978 void intel_init_audio(struct drm_device *dev);
 979 void intel_audio_codec_enable(struct intel_encoder *encoder);
 980 void intel_audio_codec_disable(struct intel_encoder *encoder);
 981 void i915_audio_component_init(struct drm_i915_private *dev_priv);
 982 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
 983
 984 /* intel_display.c */
 985 extern const struct drm_plane_funcs intel_plane_funcs;
 986 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 987 int intel_pch_rawclk(struct drm_device *dev);
 988 void intel_mark_busy(struct drm_device *dev);
 989 void intel_mark_idle(struct drm_device *dev);
 990 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 991 void intel_display_suspend(struct drm_device *dev);
 992 int intel_crtc_control(struct drm_crtc *crtc, bool enable);
 993 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 994 void intel_encoder_destroy(struct drm_encoder *encoder);
 995 int intel_connector_init(struct intel_connector *);
 996 struct intel_connector *intel_connector_alloc(void);
 997 void intel_connector_dpms(struct drm_connector *, int mode);
 998 bool intel_connector_get_hw_state(struct intel_connector *connector);
 999 void intel_modeset_check_state(struct drm_device *dev);
1000 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1001                                 struct intel_digital_port *port);
1002 void intel_connector_attach_encoder(struct intel_connector *connector,
1003                                     struct intel_encoder *encoder);
1004 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1005 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1006                                              struct drm_crtc *crtc);
1007 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1008 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1009                                 struct drm_file *file_priv);
1010 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1011                                              enum pipe pipe);
1012 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1013 static inline void
1014 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1015 {
1016         drm_wait_one_vblank(dev, pipe);
1017 }
1018 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1019 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1020                          struct intel_digital_port *dport,
1021                          unsigned int expected_mask);
1022 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1023                                 struct drm_display_mode *mode,
1024                                 struct intel_load_detect_pipe *old,
1025                                 struct drm_modeset_acquire_ctx *ctx);
1026 void intel_release_load_detect_pipe(struct drm_connector *connector,
1027                                     struct intel_load_detect_pipe *old,
1028                                     struct drm_modeset_acquire_ctx *ctx);
1029 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1030                                struct drm_framebuffer *fb,
1031                                const struct drm_plane_state *plane_state,
1032                                struct intel_engine_cs *pipelined,
1033                                struct drm_i915_gem_request **pipelined_request);
1034 struct drm_framebuffer *
1035 __intel_framebuffer_create(struct drm_device *dev,
1036                            struct drm_mode_fb_cmd2 *mode_cmd,
1037                            struct drm_i915_gem_object *obj);
1038 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1039 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1040 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1041 void intel_check_page_flip(struct drm_device *dev, int pipe);
1042 int intel_prepare_plane_fb(struct drm_plane *plane,
1043                            struct drm_framebuffer *fb,
1044                            const struct drm_plane_state *new_state);
1045 void intel_cleanup_plane_fb(struct drm_plane *plane,
1046                             struct drm_framebuffer *fb,
1047                             const struct drm_plane_state *old_state);
1048 int intel_plane_atomic_get_property(struct drm_plane *plane,
1049                                     const struct drm_plane_state *state,
1050                                     struct drm_property *property,
1051                                     uint64_t *val);
1052 int intel_plane_atomic_set_property(struct drm_plane *plane,
1053                                     struct drm_plane_state *state,
1054                                     struct drm_property *property,
1055                                     uint64_t val);
1056 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1057                                     struct drm_plane_state *plane_state);
1058
1059 unsigned int
1060 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1061                   uint64_t fb_format_modifier);
1062
1063 static inline bool
1064 intel_rotation_90_or_270(unsigned int rotation)
1065 {
1066         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1067 }
1068
1069 void intel_create_rotation_property(struct drm_device *dev,
1070                                         struct intel_plane *plane);
1071
1072 /* shared dpll functions */
1073 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1074 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1075                         struct intel_shared_dpll *pll,
1076                         bool state);
1077 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1078 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1079 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1080                                                 struct intel_crtc_state *state);
1081
1082 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1083                       const struct dpll *dpll);
1084 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1085
1086 /* modesetting asserts */
1087 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1088                            enum pipe pipe);
1089 void assert_pll(struct drm_i915_private *dev_priv,
1090                 enum pipe pipe, bool state);
1091 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1092 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1093 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1094                        enum pipe pipe, bool state);
1095 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1096 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1097 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1098 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1099 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1100 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1101                                              int *x, int *y,
1102                                              unsigned int tiling_mode,
1103                                              unsigned int bpp,
1104                                              unsigned int pitch);
1105 void intel_prepare_reset(struct drm_device *dev);
1106 void intel_finish_reset(struct drm_device *dev);
1107 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1108 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1109 void broxton_init_cdclk(struct drm_device *dev);
1110 void broxton_uninit_cdclk(struct drm_device *dev);
1111 void broxton_ddi_phy_init(struct drm_device *dev);
1112 void broxton_ddi_phy_uninit(struct drm_device *dev);
1113 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1114 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1115 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1116 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1117 void intel_dp_get_m_n(struct intel_crtc *crtc,
1118                       struct intel_crtc_state *pipe_config);
1119 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1120 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1121 void
1122 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1123                                 int dotclock);
1124 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1125                         intel_clock_t *best_clock);
1126 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1127
1128 bool intel_crtc_active(struct drm_crtc *crtc);
1129 void hsw_enable_ips(struct intel_crtc *crtc);
1130 void hsw_disable_ips(struct intel_crtc *crtc);
1131 enum intel_display_power_domain
1132 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1133 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1134                                  struct intel_crtc_state *pipe_config);
1135 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1136 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1137
1138 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1139 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1140
1141 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1142                                      struct drm_i915_gem_object *obj);
1143 u32 skl_plane_ctl_format(uint32_t pixel_format);
1144 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1145 u32 skl_plane_ctl_rotation(unsigned int rotation);
1146
1147 /* intel_csr.c */
1148 void intel_csr_ucode_init(struct drm_device *dev);
1149 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1150 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1151                                         enum csr_state state);
1152 void intel_csr_load_program(struct drm_device *dev);
1153 void intel_csr_ucode_fini(struct drm_device *dev);
1154 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1155
1156 /* intel_dp.c */
1157 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1158 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1159                              struct intel_connector *intel_connector);
1160 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1161 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1162 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1163 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1164 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1165 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1166 bool intel_dp_compute_config(struct intel_encoder *encoder,
1167                              struct intel_crtc_state *pipe_config);
1168 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1169 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1170                                   bool long_hpd);
1171 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1172 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1173 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1174 void intel_edp_panel_on(struct intel_dp *intel_dp);
1175 void intel_edp_panel_off(struct intel_dp *intel_dp);
1176 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1177 void intel_dp_mst_suspend(struct drm_device *dev);
1178 void intel_dp_mst_resume(struct drm_device *dev);
1179 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1180 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1181 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1182 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1183 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1184 void intel_plane_destroy(struct drm_plane *plane);
1185 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1186 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1187 void intel_edp_drrs_invalidate(struct drm_device *dev,
1188                 unsigned frontbuffer_bits);
1189 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1190
1191 /* intel_dp_mst.c */
1192 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1193 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1194 /* intel_dsi.c */
1195 void intel_dsi_init(struct drm_device *dev);
1196
1197
1198 /* intel_dvo.c */
1199 void intel_dvo_init(struct drm_device *dev);
1200
1201
1202 /* legacy fbdev emulation in intel_fbdev.c */
1203 #ifdef CONFIG_DRM_I915_FBDEV
1204 extern int intel_fbdev_init(struct drm_device *dev);
1205 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1206 extern void intel_fbdev_fini(struct drm_device *dev);
1207 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1208 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1209 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1210 #else
1211 static inline int intel_fbdev_init(struct drm_device *dev)
1212 {
1213         return 0;
1214 }
1215
1216 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1217 {
1218 }
1219
1220 static inline void intel_fbdev_fini(struct drm_device *dev)
1221 {
1222 }
1223
1224 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1225 {
1226 }
1227
1228 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1229 {
1230 }
1231 #endif
1232
1233 /* intel_fbc.c */
1234 bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
1235 void intel_fbc_update(struct drm_i915_private *dev_priv);
1236 void intel_fbc_init(struct drm_i915_private *dev_priv);
1237 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1238 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1239 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1240                           unsigned int frontbuffer_bits,
1241                           enum fb_op_origin origin);
1242 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1243                      unsigned int frontbuffer_bits);
1244 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1245 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1246
1247 /* intel_hdmi.c */
1248 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1249 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1250                                struct intel_connector *intel_connector);
1251 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1252 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1253                                struct intel_crtc_state *pipe_config);
1254
1255
1256 /* intel_lvds.c */
1257 void intel_lvds_init(struct drm_device *dev);
1258 bool intel_is_dual_link_lvds(struct drm_device *dev);
1259
1260
1261 /* intel_modes.c */
1262 int intel_connector_update_modes(struct drm_connector *connector,
1263                                  struct edid *edid);
1264 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1265 void intel_attach_force_audio_property(struct drm_connector *connector);
1266 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1267
1268
1269 /* intel_overlay.c */
1270 void intel_setup_overlay(struct drm_device *dev);
1271 void intel_cleanup_overlay(struct drm_device *dev);
1272 int intel_overlay_switch_off(struct intel_overlay *overlay);
1273 int intel_overlay_put_image(struct drm_device *dev, void *data,
1274                             struct drm_file *file_priv);
1275 int intel_overlay_attrs(struct drm_device *dev, void *data,
1276                         struct drm_file *file_priv);
1277 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1278
1279
1280 /* intel_panel.c */
1281 int intel_panel_init(struct intel_panel *panel,
1282                      struct drm_display_mode *fixed_mode,
1283                      struct drm_display_mode *downclock_mode);
1284 void intel_panel_fini(struct intel_panel *panel);
1285 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1286                             struct drm_display_mode *adjusted_mode);
1287 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1288                              struct intel_crtc_state *pipe_config,
1289                              int fitting_mode);
1290 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1291                               struct intel_crtc_state *pipe_config,
1292                               int fitting_mode);
1293 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1294                                     u32 level, u32 max);
1295 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1296 void intel_panel_enable_backlight(struct intel_connector *connector);
1297 void intel_panel_disable_backlight(struct intel_connector *connector);
1298 void intel_panel_destroy_backlight(struct drm_connector *connector);
1299 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1300 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1301 extern struct drm_display_mode *intel_find_panel_downclock(
1302                                 struct drm_device *dev,
1303                                 struct drm_display_mode *fixed_mode,
1304                                 struct drm_connector *connector);
1305 void intel_backlight_register(struct drm_device *dev);
1306 void intel_backlight_unregister(struct drm_device *dev);
1307
1308
1309 /* intel_psr.c */
1310 void intel_psr_enable(struct intel_dp *intel_dp);
1311 void intel_psr_disable(struct intel_dp *intel_dp);
1312 void intel_psr_invalidate(struct drm_device *dev,
1313                           unsigned frontbuffer_bits);
1314 void intel_psr_flush(struct drm_device *dev,
1315                      unsigned frontbuffer_bits,
1316                      enum fb_op_origin origin);
1317 void intel_psr_init(struct drm_device *dev);
1318 void intel_psr_single_frame_update(struct drm_device *dev,
1319                                    unsigned frontbuffer_bits);
1320
1321 /* intel_runtime_pm.c */
1322 int intel_power_domains_init(struct drm_i915_private *);
1323 void intel_power_domains_fini(struct drm_i915_private *);
1324 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1325 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1326
1327 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1328                                     enum intel_display_power_domain domain);
1329 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1330                                       enum intel_display_power_domain domain);
1331 void intel_display_power_get(struct drm_i915_private *dev_priv,
1332                              enum intel_display_power_domain domain);
1333 void intel_display_power_put(struct drm_i915_private *dev_priv,
1334                              enum intel_display_power_domain domain);
1335 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1336 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1337 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1338 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1339 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1340
1341 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1342
1343 /* intel_pm.c */
1344 void intel_init_clock_gating(struct drm_device *dev);
1345 void intel_suspend_hw(struct drm_device *dev);
1346 int ilk_wm_max_level(const struct drm_device *dev);
1347 void intel_update_watermarks(struct drm_crtc *crtc);
1348 void intel_update_sprite_watermarks(struct drm_plane *plane,
1349                                     struct drm_crtc *crtc,
1350                                     uint32_t sprite_width,
1351                                     uint32_t sprite_height,
1352                                     int pixel_size,
1353                                     bool enabled, bool scaled);
1354 void intel_init_pm(struct drm_device *dev);
1355 void intel_pm_setup(struct drm_device *dev);
1356 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1357 void intel_gpu_ips_teardown(void);
1358 void intel_init_gt_powersave(struct drm_device *dev);
1359 void intel_cleanup_gt_powersave(struct drm_device *dev);
1360 void intel_enable_gt_powersave(struct drm_device *dev);
1361 void intel_disable_gt_powersave(struct drm_device *dev);
1362 void intel_suspend_gt_powersave(struct drm_device *dev);
1363 void intel_reset_gt_powersave(struct drm_device *dev);
1364 void gen6_update_ring_freq(struct drm_device *dev);
1365 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1366 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1367 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1368 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1369                     struct intel_rps_client *rps,
1370                     unsigned long submitted);
1371 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1372                                        struct drm_i915_gem_request *req);
1373 void vlv_wm_get_hw_state(struct drm_device *dev);
1374 void ilk_wm_get_hw_state(struct drm_device *dev);
1375 void skl_wm_get_hw_state(struct drm_device *dev);
1376 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1377                           struct skl_ddb_allocation *ddb /* out */);
1378 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1379
1380 /* intel_sdvo.c */
1381 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1382
1383
1384 /* intel_sprite.c */
1385 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1386 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1387                               struct drm_file *file_priv);
1388 bool intel_pipe_update_start(struct intel_crtc *crtc,
1389                              uint32_t *start_vbl_count);
1390 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1391
1392 /* intel_tv.c */
1393 void intel_tv_init(struct drm_device *dev);
1394
1395 /* intel_atomic.c */
1396 int intel_atomic_check(struct drm_device *dev,
1397                        struct drm_atomic_state *state);
1398 int intel_atomic_commit(struct drm_device *dev,
1399                         struct drm_atomic_state *state,
1400                         bool async);
1401 int intel_connector_atomic_get_property(struct drm_connector *connector,
1402                                         const struct drm_connector_state *state,
1403                                         struct drm_property *property,
1404                                         uint64_t *val);
1405 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1406 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1407                                struct drm_crtc_state *state);
1408 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1409 void intel_atomic_state_clear(struct drm_atomic_state *);
1410 struct intel_shared_dpll_config *
1411 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1412
1413 static inline struct intel_crtc_state *
1414 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1415                             struct intel_crtc *crtc)
1416 {
1417         struct drm_crtc_state *crtc_state;
1418         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1419         if (IS_ERR(crtc_state))
1420                 return ERR_CAST(crtc_state);
1421
1422         return to_intel_crtc_state(crtc_state);
1423 }
1424 int intel_atomic_setup_scalers(struct drm_device *dev,
1425         struct intel_crtc *intel_crtc,
1426         struct intel_crtc_state *crtc_state);
1427
1428 /* intel_atomic_plane.c */
1429 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1430 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1431 void intel_plane_destroy_state(struct drm_plane *plane,
1432                                struct drm_plane_state *state);
1433 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1434
1435 #endif /* __INTEL_DRV_H__ */