drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         struct list_head fbdev_list;
 127         struct drm_display_mode *our_mode;
 128         int preferred_bpp;
 129 };
 130
 131 struct intel_encoder {
 132         struct drm_encoder base;
 133
 134         enum intel_output_type type;
 135         unsigned int cloneable;
 136         void (*hot_plug)(struct intel_encoder *);
 137         bool (*compute_config)(struct intel_encoder *,
 138                                struct intel_crtc_state *);
 139         void (*pre_pll_enable)(struct intel_encoder *);
 140         void (*pre_enable)(struct intel_encoder *);
 141         void (*enable)(struct intel_encoder *);
 142         void (*mode_set)(struct intel_encoder *intel_encoder);
 143         void (*disable)(struct intel_encoder *);
 144         void (*post_disable)(struct intel_encoder *);
 145         void (*post_pll_disable)(struct intel_encoder *);
 146         /* Read out the current hw state of this connector, returning true if
 147          * the encoder is active. If the encoder is enabled it also set the pipe
 148          * it is connected to in the pipe parameter. */
 149         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 150         /* Reconstructs the equivalent mode flags for the current hardware
 151          * state. This must be called _after_ display->get_pipe_config has
 152          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 153          * be set correctly before calling this function. */
 154         void (*get_config)(struct intel_encoder *,
 155                            struct intel_crtc_state *pipe_config);
 156         /*
 157          * Called during system suspend after all pending requests for the
 158          * encoder are flushed (for example for DP AUX transactions) and
 159          * device interrupts are disabled.
 160          */
 161         void (*suspend)(struct intel_encoder *);
 162         int crtc_mask;
 163         enum hpd_pin hpd_pin;
 164 };
 165
 166 struct intel_panel {
 167         struct drm_display_mode *fixed_mode;
 168         struct drm_display_mode *downclock_mode;
 169         int fitting_mode;
 170
 171         /* backlight */
 172         struct {
 173                 bool present;
 174                 u32 level;
 175                 u32 min;
 176                 u32 max;
 177                 bool enabled;
 178                 bool combination_mode;  /* gen 2/4 only */
 179                 bool active_low_pwm;
 180
 181                 /* PWM chip */
 182                 struct pwm_device *pwm;
 183
 184                 struct backlight_device *device;
 185         } backlight;
 186
 187         void (*backlight_power)(struct intel_connector *, bool enable);
 188 };
 189
 190 struct intel_connector {
 191         struct drm_connector base;
 192         /*
 193          * The fixed encoder this connector is connected to.
 194          */
 195         struct intel_encoder *encoder;
 196
 197         /* Reads out the current hw, returning true if the connector is enabled
 198          * and active (i.e. dpms ON state). */
 199         bool (*get_hw_state)(struct intel_connector *);
 200
 201         /*
 202          * Removes all interfaces through which the connector is accessible
 203          * - like sysfs, debugfs entries -, so that no new operations can be
 204          * started on the connector. Also makes sure all currently pending
 205          * operations finish before returing.
 206          */
 207         void (*unregister)(struct intel_connector *);
 208
 209         /* Panel info for eDP and LVDS */
 210         struct intel_panel panel;
 211
 212         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 213         struct edid *edid;
 214         struct edid *detect_edid;
 215
 216         /* since POLL and HPD connectors may use the same HPD line keep the native
 217            state of connector->polled in case hotplug storm detection changes it */
 218         u8 polled;
 219
 220         void *port; /* store this opaque as its illegal to dereference it */
 221
 222         struct intel_dp *mst_port;
 223 };
 224
 225 typedef struct dpll {
 226         /* given values */
 227         int n;
 228         int m1, m2;
 229         int p1, p2;
 230         /* derived values */
 231         int     dot;
 232         int     vco;
 233         int     m;
 234         int     p;
 235 } intel_clock_t;
 236
 237 struct intel_atomic_state {
 238         struct drm_atomic_state base;
 239
 240         unsigned int cdclk;
 241         bool dpll_set;
 242         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 243 };
 244
 245 struct intel_plane_state {
 246         struct drm_plane_state base;
 247         struct drm_rect src;
 248         struct drm_rect dst;
 249         struct drm_rect clip;
 250         bool visible;
 251
 252         /*
 253          * scaler_id
 254          *    = -1 : not using a scaler
 255          *    >=  0 : using a scalers
 256          *
 257          * plane requiring a scaler:
 258          *   - During check_plane, its bit is set in
 259          *     crtc_state->scaler_state.scaler_users by calling helper function
 260          *     update_scaler_plane.
 261          *   - scaler_id indicates the scaler it got assigned.
 262          *
 263          * plane doesn't require a scaler:
 264          *   - this can happen when scaling is no more required or plane simply
 265          *     got disabled.
 266          *   - During check_plane, corresponding bit is reset in
 267          *     crtc_state->scaler_state.scaler_users by calling helper function
 268          *     update_scaler_plane.
 269          */
 270         int scaler_id;
 271
 272         struct drm_intel_sprite_colorkey ckey;
 273 };
 274
 275 struct intel_initial_plane_config {
 276         struct intel_framebuffer *fb;
 277         unsigned int tiling;
 278         int size;
 279         u32 base;
 280 };
 281
 282 #define SKL_MIN_SRC_W 8
 283 #define SKL_MAX_SRC_W 4096
 284 #define SKL_MIN_SRC_H 8
 285 #define SKL_MAX_SRC_H 4096
 286 #define SKL_MIN_DST_W 8
 287 #define SKL_MAX_DST_W 4096
 288 #define SKL_MIN_DST_H 8
 289 #define SKL_MAX_DST_H 4096
 290
 291 struct intel_scaler {
 292         int in_use;
 293         uint32_t mode;
 294 };
 295
 296 struct intel_crtc_scaler_state {
 297 #define SKL_NUM_SCALERS 2
 298         struct intel_scaler scalers[SKL_NUM_SCALERS];
 299
 300         /*
 301          * scaler_users: keeps track of users requesting scalers on this crtc.
 302          *
 303          *     If a bit is set, a user is using a scaler.
 304          *     Here user can be a plane or crtc as defined below:
 305          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 306          *       bit 31    - crtc
 307          *
 308          * Instead of creating a new index to cover planes and crtc, using
 309          * existing drm_plane_index for planes which is well less than 31
 310          * planes and bit 31 for crtc. This should be fine to cover all
 311          * our platforms.
 312          *
 313          * intel_atomic_setup_scalers will setup available scalers to users
 314          * requesting scalers. It will gracefully fail if request exceeds
 315          * avilability.
 316          */
 317 #define SKL_CRTC_INDEX 31
 318         unsigned scaler_users;
 319
 320         /* scaler used by crtc for panel fitting purpose */
 321         int scaler_id;
 322 };
 323
 324 /* drm_mode->private_flags */
 325 #define I915_MODE_FLAG_INHERITED 1
 326
 327 struct intel_crtc_state {
 328         struct drm_crtc_state base;
 329
 330         /**
 331          * quirks - bitfield with hw state readout quirks
 332          *
 333          * For various reasons the hw state readout code might not be able to
 334          * completely faithfully read out the current state. These cases are
 335          * tracked with quirk flags so that fastboot and state checker can act
 336          * accordingly.
 337          */
 338 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 339         unsigned long quirks;
 340
 341         /* Pipe source size (ie. panel fitter input size)
 342          * All planes will be positioned inside this space,
 343          * and get clipped at the edges. */
 344         int pipe_src_w, pipe_src_h;
 345
 346         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 347          * between pch encoders and cpu encoders. */
 348         bool has_pch_encoder;
 349
 350         /* Are we sending infoframes on the attached port */
 351         bool has_infoframe;
 352
 353         /* CPU Transcoder for the pipe. Currently this can only differ from the
 354          * pipe on Haswell (where we have a special eDP transcoder). */
 355         enum transcoder cpu_transcoder;
 356
 357         /*
 358          * Use reduced/limited/broadcast rbg range, compressing from the full
 359          * range fed into the crtcs.
 360          */
 361         bool limited_color_range;
 362
 363         /* DP has a bunch of special case unfortunately, so mark the pipe
 364          * accordingly. */
 365         bool has_dp_encoder;
 366
 367         /* Whether we should send NULL infoframes. Required for audio. */
 368         bool has_hdmi_sink;
 369
 370         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 371          * has_dp_encoder is set. */
 372         bool has_audio;
 373
 374         /*
 375          * Enable dithering, used when the selected pipe bpp doesn't match the
 376          * plane bpp.
 377          */
 378         bool dither;
 379
 380         /* Controls for the clock computation, to override various stages. */
 381         bool clock_set;
 382
 383         /* SDVO TV has a bunch of special case. To make multifunction encoders
 384          * work correctly, we need to track this at runtime.*/
 385         bool sdvo_tv_clock;
 386
 387         /*
 388          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 389          * required. This is set in the 2nd loop of calling encoder's
 390          * ->compute_config if the first pick doesn't work out.
 391          */
 392         bool bw_constrained;
 393
 394         /* Settings for the intel dpll used on pretty much everything but
 395          * haswell. */
 396         struct dpll dpll;
 397
 398         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 399         enum intel_dpll_id shared_dpll;
 400
 401         /*
 402          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 403          * - enum skl_dpll on SKL
 404          */
 405         uint32_t ddi_pll_sel;
 406
 407         /* Actual register state of the dpll, for shared dpll cross-checking. */
 408         struct intel_dpll_hw_state dpll_hw_state;
 409
 410         int pipe_bpp;
 411         struct intel_link_m_n dp_m_n;
 412
 413         /* m2_n2 for eDP downclock */
 414         struct intel_link_m_n dp_m2_n2;
 415         bool has_drrs;
 416
 417         /*
 418          * Frequence the dpll for the port should run at. Differs from the
 419          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 420          * already multiplied by pixel_multiplier.
 421          */
 422         int port_clock;
 423
 424         /* Used by SDVO (and if we ever fix it, HDMI). */
 425         unsigned pixel_multiplier;
 426
 427         uint8_t lane_count;
 428
 429         /* Panel fitter controls for gen2-gen4 + VLV */
 430         struct {
 431                 u32 control;
 432                 u32 pgm_ratios;
 433                 u32 lvds_border_bits;
 434         } gmch_pfit;
 435
 436         /* Panel fitter placement and size for Ironlake+ */
 437         struct {
 438                 u32 pos;
 439                 u32 size;
 440                 bool enabled;
 441                 bool force_thru;
 442         } pch_pfit;
 443
 444         /* FDI configuration, only valid if has_pch_encoder is set. */
 445         int fdi_lanes;
 446         struct intel_link_m_n fdi_m_n;
 447
 448         bool ips_enabled;
 449
 450         bool double_wide;
 451
 452         bool dp_encoder_is_mst;
 453         int pbn;
 454
 455         struct intel_crtc_scaler_state scaler_state;
 456
 457         /* w/a for waiting 2 vblanks during crtc enable */
 458         enum pipe hsw_workaround_pipe;
 459 };
 460
 461 struct vlv_wm_state {
 462         struct vlv_pipe_wm wm[3];
 463         struct vlv_sr_wm sr[3];
 464         uint8_t num_active_planes;
 465         uint8_t num_levels;
 466         uint8_t level;
 467         bool cxsr;
 468 };
 469
 470 struct intel_pipe_wm {
 471         struct intel_wm_level wm[5];
 472         uint32_t linetime;
 473         bool fbc_wm_enabled;
 474         bool pipe_enabled;
 475         bool sprites_enabled;
 476         bool sprites_scaled;
 477 };
 478
 479 struct intel_mmio_flip {
 480         struct work_struct work;
 481         struct drm_i915_private *i915;
 482         struct drm_i915_gem_request *req;
 483         struct intel_crtc *crtc;
 484 };
 485
 486 struct skl_pipe_wm {
 487         struct skl_wm_level wm[8];
 488         struct skl_wm_level trans_wm;
 489         uint32_t linetime;
 490 };
 491
 492 /*
 493  * Tracking of operations that need to be performed at the beginning/end of an
 494  * atomic commit, outside the atomic section where interrupts are disabled.
 495  * These are generally operations that grab mutexes or might otherwise sleep
 496  * and thus can't be run with interrupts disabled.
 497  */
 498 struct intel_crtc_atomic_commit {
 499         /* Sleepable operations to perform before commit */
 500         bool wait_for_flips;
 501         bool disable_fbc;
 502         bool disable_ips;
 503         bool disable_cxsr;
 504         bool pre_disable_primary;
 505         bool update_wm_pre, update_wm_post;
 506         unsigned disabled_planes;
 507
 508         /* Sleepable operations to perform after commit */
 509         unsigned fb_bits;
 510         bool wait_vblank;
 511         bool update_fbc;
 512         bool post_enable_primary;
 513         unsigned update_sprite_watermarks;
 514 };
 515
 516 struct intel_crtc {
 517         struct drm_crtc base;
 518         enum pipe pipe;
 519         enum plane plane;
 520         u8 lut_r[256], lut_g[256], lut_b[256];
 521         /*
 522          * Whether the crtc and the connected output pipeline is active. Implies
 523          * that crtc->enabled is set, i.e. the current mode configuration has
 524          * some outputs connected to this crtc.
 525          */
 526         bool active;
 527         unsigned long enabled_power_domains;
 528         bool lowfreq_avail;
 529         struct intel_overlay *overlay;
 530         struct intel_unpin_work *unpin_work;
 531
 532         atomic_t unpin_work_count;
 533
 534         /* Display surface base address adjustement for pageflips. Note that on
 535          * gen4+ this only adjusts up to a tile, offsets within a tile are
 536          * handled in the hw itself (with the TILEOFF register). */
 537         unsigned long dspaddr_offset;
 538
 539         struct drm_i915_gem_object *cursor_bo;
 540         uint32_t cursor_addr;
 541         uint32_t cursor_cntl;
 542         uint32_t cursor_size;
 543         uint32_t cursor_base;
 544
 545         struct intel_crtc_state *config;
 546
 547         /* reset counter value when the last flip was submitted */
 548         unsigned int reset_counter;
 549
 550         /* Access to these should be protected by dev_priv->irq_lock. */
 551         bool cpu_fifo_underrun_disabled;
 552         bool pch_fifo_underrun_disabled;
 553
 554         /* per-pipe watermark state */
 555         struct {
 556                 /* watermarks currently being used  */
 557                 struct intel_pipe_wm active;
 558                 /* SKL wm values currently in use */
 559                 struct skl_pipe_wm skl_active;
 560                 /* allow CxSR on this pipe */
 561                 bool cxsr_allowed;
 562         } wm;
 563
 564         int scanline_offset;
 565
 566         unsigned start_vbl_count;
 567         ktime_t start_vbl_time;
 568
 569         struct intel_crtc_atomic_commit atomic;
 570
 571         /* scalers available on this crtc */
 572         int num_scalers;
 573
 574         struct vlv_wm_state wm_state;
 575 };
 576
 577 struct intel_plane_wm_parameters {
 578         uint32_t horiz_pixels;
 579         uint32_t vert_pixels;
 580         /*
 581          *   For packed pixel formats:
 582          *     bytes_per_pixel - holds bytes per pixel
 583          *   For planar pixel formats:
 584          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 585          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 586          */
 587         uint8_t bytes_per_pixel;
 588         uint8_t y_bytes_per_pixel;
 589         bool enabled;
 590         bool scaled;
 591         u64 tiling;
 592         unsigned int rotation;
 593         uint16_t fifo_size;
 594 };
 595
 596 struct intel_plane {
 597         struct drm_plane base;
 598         int plane;
 599         enum pipe pipe;
 600         bool can_scale;
 601         int max_downscale;
 602         uint32_t frontbuffer_bit;
 603
 604         /* Since we need to change the watermarks before/after
 605          * enabling/disabling the planes, we need to store the parameters here
 606          * as the other pieces of the struct may not reflect the values we want
 607          * for the watermark calculations. Currently only Haswell uses this.
 608          */
 609         struct intel_plane_wm_parameters wm;
 610
 611         /*
 612          * NOTE: Do not place new plane state fields here (e.g., when adding
 613          * new plane properties).  New runtime state should now be placed in
 614          * the intel_plane_state structure and accessed via drm_plane->state.
 615          */
 616
 617         void (*update_plane)(struct drm_plane *plane,
 618                              struct drm_crtc *crtc,
 619                              struct drm_framebuffer *fb,
 620                              int crtc_x, int crtc_y,
 621                              unsigned int crtc_w, unsigned int crtc_h,
 622                              uint32_t x, uint32_t y,
 623                              uint32_t src_w, uint32_t src_h);
 624         void (*disable_plane)(struct drm_plane *plane,
 625                               struct drm_crtc *crtc);
 626         int (*check_plane)(struct drm_plane *plane,
 627                            struct intel_crtc_state *crtc_state,
 628                            struct intel_plane_state *state);
 629         void (*commit_plane)(struct drm_plane *plane,
 630                              struct intel_plane_state *state);
 631 };
 632
 633 struct intel_watermark_params {
 634         unsigned long fifo_size;
 635         unsigned long max_wm;
 636         unsigned long default_wm;
 637         unsigned long guard_size;
 638         unsigned long cacheline_size;
 639 };
 640
 641 struct cxsr_latency {
 642         int is_desktop;
 643         int is_ddr3;
 644         unsigned long fsb_freq;
 645         unsigned long mem_freq;
 646         unsigned long display_sr;
 647         unsigned long display_hpll_disable;
 648         unsigned long cursor_sr;
 649         unsigned long cursor_hpll_disable;
 650 };
 651
 652 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 653 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 654 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 655 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 656 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 657 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 658 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 659 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 660 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 661
 662 struct intel_hdmi {
 663         u32 hdmi_reg;
 664         int ddc_bus;
 665         bool limited_color_range;
 666         bool color_range_auto;
 667         bool has_hdmi_sink;
 668         bool has_audio;
 669         enum hdmi_force_audio force_audio;
 670         bool rgb_quant_range_selectable;
 671         enum hdmi_picture_aspect aspect_ratio;
 672         void (*write_infoframe)(struct drm_encoder *encoder,
 673                                 enum hdmi_infoframe_type type,
 674                                 const void *frame, ssize_t len);
 675         void (*set_infoframes)(struct drm_encoder *encoder,
 676                                bool enable,
 677                                struct drm_display_mode *adjusted_mode);
 678         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 679 };
 680
 681 struct intel_dp_mst_encoder;
 682 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 683
 684 /*
 685  * enum link_m_n_set:
 686  *      When platform provides two set of M_N registers for dp, we can
 687  *      program them and switch between them incase of DRRS.
 688  *      But When only one such register is provided, we have to program the
 689  *      required divider value on that registers itself based on the DRRS state.
 690  *
 691  * M1_N1        : Program dp_m_n on M1_N1 registers
 692  *                        dp_m2_n2 on M2_N2 registers (If supported)
 693  *
 694  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 695  *                        M2_N2 registers are not supported
 696  */
 697
 698 enum link_m_n_set {
 699         /* Sets the m1_n1 and m2_n2 */
 700         M1_N1 = 0,
 701         M2_N2
 702 };
 703
 704 struct sink_crc {
 705         bool started;
 706         u8 last_crc[6];
 707         int last_count;
 708 };
 709
 710 struct intel_dp {
 711         uint32_t output_reg;
 712         uint32_t aux_ch_ctl_reg;
 713         uint32_t DP;
 714         int link_rate;
 715         uint8_t lane_count;
 716         bool has_audio;
 717         enum hdmi_force_audio force_audio;
 718         bool limited_color_range;
 719         bool color_range_auto;
 720         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 721         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 722         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 723         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 724         uint8_t num_sink_rates;
 725         int sink_rates[DP_MAX_SUPPORTED_RATES];
 726         struct sink_crc sink_crc;
 727         struct drm_dp_aux aux;
 728         uint8_t train_set[4];
 729         int panel_power_up_delay;
 730         int panel_power_down_delay;
 731         int panel_power_cycle_delay;
 732         int backlight_on_delay;
 733         int backlight_off_delay;
 734         struct delayed_work panel_vdd_work;
 735         bool want_panel_vdd;
 736         unsigned long last_power_cycle;
 737         unsigned long last_power_on;
 738         unsigned long last_backlight_off;
 739
 740         struct notifier_block edp_notifier;
 741
 742         /*
 743          * Pipe whose power sequencer is currently locked into
 744          * this port. Only relevant on VLV/CHV.
 745          */
 746         enum pipe pps_pipe;
 747         struct edp_power_seq pps_delays;
 748
 749         bool can_mst; /* this port supports mst */
 750         bool is_mst;
 751         int active_mst_links;
 752         /* connector directly attached - won't be use for modeset in mst world */
 753         struct intel_connector *attached_connector;
 754
 755         /* mst connector list */
 756         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 757         struct drm_dp_mst_topology_mgr mst_mgr;
 758
 759         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 760         /*
 761          * This function returns the value we have to program the AUX_CTL
 762          * register with to kick off an AUX transaction.
 763          */
 764         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 765                                      bool has_aux_irq,
 766                                      int send_bytes,
 767                                      uint32_t aux_clock_divider);
 768         bool train_set_valid;
 769
 770         /* Displayport compliance testing */
 771         unsigned long compliance_test_type;
 772         unsigned long compliance_test_data;
 773         bool compliance_test_active;
 774 };
 775
 776 struct intel_digital_port {
 777         struct intel_encoder base;
 778         enum port port;
 779         u32 saved_port_bits;
 780         struct intel_dp dp;
 781         struct intel_hdmi hdmi;
 782         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 783         bool release_cl2_override;
 784 };
 785
 786 struct intel_dp_mst_encoder {
 787         struct intel_encoder base;
 788         enum pipe pipe;
 789         struct intel_digital_port *primary;
 790         void *port; /* store this opaque as its illegal to dereference it */
 791 };
 792
 793 static inline enum dpio_channel
 794 vlv_dport_to_channel(struct intel_digital_port *dport)
 795 {
 796         switch (dport->port) {
 797         case PORT_B:
 798         case PORT_D:
 799                 return DPIO_CH0;
 800         case PORT_C:
 801                 return DPIO_CH1;
 802         default:
 803                 BUG();
 804         }
 805 }
 806
 807 static inline enum dpio_phy
 808 vlv_dport_to_phy(struct intel_digital_port *dport)
 809 {
 810         switch (dport->port) {
 811         case PORT_B:
 812         case PORT_C:
 813                 return DPIO_PHY0;
 814         case PORT_D:
 815                 return DPIO_PHY1;
 816         default:
 817                 BUG();
 818         }
 819 }
 820
 821 static inline enum dpio_channel
 822 vlv_pipe_to_channel(enum pipe pipe)
 823 {
 824         switch (pipe) {
 825         case PIPE_A:
 826         case PIPE_C:
 827                 return DPIO_CH0;
 828         case PIPE_B:
 829                 return DPIO_CH1;
 830         default:
 831                 BUG();
 832         }
 833 }
 834
 835 static inline struct drm_crtc *
 836 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 837 {
 838         struct drm_i915_private *dev_priv = dev->dev_private;
 839         return dev_priv->pipe_to_crtc_mapping[pipe];
 840 }
 841
 842 static inline struct drm_crtc *
 843 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 844 {
 845         struct drm_i915_private *dev_priv = dev->dev_private;
 846         return dev_priv->plane_to_crtc_mapping[plane];
 847 }
 848
 849 struct intel_unpin_work {
 850         struct work_struct work;
 851         struct drm_crtc *crtc;
 852         struct drm_framebuffer *old_fb;
 853         struct drm_i915_gem_object *pending_flip_obj;
 854         struct drm_pending_vblank_event *event;
 855         atomic_t pending;
 856 #define INTEL_FLIP_INACTIVE     0
 857 #define INTEL_FLIP_PENDING      1
 858 #define INTEL_FLIP_COMPLETE     2
 859         u32 flip_count;
 860         u32 gtt_offset;
 861         struct drm_i915_gem_request *flip_queued_req;
 862         int flip_queued_vblank;
 863         int flip_ready_vblank;
 864         bool enable_stall_check;
 865 };
 866
 867 struct intel_load_detect_pipe {
 868         struct drm_framebuffer *release_fb;
 869         bool load_detect_temp;
 870         int dpms_mode;
 871 };
 872
 873 static inline struct intel_encoder *
 874 intel_attached_encoder(struct drm_connector *connector)
 875 {
 876         return to_intel_connector(connector)->encoder;
 877 }
 878
 879 static inline struct intel_digital_port *
 880 enc_to_dig_port(struct drm_encoder *encoder)
 881 {
 882         return container_of(encoder, struct intel_digital_port, base.base);
 883 }
 884
 885 static inline struct intel_dp_mst_encoder *
 886 enc_to_mst(struct drm_encoder *encoder)
 887 {
 888         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 889 }
 890
 891 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 892 {
 893         return &enc_to_dig_port(encoder)->dp;
 894 }
 895
 896 static inline struct intel_digital_port *
 897 dp_to_dig_port(struct intel_dp *intel_dp)
 898 {
 899         return container_of(intel_dp, struct intel_digital_port, dp);
 900 }
 901
 902 static inline struct intel_digital_port *
 903 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 904 {
 905         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 906 }
 907
 908 /*
 909  * Returns the number of planes for this pipe, ie the number of sprites + 1
 910  * (primary plane). This doesn't count the cursor plane then.
 911  */
 912 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 913 {
 914         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 915 }
 916
 917 /* intel_fifo_underrun.c */
 918 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 919                                            enum pipe pipe, bool enable);
 920 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 921                                            enum transcoder pch_transcoder,
 922                                            bool enable);
 923 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 924                                          enum pipe pipe);
 925 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 926                                          enum transcoder pch_transcoder);
 927 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 928
 929 /* i915_irq.c */
 930 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 931 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 932 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 933 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 934 void gen6_reset_rps_interrupts(struct drm_device *dev);
 935 void gen6_enable_rps_interrupts(struct drm_device *dev);
 936 void gen6_disable_rps_interrupts(struct drm_device *dev);
 937 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 938 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 939 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 940 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 941 {
 942         /*
 943          * We only use drm_irq_uninstall() at unload and VT switch, so
 944          * this is the only thing we need to check.
 945          */
 946         return dev_priv->pm.irqs_enabled;
 947 }
 948
 949 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 950 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 951                                      unsigned int pipe_mask);
 952
 953 /* intel_crt.c */
 954 void intel_crt_init(struct drm_device *dev);
 955
 956
 957 /* intel_ddi.c */
 958 void intel_prepare_ddi(struct drm_device *dev);
 959 void hsw_fdi_link_train(struct drm_crtc *crtc);
 960 void intel_ddi_init(struct drm_device *dev, enum port port);
 961 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 962 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 963 void intel_ddi_pll_init(struct drm_device *dev);
 964 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 965 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 966                                        enum transcoder cpu_transcoder);
 967 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 968 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 969 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 970                           struct intel_crtc_state *crtc_state);
 971 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 972 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 973 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 974 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 975 void intel_ddi_get_config(struct intel_encoder *encoder,
 976                           struct intel_crtc_state *pipe_config);
 977 struct intel_encoder *
 978 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
 979
 980 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 981 void intel_ddi_clock_get(struct intel_encoder *encoder,
 982                          struct intel_crtc_state *pipe_config);
 983 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 984 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 985
 986 /* intel_frontbuffer.c */
 987 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 988                              enum fb_op_origin origin);
 989 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 990                                     unsigned frontbuffer_bits);
 991 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 992                                      unsigned frontbuffer_bits);
 993 void intel_frontbuffer_flip(struct drm_device *dev,
 994                             unsigned frontbuffer_bits);
 995 unsigned int intel_fb_align_height(struct drm_device *dev,
 996                                    unsigned int height,
 997                                    uint32_t pixel_format,
 998                                    uint64_t fb_format_modifier);
 999 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1000                         enum fb_op_origin origin);
1001 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
1002                               uint32_t pixel_format);
1003
1004 /* intel_audio.c */
1005 void intel_init_audio(struct drm_device *dev);
1006 void intel_audio_codec_enable(struct intel_encoder *encoder);
1007 void intel_audio_codec_disable(struct intel_encoder *encoder);
1008 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1009 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1010
1011 /* intel_display.c */
1012 extern const struct drm_plane_funcs intel_plane_funcs;
1013 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1014 int intel_pch_rawclk(struct drm_device *dev);
1015 int intel_hrawclk(struct drm_device *dev);
1016 void intel_mark_busy(struct drm_device *dev);
1017 void intel_mark_idle(struct drm_device *dev);
1018 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1019 int intel_display_suspend(struct drm_device *dev);
1020 void intel_encoder_destroy(struct drm_encoder *encoder);
1021 int intel_connector_init(struct intel_connector *);
1022 struct intel_connector *intel_connector_alloc(void);
1023 bool intel_connector_get_hw_state(struct intel_connector *connector);
1024 void intel_connector_attach_encoder(struct intel_connector *connector,
1025                                     struct intel_encoder *encoder);
1026 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1027 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1028                                              struct drm_crtc *crtc);
1029 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1030 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1031                                 struct drm_file *file_priv);
1032 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1033                                              enum pipe pipe);
1034 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1035 static inline void
1036 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1037 {
1038         drm_wait_one_vblank(dev, pipe);
1039 }
1040 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1041 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1042                          struct intel_digital_port *dport,
1043                          unsigned int expected_mask);
1044 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1045                                 struct drm_display_mode *mode,
1046                                 struct intel_load_detect_pipe *old,
1047                                 struct drm_modeset_acquire_ctx *ctx);
1048 void intel_release_load_detect_pipe(struct drm_connector *connector,
1049                                     struct intel_load_detect_pipe *old,
1050                                     struct drm_modeset_acquire_ctx *ctx);
1051 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1052                                struct drm_framebuffer *fb,
1053                                const struct drm_plane_state *plane_state,
1054                                struct intel_engine_cs *pipelined,
1055                                struct drm_i915_gem_request **pipelined_request);
1056 struct drm_framebuffer *
1057 __intel_framebuffer_create(struct drm_device *dev,
1058                            struct drm_mode_fb_cmd2 *mode_cmd,
1059                            struct drm_i915_gem_object *obj);
1060 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1061 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1062 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1063 void intel_check_page_flip(struct drm_device *dev, int pipe);
1064 int intel_prepare_plane_fb(struct drm_plane *plane,
1065                            struct drm_framebuffer *fb,
1066                            const struct drm_plane_state *new_state);
1067 void intel_cleanup_plane_fb(struct drm_plane *plane,
1068                             struct drm_framebuffer *fb,
1069                             const struct drm_plane_state *old_state);
1070 int intel_plane_atomic_get_property(struct drm_plane *plane,
1071                                     const struct drm_plane_state *state,
1072                                     struct drm_property *property,
1073                                     uint64_t *val);
1074 int intel_plane_atomic_set_property(struct drm_plane *plane,
1075                                     struct drm_plane_state *state,
1076                                     struct drm_property *property,
1077                                     uint64_t val);
1078 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1079                                     struct drm_plane_state *plane_state);
1080
1081 unsigned int
1082 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1083                   uint64_t fb_format_modifier);
1084
1085 static inline bool
1086 intel_rotation_90_or_270(unsigned int rotation)
1087 {
1088         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1089 }
1090
1091 void intel_create_rotation_property(struct drm_device *dev,
1092                                         struct intel_plane *plane);
1093
1094 /* shared dpll functions */
1095 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1096 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1097                         struct intel_shared_dpll *pll,
1098                         bool state);
1099 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1100 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1101 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1102                                                 struct intel_crtc_state *state);
1103
1104 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1105                       const struct dpll *dpll);
1106 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1107
1108 /* modesetting asserts */
1109 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1110                            enum pipe pipe);
1111 void assert_pll(struct drm_i915_private *dev_priv,
1112                 enum pipe pipe, bool state);
1113 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1114 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1115 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1116                        enum pipe pipe, bool state);
1117 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1118 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1119 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1120 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1121 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1122 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1123                                              int *x, int *y,
1124                                              unsigned int tiling_mode,
1125                                              unsigned int bpp,
1126                                              unsigned int pitch);
1127 void intel_prepare_reset(struct drm_device *dev);
1128 void intel_finish_reset(struct drm_device *dev);
1129 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1130 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1131 void broxton_init_cdclk(struct drm_device *dev);
1132 void broxton_uninit_cdclk(struct drm_device *dev);
1133 void broxton_ddi_phy_init(struct drm_device *dev);
1134 void broxton_ddi_phy_uninit(struct drm_device *dev);
1135 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1136 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1137 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1138 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1139 void intel_dp_get_m_n(struct intel_crtc *crtc,
1140                       struct intel_crtc_state *pipe_config);
1141 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1142 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1143 void
1144 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1145                                 int dotclock);
1146 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1147                         intel_clock_t *best_clock);
1148 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1149
1150 bool intel_crtc_active(struct drm_crtc *crtc);
1151 void hsw_enable_ips(struct intel_crtc *crtc);
1152 void hsw_disable_ips(struct intel_crtc *crtc);
1153 enum intel_display_power_domain
1154 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1155 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1156                                  struct intel_crtc_state *pipe_config);
1157 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1158 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1159
1160 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1161 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1162
1163 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1164                                      struct drm_i915_gem_object *obj);
1165 u32 skl_plane_ctl_format(uint32_t pixel_format);
1166 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1167 u32 skl_plane_ctl_rotation(unsigned int rotation);
1168
1169 /* intel_csr.c */
1170 void intel_csr_ucode_init(struct drm_device *dev);
1171 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1172 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1173                                         enum csr_state state);
1174 void intel_csr_load_program(struct drm_device *dev);
1175 void intel_csr_ucode_fini(struct drm_device *dev);
1176 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1177
1178 /* intel_dp.c */
1179 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1180 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1181                              struct intel_connector *intel_connector);
1182 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1183                               const struct intel_crtc_state *pipe_config);
1184 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1185 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1186 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1187 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1188 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1189 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1190 bool intel_dp_compute_config(struct intel_encoder *encoder,
1191                              struct intel_crtc_state *pipe_config);
1192 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1193 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1194                                   bool long_hpd);
1195 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1196 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1197 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1198 void intel_edp_panel_on(struct intel_dp *intel_dp);
1199 void intel_edp_panel_off(struct intel_dp *intel_dp);
1200 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1201 void intel_dp_mst_suspend(struct drm_device *dev);
1202 void intel_dp_mst_resume(struct drm_device *dev);
1203 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1204 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1205 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1206 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1207 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1208 void intel_plane_destroy(struct drm_plane *plane);
1209 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1210 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1211 void intel_edp_drrs_invalidate(struct drm_device *dev,
1212                 unsigned frontbuffer_bits);
1213 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1214 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1215
1216 /* intel_dp_mst.c */
1217 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1218 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1219 /* intel_dsi.c */
1220 void intel_dsi_init(struct drm_device *dev);
1221
1222
1223 /* intel_dvo.c */
1224 void intel_dvo_init(struct drm_device *dev);
1225
1226
1227 /* legacy fbdev emulation in intel_fbdev.c */
1228 #ifdef CONFIG_DRM_FBDEV_EMULATION
1229 extern int intel_fbdev_init(struct drm_device *dev);
1230 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1231 extern void intel_fbdev_fini(struct drm_device *dev);
1232 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1233 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1234 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1235 #else
1236 static inline int intel_fbdev_init(struct drm_device *dev)
1237 {
1238         return 0;
1239 }
1240
1241 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1242 {
1243 }
1244
1245 static inline void intel_fbdev_fini(struct drm_device *dev)
1246 {
1247 }
1248
1249 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1250 {
1251 }
1252
1253 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1254 {
1255 }
1256 #endif
1257
1258 /* intel_fbc.c */
1259 bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
1260 void intel_fbc_update(struct drm_i915_private *dev_priv);
1261 void intel_fbc_init(struct drm_i915_private *dev_priv);
1262 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1263 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1264 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1265                           unsigned int frontbuffer_bits,
1266                           enum fb_op_origin origin);
1267 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1268                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1269 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1270 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1271
1272 /* intel_hdmi.c */
1273 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1274 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1275                                struct intel_connector *intel_connector);
1276 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1277 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1278                                struct intel_crtc_state *pipe_config);
1279
1280
1281 /* intel_lvds.c */
1282 void intel_lvds_init(struct drm_device *dev);
1283 bool intel_is_dual_link_lvds(struct drm_device *dev);
1284
1285
1286 /* intel_modes.c */
1287 int intel_connector_update_modes(struct drm_connector *connector,
1288                                  struct edid *edid);
1289 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1290 void intel_attach_force_audio_property(struct drm_connector *connector);
1291 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1292
1293
1294 /* intel_overlay.c */
1295 void intel_setup_overlay(struct drm_device *dev);
1296 void intel_cleanup_overlay(struct drm_device *dev);
1297 int intel_overlay_switch_off(struct intel_overlay *overlay);
1298 int intel_overlay_put_image(struct drm_device *dev, void *data,
1299                             struct drm_file *file_priv);
1300 int intel_overlay_attrs(struct drm_device *dev, void *data,
1301                         struct drm_file *file_priv);
1302 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1303
1304
1305 /* intel_panel.c */
1306 int intel_panel_init(struct intel_panel *panel,
1307                      struct drm_display_mode *fixed_mode,
1308                      struct drm_display_mode *downclock_mode);
1309 void intel_panel_fini(struct intel_panel *panel);
1310 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1311                             struct drm_display_mode *adjusted_mode);
1312 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1313                              struct intel_crtc_state *pipe_config,
1314                              int fitting_mode);
1315 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1316                               struct intel_crtc_state *pipe_config,
1317                               int fitting_mode);
1318 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1319                                     u32 level, u32 max);
1320 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1321 void intel_panel_enable_backlight(struct intel_connector *connector);
1322 void intel_panel_disable_backlight(struct intel_connector *connector);
1323 void intel_panel_destroy_backlight(struct drm_connector *connector);
1324 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1325 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1326 extern struct drm_display_mode *intel_find_panel_downclock(
1327                                 struct drm_device *dev,
1328                                 struct drm_display_mode *fixed_mode,
1329                                 struct drm_connector *connector);
1330 void intel_backlight_register(struct drm_device *dev);
1331 void intel_backlight_unregister(struct drm_device *dev);
1332
1333
1334 /* intel_psr.c */
1335 void intel_psr_enable(struct intel_dp *intel_dp);
1336 void intel_psr_disable(struct intel_dp *intel_dp);
1337 void intel_psr_invalidate(struct drm_device *dev,
1338                           unsigned frontbuffer_bits);
1339 void intel_psr_flush(struct drm_device *dev,
1340                      unsigned frontbuffer_bits,
1341                      enum fb_op_origin origin);
1342 void intel_psr_init(struct drm_device *dev);
1343 void intel_psr_single_frame_update(struct drm_device *dev,
1344                                    unsigned frontbuffer_bits);
1345
1346 /* intel_runtime_pm.c */
1347 int intel_power_domains_init(struct drm_i915_private *);
1348 void intel_power_domains_fini(struct drm_i915_private *);
1349 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1350 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1351
1352 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1353                                     enum intel_display_power_domain domain);
1354 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1355                                       enum intel_display_power_domain domain);
1356 void intel_display_power_get(struct drm_i915_private *dev_priv,
1357                              enum intel_display_power_domain domain);
1358 void intel_display_power_put(struct drm_i915_private *dev_priv,
1359                              enum intel_display_power_domain domain);
1360 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1361 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1362 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1363 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1364 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1365
1366 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1367
1368 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1369                              bool override, unsigned int mask);
1370 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1371                           enum dpio_channel ch, bool override);
1372
1373
1374 /* intel_pm.c */
1375 void intel_init_clock_gating(struct drm_device *dev);
1376 void intel_suspend_hw(struct drm_device *dev);
1377 int ilk_wm_max_level(const struct drm_device *dev);
1378 void intel_update_watermarks(struct drm_crtc *crtc);
1379 void intel_update_sprite_watermarks(struct drm_plane *plane,
1380                                     struct drm_crtc *crtc,
1381                                     uint32_t sprite_width,
1382                                     uint32_t sprite_height,
1383                                     int pixel_size,
1384                                     bool enabled, bool scaled);
1385 void intel_init_pm(struct drm_device *dev);
1386 void intel_pm_setup(struct drm_device *dev);
1387 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1388 void intel_gpu_ips_teardown(void);
1389 void intel_init_gt_powersave(struct drm_device *dev);
1390 void intel_cleanup_gt_powersave(struct drm_device *dev);
1391 void intel_enable_gt_powersave(struct drm_device *dev);
1392 void intel_disable_gt_powersave(struct drm_device *dev);
1393 void intel_suspend_gt_powersave(struct drm_device *dev);
1394 void intel_reset_gt_powersave(struct drm_device *dev);
1395 void gen6_update_ring_freq(struct drm_device *dev);
1396 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1397 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1398 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1399 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1400                     struct intel_rps_client *rps,
1401                     unsigned long submitted);
1402 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1403                                        struct drm_i915_gem_request *req);
1404 void vlv_wm_get_hw_state(struct drm_device *dev);
1405 void ilk_wm_get_hw_state(struct drm_device *dev);
1406 void skl_wm_get_hw_state(struct drm_device *dev);
1407 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1408                           struct skl_ddb_allocation *ddb /* out */);
1409 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1410
1411 /* intel_sdvo.c */
1412 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1413
1414
1415 /* intel_sprite.c */
1416 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1417 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1418                               struct drm_file *file_priv);
1419 void intel_pipe_update_start(struct intel_crtc *crtc);
1420 void intel_pipe_update_end(struct intel_crtc *crtc);
1421
1422 /* intel_tv.c */
1423 void intel_tv_init(struct drm_device *dev);
1424
1425 /* intel_atomic.c */
1426 int intel_connector_atomic_get_property(struct drm_connector *connector,
1427                                         const struct drm_connector_state *state,
1428                                         struct drm_property *property,
1429                                         uint64_t *val);
1430 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1431 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1432                                struct drm_crtc_state *state);
1433 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1434 void intel_atomic_state_clear(struct drm_atomic_state *);
1435 struct intel_shared_dpll_config *
1436 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1437
1438 static inline struct intel_crtc_state *
1439 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1440                             struct intel_crtc *crtc)
1441 {
1442         struct drm_crtc_state *crtc_state;
1443         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1444         if (IS_ERR(crtc_state))
1445                 return ERR_CAST(crtc_state);
1446
1447         return to_intel_crtc_state(crtc_state);
1448 }
1449 int intel_atomic_setup_scalers(struct drm_device *dev,
1450         struct intel_crtc *intel_crtc,
1451         struct intel_crtc_state *crtc_state);
1452
1453 /* intel_atomic_plane.c */
1454 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1455 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1456 void intel_plane_destroy_state(struct drm_plane *plane,
1457                                struct drm_plane_state *state);
1458 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1459
1460 #endif /* __INTEL_DRV_H__ */