2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <linux/hdmi.h>
30 #include <drm/i915_drm.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_dp_helper.h>
38 * _wait_for - magic (register) wait macro
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
45 #define _wait_for(COND, MS, W) ({ \
46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
49 if (time_after(jiffies, timeout__)) { \
54 if (W && drm_can_sleep()) { \
63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
68 #define KHz(x) (1000*x)
69 #define MHz(x) KHz(1000*x)
72 * Display related stuff
75 /* store information about an Ixxx DVO */
76 /* The i830->i865 use multiple DVOs with multiple i2cs */
77 /* the i915, i945 have a single sDVO i2c bus - which is different */
79 /* maximum connectors per crtcs in the mode set */
81 #define INTEL_I2C_BUS_DVO 1
82 #define INTEL_I2C_BUS_SDVO 2
84 /* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86 #define INTEL_OUTPUT_UNUSED 0
87 #define INTEL_OUTPUT_ANALOG 1
88 #define INTEL_OUTPUT_DVO 2
89 #define INTEL_OUTPUT_SDVO 3
90 #define INTEL_OUTPUT_LVDS 4
91 #define INTEL_OUTPUT_TVOUT 5
92 #define INTEL_OUTPUT_HDMI 6
93 #define INTEL_OUTPUT_DISPLAYPORT 7
94 #define INTEL_OUTPUT_EDP 8
95 #define INTEL_OUTPUT_DSI 9
96 #define INTEL_OUTPUT_UNKNOWN 10
98 #define INTEL_DVO_CHIP_NONE 0
99 #define INTEL_DVO_CHIP_LVDS 1
100 #define INTEL_DVO_CHIP_TMDS 2
101 #define INTEL_DVO_CHIP_TVOUT 4
103 #define INTEL_DSI_COMMAND_MODE 0
104 #define INTEL_DSI_VIDEO_MODE 1
106 struct intel_framebuffer
{
107 struct drm_framebuffer base
;
108 struct drm_i915_gem_object
*obj
;
112 struct drm_fb_helper helper
;
113 struct intel_framebuffer ifb
;
114 struct list_head fbdev_list
;
115 struct drm_display_mode
*our_mode
;
118 struct intel_encoder
{
119 struct drm_encoder base
;
121 * The new crtc this encoder will be driven from. Only differs from
122 * base->crtc while a modeset is in progress.
124 struct intel_crtc
*new_crtc
;
128 * Intel hw has only one MUX where encoders could be clone, hence a
129 * simple flag is enough to compute the possible_clones mask.
132 bool connectors_active
;
133 void (*hot_plug
)(struct intel_encoder
*);
134 bool (*compute_config
)(struct intel_encoder
*,
135 struct intel_crtc_config
*);
136 void (*pre_pll_enable
)(struct intel_encoder
*);
137 void (*pre_enable
)(struct intel_encoder
*);
138 void (*enable
)(struct intel_encoder
*);
139 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
140 void (*disable
)(struct intel_encoder
*);
141 void (*post_disable
)(struct intel_encoder
*);
142 /* Read out the current hw state of this connector, returning true if
143 * the encoder is active. If the encoder is enabled it also set the pipe
144 * it is connected to in the pipe parameter. */
145 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
146 /* Reconstructs the equivalent mode flags for the current hardware
147 * state. This must be called _after_ display->get_pipe_config has
148 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
149 * be set correctly before calling this function. */
150 void (*get_config
)(struct intel_encoder
*,
151 struct intel_crtc_config
*pipe_config
);
153 enum hpd_pin hpd_pin
;
157 struct drm_display_mode
*fixed_mode
;
161 struct intel_connector
{
162 struct drm_connector base
;
164 * The fixed encoder this connector is connected to.
166 struct intel_encoder
*encoder
;
169 * The new encoder this connector will be driven. Only differs from
170 * encoder while a modeset is in progress.
172 struct intel_encoder
*new_encoder
;
174 /* Reads out the current hw, returning true if the connector is enabled
175 * and active (i.e. dpms ON state). */
176 bool (*get_hw_state
)(struct intel_connector
*);
178 /* Panel info for eDP and LVDS */
179 struct intel_panel panel
;
181 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
184 /* since POLL and HPD connectors may use the same HPD line keep the native
185 state of connector->polled in case hotplug storm detection changes it */
189 typedef struct dpll
{
201 struct intel_crtc_config
{
203 * quirks - bitfield with hw state readout quirks
205 * For various reasons the hw state readout code might not be able to
206 * completely faithfully read out the current state. These cases are
207 * tracked with quirk flags so that fastboot and state checker can act
210 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
211 unsigned long quirks
;
213 /* User requested mode, only valid as a starting point to
214 * compute adjusted_mode, except in the case of (S)DVO where
215 * it's also for the output timings of the (S)DVO chip.
216 * adjusted_mode will then correspond to the S(DVO) chip's
217 * preferred input timings. */
218 struct drm_display_mode requested_mode
;
219 /* Actual pipe timings ie. what we program into the pipe timing
220 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
221 struct drm_display_mode adjusted_mode
;
223 /* Pipe source size (ie. panel fitter input size)
224 * All planes will be positioned inside this space,
225 * and get clipped at the edges. */
226 int pipe_src_w
, pipe_src_h
;
228 /* Whether to set up the PCH/FDI. Note that we never allow sharing
229 * between pch encoders and cpu encoders. */
230 bool has_pch_encoder
;
232 /* CPU Transcoder for the pipe. Currently this can only differ from the
233 * pipe on Haswell (where we have a special eDP transcoder). */
234 enum transcoder cpu_transcoder
;
237 * Use reduced/limited/broadcast rbg range, compressing from the full
238 * range fed into the crtcs.
240 bool limited_color_range
;
242 /* DP has a bunch of special case unfortunately, so mark the pipe
247 * Enable dithering, used when the selected pipe bpp doesn't match the
252 /* Controls for the clock computation, to override various stages. */
255 /* SDVO TV has a bunch of special case. To make multifunction encoders
256 * work correctly, we need to track this at runtime.*/
260 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
261 * required. This is set in the 2nd loop of calling encoder's
262 * ->compute_config if the first pick doesn't work out.
266 /* Settings for the intel dpll used on pretty much everything but
270 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
271 enum intel_dpll_id shared_dpll
;
273 /* Actual register state of the dpll, for shared dpll cross-checking. */
274 struct intel_dpll_hw_state dpll_hw_state
;
277 struct intel_link_m_n dp_m_n
;
280 * Frequence the dpll for the port should run at. Differs from the
281 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
282 * already multiplied by pixel_multiplier.
286 /* Used by SDVO (and if we ever fix it, HDMI). */
287 unsigned pixel_multiplier
;
289 /* Panel fitter controls for gen2-gen4 + VLV */
293 u32 lvds_border_bits
;
296 /* Panel fitter placement and size for Ironlake+ */
303 /* FDI configuration, only valid if has_pch_encoder is set. */
305 struct intel_link_m_n fdi_m_n
;
312 struct intel_pipe_wm
{
313 struct intel_wm_level wm
[5];
319 struct drm_crtc base
;
322 u8 lut_r
[256], lut_g
[256], lut_b
[256];
324 * Whether the crtc and the connected output pipeline is active. Implies
325 * that crtc->enabled is set, i.e. the current mode configuration has
326 * some outputs connected to this crtc.
329 unsigned long enabled_power_domains
;
331 bool primary_enabled
; /* is the primary plane (partially) visible? */
333 struct intel_overlay
*overlay
;
334 struct intel_unpin_work
*unpin_work
;
336 atomic_t unpin_work_count
;
338 /* Display surface base address adjustement for pageflips. Note that on
339 * gen4+ this only adjusts up to a tile, offsets within a tile are
340 * handled in the hw itself (with the TILEOFF register). */
341 unsigned long dspaddr_offset
;
343 struct drm_i915_gem_object
*cursor_bo
;
344 uint32_t cursor_addr
;
345 int16_t cursor_x
, cursor_y
;
346 int16_t cursor_width
, cursor_height
;
349 struct intel_crtc_config config
;
351 uint32_t ddi_pll_sel
;
353 /* reset counter value when the last flip was submitted */
354 unsigned int reset_counter
;
356 /* Access to these should be protected by dev_priv->irq_lock. */
357 bool cpu_fifo_underrun_disabled
;
358 bool pch_fifo_underrun_disabled
;
360 /* per-pipe watermark state */
362 /* watermarks currently being used */
363 struct intel_pipe_wm active
;
367 struct intel_plane_wm_parameters
{
368 uint32_t horiz_pixels
;
369 uint8_t bytes_per_pixel
;
375 struct drm_plane base
;
378 struct drm_i915_gem_object
*obj
;
381 u32 lut_r
[1024], lut_g
[1024], lut_b
[1024];
383 unsigned int crtc_w
, crtc_h
;
384 uint32_t src_x
, src_y
;
385 uint32_t src_w
, src_h
;
387 /* Since we need to change the watermarks before/after
388 * enabling/disabling the planes, we need to store the parameters here
389 * as the other pieces of the struct may not reflect the values we want
390 * for the watermark calculations. Currently only Haswell uses this.
392 struct intel_plane_wm_parameters wm
;
394 void (*update_plane
)(struct drm_plane
*plane
,
395 struct drm_crtc
*crtc
,
396 struct drm_framebuffer
*fb
,
397 struct drm_i915_gem_object
*obj
,
398 int crtc_x
, int crtc_y
,
399 unsigned int crtc_w
, unsigned int crtc_h
,
400 uint32_t x
, uint32_t y
,
401 uint32_t src_w
, uint32_t src_h
);
402 void (*disable_plane
)(struct drm_plane
*plane
,
403 struct drm_crtc
*crtc
);
404 int (*update_colorkey
)(struct drm_plane
*plane
,
405 struct drm_intel_sprite_colorkey
*key
);
406 void (*get_colorkey
)(struct drm_plane
*plane
,
407 struct drm_intel_sprite_colorkey
*key
);
410 struct intel_watermark_params
{
411 unsigned long fifo_size
;
412 unsigned long max_wm
;
413 unsigned long default_wm
;
414 unsigned long guard_size
;
415 unsigned long cacheline_size
;
418 struct cxsr_latency
{
421 unsigned long fsb_freq
;
422 unsigned long mem_freq
;
423 unsigned long display_sr
;
424 unsigned long display_hpll_disable
;
425 unsigned long cursor_sr
;
426 unsigned long cursor_hpll_disable
;
429 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
430 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
431 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
432 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
433 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
438 uint32_t color_range
;
439 bool color_range_auto
;
442 enum hdmi_force_audio force_audio
;
443 bool rgb_quant_range_selectable
;
444 void (*write_infoframe
)(struct drm_encoder
*encoder
,
445 enum hdmi_infoframe_type type
,
446 const uint8_t *frame
, ssize_t len
);
447 void (*set_infoframes
)(struct drm_encoder
*encoder
,
448 struct drm_display_mode
*adjusted_mode
);
451 #define DP_MAX_DOWNSTREAM_PORTS 0x10
455 uint32_t aux_ch_ctl_reg
;
458 enum hdmi_force_audio force_audio
;
459 uint32_t color_range
;
460 bool color_range_auto
;
463 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
464 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
465 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
466 struct i2c_adapter adapter
;
467 struct i2c_algo_dp_aux_data algo
;
468 uint8_t train_set
[4];
469 int panel_power_up_delay
;
470 int panel_power_down_delay
;
471 int panel_power_cycle_delay
;
472 int backlight_on_delay
;
473 int backlight_off_delay
;
474 struct delayed_work panel_vdd_work
;
477 struct intel_connector
*attached_connector
;
480 struct intel_digital_port
{
481 struct intel_encoder base
;
485 struct intel_hdmi hdmi
;
489 vlv_dport_to_channel(struct intel_digital_port
*dport
)
491 switch (dport
->port
) {
501 static inline struct drm_crtc
*
502 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
505 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
508 static inline struct drm_crtc
*
509 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
512 return dev_priv
->plane_to_crtc_mapping
[plane
];
515 struct intel_unpin_work
{
516 struct work_struct work
;
517 struct drm_crtc
*crtc
;
518 struct drm_i915_gem_object
*old_fb_obj
;
519 struct drm_i915_gem_object
*pending_flip_obj
;
520 struct drm_pending_vblank_event
*event
;
522 #define INTEL_FLIP_INACTIVE 0
523 #define INTEL_FLIP_PENDING 1
524 #define INTEL_FLIP_COMPLETE 2
525 bool enable_stall_check
;
528 struct intel_set_config
{
529 struct drm_encoder
**save_connector_encoders
;
530 struct drm_crtc
**save_encoder_crtcs
;
536 struct intel_load_detect_pipe
{
537 struct drm_framebuffer
*release_fb
;
538 bool load_detect_temp
;
542 static inline struct intel_encoder
*
543 intel_attached_encoder(struct drm_connector
*connector
)
545 return to_intel_connector(connector
)->encoder
;
548 static inline struct intel_digital_port
*
549 enc_to_dig_port(struct drm_encoder
*encoder
)
551 return container_of(encoder
, struct intel_digital_port
, base
.base
);
554 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
556 return &enc_to_dig_port(encoder
)->dp
;
559 static inline struct intel_digital_port
*
560 dp_to_dig_port(struct intel_dp
*intel_dp
)
562 return container_of(intel_dp
, struct intel_digital_port
, dp
);
565 static inline struct intel_digital_port
*
566 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
568 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
573 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
574 enum pipe pipe
, bool enable
);
575 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
576 enum transcoder pch_transcoder
,
578 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
579 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
580 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
581 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
582 void hsw_pc8_disable_interrupts(struct drm_device
*dev
);
583 void hsw_pc8_restore_interrupts(struct drm_device
*dev
);
587 void intel_crt_init(struct drm_device
*dev
);
591 void intel_prepare_ddi(struct drm_device
*dev
);
592 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
593 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
594 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
595 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
596 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
);
597 void intel_ddi_pll_init(struct drm_device
*dev
);
598 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
599 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
600 enum transcoder cpu_transcoder
);
601 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
602 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
603 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
);
604 bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
);
605 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
);
606 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
607 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
);
608 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
609 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
610 void intel_ddi_get_config(struct intel_encoder
*encoder
,
611 struct intel_crtc_config
*pipe_config
);
614 /* intel_display.c */
615 int intel_pch_rawclk(struct drm_device
*dev
);
616 void intel_mark_busy(struct drm_device
*dev
);
617 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
618 struct intel_ring_buffer
*ring
);
619 void intel_mark_idle(struct drm_device
*dev
);
620 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
621 void intel_crtc_update_dpms(struct drm_crtc
*crtc
);
622 void intel_encoder_destroy(struct drm_encoder
*encoder
);
623 void intel_connector_dpms(struct drm_connector
*, int mode
);
624 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
625 void intel_modeset_check_state(struct drm_device
*dev
);
626 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
627 struct intel_digital_port
*port
);
628 void intel_connector_attach_encoder(struct intel_connector
*connector
,
629 struct intel_encoder
*encoder
);
630 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
631 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
632 struct drm_crtc
*crtc
);
633 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
634 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
635 struct drm_file
*file_priv
);
636 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
638 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
);
639 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
);
640 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
641 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
);
642 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
643 struct drm_display_mode
*mode
,
644 struct intel_load_detect_pipe
*old
);
645 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
646 struct intel_load_detect_pipe
*old
);
647 int intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
648 struct drm_i915_gem_object
*obj
,
649 struct intel_ring_buffer
*pipelined
);
650 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
);
651 int intel_framebuffer_init(struct drm_device
*dev
,
652 struct intel_framebuffer
*ifb
,
653 struct drm_mode_fb_cmd2
*mode_cmd
,
654 struct drm_i915_gem_object
*obj
);
655 void intel_framebuffer_fini(struct intel_framebuffer
*fb
);
656 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
657 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
658 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
659 struct intel_shared_dpll
*intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
);
660 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
661 struct intel_shared_dpll
*pll
,
663 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
664 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
665 void assert_pll(struct drm_i915_private
*dev_priv
,
666 enum pipe pipe
, bool state
);
667 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
668 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
669 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
670 enum pipe pipe
, bool state
);
671 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
672 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
673 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
674 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
675 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
676 void intel_write_eld(struct drm_encoder
*encoder
,
677 struct drm_display_mode
*mode
);
678 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
679 unsigned int tiling_mode
,
682 void intel_display_handle_reset(struct drm_device
*dev
);
683 void hsw_enable_pc8_work(struct work_struct
*__work
);
684 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
);
685 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
);
686 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
687 struct intel_crtc_config
*pipe_config
);
688 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
690 ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
692 bool intel_crtc_active(struct drm_crtc
*crtc
);
693 void i915_disable_vga_mem(struct drm_device
*dev
);
694 void hsw_enable_ips(struct intel_crtc
*crtc
);
695 void hsw_disable_ips(struct intel_crtc
*crtc
);
696 void intel_display_set_init_power(struct drm_device
*dev
, bool enable
);
700 void intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
);
701 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
702 struct intel_connector
*intel_connector
);
703 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
704 void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
705 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
706 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
707 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
708 void intel_dp_check_link_status(struct intel_dp
*intel_dp
);
709 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
710 struct intel_crtc_config
*pipe_config
);
711 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
712 void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
);
713 void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
);
714 void ironlake_edp_panel_on(struct intel_dp
*intel_dp
);
715 void ironlake_edp_panel_off(struct intel_dp
*intel_dp
);
716 void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
717 void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
718 void intel_edp_psr_enable(struct intel_dp
*intel_dp
);
719 void intel_edp_psr_disable(struct intel_dp
*intel_dp
);
720 void intel_edp_psr_update(struct drm_device
*dev
);
724 bool intel_dsi_init(struct drm_device
*dev
);
728 void intel_dvo_init(struct drm_device
*dev
);
731 /* legacy fbdev emulation in intel_fbdev.c */
732 #ifdef CONFIG_DRM_I915_FBDEV
733 extern int intel_fbdev_init(struct drm_device
*dev
);
734 extern void intel_fbdev_initial_config(struct drm_device
*dev
);
735 extern void intel_fbdev_fini(struct drm_device
*dev
);
736 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
);
737 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
738 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
740 static inline int intel_fbdev_init(struct drm_device
*dev
)
745 static inline void intel_fbdev_initial_config(struct drm_device
*dev
)
749 static inline void intel_fbdev_fini(struct drm_device
*dev
)
753 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
)
757 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
763 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
);
764 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
765 struct intel_connector
*intel_connector
);
766 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
767 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
768 struct intel_crtc_config
*pipe_config
);
772 void intel_lvds_init(struct drm_device
*dev
);
773 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
777 int intel_connector_update_modes(struct drm_connector
*connector
,
779 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
780 void intel_attach_force_audio_property(struct drm_connector
*connector
);
781 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
784 /* intel_overlay.c */
785 void intel_setup_overlay(struct drm_device
*dev
);
786 void intel_cleanup_overlay(struct drm_device
*dev
);
787 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
788 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
789 struct drm_file
*file_priv
);
790 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
791 struct drm_file
*file_priv
);
795 int intel_panel_init(struct intel_panel
*panel
,
796 struct drm_display_mode
*fixed_mode
);
797 void intel_panel_fini(struct intel_panel
*panel
);
798 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
799 struct drm_display_mode
*adjusted_mode
);
800 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
801 struct intel_crtc_config
*pipe_config
,
803 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
804 struct intel_crtc_config
*pipe_config
,
806 void intel_panel_set_backlight(struct intel_connector
*connector
, u32 level
,
808 int intel_panel_setup_backlight(struct drm_connector
*connector
);
809 void intel_panel_enable_backlight(struct intel_connector
*connector
);
810 void intel_panel_disable_backlight(struct intel_connector
*connector
);
811 void intel_panel_destroy_backlight(struct drm_device
*dev
);
812 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
816 void intel_init_clock_gating(struct drm_device
*dev
);
817 void intel_suspend_hw(struct drm_device
*dev
);
818 void intel_update_watermarks(struct drm_crtc
*crtc
);
819 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
820 struct drm_crtc
*crtc
,
821 uint32_t sprite_width
, int pixel_size
,
822 bool enabled
, bool scaled
);
823 void intel_init_pm(struct drm_device
*dev
);
824 bool intel_fbc_enabled(struct drm_device
*dev
);
825 void intel_update_fbc(struct drm_device
*dev
);
826 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
827 void intel_gpu_ips_teardown(void);
828 int intel_power_domains_init(struct drm_device
*dev
);
829 void intel_power_domains_remove(struct drm_device
*dev
);
830 bool intel_display_power_enabled(struct drm_device
*dev
,
831 enum intel_display_power_domain domain
);
832 void intel_display_power_get(struct drm_device
*dev
,
833 enum intel_display_power_domain domain
);
834 void intel_display_power_put(struct drm_device
*dev
,
835 enum intel_display_power_domain domain
);
836 void intel_power_domains_init_hw(struct drm_device
*dev
);
837 void intel_set_power_well(struct drm_device
*dev
, bool enable
);
838 void intel_enable_gt_powersave(struct drm_device
*dev
);
839 void intel_disable_gt_powersave(struct drm_device
*dev
);
840 void ironlake_teardown_rc6(struct drm_device
*dev
);
841 void gen6_update_ring_freq(struct drm_device
*dev
);
842 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
843 void gen6_rps_boost(struct drm_i915_private
*dev_priv
);
844 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
);
845 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
);
846 void ilk_wm_get_hw_state(struct drm_device
*dev
);
850 bool intel_sdvo_init(struct drm_device
*dev
, uint32_t sdvo_reg
, bool is_sdvob
);
854 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
855 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
857 void intel_plane_restore(struct drm_plane
*plane
);
858 void intel_plane_disable(struct drm_plane
*plane
);
859 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
860 struct drm_file
*file_priv
);
861 int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
862 struct drm_file
*file_priv
);
866 void intel_tv_init(struct drm_device
*dev
);
868 #endif /* __INTEL_DRV_H__ */