drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_mst_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000 * (x))
  69 #define MHz(x) KHz(1000 * (x))
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80
  81 /* Maximum cursor sizes */
  82 #define GEN2_CURSOR_WIDTH 64
  83 #define GEN2_CURSOR_HEIGHT 64
  84 #define MAX_CURSOR_WIDTH 256
  85 #define MAX_CURSOR_HEIGHT 256
  86
  87 #define INTEL_I2C_BUS_DVO 1
  88 #define INTEL_I2C_BUS_SDVO 2
  89
  90 /* these are outputs from the chip - integrated only
  91    external chips are via DVO or SDVO output */
  92 #define INTEL_OUTPUT_UNUSED 0
  93 #define INTEL_OUTPUT_ANALOG 1
  94 #define INTEL_OUTPUT_DVO 2
  95 #define INTEL_OUTPUT_SDVO 3
  96 #define INTEL_OUTPUT_LVDS 4
  97 #define INTEL_OUTPUT_TVOUT 5
  98 #define INTEL_OUTPUT_HDMI 6
  99 #define INTEL_OUTPUT_DISPLAYPORT 7
 100 #define INTEL_OUTPUT_EDP 8
 101 #define INTEL_OUTPUT_DSI 9
 102 #define INTEL_OUTPUT_UNKNOWN 10
 103 #define INTEL_OUTPUT_DP_MST 11
 104
 105 #define INTEL_DVO_CHIP_NONE 0
 106 #define INTEL_DVO_CHIP_LVDS 1
 107 #define INTEL_DVO_CHIP_TMDS 2
 108 #define INTEL_DVO_CHIP_TVOUT 4
 109
 110 #define INTEL_DSI_VIDEO_MODE    0
 111 #define INTEL_DSI_COMMAND_MODE  1
 112
 113 struct intel_framebuffer {
 114         struct drm_framebuffer base;
 115         struct drm_i915_gem_object *obj;
 116 };
 117
 118 struct intel_fbdev {
 119         struct drm_fb_helper helper;
 120         struct intel_framebuffer *fb;
 121         struct list_head fbdev_list;
 122         struct drm_display_mode *our_mode;
 123         int preferred_bpp;
 124 };
 125
 126 struct intel_encoder {
 127         struct drm_encoder base;
 128         /*
 129          * The new crtc this encoder will be driven from. Only differs from
 130          * base->crtc while a modeset is in progress.
 131          */
 132         struct intel_crtc *new_crtc;
 133
 134         int type;
 135         unsigned int cloneable;
 136         bool connectors_active;
 137         void (*hot_plug)(struct intel_encoder *);
 138         bool (*compute_config)(struct intel_encoder *,
 139                                struct intel_crtc_config *);
 140         void (*pre_pll_enable)(struct intel_encoder *);
 141         void (*pre_enable)(struct intel_encoder *);
 142         void (*enable)(struct intel_encoder *);
 143         void (*mode_set)(struct intel_encoder *intel_encoder);
 144         void (*disable)(struct intel_encoder *);
 145         void (*post_disable)(struct intel_encoder *);
 146         /* Read out the current hw state of this connector, returning true if
 147          * the encoder is active. If the encoder is enabled it also set the pipe
 148          * it is connected to in the pipe parameter. */
 149         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 150         /* Reconstructs the equivalent mode flags for the current hardware
 151          * state. This must be called _after_ display->get_pipe_config has
 152          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 153          * be set correctly before calling this function. */
 154         void (*get_config)(struct intel_encoder *,
 155                            struct intel_crtc_config *pipe_config);
 156         /*
 157          * Called during system suspend after all pending requests for the
 158          * encoder are flushed (for example for DP AUX transactions) and
 159          * device interrupts are disabled.
 160          */
 161         void (*suspend)(struct intel_encoder *);
 162         int crtc_mask;
 163         enum hpd_pin hpd_pin;
 164 };
 165
 166 struct intel_panel {
 167         struct drm_display_mode *fixed_mode;
 168         struct drm_display_mode *downclock_mode;
 169         int fitting_mode;
 170
 171         /* backlight */
 172         struct {
 173                 bool present;
 174                 u32 level;
 175                 u32 min;
 176                 u32 max;
 177                 bool enabled;
 178                 bool combination_mode;  /* gen 2/4 only */
 179                 bool active_low_pwm;
 180                 struct backlight_device *device;
 181         } backlight;
 182 };
 183
 184 struct intel_connector {
 185         struct drm_connector base;
 186         /*
 187          * The fixed encoder this connector is connected to.
 188          */
 189         struct intel_encoder *encoder;
 190
 191         /*
 192          * The new encoder this connector will be driven. Only differs from
 193          * encoder while a modeset is in progress.
 194          */
 195         struct intel_encoder *new_encoder;
 196
 197         /* Reads out the current hw, returning true if the connector is enabled
 198          * and active (i.e. dpms ON state). */
 199         bool (*get_hw_state)(struct intel_connector *);
 200
 201         /*
 202          * Removes all interfaces through which the connector is accessible
 203          * - like sysfs, debugfs entries -, so that no new operations can be
 204          * started on the connector. Also makes sure all currently pending
 205          * operations finish before returing.
 206          */
 207         void (*unregister)(struct intel_connector *);
 208
 209         /* Panel info for eDP and LVDS */
 210         struct intel_panel panel;
 211
 212         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 213         struct edid *edid;
 214
 215         /* since POLL and HPD connectors may use the same HPD line keep the native
 216            state of connector->polled in case hotplug storm detection changes it */
 217         u8 polled;
 218
 219         void *port; /* store this opaque as its illegal to dereference it */
 220
 221         struct intel_dp *mst_port;
 222 };
 223
 224 typedef struct dpll {
 225         /* given values */
 226         int n;
 227         int m1, m2;
 228         int p1, p2;
 229         /* derived values */
 230         int     dot;
 231         int     vco;
 232         int     m;
 233         int     p;
 234 } intel_clock_t;
 235
 236 struct intel_plane_config {
 237         bool tiled;
 238         int size;
 239         u32 base;
 240 };
 241
 242 struct intel_crtc_config {
 243         /**
 244          * quirks - bitfield with hw state readout quirks
 245          *
 246          * For various reasons the hw state readout code might not be able to
 247          * completely faithfully read out the current state. These cases are
 248          * tracked with quirk flags so that fastboot and state checker can act
 249          * accordingly.
 250          */
 251 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 252 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 253         unsigned long quirks;
 254
 255         /* User requested mode, only valid as a starting point to
 256          * compute adjusted_mode, except in the case of (S)DVO where
 257          * it's also for the output timings of the (S)DVO chip.
 258          * adjusted_mode will then correspond to the S(DVO) chip's
 259          * preferred input timings. */
 260         struct drm_display_mode requested_mode;
 261         /* Actual pipe timings ie. what we program into the pipe timing
 262          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 263         struct drm_display_mode adjusted_mode;
 264
 265         /* Pipe source size (ie. panel fitter input size)
 266          * All planes will be positioned inside this space,
 267          * and get clipped at the edges. */
 268         int pipe_src_w, pipe_src_h;
 269
 270         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 271          * between pch encoders and cpu encoders. */
 272         bool has_pch_encoder;
 273
 274         /* CPU Transcoder for the pipe. Currently this can only differ from the
 275          * pipe on Haswell (where we have a special eDP transcoder). */
 276         enum transcoder cpu_transcoder;
 277
 278         /*
 279          * Use reduced/limited/broadcast rbg range, compressing from the full
 280          * range fed into the crtcs.
 281          */
 282         bool limited_color_range;
 283
 284         /* DP has a bunch of special case unfortunately, so mark the pipe
 285          * accordingly. */
 286         bool has_dp_encoder;
 287
 288         /* Whether we should send NULL infoframes. Required for audio. */
 289         bool has_hdmi_sink;
 290
 291         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 292          * has_dp_encoder is set. */
 293         bool has_audio;
 294
 295         /*
 296          * Enable dithering, used when the selected pipe bpp doesn't match the
 297          * plane bpp.
 298          */
 299         bool dither;
 300
 301         /* Controls for the clock computation, to override various stages. */
 302         bool clock_set;
 303
 304         /* SDVO TV has a bunch of special case. To make multifunction encoders
 305          * work correctly, we need to track this at runtime.*/
 306         bool sdvo_tv_clock;
 307
 308         /*
 309          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 310          * required. This is set in the 2nd loop of calling encoder's
 311          * ->compute_config if the first pick doesn't work out.
 312          */
 313         bool bw_constrained;
 314
 315         /* Settings for the intel dpll used on pretty much everything but
 316          * haswell. */
 317         struct dpll dpll;
 318
 319         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 320         enum intel_dpll_id shared_dpll;
 321
 322         /* PORT_CLK_SEL for DDI ports. */
 323         uint32_t ddi_pll_sel;
 324
 325         /* Actual register state of the dpll, for shared dpll cross-checking. */
 326         struct intel_dpll_hw_state dpll_hw_state;
 327
 328         int pipe_bpp;
 329         struct intel_link_m_n dp_m_n;
 330
 331         /* m2_n2 for eDP downclock */
 332         struct intel_link_m_n dp_m2_n2;
 333
 334         /*
 335          * Frequence the dpll for the port should run at. Differs from the
 336          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 337          * already multiplied by pixel_multiplier.
 338          */
 339         int port_clock;
 340
 341         /* Used by SDVO (and if we ever fix it, HDMI). */
 342         unsigned pixel_multiplier;
 343
 344         /* Panel fitter controls for gen2-gen4 + VLV */
 345         struct {
 346                 u32 control;
 347                 u32 pgm_ratios;
 348                 u32 lvds_border_bits;
 349         } gmch_pfit;
 350
 351         /* Panel fitter placement and size for Ironlake+ */
 352         struct {
 353                 u32 pos;
 354                 u32 size;
 355                 bool enabled;
 356                 bool force_thru;
 357         } pch_pfit;
 358
 359         /* FDI configuration, only valid if has_pch_encoder is set. */
 360         int fdi_lanes;
 361         struct intel_link_m_n fdi_m_n;
 362
 363         bool ips_enabled;
 364
 365         bool double_wide;
 366
 367         bool dp_encoder_is_mst;
 368         int pbn;
 369 };
 370
 371 struct intel_pipe_wm {
 372         struct intel_wm_level wm[5];
 373         uint32_t linetime;
 374         bool fbc_wm_enabled;
 375         bool pipe_enabled;
 376         bool sprites_enabled;
 377         bool sprites_scaled;
 378 };
 379
 380 struct intel_mmio_flip {
 381         u32 seqno;
 382         u32 ring_id;
 383 };
 384
 385 struct intel_crtc {
 386         struct drm_crtc base;
 387         enum pipe pipe;
 388         enum plane plane;
 389         u8 lut_r[256], lut_g[256], lut_b[256];
 390         /*
 391          * Whether the crtc and the connected output pipeline is active. Implies
 392          * that crtc->enabled is set, i.e. the current mode configuration has
 393          * some outputs connected to this crtc.
 394          */
 395         bool active;
 396         unsigned long enabled_power_domains;
 397         bool primary_enabled; /* is the primary plane (partially) visible? */
 398         bool lowfreq_avail;
 399         struct intel_overlay *overlay;
 400         struct intel_unpin_work *unpin_work;
 401
 402         atomic_t unpin_work_count;
 403
 404         /* Display surface base address adjustement for pageflips. Note that on
 405          * gen4+ this only adjusts up to a tile, offsets within a tile are
 406          * handled in the hw itself (with the TILEOFF register). */
 407         unsigned long dspaddr_offset;
 408
 409         struct drm_i915_gem_object *cursor_bo;
 410         uint32_t cursor_addr;
 411         int16_t cursor_width, cursor_height;
 412         uint32_t cursor_cntl;
 413         uint32_t cursor_base;
 414
 415         struct intel_plane_config plane_config;
 416         struct intel_crtc_config config;
 417         struct intel_crtc_config *new_config;
 418         bool new_enabled;
 419
 420         /* reset counter value when the last flip was submitted */
 421         unsigned int reset_counter;
 422
 423         /* Access to these should be protected by dev_priv->irq_lock. */
 424         bool cpu_fifo_underrun_disabled;
 425         bool pch_fifo_underrun_disabled;
 426
 427         /* per-pipe watermark state */
 428         struct {
 429                 /* watermarks currently being used  */
 430                 struct intel_pipe_wm active;
 431         } wm;
 432
 433         wait_queue_head_t vbl_wait;
 434
 435         int scanline_offset;
 436         struct intel_mmio_flip mmio_flip;
 437 };
 438
 439 struct intel_plane_wm_parameters {
 440         uint32_t horiz_pixels;
 441         uint32_t vert_pixels;
 442         uint8_t bytes_per_pixel;
 443         bool enabled;
 444         bool scaled;
 445 };
 446
 447 struct intel_plane {
 448         struct drm_plane base;
 449         int plane;
 450         enum pipe pipe;
 451         struct drm_i915_gem_object *obj;
 452         bool can_scale;
 453         int max_downscale;
 454         int crtc_x, crtc_y;
 455         unsigned int crtc_w, crtc_h;
 456         uint32_t src_x, src_y;
 457         uint32_t src_w, src_h;
 458
 459         /* Since we need to change the watermarks before/after
 460          * enabling/disabling the planes, we need to store the parameters here
 461          * as the other pieces of the struct may not reflect the values we want
 462          * for the watermark calculations. Currently only Haswell uses this.
 463          */
 464         struct intel_plane_wm_parameters wm;
 465
 466         void (*update_plane)(struct drm_plane *plane,
 467                              struct drm_crtc *crtc,
 468                              struct drm_framebuffer *fb,
 469                              struct drm_i915_gem_object *obj,
 470                              int crtc_x, int crtc_y,
 471                              unsigned int crtc_w, unsigned int crtc_h,
 472                              uint32_t x, uint32_t y,
 473                              uint32_t src_w, uint32_t src_h);
 474         void (*disable_plane)(struct drm_plane *plane,
 475                               struct drm_crtc *crtc);
 476         int (*update_colorkey)(struct drm_plane *plane,
 477                                struct drm_intel_sprite_colorkey *key);
 478         void (*get_colorkey)(struct drm_plane *plane,
 479                              struct drm_intel_sprite_colorkey *key);
 480 };
 481
 482 struct intel_watermark_params {
 483         unsigned long fifo_size;
 484         unsigned long max_wm;
 485         unsigned long default_wm;
 486         unsigned long guard_size;
 487         unsigned long cacheline_size;
 488 };
 489
 490 struct cxsr_latency {
 491         int is_desktop;
 492         int is_ddr3;
 493         unsigned long fsb_freq;
 494         unsigned long mem_freq;
 495         unsigned long display_sr;
 496         unsigned long display_hpll_disable;
 497         unsigned long cursor_sr;
 498         unsigned long cursor_hpll_disable;
 499 };
 500
 501 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 502 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 503 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 504 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 505 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 506 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 507
 508 struct intel_hdmi {
 509         u32 hdmi_reg;
 510         int ddc_bus;
 511         uint32_t color_range;
 512         bool color_range_auto;
 513         bool has_hdmi_sink;
 514         bool has_audio;
 515         enum hdmi_force_audio force_audio;
 516         bool rgb_quant_range_selectable;
 517         enum hdmi_picture_aspect aspect_ratio;
 518         void (*write_infoframe)(struct drm_encoder *encoder,
 519                                 enum hdmi_infoframe_type type,
 520                                 const void *frame, ssize_t len);
 521         void (*set_infoframes)(struct drm_encoder *encoder,
 522                                bool enable,
 523                                struct drm_display_mode *adjusted_mode);
 524 };
 525
 526 struct intel_dp_mst_encoder;
 527 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 528
 529 /**
 530  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 531  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 532  * parsing for same resolution.
 533  */
 534 enum edp_drrs_refresh_rate_type {
 535         DRRS_HIGH_RR,
 536         DRRS_LOW_RR,
 537         DRRS_MAX_RR, /* RR count */
 538 };
 539
 540 struct intel_dp {
 541         uint32_t output_reg;
 542         uint32_t aux_ch_ctl_reg;
 543         uint32_t DP;
 544         bool has_audio;
 545         enum hdmi_force_audio force_audio;
 546         uint32_t color_range;
 547         bool color_range_auto;
 548         uint8_t link_bw;
 549         uint8_t lane_count;
 550         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 551         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 552         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 553         struct drm_dp_aux aux;
 554         uint8_t train_set[4];
 555         int panel_power_up_delay;
 556         int panel_power_down_delay;
 557         int panel_power_cycle_delay;
 558         int backlight_on_delay;
 559         int backlight_off_delay;
 560         struct delayed_work panel_vdd_work;
 561         bool want_panel_vdd;
 562         unsigned long last_power_cycle;
 563         unsigned long last_power_on;
 564         unsigned long last_backlight_off;
 565
 566         struct notifier_block edp_notifier;
 567
 568         bool use_tps3;
 569         bool can_mst; /* this port supports mst */
 570         bool is_mst;
 571         int active_mst_links;
 572         /* connector directly attached - won't be use for modeset in mst world */
 573         struct intel_connector *attached_connector;
 574
 575         /* mst connector list */
 576         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 577         struct drm_dp_mst_topology_mgr mst_mgr;
 578
 579         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 580         /*
 581          * This function returns the value we have to program the AUX_CTL
 582          * register with to kick off an AUX transaction.
 583          */
 584         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 585                                      bool has_aux_irq,
 586                                      int send_bytes,
 587                                      uint32_t aux_clock_divider);
 588         struct {
 589                 enum drrs_support_type type;
 590                 enum edp_drrs_refresh_rate_type refresh_rate_type;
 591                 struct mutex mutex;
 592         } drrs_state;
 593
 594 };
 595
 596 struct intel_digital_port {
 597         struct intel_encoder base;
 598         enum port port;
 599         u32 saved_port_bits;
 600         struct intel_dp dp;
 601         struct intel_hdmi hdmi;
 602         bool (*hpd_pulse)(struct intel_digital_port *, bool);
 603 };
 604
 605 struct intel_dp_mst_encoder {
 606         struct intel_encoder base;
 607         enum pipe pipe;
 608         struct intel_digital_port *primary;
 609         void *port; /* store this opaque as its illegal to dereference it */
 610 };
 611
 612 static inline int
 613 vlv_dport_to_channel(struct intel_digital_port *dport)
 614 {
 615         switch (dport->port) {
 616         case PORT_B:
 617         case PORT_D:
 618                 return DPIO_CH0;
 619         case PORT_C:
 620                 return DPIO_CH1;
 621         default:
 622                 BUG();
 623         }
 624 }
 625
 626 static inline int
 627 vlv_pipe_to_channel(enum pipe pipe)
 628 {
 629         switch (pipe) {
 630         case PIPE_A:
 631         case PIPE_C:
 632                 return DPIO_CH0;
 633         case PIPE_B:
 634                 return DPIO_CH1;
 635         default:
 636                 BUG();
 637         }
 638 }
 639
 640 static inline struct drm_crtc *
 641 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 642 {
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         return dev_priv->pipe_to_crtc_mapping[pipe];
 645 }
 646
 647 static inline struct drm_crtc *
 648 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 649 {
 650         struct drm_i915_private *dev_priv = dev->dev_private;
 651         return dev_priv->plane_to_crtc_mapping[plane];
 652 }
 653
 654 struct intel_unpin_work {
 655         struct work_struct work;
 656         struct drm_crtc *crtc;
 657         struct drm_i915_gem_object *old_fb_obj;
 658         struct drm_i915_gem_object *pending_flip_obj;
 659         struct drm_pending_vblank_event *event;
 660         atomic_t pending;
 661 #define INTEL_FLIP_INACTIVE     0
 662 #define INTEL_FLIP_PENDING      1
 663 #define INTEL_FLIP_COMPLETE     2
 664         u32 flip_count;
 665         u32 gtt_offset;
 666         bool enable_stall_check;
 667 };
 668
 669 struct intel_set_config {
 670         struct drm_encoder **save_connector_encoders;
 671         struct drm_crtc **save_encoder_crtcs;
 672         bool *save_crtc_enabled;
 673
 674         bool fb_changed;
 675         bool mode_changed;
 676 };
 677
 678 struct intel_load_detect_pipe {
 679         struct drm_framebuffer *release_fb;
 680         bool load_detect_temp;
 681         int dpms_mode;
 682 };
 683
 684 static inline struct intel_encoder *
 685 intel_attached_encoder(struct drm_connector *connector)
 686 {
 687         return to_intel_connector(connector)->encoder;
 688 }
 689
 690 static inline struct intel_digital_port *
 691 enc_to_dig_port(struct drm_encoder *encoder)
 692 {
 693         return container_of(encoder, struct intel_digital_port, base.base);
 694 }
 695
 696 static inline struct intel_dp_mst_encoder *
 697 enc_to_mst(struct drm_encoder *encoder)
 698 {
 699         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 700 }
 701
 702 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 703 {
 704         return &enc_to_dig_port(encoder)->dp;
 705 }
 706
 707 static inline struct intel_digital_port *
 708 dp_to_dig_port(struct intel_dp *intel_dp)
 709 {
 710         return container_of(intel_dp, struct intel_digital_port, dp);
 711 }
 712
 713 static inline struct intel_digital_port *
 714 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 715 {
 716         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 717 }
 718
 719
 720 /* i915_irq.c */
 721 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 722                                            enum pipe pipe, bool enable);
 723 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 724                                            enum transcoder pch_transcoder,
 725                                            bool enable);
 726 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 727 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 728 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 729 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 730 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 731 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 732 void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
 733 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
 734 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 735 {
 736         /*
 737          * We only use drm_irq_uninstall() at unload and VT switch, so
 738          * this is the only thing we need to check.
 739          */
 740         return !dev_priv->pm._irqs_disabled;
 741 }
 742
 743 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 744 void i9xx_check_fifo_underruns(struct drm_device *dev);
 745 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
 746
 747 /* intel_crt.c */
 748 void intel_crt_init(struct drm_device *dev);
 749
 750
 751 /* intel_ddi.c */
 752 void intel_prepare_ddi(struct drm_device *dev);
 753 void hsw_fdi_link_train(struct drm_crtc *crtc);
 754 void intel_ddi_init(struct drm_device *dev, enum port port);
 755 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 756 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 757 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 758 void intel_ddi_pll_init(struct drm_device *dev);
 759 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 760 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 761                                        enum transcoder cpu_transcoder);
 762 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 763 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 764 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 765 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 766 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 767 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 768 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 769 void intel_ddi_get_config(struct intel_encoder *encoder,
 770                           struct intel_crtc_config *pipe_config);
 771
 772 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 773 void intel_ddi_clock_get(struct intel_encoder *encoder,
 774                          struct intel_crtc_config *pipe_config);
 775 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 776
 777 /* intel_display.c */
 778 const char *intel_output_name(int output);
 779 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 780 int intel_pch_rawclk(struct drm_device *dev);
 781 void intel_mark_busy(struct drm_device *dev);
 782 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 783                              struct intel_engine_cs *ring);
 784 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 785                                     unsigned frontbuffer_bits);
 786 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 787                                      unsigned frontbuffer_bits);
 788 void intel_frontbuffer_flush(struct drm_device *dev,
 789                              unsigned frontbuffer_bits);
 790 /**
 791  * intel_frontbuffer_flip - prepare frontbuffer flip
 792  * @dev: DRM device
 793  * @frontbuffer_bits: frontbuffer plane tracking bits
 794  *
 795  * This function gets called after scheduling a flip on @obj. This is for
 796  * synchronous plane updates which will happen on the next vblank and which will
 797  * not get delayed by pending gpu rendering.
 798  *
 799  * Can be called without any locks held.
 800  */
 801 static inline
 802 void intel_frontbuffer_flip(struct drm_device *dev,
 803                             unsigned frontbuffer_bits)
 804 {
 805         intel_frontbuffer_flush(dev, frontbuffer_bits);
 806 }
 807
 808 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 809 void intel_mark_idle(struct drm_device *dev);
 810 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 811 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
 812 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 813 void intel_encoder_destroy(struct drm_encoder *encoder);
 814 void intel_connector_dpms(struct drm_connector *, int mode);
 815 bool intel_connector_get_hw_state(struct intel_connector *connector);
 816 void intel_modeset_check_state(struct drm_device *dev);
 817 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 818                                 struct intel_digital_port *port);
 819 void intel_connector_attach_encoder(struct intel_connector *connector,
 820                                     struct intel_encoder *encoder);
 821 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 822 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 823                                              struct drm_crtc *crtc);
 824 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 825 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 826                                 struct drm_file *file_priv);
 827 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 828                                              enum pipe pipe);
 829 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 830 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 831 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 832 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 833                          struct intel_digital_port *dport);
 834 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 835                                 struct drm_display_mode *mode,
 836                                 struct intel_load_detect_pipe *old,
 837                                 struct drm_modeset_acquire_ctx *ctx);
 838 void intel_release_load_detect_pipe(struct drm_connector *connector,
 839                                     struct intel_load_detect_pipe *old);
 840 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 841                                struct drm_i915_gem_object *obj,
 842                                struct intel_engine_cs *pipelined);
 843 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 844 struct drm_framebuffer *
 845 __intel_framebuffer_create(struct drm_device *dev,
 846                            struct drm_mode_fb_cmd2 *mode_cmd,
 847                            struct drm_i915_gem_object *obj);
 848 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 849 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 850 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 851
 852 /* shared dpll functions */
 853 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 854 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 855                         struct intel_shared_dpll *pll,
 856                         bool state);
 857 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 858 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 859 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
 860 void intel_put_shared_dpll(struct intel_crtc *crtc);
 861
 862 /* modesetting asserts */
 863 void assert_pll(struct drm_i915_private *dev_priv,
 864                 enum pipe pipe, bool state);
 865 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 866 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 867 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 868                        enum pipe pipe, bool state);
 869 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 870 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 871 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 872 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 873 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 874 void intel_write_eld(struct drm_encoder *encoder,
 875                      struct drm_display_mode *mode);
 876 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 877                                              unsigned int tiling_mode,
 878                                              unsigned int bpp,
 879                                              unsigned int pitch);
 880 void intel_display_handle_reset(struct drm_device *dev);
 881 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 882 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 883 void intel_dp_get_m_n(struct intel_crtc *crtc,
 884                       struct intel_crtc_config *pipe_config);
 885 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 886 void
 887 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 888                                 int dotclock);
 889 bool intel_crtc_active(struct drm_crtc *crtc);
 890 void hsw_enable_ips(struct intel_crtc *crtc);
 891 void hsw_disable_ips(struct intel_crtc *crtc);
 892 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
 893 enum intel_display_power_domain
 894 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 895 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 896                                  struct intel_crtc_config *pipe_config);
 897 int intel_format_to_fourcc(int format);
 898 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 899
 900
 901 /* intel_dp.c */
 902 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 903 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 904                              struct intel_connector *intel_connector);
 905 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 906 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 907 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 908 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 909 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 910 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 911 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 912 bool intel_dp_compute_config(struct intel_encoder *encoder,
 913                              struct intel_crtc_config *pipe_config);
 914 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 915 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
 916                         bool long_hpd);
 917 void intel_edp_backlight_on(struct intel_dp *intel_dp);
 918 void intel_edp_backlight_off(struct intel_dp *intel_dp);
 919 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 920 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder);
 921 void intel_edp_panel_on(struct intel_dp *intel_dp);
 922 void intel_edp_panel_off(struct intel_dp *intel_dp);
 923 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 924 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 925 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
 926 void intel_edp_psr_invalidate(struct drm_device *dev,
 927                               unsigned frontbuffer_bits);
 928 void intel_edp_psr_flush(struct drm_device *dev,
 929                          unsigned frontbuffer_bits);
 930 void intel_edp_psr_init(struct drm_device *dev);
 931
 932 int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd);
 933 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
 934 void intel_dp_mst_suspend(struct drm_device *dev);
 935 void intel_dp_mst_resume(struct drm_device *dev);
 936 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
 937 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
 938 /* intel_dp_mst.c */
 939 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 940 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
 941 /* intel_dsi.c */
 942 void intel_dsi_init(struct drm_device *dev);
 943
 944
 945 /* intel_dvo.c */
 946 void intel_dvo_init(struct drm_device *dev);
 947
 948
 949 /* legacy fbdev emulation in intel_fbdev.c */
 950 #ifdef CONFIG_DRM_I915_FBDEV
 951 extern int intel_fbdev_init(struct drm_device *dev);
 952 extern void intel_fbdev_initial_config(struct drm_device *dev);
 953 extern void intel_fbdev_fini(struct drm_device *dev);
 954 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 955 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 956 extern void intel_fbdev_restore_mode(struct drm_device *dev);
 957 #else
 958 static inline int intel_fbdev_init(struct drm_device *dev)
 959 {
 960         return 0;
 961 }
 962
 963 static inline void intel_fbdev_initial_config(struct drm_device *dev)
 964 {
 965 }
 966
 967 static inline void intel_fbdev_fini(struct drm_device *dev)
 968 {
 969 }
 970
 971 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
 972 {
 973 }
 974
 975 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 976 {
 977 }
 978 #endif
 979
 980 /* intel_hdmi.c */
 981 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 982 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 983                                struct intel_connector *intel_connector);
 984 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 985 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 986                                struct intel_crtc_config *pipe_config);
 987
 988
 989 /* intel_lvds.c */
 990 void intel_lvds_init(struct drm_device *dev);
 991 bool intel_is_dual_link_lvds(struct drm_device *dev);
 992
 993
 994 /* intel_modes.c */
 995 int intel_connector_update_modes(struct drm_connector *connector,
 996                                  struct edid *edid);
 997 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 998 void intel_attach_force_audio_property(struct drm_connector *connector);
 999 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1000
1001
1002 /* intel_overlay.c */
1003 void intel_setup_overlay(struct drm_device *dev);
1004 void intel_cleanup_overlay(struct drm_device *dev);
1005 int intel_overlay_switch_off(struct intel_overlay *overlay);
1006 int intel_overlay_put_image(struct drm_device *dev, void *data,
1007                             struct drm_file *file_priv);
1008 int intel_overlay_attrs(struct drm_device *dev, void *data,
1009                         struct drm_file *file_priv);
1010
1011
1012 /* intel_panel.c */
1013 int intel_panel_init(struct intel_panel *panel,
1014                      struct drm_display_mode *fixed_mode,
1015                      struct drm_display_mode *downclock_mode);
1016 void intel_panel_fini(struct intel_panel *panel);
1017 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1018                             struct drm_display_mode *adjusted_mode);
1019 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1020                              struct intel_crtc_config *pipe_config,
1021                              int fitting_mode);
1022 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1023                               struct intel_crtc_config *pipe_config,
1024                               int fitting_mode);
1025 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1026                                     u32 level, u32 max);
1027 int intel_panel_setup_backlight(struct drm_connector *connector);
1028 void intel_panel_enable_backlight(struct intel_connector *connector);
1029 void intel_panel_disable_backlight(struct intel_connector *connector);
1030 void intel_panel_destroy_backlight(struct drm_connector *connector);
1031 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1032 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1033 extern struct drm_display_mode *intel_find_panel_downclock(
1034                                 struct drm_device *dev,
1035                                 struct drm_display_mode *fixed_mode,
1036                                 struct drm_connector *connector);
1037
1038 /* intel_pm.c */
1039 void intel_init_clock_gating(struct drm_device *dev);
1040 void intel_suspend_hw(struct drm_device *dev);
1041 int ilk_wm_max_level(const struct drm_device *dev);
1042 void intel_update_watermarks(struct drm_crtc *crtc);
1043 void intel_update_sprite_watermarks(struct drm_plane *plane,
1044                                     struct drm_crtc *crtc,
1045                                     uint32_t sprite_width,
1046                                     uint32_t sprite_height,
1047                                     int pixel_size,
1048                                     bool enabled, bool scaled);
1049 void intel_init_pm(struct drm_device *dev);
1050 void intel_pm_setup(struct drm_device *dev);
1051 bool intel_fbc_enabled(struct drm_device *dev);
1052 void intel_update_fbc(struct drm_device *dev);
1053 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1054 void intel_gpu_ips_teardown(void);
1055 int intel_power_domains_init(struct drm_i915_private *);
1056 void intel_power_domains_remove(struct drm_i915_private *);
1057 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
1058                                  enum intel_display_power_domain domain);
1059 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
1060                                           enum intel_display_power_domain domain);
1061 void intel_display_power_get(struct drm_i915_private *dev_priv,
1062                              enum intel_display_power_domain domain);
1063 void intel_display_power_put(struct drm_i915_private *dev_priv,
1064                              enum intel_display_power_domain domain);
1065 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1066 void intel_init_gt_powersave(struct drm_device *dev);
1067 void intel_cleanup_gt_powersave(struct drm_device *dev);
1068 void intel_enable_gt_powersave(struct drm_device *dev);
1069 void intel_disable_gt_powersave(struct drm_device *dev);
1070 void intel_suspend_gt_powersave(struct drm_device *dev);
1071 void intel_reset_gt_powersave(struct drm_device *dev);
1072 void ironlake_teardown_rc6(struct drm_device *dev);
1073 void gen6_update_ring_freq(struct drm_device *dev);
1074 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1075 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1076 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1077 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1078 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1079 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1080 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1081 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
1082 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
1083 void ilk_wm_get_hw_state(struct drm_device *dev);
1084
1085
1086 /* intel_sdvo.c */
1087 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1088
1089
1090 /* intel_sprite.c */
1091 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1092 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1093                                enum plane plane);
1094 void intel_plane_restore(struct drm_plane *plane);
1095 void intel_plane_disable(struct drm_plane *plane);
1096 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1097                               struct drm_file *file_priv);
1098 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1099                               struct drm_file *file_priv);
1100
1101
1102 /* intel_tv.c */
1103 void intel_tv_init(struct drm_device *dev);
1104
1105 #endif /* __INTEL_DRV_H__ */