drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         struct list_head fbdev_list;
 127         struct drm_display_mode *our_mode;
 128         int preferred_bpp;
 129 };
 130
 131 struct intel_encoder {
 132         struct drm_encoder base;
 133         /*
 134          * The new crtc this encoder will be driven from. Only differs from
 135          * base->crtc while a modeset is in progress.
 136          */
 137         struct intel_crtc *new_crtc;
 138
 139         enum intel_output_type type;
 140         unsigned int cloneable;
 141         bool connectors_active;
 142         void (*hot_plug)(struct intel_encoder *);
 143         bool (*compute_config)(struct intel_encoder *,
 144                                struct intel_crtc_state *);
 145         void (*pre_pll_enable)(struct intel_encoder *);
 146         void (*pre_enable)(struct intel_encoder *);
 147         void (*enable)(struct intel_encoder *);
 148         void (*mode_set)(struct intel_encoder *intel_encoder);
 149         void (*disable)(struct intel_encoder *);
 150         void (*post_disable)(struct intel_encoder *);
 151         /* Read out the current hw state of this connector, returning true if
 152          * the encoder is active. If the encoder is enabled it also set the pipe
 153          * it is connected to in the pipe parameter. */
 154         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 155         /* Reconstructs the equivalent mode flags for the current hardware
 156          * state. This must be called _after_ display->get_pipe_config has
 157          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 158          * be set correctly before calling this function. */
 159         void (*get_config)(struct intel_encoder *,
 160                            struct intel_crtc_state *pipe_config);
 161         /*
 162          * Called during system suspend after all pending requests for the
 163          * encoder are flushed (for example for DP AUX transactions) and
 164          * device interrupts are disabled.
 165          */
 166         void (*suspend)(struct intel_encoder *);
 167         int crtc_mask;
 168         enum hpd_pin hpd_pin;
 169 };
 170
 171 struct intel_panel {
 172         struct drm_display_mode *fixed_mode;
 173         struct drm_display_mode *downclock_mode;
 174         int fitting_mode;
 175
 176         /* backlight */
 177         struct {
 178                 bool present;
 179                 u32 level;
 180                 u32 min;
 181                 u32 max;
 182                 bool enabled;
 183                 bool combination_mode;  /* gen 2/4 only */
 184                 bool active_low_pwm;
 185                 struct backlight_device *device;
 186         } backlight;
 187
 188         void (*backlight_power)(struct intel_connector *, bool enable);
 189 };
 190
 191 struct intel_connector {
 192         struct drm_connector base;
 193         /*
 194          * The fixed encoder this connector is connected to.
 195          */
 196         struct intel_encoder *encoder;
 197
 198         /*
 199          * The new encoder this connector will be driven. Only differs from
 200          * encoder while a modeset is in progress.
 201          */
 202         struct intel_encoder *new_encoder;
 203
 204         /* Reads out the current hw, returning true if the connector is enabled
 205          * and active (i.e. dpms ON state). */
 206         bool (*get_hw_state)(struct intel_connector *);
 207
 208         /*
 209          * Removes all interfaces through which the connector is accessible
 210          * - like sysfs, debugfs entries -, so that no new operations can be
 211          * started on the connector. Also makes sure all currently pending
 212          * operations finish before returing.
 213          */
 214         void (*unregister)(struct intel_connector *);
 215
 216         /* Panel info for eDP and LVDS */
 217         struct intel_panel panel;
 218
 219         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 220         struct edid *edid;
 221         struct edid *detect_edid;
 222
 223         /* since POLL and HPD connectors may use the same HPD line keep the native
 224            state of connector->polled in case hotplug storm detection changes it */
 225         u8 polled;
 226
 227         void *port; /* store this opaque as its illegal to dereference it */
 228
 229         struct intel_dp *mst_port;
 230 };
 231
 232 typedef struct dpll {
 233         /* given values */
 234         int n;
 235         int m1, m2;
 236         int p1, p2;
 237         /* derived values */
 238         int     dot;
 239         int     vco;
 240         int     m;
 241         int     p;
 242 } intel_clock_t;
 243
 244 struct intel_plane_state {
 245         struct drm_plane_state base;
 246         struct drm_rect src;
 247         struct drm_rect dst;
 248         struct drm_rect clip;
 249         bool visible;
 250
 251         /*
 252          * scaler_id
 253          *    = -1 : not using a scaler
 254          *    >=  0 : using a scalers
 255          *
 256          * plane requiring a scaler:
 257          *   - During check_plane, its bit is set in
 258          *     crtc_state->scaler_state.scaler_users by calling helper function
 259          *     update_scaler_users.
 260          *   - scaler_id indicates the scaler it got assigned.
 261          *
 262          * plane doesn't require a scaler:
 263          *   - this can happen when scaling is no more required or plane simply
 264          *     got disabled.
 265          *   - During check_plane, corresponding bit is reset in
 266          *     crtc_state->scaler_state.scaler_users by calling helper function
 267          *     update_scaler_users.
 268          */
 269         int scaler_id;
 270 };
 271
 272 struct intel_initial_plane_config {
 273         struct intel_framebuffer *fb;
 274         unsigned int tiling;
 275         int size;
 276         u32 base;
 277 };
 278
 279 #define SKL_MIN_SRC_W 8
 280 #define SKL_MAX_SRC_W 4096
 281 #define SKL_MIN_SRC_H 8
 282 #define SKL_MAX_SRC_H 4096
 283 #define SKL_MIN_DST_W 8
 284 #define SKL_MAX_DST_W 4096
 285 #define SKL_MIN_DST_H 8
 286 #define SKL_MAX_DST_H 4096
 287
 288 struct intel_scaler {
 289         int id;
 290         int in_use;
 291         uint32_t mode;
 292 };
 293
 294 struct intel_crtc_scaler_state {
 295 #define SKL_NUM_SCALERS 2
 296         struct intel_scaler scalers[SKL_NUM_SCALERS];
 297
 298         /*
 299          * scaler_users: keeps track of users requesting scalers on this crtc.
 300          *
 301          *     If a bit is set, a user is using a scaler.
 302          *     Here user can be a plane or crtc as defined below:
 303          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 304          *       bit 31    - crtc
 305          *
 306          * Instead of creating a new index to cover planes and crtc, using
 307          * existing drm_plane_index for planes which is well less than 31
 308          * planes and bit 31 for crtc. This should be fine to cover all
 309          * our platforms.
 310          *
 311          * intel_atomic_setup_scalers will setup available scalers to users
 312          * requesting scalers. It will gracefully fail if request exceeds
 313          * avilability.
 314          */
 315 #define SKL_CRTC_INDEX 31
 316         unsigned scaler_users;
 317
 318         /* scaler used by crtc for panel fitting purpose */
 319         int scaler_id;
 320 };
 321
 322 struct intel_crtc_state {
 323         struct drm_crtc_state base;
 324
 325         /**
 326          * quirks - bitfield with hw state readout quirks
 327          *
 328          * For various reasons the hw state readout code might not be able to
 329          * completely faithfully read out the current state. These cases are
 330          * tracked with quirk flags so that fastboot and state checker can act
 331          * accordingly.
 332          */
 333 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 334 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 335         unsigned long quirks;
 336
 337         /* Pipe source size (ie. panel fitter input size)
 338          * All planes will be positioned inside this space,
 339          * and get clipped at the edges. */
 340         int pipe_src_w, pipe_src_h;
 341
 342         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 343          * between pch encoders and cpu encoders. */
 344         bool has_pch_encoder;
 345
 346         /* Are we sending infoframes on the attached port */
 347         bool has_infoframe;
 348
 349         /* CPU Transcoder for the pipe. Currently this can only differ from the
 350          * pipe on Haswell (where we have a special eDP transcoder). */
 351         enum transcoder cpu_transcoder;
 352
 353         /*
 354          * Use reduced/limited/broadcast rbg range, compressing from the full
 355          * range fed into the crtcs.
 356          */
 357         bool limited_color_range;
 358
 359         /* DP has a bunch of special case unfortunately, so mark the pipe
 360          * accordingly. */
 361         bool has_dp_encoder;
 362
 363         /* Whether we should send NULL infoframes. Required for audio. */
 364         bool has_hdmi_sink;
 365
 366         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 367          * has_dp_encoder is set. */
 368         bool has_audio;
 369
 370         /*
 371          * Enable dithering, used when the selected pipe bpp doesn't match the
 372          * plane bpp.
 373          */
 374         bool dither;
 375
 376         /* Controls for the clock computation, to override various stages. */
 377         bool clock_set;
 378
 379         /* SDVO TV has a bunch of special case. To make multifunction encoders
 380          * work correctly, we need to track this at runtime.*/
 381         bool sdvo_tv_clock;
 382
 383         /*
 384          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 385          * required. This is set in the 2nd loop of calling encoder's
 386          * ->compute_config if the first pick doesn't work out.
 387          */
 388         bool bw_constrained;
 389
 390         /* Settings for the intel dpll used on pretty much everything but
 391          * haswell. */
 392         struct dpll dpll;
 393
 394         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 395         enum intel_dpll_id shared_dpll;
 396
 397         /*
 398          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 399          * - enum skl_dpll on SKL
 400          */
 401         uint32_t ddi_pll_sel;
 402
 403         /* Actual register state of the dpll, for shared dpll cross-checking. */
 404         struct intel_dpll_hw_state dpll_hw_state;
 405
 406         int pipe_bpp;
 407         struct intel_link_m_n dp_m_n;
 408
 409         /* m2_n2 for eDP downclock */
 410         struct intel_link_m_n dp_m2_n2;
 411         bool has_drrs;
 412
 413         /*
 414          * Frequence the dpll for the port should run at. Differs from the
 415          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 416          * already multiplied by pixel_multiplier.
 417          */
 418         int port_clock;
 419
 420         /* Used by SDVO (and if we ever fix it, HDMI). */
 421         unsigned pixel_multiplier;
 422
 423         /* Panel fitter controls for gen2-gen4 + VLV */
 424         struct {
 425                 u32 control;
 426                 u32 pgm_ratios;
 427                 u32 lvds_border_bits;
 428         } gmch_pfit;
 429
 430         /* Panel fitter placement and size for Ironlake+ */
 431         struct {
 432                 u32 pos;
 433                 u32 size;
 434                 bool enabled;
 435                 bool force_thru;
 436         } pch_pfit;
 437
 438         /* FDI configuration, only valid if has_pch_encoder is set. */
 439         int fdi_lanes;
 440         struct intel_link_m_n fdi_m_n;
 441
 442         bool ips_enabled;
 443
 444         bool double_wide;
 445
 446         bool dp_encoder_is_mst;
 447         int pbn;
 448
 449         struct intel_crtc_scaler_state scaler_state;
 450 };
 451
 452 struct intel_pipe_wm {
 453         struct intel_wm_level wm[5];
 454         uint32_t linetime;
 455         bool fbc_wm_enabled;
 456         bool pipe_enabled;
 457         bool sprites_enabled;
 458         bool sprites_scaled;
 459 };
 460
 461 struct intel_mmio_flip {
 462         struct work_struct work;
 463         struct drm_i915_gem_request *req;
 464         struct intel_crtc *crtc;
 465 };
 466
 467 struct skl_pipe_wm {
 468         struct skl_wm_level wm[8];
 469         struct skl_wm_level trans_wm;
 470         uint32_t linetime;
 471 };
 472
 473 /*
 474  * Tracking of operations that need to be performed at the beginning/end of an
 475  * atomic commit, outside the atomic section where interrupts are disabled.
 476  * These are generally operations that grab mutexes or might otherwise sleep
 477  * and thus can't be run with interrupts disabled.
 478  */
 479 struct intel_crtc_atomic_commit {
 480         /* vblank evasion */
 481         bool evade;
 482         unsigned start_vbl_count;
 483
 484         /* Sleepable operations to perform before commit */
 485         bool wait_for_flips;
 486         bool disable_fbc;
 487         bool pre_disable_primary;
 488         bool update_wm;
 489         unsigned disabled_planes;
 490
 491         /* Sleepable operations to perform after commit */
 492         unsigned fb_bits;
 493         bool wait_vblank;
 494         bool update_fbc;
 495         bool post_enable_primary;
 496         unsigned update_sprite_watermarks;
 497 };
 498
 499 struct intel_crtc {
 500         struct drm_crtc base;
 501         enum pipe pipe;
 502         enum plane plane;
 503         u8 lut_r[256], lut_g[256], lut_b[256];
 504         /*
 505          * Whether the crtc and the connected output pipeline is active. Implies
 506          * that crtc->enabled is set, i.e. the current mode configuration has
 507          * some outputs connected to this crtc.
 508          */
 509         bool active;
 510         unsigned long enabled_power_domains;
 511         bool lowfreq_avail;
 512         struct intel_overlay *overlay;
 513         struct intel_unpin_work *unpin_work;
 514
 515         atomic_t unpin_work_count;
 516
 517         /* Display surface base address adjustement for pageflips. Note that on
 518          * gen4+ this only adjusts up to a tile, offsets within a tile are
 519          * handled in the hw itself (with the TILEOFF register). */
 520         unsigned long dspaddr_offset;
 521
 522         struct drm_i915_gem_object *cursor_bo;
 523         uint32_t cursor_addr;
 524         uint32_t cursor_cntl;
 525         uint32_t cursor_size;
 526         uint32_t cursor_base;
 527
 528         struct intel_initial_plane_config plane_config;
 529         struct intel_crtc_state *config;
 530         bool new_enabled;
 531
 532         /* reset counter value when the last flip was submitted */
 533         unsigned int reset_counter;
 534
 535         /* Access to these should be protected by dev_priv->irq_lock. */
 536         bool cpu_fifo_underrun_disabled;
 537         bool pch_fifo_underrun_disabled;
 538
 539         /* per-pipe watermark state */
 540         struct {
 541                 /* watermarks currently being used  */
 542                 struct intel_pipe_wm active;
 543                 /* SKL wm values currently in use */
 544                 struct skl_pipe_wm skl_active;
 545         } wm;
 546
 547         int scanline_offset;
 548
 549         struct intel_crtc_atomic_commit atomic;
 550
 551         /* scalers available on this crtc */
 552         int num_scalers;
 553 };
 554
 555 struct intel_plane_wm_parameters {
 556         uint32_t horiz_pixels;
 557         uint32_t vert_pixels;
 558         /*
 559          *   For packed pixel formats:
 560          *     bytes_per_pixel - holds bytes per pixel
 561          *   For planar pixel formats:
 562          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 563          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 564          */
 565         uint8_t bytes_per_pixel;
 566         uint8_t y_bytes_per_pixel;
 567         bool enabled;
 568         bool scaled;
 569         u64 tiling;
 570         unsigned int rotation;
 571 };
 572
 573 struct intel_plane {
 574         struct drm_plane base;
 575         int plane;
 576         enum pipe pipe;
 577         bool can_scale;
 578         int max_downscale;
 579
 580         /* FIXME convert to properties */
 581         struct drm_intel_sprite_colorkey ckey;
 582
 583         /* Since we need to change the watermarks before/after
 584          * enabling/disabling the planes, we need to store the parameters here
 585          * as the other pieces of the struct may not reflect the values we want
 586          * for the watermark calculations. Currently only Haswell uses this.
 587          */
 588         struct intel_plane_wm_parameters wm;
 589
 590         /*
 591          * NOTE: Do not place new plane state fields here (e.g., when adding
 592          * new plane properties).  New runtime state should now be placed in
 593          * the intel_plane_state structure and accessed via drm_plane->state.
 594          */
 595
 596         void (*update_plane)(struct drm_plane *plane,
 597                              struct drm_crtc *crtc,
 598                              struct drm_framebuffer *fb,
 599                              int crtc_x, int crtc_y,
 600                              unsigned int crtc_w, unsigned int crtc_h,
 601                              uint32_t x, uint32_t y,
 602                              uint32_t src_w, uint32_t src_h);
 603         void (*disable_plane)(struct drm_plane *plane,
 604                               struct drm_crtc *crtc, bool force);
 605         int (*check_plane)(struct drm_plane *plane,
 606                            struct intel_plane_state *state);
 607         void (*commit_plane)(struct drm_plane *plane,
 608                              struct intel_plane_state *state);
 609 };
 610
 611 struct intel_watermark_params {
 612         unsigned long fifo_size;
 613         unsigned long max_wm;
 614         unsigned long default_wm;
 615         unsigned long guard_size;
 616         unsigned long cacheline_size;
 617 };
 618
 619 struct cxsr_latency {
 620         int is_desktop;
 621         int is_ddr3;
 622         unsigned long fsb_freq;
 623         unsigned long mem_freq;
 624         unsigned long display_sr;
 625         unsigned long display_hpll_disable;
 626         unsigned long cursor_sr;
 627         unsigned long cursor_hpll_disable;
 628 };
 629
 630 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 631 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 632 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 633 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 634 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 635 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 636 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 637 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 638
 639 struct intel_hdmi {
 640         u32 hdmi_reg;
 641         int ddc_bus;
 642         uint32_t color_range;
 643         bool color_range_auto;
 644         bool has_hdmi_sink;
 645         bool has_audio;
 646         enum hdmi_force_audio force_audio;
 647         bool rgb_quant_range_selectable;
 648         enum hdmi_picture_aspect aspect_ratio;
 649         void (*write_infoframe)(struct drm_encoder *encoder,
 650                                 enum hdmi_infoframe_type type,
 651                                 const void *frame, ssize_t len);
 652         void (*set_infoframes)(struct drm_encoder *encoder,
 653                                bool enable,
 654                                struct drm_display_mode *adjusted_mode);
 655         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 656 };
 657
 658 struct intel_dp_mst_encoder;
 659 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 660
 661 /*
 662  * enum link_m_n_set:
 663  *      When platform provides two set of M_N registers for dp, we can
 664  *      program them and switch between them incase of DRRS.
 665  *      But When only one such register is provided, we have to program the
 666  *      required divider value on that registers itself based on the DRRS state.
 667  *
 668  * M1_N1        : Program dp_m_n on M1_N1 registers
 669  *                        dp_m2_n2 on M2_N2 registers (If supported)
 670  *
 671  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 672  *                        M2_N2 registers are not supported
 673  */
 674
 675 enum link_m_n_set {
 676         /* Sets the m1_n1 and m2_n2 */
 677         M1_N1 = 0,
 678         M2_N2
 679 };
 680
 681 struct intel_dp {
 682         uint32_t output_reg;
 683         uint32_t aux_ch_ctl_reg;
 684         uint32_t DP;
 685         bool has_audio;
 686         enum hdmi_force_audio force_audio;
 687         uint32_t color_range;
 688         bool color_range_auto;
 689         uint8_t link_bw;
 690         uint8_t rate_select;
 691         uint8_t lane_count;
 692         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 693         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 694         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 695         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 696         uint8_t num_sink_rates;
 697         int sink_rates[DP_MAX_SUPPORTED_RATES];
 698         struct drm_dp_aux aux;
 699         uint8_t train_set[4];
 700         int panel_power_up_delay;
 701         int panel_power_down_delay;
 702         int panel_power_cycle_delay;
 703         int backlight_on_delay;
 704         int backlight_off_delay;
 705         struct delayed_work panel_vdd_work;
 706         bool want_panel_vdd;
 707         unsigned long last_power_cycle;
 708         unsigned long last_power_on;
 709         unsigned long last_backlight_off;
 710
 711         struct notifier_block edp_notifier;
 712
 713         /*
 714          * Pipe whose power sequencer is currently locked into
 715          * this port. Only relevant on VLV/CHV.
 716          */
 717         enum pipe pps_pipe;
 718         struct edp_power_seq pps_delays;
 719
 720         bool use_tps3;
 721         bool can_mst; /* this port supports mst */
 722         bool is_mst;
 723         int active_mst_links;
 724         /* connector directly attached - won't be use for modeset in mst world */
 725         struct intel_connector *attached_connector;
 726
 727         /* mst connector list */
 728         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 729         struct drm_dp_mst_topology_mgr mst_mgr;
 730
 731         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 732         /*
 733          * This function returns the value we have to program the AUX_CTL
 734          * register with to kick off an AUX transaction.
 735          */
 736         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 737                                      bool has_aux_irq,
 738                                      int send_bytes,
 739                                      uint32_t aux_clock_divider);
 740         bool train_set_valid;
 741
 742         /* Displayport compliance testing */
 743         unsigned long compliance_test_type;
 744         unsigned long compliance_test_data;
 745         bool compliance_test_active;
 746 };
 747
 748 struct intel_digital_port {
 749         struct intel_encoder base;
 750         enum port port;
 751         u32 saved_port_bits;
 752         struct intel_dp dp;
 753         struct intel_hdmi hdmi;
 754         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 755 };
 756
 757 struct intel_dp_mst_encoder {
 758         struct intel_encoder base;
 759         enum pipe pipe;
 760         struct intel_digital_port *primary;
 761         void *port; /* store this opaque as its illegal to dereference it */
 762 };
 763
 764 static inline int
 765 vlv_dport_to_channel(struct intel_digital_port *dport)
 766 {
 767         switch (dport->port) {
 768         case PORT_B:
 769         case PORT_D:
 770                 return DPIO_CH0;
 771         case PORT_C:
 772                 return DPIO_CH1;
 773         default:
 774                 BUG();
 775         }
 776 }
 777
 778 static inline int
 779 vlv_pipe_to_channel(enum pipe pipe)
 780 {
 781         switch (pipe) {
 782         case PIPE_A:
 783         case PIPE_C:
 784                 return DPIO_CH0;
 785         case PIPE_B:
 786                 return DPIO_CH1;
 787         default:
 788                 BUG();
 789         }
 790 }
 791
 792 static inline struct drm_crtc *
 793 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 794 {
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796         return dev_priv->pipe_to_crtc_mapping[pipe];
 797 }
 798
 799 static inline struct drm_crtc *
 800 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 801 {
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         return dev_priv->plane_to_crtc_mapping[plane];
 804 }
 805
 806 struct intel_unpin_work {
 807         struct work_struct work;
 808         struct drm_crtc *crtc;
 809         struct drm_framebuffer *old_fb;
 810         struct drm_i915_gem_object *pending_flip_obj;
 811         struct drm_pending_vblank_event *event;
 812         atomic_t pending;
 813 #define INTEL_FLIP_INACTIVE     0
 814 #define INTEL_FLIP_PENDING      1
 815 #define INTEL_FLIP_COMPLETE     2
 816         u32 flip_count;
 817         u32 gtt_offset;
 818         struct drm_i915_gem_request *flip_queued_req;
 819         int flip_queued_vblank;
 820         int flip_ready_vblank;
 821         bool enable_stall_check;
 822 };
 823
 824 struct intel_load_detect_pipe {
 825         struct drm_framebuffer *release_fb;
 826         bool load_detect_temp;
 827         int dpms_mode;
 828 };
 829
 830 static inline struct intel_encoder *
 831 intel_attached_encoder(struct drm_connector *connector)
 832 {
 833         return to_intel_connector(connector)->encoder;
 834 }
 835
 836 static inline struct intel_digital_port *
 837 enc_to_dig_port(struct drm_encoder *encoder)
 838 {
 839         return container_of(encoder, struct intel_digital_port, base.base);
 840 }
 841
 842 static inline struct intel_dp_mst_encoder *
 843 enc_to_mst(struct drm_encoder *encoder)
 844 {
 845         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 846 }
 847
 848 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 849 {
 850         return &enc_to_dig_port(encoder)->dp;
 851 }
 852
 853 static inline struct intel_digital_port *
 854 dp_to_dig_port(struct intel_dp *intel_dp)
 855 {
 856         return container_of(intel_dp, struct intel_digital_port, dp);
 857 }
 858
 859 static inline struct intel_digital_port *
 860 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 861 {
 862         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 863 }
 864
 865 /*
 866  * Returns the number of planes for this pipe, ie the number of sprites + 1
 867  * (primary plane). This doesn't count the cursor plane then.
 868  */
 869 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 870 {
 871         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 872 }
 873
 874 /* intel_fifo_underrun.c */
 875 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 876                                            enum pipe pipe, bool enable);
 877 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 878                                            enum transcoder pch_transcoder,
 879                                            bool enable);
 880 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 881                                          enum pipe pipe);
 882 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 883                                          enum transcoder pch_transcoder);
 884 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 885
 886 /* i915_irq.c */
 887 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 888 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 889 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 890 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 891 void gen6_reset_rps_interrupts(struct drm_device *dev);
 892 void gen6_enable_rps_interrupts(struct drm_device *dev);
 893 void gen6_disable_rps_interrupts(struct drm_device *dev);
 894 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 895 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 896 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 897 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 898 {
 899         /*
 900          * We only use drm_irq_uninstall() at unload and VT switch, so
 901          * this is the only thing we need to check.
 902          */
 903         return dev_priv->pm.irqs_enabled;
 904 }
 905
 906 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 907 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 908                                      unsigned int pipe_mask);
 909
 910 /* intel_crt.c */
 911 void intel_crt_init(struct drm_device *dev);
 912
 913
 914 /* intel_ddi.c */
 915 void intel_prepare_ddi(struct drm_device *dev);
 916 void hsw_fdi_link_train(struct drm_crtc *crtc);
 917 void intel_ddi_init(struct drm_device *dev, enum port port);
 918 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 919 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 920 void intel_ddi_pll_init(struct drm_device *dev);
 921 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 922 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 923                                        enum transcoder cpu_transcoder);
 924 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 925 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 926 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 927                           struct intel_crtc_state *crtc_state);
 928 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 929 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 930 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 931 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 932 void intel_ddi_get_config(struct intel_encoder *encoder,
 933                           struct intel_crtc_state *pipe_config);
 934 struct intel_encoder *
 935 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
 936
 937 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 938 void intel_ddi_clock_get(struct intel_encoder *encoder,
 939                          struct intel_crtc_state *pipe_config);
 940 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 941 void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
 942                                 enum port port, int type);
 943
 944 /* intel_frontbuffer.c */
 945 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 946                              struct intel_engine_cs *ring,
 947                              enum fb_op_origin origin);
 948 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 949                                     unsigned frontbuffer_bits);
 950 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 951                                      unsigned frontbuffer_bits);
 952 void intel_frontbuffer_flush(struct drm_device *dev,
 953                              unsigned frontbuffer_bits);
 954 /**
 955  * intel_frontbuffer_flip - synchronous frontbuffer flip
 956  * @dev: DRM device
 957  * @frontbuffer_bits: frontbuffer plane tracking bits
 958  *
 959  * This function gets called after scheduling a flip on @obj. This is for
 960  * synchronous plane updates which will happen on the next vblank and which will
 961  * not get delayed by pending gpu rendering.
 962  *
 963  * Can be called without any locks held.
 964  */
 965 static inline
 966 void intel_frontbuffer_flip(struct drm_device *dev,
 967                             unsigned frontbuffer_bits)
 968 {
 969         intel_frontbuffer_flush(dev, frontbuffer_bits);
 970 }
 971
 972 unsigned int intel_fb_align_height(struct drm_device *dev,
 973                                    unsigned int height,
 974                                    uint32_t pixel_format,
 975                                    uint64_t fb_format_modifier);
 976 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 977
 978 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
 979                               uint32_t pixel_format);
 980
 981 /* intel_audio.c */
 982 void intel_init_audio(struct drm_device *dev);
 983 void intel_audio_codec_enable(struct intel_encoder *encoder);
 984 void intel_audio_codec_disable(struct intel_encoder *encoder);
 985 void i915_audio_component_init(struct drm_i915_private *dev_priv);
 986 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
 987
 988 /* intel_display.c */
 989 extern const struct drm_plane_funcs intel_plane_funcs;
 990 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 991 int intel_pch_rawclk(struct drm_device *dev);
 992 void intel_mark_busy(struct drm_device *dev);
 993 void intel_mark_idle(struct drm_device *dev);
 994 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 995 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
 996 void intel_crtc_reset(struct intel_crtc *crtc);
 997 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 998 void intel_encoder_destroy(struct drm_encoder *encoder);
 999 int intel_connector_init(struct intel_connector *);
1000 struct intel_connector *intel_connector_alloc(void);
1001 void intel_connector_dpms(struct drm_connector *, int mode);
1002 bool intel_connector_get_hw_state(struct intel_connector *connector);
1003 void intel_modeset_check_state(struct drm_device *dev);
1004 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1005                                 struct intel_digital_port *port);
1006 void intel_connector_attach_encoder(struct intel_connector *connector,
1007                                     struct intel_encoder *encoder);
1008 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1009 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1010                                              struct drm_crtc *crtc);
1011 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1012 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1013                                 struct drm_file *file_priv);
1014 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1015                                              enum pipe pipe);
1016 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1017 static inline void
1018 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1019 {
1020         drm_wait_one_vblank(dev, pipe);
1021 }
1022 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1023 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1024                          struct intel_digital_port *dport,
1025                          unsigned int expected_mask);
1026 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1027                                 struct drm_display_mode *mode,
1028                                 struct intel_load_detect_pipe *old,
1029                                 struct drm_modeset_acquire_ctx *ctx);
1030 void intel_release_load_detect_pipe(struct drm_connector *connector,
1031                                     struct intel_load_detect_pipe *old,
1032                                     struct drm_modeset_acquire_ctx *ctx);
1033 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1034                                struct drm_framebuffer *fb,
1035                                const struct drm_plane_state *plane_state,
1036                                struct intel_engine_cs *pipelined);
1037 struct drm_framebuffer *
1038 __intel_framebuffer_create(struct drm_device *dev,
1039                            struct drm_mode_fb_cmd2 *mode_cmd,
1040                            struct drm_i915_gem_object *obj);
1041 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1042 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1043 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1044 void intel_check_page_flip(struct drm_device *dev, int pipe);
1045 int intel_prepare_plane_fb(struct drm_plane *plane,
1046                            struct drm_framebuffer *fb,
1047                            const struct drm_plane_state *new_state);
1048 void intel_cleanup_plane_fb(struct drm_plane *plane,
1049                             struct drm_framebuffer *fb,
1050                             const struct drm_plane_state *old_state);
1051 int intel_plane_atomic_get_property(struct drm_plane *plane,
1052                                     const struct drm_plane_state *state,
1053                                     struct drm_property *property,
1054                                     uint64_t *val);
1055 int intel_plane_atomic_set_property(struct drm_plane *plane,
1056                                     struct drm_plane_state *state,
1057                                     struct drm_property *property,
1058                                     uint64_t val);
1059
1060 unsigned int
1061 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1062                   uint64_t fb_format_modifier);
1063
1064 static inline bool
1065 intel_rotation_90_or_270(unsigned int rotation)
1066 {
1067         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1068 }
1069
1070 void intel_create_rotation_property(struct drm_device *dev,
1071                                         struct intel_plane *plane);
1072
1073 bool intel_wm_need_update(struct drm_plane *plane,
1074                           struct drm_plane_state *state);
1075
1076 /* shared dpll functions */
1077 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1078 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1079                         struct intel_shared_dpll *pll,
1080                         bool state);
1081 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1082 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1083 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1084                                                 struct intel_crtc_state *state);
1085 void intel_put_shared_dpll(struct intel_crtc *crtc);
1086
1087 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1088                       const struct dpll *dpll);
1089 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1090
1091 /* modesetting asserts */
1092 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1093                            enum pipe pipe);
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state);
1096 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1097 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1098 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1099                        enum pipe pipe, bool state);
1100 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1101 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1102 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1103 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1104 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1105 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1106                                              unsigned int tiling_mode,
1107                                              unsigned int bpp,
1108                                              unsigned int pitch);
1109 void intel_prepare_reset(struct drm_device *dev);
1110 void intel_finish_reset(struct drm_device *dev);
1111 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1112 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1113 void broxton_init_cdclk(struct drm_device *dev);
1114 void broxton_uninit_cdclk(struct drm_device *dev);
1115 void broxton_set_cdclk(struct drm_device *dev, int frequency);
1116 void broxton_ddi_phy_init(struct drm_device *dev);
1117 void broxton_ddi_phy_uninit(struct drm_device *dev);
1118 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1119 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1120 void intel_dp_get_m_n(struct intel_crtc *crtc,
1121                       struct intel_crtc_state *pipe_config);
1122 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1123 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1124 void
1125 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1126                                 int dotclock);
1127 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1128                         intel_clock_t *best_clock);
1129 bool intel_crtc_active(struct drm_crtc *crtc);
1130 void hsw_enable_ips(struct intel_crtc *crtc);
1131 void hsw_disable_ips(struct intel_crtc *crtc);
1132 enum intel_display_power_domain
1133 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1134 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1135                                  struct intel_crtc_state *pipe_config);
1136 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1137 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1138 void skl_detach_scalers(struct intel_crtc *intel_crtc);
1139 int skl_update_scaler_users(struct intel_crtc *intel_crtc,
1140         struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane,
1141         struct intel_plane_state *plane_state, int force_detach);
1142 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1143
1144 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1145                                      struct drm_i915_gem_object *obj);
1146 u32 skl_plane_ctl_format(uint32_t pixel_format);
1147 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1148 u32 skl_plane_ctl_rotation(unsigned int rotation);
1149
1150 /* intel_csr.c */
1151 void intel_csr_ucode_init(struct drm_device *dev);
1152 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1153 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1154                                         enum csr_state state);
1155 void intel_csr_load_program(struct drm_device *dev);
1156 void intel_csr_ucode_fini(struct drm_device *dev);
1157 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1158
1159 /* intel_dp.c */
1160 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1161 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1162                              struct intel_connector *intel_connector);
1163 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1164 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1165 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1166 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1167 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1168 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1169 bool intel_dp_compute_config(struct intel_encoder *encoder,
1170                              struct intel_crtc_state *pipe_config);
1171 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1172 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1173                                   bool long_hpd);
1174 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1175 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1176 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1177 void intel_edp_panel_on(struct intel_dp *intel_dp);
1178 void intel_edp_panel_off(struct intel_dp *intel_dp);
1179 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1180 void intel_dp_mst_suspend(struct drm_device *dev);
1181 void intel_dp_mst_resume(struct drm_device *dev);
1182 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1183 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1184 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1185 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1186 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1187 void intel_plane_destroy(struct drm_plane *plane);
1188 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1189 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1190 void intel_edp_drrs_invalidate(struct drm_device *dev,
1191                 unsigned frontbuffer_bits);
1192 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1193
1194 /* intel_dp_mst.c */
1195 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1196 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1197 /* intel_dsi.c */
1198 void intel_dsi_init(struct drm_device *dev);
1199
1200
1201 /* intel_dvo.c */
1202 void intel_dvo_init(struct drm_device *dev);
1203
1204
1205 /* legacy fbdev emulation in intel_fbdev.c */
1206 #ifdef CONFIG_DRM_I915_FBDEV
1207 extern int intel_fbdev_init(struct drm_device *dev);
1208 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1209 extern void intel_fbdev_fini(struct drm_device *dev);
1210 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1211 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1212 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1213 #else
1214 static inline int intel_fbdev_init(struct drm_device *dev)
1215 {
1216         return 0;
1217 }
1218
1219 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1220 {
1221 }
1222
1223 static inline void intel_fbdev_fini(struct drm_device *dev)
1224 {
1225 }
1226
1227 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1228 {
1229 }
1230
1231 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1232 {
1233 }
1234 #endif
1235
1236 /* intel_fbc.c */
1237 bool intel_fbc_enabled(struct drm_device *dev);
1238 void intel_fbc_update(struct drm_device *dev);
1239 void intel_fbc_init(struct drm_i915_private *dev_priv);
1240 void intel_fbc_disable(struct drm_device *dev);
1241 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1242                           unsigned int frontbuffer_bits,
1243                           enum fb_op_origin origin);
1244 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1245                      unsigned int frontbuffer_bits);
1246
1247 /* intel_hdmi.c */
1248 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1249 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1250                                struct intel_connector *intel_connector);
1251 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1252 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1253                                struct intel_crtc_state *pipe_config);
1254
1255
1256 /* intel_lvds.c */
1257 void intel_lvds_init(struct drm_device *dev);
1258 bool intel_is_dual_link_lvds(struct drm_device *dev);
1259
1260
1261 /* intel_modes.c */
1262 int intel_connector_update_modes(struct drm_connector *connector,
1263                                  struct edid *edid);
1264 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1265 void intel_attach_force_audio_property(struct drm_connector *connector);
1266 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1267
1268
1269 /* intel_overlay.c */
1270 void intel_setup_overlay(struct drm_device *dev);
1271 void intel_cleanup_overlay(struct drm_device *dev);
1272 int intel_overlay_switch_off(struct intel_overlay *overlay);
1273 int intel_overlay_put_image(struct drm_device *dev, void *data,
1274                             struct drm_file *file_priv);
1275 int intel_overlay_attrs(struct drm_device *dev, void *data,
1276                         struct drm_file *file_priv);
1277 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1278
1279
1280 /* intel_panel.c */
1281 int intel_panel_init(struct intel_panel *panel,
1282                      struct drm_display_mode *fixed_mode,
1283                      struct drm_display_mode *downclock_mode);
1284 void intel_panel_fini(struct intel_panel *panel);
1285 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1286                             struct drm_display_mode *adjusted_mode);
1287 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1288                              struct intel_crtc_state *pipe_config,
1289                              int fitting_mode);
1290 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1291                               struct intel_crtc_state *pipe_config,
1292                               int fitting_mode);
1293 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1294                                     u32 level, u32 max);
1295 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1296 void intel_panel_enable_backlight(struct intel_connector *connector);
1297 void intel_panel_disable_backlight(struct intel_connector *connector);
1298 void intel_panel_destroy_backlight(struct drm_connector *connector);
1299 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1300 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1301 extern struct drm_display_mode *intel_find_panel_downclock(
1302                                 struct drm_device *dev,
1303                                 struct drm_display_mode *fixed_mode,
1304                                 struct drm_connector *connector);
1305 void intel_backlight_register(struct drm_device *dev);
1306 void intel_backlight_unregister(struct drm_device *dev);
1307
1308
1309 /* intel_psr.c */
1310 void intel_psr_enable(struct intel_dp *intel_dp);
1311 void intel_psr_disable(struct intel_dp *intel_dp);
1312 void intel_psr_invalidate(struct drm_device *dev,
1313                               unsigned frontbuffer_bits);
1314 void intel_psr_flush(struct drm_device *dev,
1315                          unsigned frontbuffer_bits);
1316 void intel_psr_init(struct drm_device *dev);
1317 void intel_psr_single_frame_update(struct drm_device *dev);
1318
1319 /* intel_runtime_pm.c */
1320 int intel_power_domains_init(struct drm_i915_private *);
1321 void intel_power_domains_fini(struct drm_i915_private *);
1322 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1323 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1324
1325 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1326                                     enum intel_display_power_domain domain);
1327 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1328                                       enum intel_display_power_domain domain);
1329 void intel_display_power_get(struct drm_i915_private *dev_priv,
1330                              enum intel_display_power_domain domain);
1331 void intel_display_power_put(struct drm_i915_private *dev_priv,
1332                              enum intel_display_power_domain domain);
1333 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1334 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1335 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1336 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1337 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1338
1339 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1340
1341 /* intel_pm.c */
1342 void intel_init_clock_gating(struct drm_device *dev);
1343 void intel_suspend_hw(struct drm_device *dev);
1344 int ilk_wm_max_level(const struct drm_device *dev);
1345 void intel_update_watermarks(struct drm_crtc *crtc);
1346 void intel_update_sprite_watermarks(struct drm_plane *plane,
1347                                     struct drm_crtc *crtc,
1348                                     uint32_t sprite_width,
1349                                     uint32_t sprite_height,
1350                                     int pixel_size,
1351                                     bool enabled, bool scaled);
1352 void intel_init_pm(struct drm_device *dev);
1353 void intel_pm_setup(struct drm_device *dev);
1354 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1355 void intel_gpu_ips_teardown(void);
1356 void intel_init_gt_powersave(struct drm_device *dev);
1357 void intel_cleanup_gt_powersave(struct drm_device *dev);
1358 void intel_enable_gt_powersave(struct drm_device *dev);
1359 void intel_disable_gt_powersave(struct drm_device *dev);
1360 void intel_suspend_gt_powersave(struct drm_device *dev);
1361 void intel_reset_gt_powersave(struct drm_device *dev);
1362 void gen6_update_ring_freq(struct drm_device *dev);
1363 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1364 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1365 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1366 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1367                     struct drm_i915_file_private *file_priv);
1368 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1369                                        struct drm_i915_gem_request *req);
1370 void ilk_wm_get_hw_state(struct drm_device *dev);
1371 void skl_wm_get_hw_state(struct drm_device *dev);
1372 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1373                           struct skl_ddb_allocation *ddb /* out */);
1374
1375
1376 /* intel_sdvo.c */
1377 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1378
1379
1380 /* intel_sprite.c */
1381 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1382 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1383                                enum plane plane);
1384 int intel_plane_restore(struct drm_plane *plane);
1385 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1386                               struct drm_file *file_priv);
1387 bool intel_pipe_update_start(struct intel_crtc *crtc,
1388                              uint32_t *start_vbl_count);
1389 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1390
1391 /* intel_tv.c */
1392 void intel_tv_init(struct drm_device *dev);
1393
1394 /* intel_atomic.c */
1395 int intel_atomic_check(struct drm_device *dev,
1396                        struct drm_atomic_state *state);
1397 int intel_atomic_commit(struct drm_device *dev,
1398                         struct drm_atomic_state *state,
1399                         bool async);
1400 int intel_connector_atomic_get_property(struct drm_connector *connector,
1401                                         const struct drm_connector_state *state,
1402                                         struct drm_property *property,
1403                                         uint64_t *val);
1404 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1405 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1406                                struct drm_crtc_state *state);
1407 static inline struct intel_crtc_state *
1408 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1409                             struct intel_crtc *crtc)
1410 {
1411         struct drm_crtc_state *crtc_state;
1412         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1413         if (IS_ERR(crtc_state))
1414                 return ERR_CAST(crtc_state);
1415
1416         return to_intel_crtc_state(crtc_state);
1417 }
1418 int intel_atomic_setup_scalers(struct drm_device *dev,
1419         struct intel_crtc *intel_crtc,
1420         struct intel_crtc_state *crtc_state);
1421
1422 /* intel_atomic_plane.c */
1423 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1424 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1425 void intel_plane_destroy_state(struct drm_plane *plane,
1426                                struct drm_plane_state *state);
1427 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1428
1429 #endif /* __INTEL_DRV_H__ */