2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Jani Nikula <jani.nikula@intel.com>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_mipi_dsi.h>
33 #include <linux/slab.h>
35 #include "intel_drv.h"
36 #include "intel_dsi.h"
40 struct drm_panel
* (*init
)(struct intel_dsi
*intel_dsi
, u16 panel_id
);
41 } intel_dsi_drivers
[] = {
43 .panel_id
= MIPI_DSI_GENERIC_PANEL_ID
,
44 .init
= vbt_panel_init
,
48 static void wait_for_dsi_fifo_empty(struct intel_dsi
*intel_dsi
, enum port port
)
50 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
51 struct drm_device
*dev
= encoder
->dev
;
52 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
55 mask
= LP_CTRL_FIFO_EMPTY
| HS_CTRL_FIFO_EMPTY
|
56 LP_DATA_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
;
58 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & mask
) == mask
, 100))
59 DRM_ERROR("DPI FIFOs are not empty\n");
62 static void write_data(struct drm_i915_private
*dev_priv
, u32 reg
,
63 const u8
*data
, u32 len
)
67 for (i
= 0; i
< len
; i
+= 4) {
70 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
71 val
|= *data
++ << 8 * j
;
77 static void read_data(struct drm_i915_private
*dev_priv
, u32 reg
,
82 for (i
= 0; i
< len
; i
+= 4) {
83 u32 val
= I915_READ(reg
);
85 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
86 *data
++ = val
>> 8 * j
;
90 static ssize_t
intel_dsi_host_transfer(struct mipi_dsi_host
*host
,
91 const struct mipi_dsi_msg
*msg
)
93 struct intel_dsi_host
*intel_dsi_host
= to_intel_dsi_host(host
);
94 struct drm_device
*dev
= intel_dsi_host
->intel_dsi
->base
.base
.dev
;
95 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
96 enum port port
= intel_dsi_host
->port
;
97 struct mipi_dsi_packet packet
;
99 const u8
*header
, *data
;
100 u32 data_reg
, data_mask
, ctrl_reg
, ctrl_mask
;
102 ret
= mipi_dsi_create_packet(&packet
, msg
);
106 header
= packet
.header
;
107 data
= packet
.payload
;
109 if (msg
->flags
& MIPI_DSI_MSG_USE_LPM
) {
110 data_reg
= MIPI_LP_GEN_DATA(port
);
111 data_mask
= LP_DATA_FIFO_FULL
;
112 ctrl_reg
= MIPI_LP_GEN_CTRL(port
);
113 ctrl_mask
= LP_CTRL_FIFO_FULL
;
115 data_reg
= MIPI_HS_GEN_DATA(port
);
116 data_mask
= HS_DATA_FIFO_FULL
;
117 ctrl_reg
= MIPI_HS_GEN_CTRL(port
);
118 ctrl_mask
= HS_CTRL_FIFO_FULL
;
121 /* note: this is never true for reads */
122 if (packet
.payload_length
) {
124 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & data_mask
) == 0, 50))
125 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
127 write_data(dev_priv
, data_reg
, packet
.payload
,
128 packet
.payload_length
);
132 I915_WRITE(MIPI_INTR_STAT(port
), GEN_READ_DATA_AVAIL
);
135 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & ctrl_mask
) == 0, 50)) {
136 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
139 I915_WRITE(ctrl_reg
, header
[2] << 16 | header
[1] << 8 | header
[0]);
141 /* ->rx_len is set only for reads */
143 data_mask
= GEN_READ_DATA_AVAIL
;
144 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & data_mask
) == data_mask
, 50))
145 DRM_ERROR("Timeout waiting for read data.\n");
147 read_data(dev_priv
, data_reg
, msg
->rx_buf
, msg
->rx_len
);
150 /* XXX: fix for reads and writes */
151 return 4 + packet
.payload_length
;
154 static int intel_dsi_host_attach(struct mipi_dsi_host
*host
,
155 struct mipi_dsi_device
*dsi
)
160 static int intel_dsi_host_detach(struct mipi_dsi_host
*host
,
161 struct mipi_dsi_device
*dsi
)
166 static const struct mipi_dsi_host_ops intel_dsi_host_ops
= {
167 .attach
= intel_dsi_host_attach
,
168 .detach
= intel_dsi_host_detach
,
169 .transfer
= intel_dsi_host_transfer
,
172 static struct intel_dsi_host
*intel_dsi_host_init(struct intel_dsi
*intel_dsi
,
175 struct intel_dsi_host
*host
;
176 struct mipi_dsi_device
*device
;
178 host
= kzalloc(sizeof(*host
), GFP_KERNEL
);
182 host
->base
.ops
= &intel_dsi_host_ops
;
183 host
->intel_dsi
= intel_dsi
;
187 * We should call mipi_dsi_host_register(&host->base) here, but we don't
188 * have a host->dev, and we don't have OF stuff either. So just use the
189 * dsi framework as a library and hope for the best. Create the dsi
190 * devices by ourselves here too. Need to be careful though, because we
191 * don't initialize any of the driver model devices here.
193 device
= kzalloc(sizeof(*device
), GFP_KERNEL
);
199 device
->host
= &host
->base
;
200 host
->device
= device
;
206 * send a video mode command
208 * XXX: commands with data in MIPI_DPI_DATA?
210 static int dpi_send_cmd(struct intel_dsi
*intel_dsi
, u32 cmd
, bool hs
,
213 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
214 struct drm_device
*dev
= encoder
->dev
;
215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
225 I915_WRITE(MIPI_INTR_STAT(port
), SPL_PKT_SENT_INTERRUPT
);
227 /* XXX: old code skips write if control unchanged */
228 if (cmd
== I915_READ(MIPI_DPI_CONTROL(port
)))
229 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd
);
231 I915_WRITE(MIPI_DPI_CONTROL(port
), cmd
);
233 mask
= SPL_PKT_SENT_INTERRUPT
;
234 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & mask
) == mask
, 100))
235 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd
);
240 static void band_gap_reset(struct drm_i915_private
*dev_priv
)
242 mutex_lock(&dev_priv
->dpio_lock
);
244 vlv_flisdsi_write(dev_priv
, 0x08, 0x0001);
245 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0005);
246 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0025);
248 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0000);
249 vlv_flisdsi_write(dev_priv
, 0x08, 0x0000);
251 mutex_unlock(&dev_priv
->dpio_lock
);
254 static inline bool is_vid_mode(struct intel_dsi
*intel_dsi
)
256 return intel_dsi
->operation_mode
== INTEL_DSI_VIDEO_MODE
;
259 static inline bool is_cmd_mode(struct intel_dsi
*intel_dsi
)
261 return intel_dsi
->operation_mode
== INTEL_DSI_COMMAND_MODE
;
264 static void intel_dsi_hot_plug(struct intel_encoder
*encoder
)
269 static bool intel_dsi_compute_config(struct intel_encoder
*encoder
,
270 struct intel_crtc_state
*config
)
272 struct intel_dsi
*intel_dsi
= container_of(encoder
, struct intel_dsi
,
274 struct intel_connector
*intel_connector
= intel_dsi
->attached_connector
;
275 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
276 struct drm_display_mode
*adjusted_mode
= &config
->base
.adjusted_mode
;
281 intel_fixed_panel_mode(fixed_mode
, adjusted_mode
);
283 /* DSI uses short packets for sync events, so clear mode flags for DSI */
284 adjusted_mode
->flags
= 0;
289 static void intel_dsi_port_enable(struct intel_encoder
*encoder
)
291 struct drm_device
*dev
= encoder
->base
.dev
;
292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
293 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
294 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
298 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
299 temp
= I915_READ(VLV_CHICKEN_3
);
300 temp
&= ~PIXEL_OVERLAP_CNT_MASK
|
301 intel_dsi
->pixel_overlap
<<
302 PIXEL_OVERLAP_CNT_SHIFT
;
303 I915_WRITE(VLV_CHICKEN_3
, temp
);
306 for_each_dsi_port(port
, intel_dsi
->ports
) {
307 temp
= I915_READ(MIPI_PORT_CTRL(port
));
308 temp
&= ~LANE_CONFIGURATION_MASK
;
309 temp
&= ~DUAL_LINK_MODE_MASK
;
311 if (intel_dsi
->ports
== ((1 << PORT_A
) | (1 << PORT_C
))) {
312 temp
|= (intel_dsi
->dual_link
- 1)
313 << DUAL_LINK_MODE_SHIFT
;
314 temp
|= intel_crtc
->pipe
?
315 LANE_CONFIGURATION_DUAL_LINK_B
:
316 LANE_CONFIGURATION_DUAL_LINK_A
;
318 /* assert ip_tg_enable signal */
319 I915_WRITE(MIPI_PORT_CTRL(port
), temp
| DPI_ENABLE
);
320 POSTING_READ(MIPI_PORT_CTRL(port
));
324 static void intel_dsi_port_disable(struct intel_encoder
*encoder
)
326 struct drm_device
*dev
= encoder
->base
.dev
;
327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
328 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
332 for_each_dsi_port(port
, intel_dsi
->ports
) {
333 /* de-assert ip_tg_enable signal */
334 temp
= I915_READ(MIPI_PORT_CTRL(port
));
335 I915_WRITE(MIPI_PORT_CTRL(port
), temp
& ~DPI_ENABLE
);
336 POSTING_READ(MIPI_PORT_CTRL(port
));
340 static void intel_dsi_device_ready(struct intel_encoder
*encoder
)
342 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
343 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
349 mutex_lock(&dev_priv
->dpio_lock
);
350 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
351 * needed everytime after power gate */
352 vlv_flisdsi_write(dev_priv
, 0x04, 0x0004);
353 mutex_unlock(&dev_priv
->dpio_lock
);
355 /* bandgap reset is needed after everytime we do power gate */
356 band_gap_reset(dev_priv
);
358 for_each_dsi_port(port
, intel_dsi
->ports
) {
360 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_ENTER
);
361 usleep_range(2500, 3000);
363 /* Enable MIPI PHY transparent latch
364 * Common bit for both MIPI Port A & MIPI Port C
365 * No similar bit in MIPI Port C reg
367 val
= I915_READ(MIPI_PORT_CTRL(PORT_A
));
368 I915_WRITE(MIPI_PORT_CTRL(PORT_A
), val
| LP_OUTPUT_HOLD
);
369 usleep_range(1000, 1500);
371 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_EXIT
);
372 usleep_range(2500, 3000);
374 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
);
375 usleep_range(2500, 3000);
379 static void intel_dsi_enable(struct intel_encoder
*encoder
)
381 struct drm_device
*dev
= encoder
->base
.dev
;
382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
383 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
388 if (is_cmd_mode(intel_dsi
)) {
389 for_each_dsi_port(port
, intel_dsi
->ports
)
390 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port
), 8 * 4);
392 msleep(20); /* XXX */
393 for_each_dsi_port(port
, intel_dsi
->ports
)
394 dpi_send_cmd(intel_dsi
, TURN_ON
, false, port
);
397 drm_panel_enable(intel_dsi
->panel
);
399 for_each_dsi_port(port
, intel_dsi
->ports
)
400 wait_for_dsi_fifo_empty(intel_dsi
, port
);
402 intel_dsi_port_enable(encoder
);
406 static void intel_dsi_pre_enable(struct intel_encoder
*encoder
)
408 struct drm_device
*dev
= encoder
->base
.dev
;
409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
410 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
411 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
412 enum pipe pipe
= intel_crtc
->pipe
;
418 /* Disable DPOunit clock gating, can stall pipe
419 * and we need DPLL REFA always enabled */
420 tmp
= I915_READ(DPLL(pipe
));
421 tmp
|= DPLL_REFA_CLK_ENABLE_VLV
;
422 I915_WRITE(DPLL(pipe
), tmp
);
424 /* update the hw state for DPLL */
425 intel_crtc
->config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_CLOCK_VLV
|
426 DPLL_REFA_CLK_ENABLE_VLV
;
428 tmp
= I915_READ(DSPCLK_GATE_D
);
429 tmp
|= DPOUNIT_CLOCK_GATE_DISABLE
;
430 I915_WRITE(DSPCLK_GATE_D
, tmp
);
432 /* put device in ready state */
433 intel_dsi_device_ready(encoder
);
435 msleep(intel_dsi
->panel_on_delay
);
437 drm_panel_prepare(intel_dsi
->panel
);
439 for_each_dsi_port(port
, intel_dsi
->ports
)
440 wait_for_dsi_fifo_empty(intel_dsi
, port
);
442 /* Enable port in pre-enable phase itself because as per hw team
443 * recommendation, port should be enabled befor plane & pipe */
444 intel_dsi_enable(encoder
);
447 static void intel_dsi_enable_nop(struct intel_encoder
*encoder
)
451 /* for DSI port enable has to be done before pipe
452 * and plane enable, so port enable is done in
453 * pre_enable phase itself unlike other encoders
457 static void intel_dsi_pre_disable(struct intel_encoder
*encoder
)
459 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
464 if (is_vid_mode(intel_dsi
)) {
465 /* Send Shutdown command to the panel in LP mode */
466 for_each_dsi_port(port
, intel_dsi
->ports
)
467 dpi_send_cmd(intel_dsi
, SHUTDOWN
, false, port
);
472 static void intel_dsi_disable(struct intel_encoder
*encoder
)
474 struct drm_device
*dev
= encoder
->base
.dev
;
475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
476 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
482 if (is_vid_mode(intel_dsi
)) {
483 for_each_dsi_port(port
, intel_dsi
->ports
)
484 wait_for_dsi_fifo_empty(intel_dsi
, port
);
486 intel_dsi_port_disable(encoder
);
490 for_each_dsi_port(port
, intel_dsi
->ports
) {
491 /* Panel commands can be sent when clock is in LP11 */
492 I915_WRITE(MIPI_DEVICE_READY(port
), 0x0);
494 temp
= I915_READ(MIPI_CTRL(port
));
495 temp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
496 I915_WRITE(MIPI_CTRL(port
), temp
|
497 intel_dsi
->escape_clk_div
<<
498 ESCAPE_CLOCK_DIVIDER_SHIFT
);
500 I915_WRITE(MIPI_EOT_DISABLE(port
), CLOCKSTOP
);
502 temp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
503 temp
&= ~VID_MODE_FORMAT_MASK
;
504 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), temp
);
506 I915_WRITE(MIPI_DEVICE_READY(port
), 0x1);
508 /* if disable packets are sent before sending shutdown packet then in
509 * some next enable sequence send turn on packet error is observed */
510 drm_panel_disable(intel_dsi
->panel
);
512 for_each_dsi_port(port
, intel_dsi
->ports
)
513 wait_for_dsi_fifo_empty(intel_dsi
, port
);
516 static void intel_dsi_clear_device_ready(struct intel_encoder
*encoder
)
518 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
519 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
524 for_each_dsi_port(port
, intel_dsi
->ports
) {
526 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
528 usleep_range(2000, 2500);
530 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
532 usleep_range(2000, 2500);
534 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
536 usleep_range(2000, 2500);
538 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
539 * only. MIPI Port C has no similar bit for checking
541 if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A
)) & AFE_LATCHOUT
)
543 DRM_ERROR("DSI LP not going Low\n");
545 /* Disable MIPI PHY transparent latch
546 * Common bit for both MIPI Port A & MIPI Port C
548 val
= I915_READ(MIPI_PORT_CTRL(PORT_A
));
549 I915_WRITE(MIPI_PORT_CTRL(PORT_A
), val
& ~LP_OUTPUT_HOLD
);
550 usleep_range(1000, 1500);
552 I915_WRITE(MIPI_DEVICE_READY(port
), 0x00);
553 usleep_range(2000, 2500);
556 vlv_disable_dsi_pll(encoder
);
559 static void intel_dsi_post_disable(struct intel_encoder
*encoder
)
561 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
562 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
567 intel_dsi_disable(encoder
);
569 intel_dsi_clear_device_ready(encoder
);
571 val
= I915_READ(DSPCLK_GATE_D
);
572 val
&= ~DPOUNIT_CLOCK_GATE_DISABLE
;
573 I915_WRITE(DSPCLK_GATE_D
, val
);
575 drm_panel_unprepare(intel_dsi
->panel
);
577 msleep(intel_dsi
->panel_off_delay
);
578 msleep(intel_dsi
->panel_pwr_cycle_delay
);
581 static bool intel_dsi_get_hw_state(struct intel_encoder
*encoder
,
584 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
585 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
586 struct drm_device
*dev
= encoder
->base
.dev
;
587 enum intel_display_power_domain power_domain
;
588 u32 dpi_enabled
, func
;
593 power_domain
= intel_display_port_power_domain(encoder
);
594 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
597 /* XXX: this only works for one DSI output */
598 for_each_dsi_port(port
, intel_dsi
->ports
) {
599 func
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
600 dpi_enabled
= I915_READ(MIPI_PORT_CTRL(port
)) &
603 /* Due to some hardware limitations on BYT, MIPI Port C DPI
604 * Enable bit does not get set. To check whether DSI Port C
605 * was enabled in BIOS, check the Pipe B enable bit
607 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
609 dpi_enabled
= I915_READ(PIPECONF(PIPE_B
)) &
612 if (dpi_enabled
|| (func
& CMD_MODE_DATA_WIDTH_MASK
)) {
613 if (I915_READ(MIPI_DEVICE_READY(port
)) & DEVICE_READY
) {
614 *pipe
= port
== PORT_A
? PIPE_A
: PIPE_B
;
623 static void intel_dsi_get_config(struct intel_encoder
*encoder
,
624 struct intel_crtc_state
*pipe_config
)
630 * DPLL_MD is not used in case of DSI, reading will get some default value
633 pipe_config
->dpll_hw_state
.dpll_md
= 0;
635 pclk
= vlv_get_dsi_pclk(encoder
, pipe_config
->pipe_bpp
);
639 pipe_config
->base
.adjusted_mode
.crtc_clock
= pclk
;
640 pipe_config
->port_clock
= pclk
;
643 static enum drm_mode_status
644 intel_dsi_mode_valid(struct drm_connector
*connector
,
645 struct drm_display_mode
*mode
)
647 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
648 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
652 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
653 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
654 return MODE_NO_DBLESCAN
;
658 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
660 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
667 /* return txclkesc cycles in terms of divider and duration in us */
668 static u16
txclkesc(u32 divider
, unsigned int us
)
671 case ESCAPE_CLOCK_DIVIDER_1
:
674 case ESCAPE_CLOCK_DIVIDER_2
:
676 case ESCAPE_CLOCK_DIVIDER_4
:
681 /* return pixels in terms of txbyteclkhs */
682 static u16
txbyteclkhs(u16 pixels
, int bpp
, int lane_count
,
683 u16 burst_mode_ratio
)
685 return DIV_ROUND_UP(DIV_ROUND_UP(pixels
* bpp
* burst_mode_ratio
,
686 8 * 100), lane_count
);
689 static void set_dsi_timings(struct drm_encoder
*encoder
,
690 const struct drm_display_mode
*mode
)
692 struct drm_device
*dev
= encoder
->dev
;
693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
694 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
695 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
697 unsigned int bpp
= intel_crtc
->config
->pipe_bpp
;
698 unsigned int lane_count
= intel_dsi
->lane_count
;
700 u16 hactive
, hfp
, hsync
, hbp
, vfp
, vsync
, vbp
;
702 hactive
= mode
->hdisplay
;
703 hfp
= mode
->hsync_start
- mode
->hdisplay
;
704 hsync
= mode
->hsync_end
- mode
->hsync_start
;
705 hbp
= mode
->htotal
- mode
->hsync_end
;
707 if (intel_dsi
->dual_link
) {
709 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
710 hactive
+= intel_dsi
->pixel_overlap
;
716 vfp
= mode
->vsync_start
- mode
->vdisplay
;
717 vsync
= mode
->vsync_end
- mode
->vsync_start
;
718 vbp
= mode
->vtotal
- mode
->vsync_end
;
720 /* horizontal values are in terms of high speed byte clock */
721 hactive
= txbyteclkhs(hactive
, bpp
, lane_count
,
722 intel_dsi
->burst_mode_ratio
);
723 hfp
= txbyteclkhs(hfp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
724 hsync
= txbyteclkhs(hsync
, bpp
, lane_count
,
725 intel_dsi
->burst_mode_ratio
);
726 hbp
= txbyteclkhs(hbp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
728 for_each_dsi_port(port
, intel_dsi
->ports
) {
729 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port
), hactive
);
730 I915_WRITE(MIPI_HFP_COUNT(port
), hfp
);
732 /* meaningful for video mode non-burst sync pulse mode only,
733 * can be zero for non-burst sync events and burst modes */
734 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port
), hsync
);
735 I915_WRITE(MIPI_HBP_COUNT(port
), hbp
);
737 /* vertical values are in terms of lines */
738 I915_WRITE(MIPI_VFP_COUNT(port
), vfp
);
739 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port
), vsync
);
740 I915_WRITE(MIPI_VBP_COUNT(port
), vbp
);
744 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
)
746 struct drm_encoder
*encoder
= &intel_encoder
->base
;
747 struct drm_device
*dev
= encoder
->dev
;
748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
749 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
750 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
751 struct drm_display_mode
*adjusted_mode
=
752 &intel_crtc
->config
->base
.adjusted_mode
;
754 unsigned int bpp
= intel_crtc
->config
->pipe_bpp
;
758 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc
->pipe
));
760 mode_hdisplay
= adjusted_mode
->hdisplay
;
762 if (intel_dsi
->dual_link
) {
764 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
765 mode_hdisplay
+= intel_dsi
->pixel_overlap
;
768 for_each_dsi_port(port
, intel_dsi
->ports
) {
769 /* escape clock divider, 20MHz, shared for A and C.
770 * device ready must be off when doing this! txclkesc? */
771 tmp
= I915_READ(MIPI_CTRL(PORT_A
));
772 tmp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
773 I915_WRITE(MIPI_CTRL(PORT_A
), tmp
| ESCAPE_CLOCK_DIVIDER_1
);
775 /* read request priority is per pipe */
776 tmp
= I915_READ(MIPI_CTRL(port
));
777 tmp
&= ~READ_REQUEST_PRIORITY_MASK
;
778 I915_WRITE(MIPI_CTRL(port
), tmp
| READ_REQUEST_PRIORITY_HIGH
);
780 /* XXX: why here, why like this? handling in irq handler?! */
781 I915_WRITE(MIPI_INTR_STAT(port
), 0xffffffff);
782 I915_WRITE(MIPI_INTR_EN(port
), 0xffffffff);
784 I915_WRITE(MIPI_DPHY_PARAM(port
), intel_dsi
->dphy_reg
);
786 I915_WRITE(MIPI_DPI_RESOLUTION(port
),
787 adjusted_mode
->vdisplay
<< VERTICAL_ADDRESS_SHIFT
|
788 mode_hdisplay
<< HORIZONTAL_ADDRESS_SHIFT
);
791 set_dsi_timings(encoder
, adjusted_mode
);
793 val
= intel_dsi
->lane_count
<< DATA_LANES_PRG_REG_SHIFT
;
794 if (is_cmd_mode(intel_dsi
)) {
795 val
|= intel_dsi
->channel
<< CMD_MODE_CHANNEL_NUMBER_SHIFT
;
796 val
|= CMD_MODE_DATA_WIDTH_8_BIT
; /* XXX */
798 val
|= intel_dsi
->channel
<< VID_MODE_CHANNEL_NUMBER_SHIFT
;
800 /* XXX: cross-check bpp vs. pixel format? */
801 val
|= intel_dsi
->pixel_format
;
805 if (intel_dsi
->eotp_pkt
== 0)
807 if (intel_dsi
->clock_stop
)
810 for_each_dsi_port(port
, intel_dsi
->ports
) {
811 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), val
);
813 /* timeouts for recovery. one frame IIUC. if counter expires,
814 * EOT and stop state. */
817 * In burst mode, value greater than one DPI line Time in byte
818 * clock (txbyteclkhs) To timeout this timer 1+ of the above
819 * said value is recommended.
821 * In non-burst mode, Value greater than one DPI frame time in
822 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
823 * said value is recommended.
825 * In DBI only mode, value greater than one DBI frame time in
826 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
827 * said value is recommended.
830 if (is_vid_mode(intel_dsi
) &&
831 intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
832 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
833 txbyteclkhs(adjusted_mode
->htotal
, bpp
,
834 intel_dsi
->lane_count
,
835 intel_dsi
->burst_mode_ratio
) + 1);
837 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
838 txbyteclkhs(adjusted_mode
->vtotal
*
839 adjusted_mode
->htotal
,
840 bpp
, intel_dsi
->lane_count
,
841 intel_dsi
->burst_mode_ratio
) + 1);
843 I915_WRITE(MIPI_LP_RX_TIMEOUT(port
), intel_dsi
->lp_rx_timeout
);
844 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port
),
845 intel_dsi
->turn_arnd_val
);
846 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port
),
847 intel_dsi
->rst_timer_val
);
851 /* in terms of low power clock */
852 I915_WRITE(MIPI_INIT_COUNT(port
),
853 txclkesc(intel_dsi
->escape_clk_div
, 100));
856 /* recovery disables */
857 I915_WRITE(MIPI_EOT_DISABLE(port
), val
);
859 /* in terms of low power clock */
860 I915_WRITE(MIPI_INIT_COUNT(port
), intel_dsi
->init_count
);
862 /* in terms of txbyteclkhs. actual high to low switch +
863 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
865 * XXX: write MIPI_STOP_STATE_STALL?
867 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port
),
868 intel_dsi
->hs_to_lp_count
);
870 /* XXX: low power clock equivalence in terms of byte clock.
871 * the number of byte clocks occupied in one low power clock.
872 * based on txbyteclkhs and txclkesc.
873 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
876 I915_WRITE(MIPI_LP_BYTECLK(port
), intel_dsi
->lp_byte_clk
);
878 /* the bw essential for transmitting 16 long packets containing
879 * 252 bytes meant for dcs write memory command is programmed in
880 * this register in terms of byte clocks. based on dsi transfer
881 * rate and the number of lanes configured the time taken to
882 * transmit 16 long packets in a dsi stream varies. */
883 I915_WRITE(MIPI_DBI_BW_CTRL(port
), intel_dsi
->bw_timer
);
885 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port
),
886 intel_dsi
->clk_lp_to_hs_count
<< LP_HS_SSW_CNT_SHIFT
|
887 intel_dsi
->clk_hs_to_lp_count
<< HS_LP_PWR_SW_CNT_SHIFT
);
889 if (is_vid_mode(intel_dsi
))
890 /* Some panels might have resolution which is not a
891 * multiple of 64 like 1366 x 768. Enable RANDOM
892 * resolution support for such panels by default */
893 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port
),
894 intel_dsi
->video_frmt_cfg_bits
|
895 intel_dsi
->video_mode_format
|
897 RANDOM_DPI_DISPLAY_RESOLUTION
);
901 static void intel_dsi_pre_pll_enable(struct intel_encoder
*encoder
)
905 intel_dsi_prepare(encoder
);
907 vlv_enable_dsi_pll(encoder
);
910 static enum drm_connector_status
911 intel_dsi_detect(struct drm_connector
*connector
, bool force
)
913 return connector_status_connected
;
916 static int intel_dsi_get_modes(struct drm_connector
*connector
)
918 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
919 struct drm_display_mode
*mode
;
923 if (!intel_connector
->panel
.fixed_mode
) {
924 DRM_DEBUG_KMS("no fixed mode\n");
928 mode
= drm_mode_duplicate(connector
->dev
,
929 intel_connector
->panel
.fixed_mode
);
931 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
935 drm_mode_probed_add(connector
, mode
);
939 static void intel_dsi_connector_destroy(struct drm_connector
*connector
)
941 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
944 intel_panel_fini(&intel_connector
->panel
);
945 drm_connector_cleanup(connector
);
949 static void intel_dsi_encoder_destroy(struct drm_encoder
*encoder
)
951 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
953 if (intel_dsi
->panel
) {
954 drm_panel_detach(intel_dsi
->panel
);
955 /* XXX: Logically this call belongs in the panel driver. */
956 drm_panel_remove(intel_dsi
->panel
);
958 intel_encoder_destroy(encoder
);
961 static const struct drm_encoder_funcs intel_dsi_funcs
= {
962 .destroy
= intel_dsi_encoder_destroy
,
965 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs
= {
966 .get_modes
= intel_dsi_get_modes
,
967 .mode_valid
= intel_dsi_mode_valid
,
968 .best_encoder
= intel_best_encoder
,
971 static const struct drm_connector_funcs intel_dsi_connector_funcs
= {
972 .dpms
= intel_connector_dpms
,
973 .detect
= intel_dsi_detect
,
974 .destroy
= intel_dsi_connector_destroy
,
975 .fill_modes
= drm_helper_probe_single_connector_modes
,
976 .atomic_get_property
= intel_connector_atomic_get_property
,
977 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
980 void intel_dsi_init(struct drm_device
*dev
)
982 struct intel_dsi
*intel_dsi
;
983 struct intel_encoder
*intel_encoder
;
984 struct drm_encoder
*encoder
;
985 struct intel_connector
*intel_connector
;
986 struct drm_connector
*connector
;
987 struct drm_display_mode
*scan
, *fixed_mode
= NULL
;
988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
994 /* There is no detection method for MIPI so rely on VBT */
995 if (!dev_priv
->vbt
.has_mipi
)
998 if (IS_VALLEYVIEW(dev
)) {
999 dev_priv
->mipi_mmio_base
= VLV_MIPI_BASE
;
1001 DRM_ERROR("Unsupported Mipi device to reg base");
1005 intel_dsi
= kzalloc(sizeof(*intel_dsi
), GFP_KERNEL
);
1009 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
1010 if (!intel_connector
) {
1015 intel_encoder
= &intel_dsi
->base
;
1016 encoder
= &intel_encoder
->base
;
1017 intel_dsi
->attached_connector
= intel_connector
;
1019 connector
= &intel_connector
->base
;
1021 drm_encoder_init(dev
, encoder
, &intel_dsi_funcs
, DRM_MODE_ENCODER_DSI
);
1023 /* XXX: very likely not all of these are needed */
1024 intel_encoder
->hot_plug
= intel_dsi_hot_plug
;
1025 intel_encoder
->compute_config
= intel_dsi_compute_config
;
1026 intel_encoder
->pre_pll_enable
= intel_dsi_pre_pll_enable
;
1027 intel_encoder
->pre_enable
= intel_dsi_pre_enable
;
1028 intel_encoder
->enable
= intel_dsi_enable_nop
;
1029 intel_encoder
->disable
= intel_dsi_pre_disable
;
1030 intel_encoder
->post_disable
= intel_dsi_post_disable
;
1031 intel_encoder
->get_hw_state
= intel_dsi_get_hw_state
;
1032 intel_encoder
->get_config
= intel_dsi_get_config
;
1034 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1035 intel_connector
->unregister
= intel_connector_unregister
;
1037 /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
1038 if (dev_priv
->vbt
.dsi
.config
->dual_link
) {
1039 /* XXX: does dual link work on either pipe? */
1040 intel_encoder
->crtc_mask
= (1 << PIPE_A
);
1041 intel_dsi
->ports
= ((1 << PORT_A
) | (1 << PORT_C
));
1042 } else if (dev_priv
->vbt
.dsi
.port
== DVO_PORT_MIPIA
) {
1043 intel_encoder
->crtc_mask
= (1 << PIPE_A
);
1044 intel_dsi
->ports
= (1 << PORT_A
);
1045 } else if (dev_priv
->vbt
.dsi
.port
== DVO_PORT_MIPIC
) {
1046 intel_encoder
->crtc_mask
= (1 << PIPE_B
);
1047 intel_dsi
->ports
= (1 << PORT_C
);
1050 /* Create a DSI host (and a device) for each port. */
1051 for_each_dsi_port(port
, intel_dsi
->ports
) {
1052 struct intel_dsi_host
*host
;
1054 host
= intel_dsi_host_init(intel_dsi
, port
);
1058 intel_dsi
->dsi_hosts
[port
] = host
;
1061 for (i
= 0; i
< ARRAY_SIZE(intel_dsi_drivers
); i
++) {
1062 intel_dsi
->panel
= intel_dsi_drivers
[i
].init(intel_dsi
,
1063 intel_dsi_drivers
[i
].panel_id
);
1064 if (intel_dsi
->panel
)
1068 if (!intel_dsi
->panel
) {
1069 DRM_DEBUG_KMS("no device found\n");
1073 intel_encoder
->type
= INTEL_OUTPUT_DSI
;
1074 intel_encoder
->cloneable
= 0;
1075 drm_connector_init(dev
, connector
, &intel_dsi_connector_funcs
,
1076 DRM_MODE_CONNECTOR_DSI
);
1078 drm_connector_helper_add(connector
, &intel_dsi_connector_helper_funcs
);
1080 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
; /*XXX*/
1081 connector
->interlace_allowed
= false;
1082 connector
->doublescan_allowed
= false;
1084 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1086 drm_connector_register(connector
);
1088 drm_panel_attach(intel_dsi
->panel
, connector
);
1090 mutex_lock(&dev
->mode_config
.mutex
);
1091 drm_panel_get_modes(intel_dsi
->panel
);
1092 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
1093 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
1094 fixed_mode
= drm_mode_duplicate(dev
, scan
);
1098 mutex_unlock(&dev
->mode_config
.mutex
);
1101 DRM_DEBUG_KMS("no fixed mode\n");
1105 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
1110 drm_encoder_cleanup(&intel_encoder
->base
);
1112 kfree(intel_connector
);