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drm/i915: Force clean compilation with -Werror
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dsi.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26 #include <drm/drmP.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_mipi_dsi.h>
33 #include <linux/slab.h>
34 #include <linux/gpio/consumer.h>
35 #include "i915_drv.h"
36 #include "intel_drv.h"
37 #include "intel_dsi.h"
38
39 static const struct {
40 u16 panel_id;
41 struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
42 } intel_dsi_drivers[] = {
43 {
44 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
45 .init = vbt_panel_init,
46 },
47 };
48
49 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
50 {
51 /* It just so happens the VBT matches register contents. */
52 switch (fmt) {
53 case VID_MODE_FORMAT_RGB888:
54 return MIPI_DSI_FMT_RGB888;
55 case VID_MODE_FORMAT_RGB666:
56 return MIPI_DSI_FMT_RGB666;
57 case VID_MODE_FORMAT_RGB666_PACKED:
58 return MIPI_DSI_FMT_RGB666_PACKED;
59 case VID_MODE_FORMAT_RGB565:
60 return MIPI_DSI_FMT_RGB565;
61 default:
62 MISSING_CASE(fmt);
63 return MIPI_DSI_FMT_RGB666;
64 }
65 }
66
67 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
68 {
69 struct drm_encoder *encoder = &intel_dsi->base.base;
70 struct drm_device *dev = encoder->dev;
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 mask;
73
74 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
75 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
76
77 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
78 DRM_ERROR("DPI FIFOs are not empty\n");
79 }
80
81 static void write_data(struct drm_i915_private *dev_priv,
82 i915_reg_t reg,
83 const u8 *data, u32 len)
84 {
85 u32 i, j;
86
87 for (i = 0; i < len; i += 4) {
88 u32 val = 0;
89
90 for (j = 0; j < min_t(u32, len - i, 4); j++)
91 val |= *data++ << 8 * j;
92
93 I915_WRITE(reg, val);
94 }
95 }
96
97 static void read_data(struct drm_i915_private *dev_priv,
98 i915_reg_t reg,
99 u8 *data, u32 len)
100 {
101 u32 i, j;
102
103 for (i = 0; i < len; i += 4) {
104 u32 val = I915_READ(reg);
105
106 for (j = 0; j < min_t(u32, len - i, 4); j++)
107 *data++ = val >> 8 * j;
108 }
109 }
110
111 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
112 const struct mipi_dsi_msg *msg)
113 {
114 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
115 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
116 struct drm_i915_private *dev_priv = dev->dev_private;
117 enum port port = intel_dsi_host->port;
118 struct mipi_dsi_packet packet;
119 ssize_t ret;
120 const u8 *header, *data;
121 i915_reg_t data_reg, ctrl_reg;
122 u32 data_mask, ctrl_mask;
123
124 ret = mipi_dsi_create_packet(&packet, msg);
125 if (ret < 0)
126 return ret;
127
128 header = packet.header;
129 data = packet.payload;
130
131 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
132 data_reg = MIPI_LP_GEN_DATA(port);
133 data_mask = LP_DATA_FIFO_FULL;
134 ctrl_reg = MIPI_LP_GEN_CTRL(port);
135 ctrl_mask = LP_CTRL_FIFO_FULL;
136 } else {
137 data_reg = MIPI_HS_GEN_DATA(port);
138 data_mask = HS_DATA_FIFO_FULL;
139 ctrl_reg = MIPI_HS_GEN_CTRL(port);
140 ctrl_mask = HS_CTRL_FIFO_FULL;
141 }
142
143 /* note: this is never true for reads */
144 if (packet.payload_length) {
145
146 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50))
147 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
148
149 write_data(dev_priv, data_reg, packet.payload,
150 packet.payload_length);
151 }
152
153 if (msg->rx_len) {
154 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
155 }
156
157 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) {
158 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
159 }
160
161 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
162
163 /* ->rx_len is set only for reads */
164 if (msg->rx_len) {
165 data_mask = GEN_READ_DATA_AVAIL;
166 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50))
167 DRM_ERROR("Timeout waiting for read data.\n");
168
169 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
170 }
171
172 /* XXX: fix for reads and writes */
173 return 4 + packet.payload_length;
174 }
175
176 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
177 struct mipi_dsi_device *dsi)
178 {
179 return 0;
180 }
181
182 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
183 struct mipi_dsi_device *dsi)
184 {
185 return 0;
186 }
187
188 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
189 .attach = intel_dsi_host_attach,
190 .detach = intel_dsi_host_detach,
191 .transfer = intel_dsi_host_transfer,
192 };
193
194 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
195 enum port port)
196 {
197 struct intel_dsi_host *host;
198 struct mipi_dsi_device *device;
199
200 host = kzalloc(sizeof(*host), GFP_KERNEL);
201 if (!host)
202 return NULL;
203
204 host->base.ops = &intel_dsi_host_ops;
205 host->intel_dsi = intel_dsi;
206 host->port = port;
207
208 /*
209 * We should call mipi_dsi_host_register(&host->base) here, but we don't
210 * have a host->dev, and we don't have OF stuff either. So just use the
211 * dsi framework as a library and hope for the best. Create the dsi
212 * devices by ourselves here too. Need to be careful though, because we
213 * don't initialize any of the driver model devices here.
214 */
215 device = kzalloc(sizeof(*device), GFP_KERNEL);
216 if (!device) {
217 kfree(host);
218 return NULL;
219 }
220
221 device->host = &host->base;
222 host->device = device;
223
224 return host;
225 }
226
227 /*
228 * send a video mode command
229 *
230 * XXX: commands with data in MIPI_DPI_DATA?
231 */
232 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
233 enum port port)
234 {
235 struct drm_encoder *encoder = &intel_dsi->base.base;
236 struct drm_device *dev = encoder->dev;
237 struct drm_i915_private *dev_priv = dev->dev_private;
238 u32 mask;
239
240 /* XXX: pipe, hs */
241 if (hs)
242 cmd &= ~DPI_LP_MODE;
243 else
244 cmd |= DPI_LP_MODE;
245
246 /* clear bit */
247 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
248
249 /* XXX: old code skips write if control unchanged */
250 if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
251 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
252
253 I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
254
255 mask = SPL_PKT_SENT_INTERRUPT;
256 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
257 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
258
259 return 0;
260 }
261
262 static void band_gap_reset(struct drm_i915_private *dev_priv)
263 {
264 mutex_lock(&dev_priv->sb_lock);
265
266 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
267 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
268 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
269 udelay(150);
270 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
271 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
272
273 mutex_unlock(&dev_priv->sb_lock);
274 }
275
276 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
277 {
278 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
279 }
280
281 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
282 {
283 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
284 }
285
286 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
287 struct intel_crtc_state *pipe_config)
288 {
289 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
290 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
291 base);
292 struct intel_connector *intel_connector = intel_dsi->attached_connector;
293 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
294 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
295
296 DRM_DEBUG_KMS("\n");
297
298 pipe_config->has_dsi_encoder = true;
299
300 if (fixed_mode)
301 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
302
303 /* DSI uses short packets for sync events, so clear mode flags for DSI */
304 adjusted_mode->flags = 0;
305
306 if (IS_BROXTON(dev_priv)) {
307 /* Dual link goes to DSI transcoder A. */
308 if (intel_dsi->ports == BIT(PORT_C))
309 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
310 else
311 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
312 }
313
314 return true;
315 }
316
317 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
318 {
319 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
320 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
321 enum port port;
322 u32 val;
323
324 DRM_DEBUG_KMS("\n");
325
326 /* Exit Low power state in 4 steps*/
327 for_each_dsi_port(port, intel_dsi->ports) {
328
329 /* 1. Enable MIPI PHY transparent latch */
330 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
331 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
332 usleep_range(2000, 2500);
333
334 /* 2. Enter ULPS */
335 val = I915_READ(MIPI_DEVICE_READY(port));
336 val &= ~ULPS_STATE_MASK;
337 val |= (ULPS_STATE_ENTER | DEVICE_READY);
338 I915_WRITE(MIPI_DEVICE_READY(port), val);
339 usleep_range(2, 3);
340
341 /* 3. Exit ULPS */
342 val = I915_READ(MIPI_DEVICE_READY(port));
343 val &= ~ULPS_STATE_MASK;
344 val |= (ULPS_STATE_EXIT | DEVICE_READY);
345 I915_WRITE(MIPI_DEVICE_READY(port), val);
346 usleep_range(1000, 1500);
347
348 /* Clear ULPS and set device ready */
349 val = I915_READ(MIPI_DEVICE_READY(port));
350 val &= ~ULPS_STATE_MASK;
351 val |= DEVICE_READY;
352 I915_WRITE(MIPI_DEVICE_READY(port), val);
353 }
354 }
355
356 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
357 {
358 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
359 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
360 enum port port;
361 u32 val;
362
363 DRM_DEBUG_KMS("\n");
364
365 mutex_lock(&dev_priv->sb_lock);
366 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
367 * needed everytime after power gate */
368 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
369 mutex_unlock(&dev_priv->sb_lock);
370
371 /* bandgap reset is needed after everytime we do power gate */
372 band_gap_reset(dev_priv);
373
374 for_each_dsi_port(port, intel_dsi->ports) {
375
376 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
377 usleep_range(2500, 3000);
378
379 /* Enable MIPI PHY transparent latch
380 * Common bit for both MIPI Port A & MIPI Port C
381 * No similar bit in MIPI Port C reg
382 */
383 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
384 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
385 usleep_range(1000, 1500);
386
387 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
388 usleep_range(2500, 3000);
389
390 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
391 usleep_range(2500, 3000);
392 }
393 }
394
395 static void intel_dsi_device_ready(struct intel_encoder *encoder)
396 {
397 struct drm_device *dev = encoder->base.dev;
398
399 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
400 vlv_dsi_device_ready(encoder);
401 else if (IS_BROXTON(dev))
402 bxt_dsi_device_ready(encoder);
403 }
404
405 static void intel_dsi_port_enable(struct intel_encoder *encoder)
406 {
407 struct drm_device *dev = encoder->base.dev;
408 struct drm_i915_private *dev_priv = dev->dev_private;
409 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
410 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
411 enum port port;
412
413 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
414 u32 temp;
415
416 temp = I915_READ(VLV_CHICKEN_3);
417 temp &= ~PIXEL_OVERLAP_CNT_MASK |
418 intel_dsi->pixel_overlap <<
419 PIXEL_OVERLAP_CNT_SHIFT;
420 I915_WRITE(VLV_CHICKEN_3, temp);
421 }
422
423 for_each_dsi_port(port, intel_dsi->ports) {
424 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
425 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
426 u32 temp;
427
428 temp = I915_READ(port_ctrl);
429
430 temp &= ~LANE_CONFIGURATION_MASK;
431 temp &= ~DUAL_LINK_MODE_MASK;
432
433 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
434 temp |= (intel_dsi->dual_link - 1)
435 << DUAL_LINK_MODE_SHIFT;
436 temp |= intel_crtc->pipe ?
437 LANE_CONFIGURATION_DUAL_LINK_B :
438 LANE_CONFIGURATION_DUAL_LINK_A;
439 }
440 /* assert ip_tg_enable signal */
441 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
442 POSTING_READ(port_ctrl);
443 }
444 }
445
446 static void intel_dsi_port_disable(struct intel_encoder *encoder)
447 {
448 struct drm_device *dev = encoder->base.dev;
449 struct drm_i915_private *dev_priv = dev->dev_private;
450 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
451 enum port port;
452
453 for_each_dsi_port(port, intel_dsi->ports) {
454 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
455 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
456 u32 temp;
457
458 /* de-assert ip_tg_enable signal */
459 temp = I915_READ(port_ctrl);
460 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
461 POSTING_READ(port_ctrl);
462 }
463 }
464
465 static void intel_dsi_enable(struct intel_encoder *encoder)
466 {
467 struct drm_device *dev = encoder->base.dev;
468 struct drm_i915_private *dev_priv = dev->dev_private;
469 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
470 enum port port;
471
472 DRM_DEBUG_KMS("\n");
473
474 if (is_cmd_mode(intel_dsi)) {
475 for_each_dsi_port(port, intel_dsi->ports)
476 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
477 } else {
478 msleep(20); /* XXX */
479 for_each_dsi_port(port, intel_dsi->ports)
480 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
481 msleep(100);
482
483 drm_panel_enable(intel_dsi->panel);
484
485 for_each_dsi_port(port, intel_dsi->ports)
486 wait_for_dsi_fifo_empty(intel_dsi, port);
487
488 intel_dsi_port_enable(encoder);
489 }
490
491 intel_panel_enable_backlight(intel_dsi->attached_connector);
492 }
493
494 static void intel_dsi_prepare(struct intel_encoder *intel_encoder);
495
496 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
497 {
498 struct drm_device *dev = encoder->base.dev;
499 struct drm_i915_private *dev_priv = dev->dev_private;
500 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
501 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
502 enum pipe pipe = intel_crtc->pipe;
503 enum port port;
504 u32 tmp;
505
506 DRM_DEBUG_KMS("\n");
507
508 /*
509 * The BIOS may leave the PLL in a wonky state where it doesn't
510 * lock. It needs to be fully powered down to fix it.
511 */
512 intel_disable_dsi_pll(encoder);
513 intel_enable_dsi_pll(encoder);
514
515 intel_dsi_prepare(encoder);
516
517 /* Panel Enable over CRC PMIC */
518 if (intel_dsi->gpio_panel)
519 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
520
521 msleep(intel_dsi->panel_on_delay);
522
523 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
524 /*
525 * Disable DPOunit clock gating, can stall pipe
526 * and we need DPLL REFA always enabled
527 */
528 tmp = I915_READ(DPLL(pipe));
529 tmp |= DPLL_REF_CLK_ENABLE_VLV;
530 I915_WRITE(DPLL(pipe), tmp);
531
532 /* update the hw state for DPLL */
533 intel_crtc->config->dpll_hw_state.dpll =
534 DPLL_INTEGRATED_REF_CLK_VLV |
535 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
536
537 tmp = I915_READ(DSPCLK_GATE_D);
538 tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
539 I915_WRITE(DSPCLK_GATE_D, tmp);
540 }
541
542 /* put device in ready state */
543 intel_dsi_device_ready(encoder);
544
545 drm_panel_prepare(intel_dsi->panel);
546
547 for_each_dsi_port(port, intel_dsi->ports)
548 wait_for_dsi_fifo_empty(intel_dsi, port);
549
550 /* Enable port in pre-enable phase itself because as per hw team
551 * recommendation, port should be enabled befor plane & pipe */
552 intel_dsi_enable(encoder);
553 }
554
555 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
556 {
557 DRM_DEBUG_KMS("\n");
558
559 /* for DSI port enable has to be done before pipe
560 * and plane enable, so port enable is done in
561 * pre_enable phase itself unlike other encoders
562 */
563 }
564
565 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
566 {
567 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
568 enum port port;
569
570 DRM_DEBUG_KMS("\n");
571
572 intel_panel_disable_backlight(intel_dsi->attached_connector);
573
574 if (is_vid_mode(intel_dsi)) {
575 /* Send Shutdown command to the panel in LP mode */
576 for_each_dsi_port(port, intel_dsi->ports)
577 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
578 msleep(10);
579 }
580 }
581
582 static void intel_dsi_disable(struct intel_encoder *encoder)
583 {
584 struct drm_device *dev = encoder->base.dev;
585 struct drm_i915_private *dev_priv = dev->dev_private;
586 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
587 enum port port;
588 u32 temp;
589
590 DRM_DEBUG_KMS("\n");
591
592 if (is_vid_mode(intel_dsi)) {
593 for_each_dsi_port(port, intel_dsi->ports)
594 wait_for_dsi_fifo_empty(intel_dsi, port);
595
596 intel_dsi_port_disable(encoder);
597 msleep(2);
598 }
599
600 for_each_dsi_port(port, intel_dsi->ports) {
601 /* Panel commands can be sent when clock is in LP11 */
602 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
603
604 intel_dsi_reset_clocks(encoder, port);
605 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
606
607 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
608 temp &= ~VID_MODE_FORMAT_MASK;
609 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
610
611 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
612 }
613 /* if disable packets are sent before sending shutdown packet then in
614 * some next enable sequence send turn on packet error is observed */
615 drm_panel_disable(intel_dsi->panel);
616
617 for_each_dsi_port(port, intel_dsi->ports)
618 wait_for_dsi_fifo_empty(intel_dsi, port);
619 }
620
621 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
622 {
623 struct drm_device *dev = encoder->base.dev;
624 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
625 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
626 enum port port;
627
628 DRM_DEBUG_KMS("\n");
629 for_each_dsi_port(port, intel_dsi->ports) {
630 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
631 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
632 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
633 u32 val;
634
635 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
636 ULPS_STATE_ENTER);
637 usleep_range(2000, 2500);
638
639 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
640 ULPS_STATE_EXIT);
641 usleep_range(2000, 2500);
642
643 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
644 ULPS_STATE_ENTER);
645 usleep_range(2000, 2500);
646
647 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
648 * only. MIPI Port C has no similar bit for checking
649 */
650 if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT)
651 == 0x00000), 30))
652 DRM_ERROR("DSI LP not going Low\n");
653
654 /* Disable MIPI PHY transparent latch */
655 val = I915_READ(port_ctrl);
656 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
657 usleep_range(1000, 1500);
658
659 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
660 usleep_range(2000, 2500);
661 }
662
663 intel_disable_dsi_pll(encoder);
664 }
665
666 static void intel_dsi_post_disable(struct intel_encoder *encoder)
667 {
668 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
669 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
670
671 DRM_DEBUG_KMS("\n");
672
673 intel_dsi_disable(encoder);
674
675 intel_dsi_clear_device_ready(encoder);
676
677 if (!IS_BROXTON(dev_priv)) {
678 u32 val;
679
680 val = I915_READ(DSPCLK_GATE_D);
681 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
682 I915_WRITE(DSPCLK_GATE_D, val);
683 }
684
685 drm_panel_unprepare(intel_dsi->panel);
686
687 msleep(intel_dsi->panel_off_delay);
688 msleep(intel_dsi->panel_pwr_cycle_delay);
689
690 /* Panel Disable over CRC PMIC */
691 if (intel_dsi->gpio_panel)
692 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
693 }
694
695 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
696 enum pipe *pipe)
697 {
698 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
699 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
700 struct drm_device *dev = encoder->base.dev;
701 enum intel_display_power_domain power_domain;
702 enum port port;
703 bool active = false;
704
705 DRM_DEBUG_KMS("\n");
706
707 power_domain = intel_display_port_power_domain(encoder);
708 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
709 return false;
710
711 /*
712 * On Broxton the PLL needs to be enabled with a valid divider
713 * configuration, otherwise accessing DSI registers will hang the
714 * machine. See BSpec North Display Engine registers/MIPI[BXT].
715 */
716 if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
717 goto out_put_power;
718
719 /* XXX: this only works for one DSI output */
720 for_each_dsi_port(port, intel_dsi->ports) {
721 i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
722 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
723 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
724
725 /* Due to some hardware limitations on BYT, MIPI Port C DPI
726 * Enable bit does not get set. To check whether DSI Port C
727 * was enabled in BIOS, check the Pipe B enable bit
728 */
729 if (IS_VALLEYVIEW(dev) && port == PORT_C)
730 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
731
732 /* Try command mode if video mode not enabled */
733 if (!enabled) {
734 u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
735 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
736 }
737
738 if (!enabled)
739 continue;
740
741 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
742 continue;
743
744 if (IS_BROXTON(dev_priv)) {
745 u32 tmp = I915_READ(MIPI_CTRL(port));
746 tmp &= BXT_PIPE_SELECT_MASK;
747 tmp >>= BXT_PIPE_SELECT_SHIFT;
748
749 if (WARN_ON(tmp > PIPE_C))
750 continue;
751
752 *pipe = tmp;
753 } else {
754 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
755 }
756
757 active = true;
758 break;
759 }
760
761 out_put_power:
762 intel_display_power_put(dev_priv, power_domain);
763
764 return active;
765 }
766
767 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
768 struct intel_crtc_state *pipe_config)
769 {
770 struct drm_device *dev = encoder->base.dev;
771 struct drm_i915_private *dev_priv = dev->dev_private;
772 struct drm_display_mode *adjusted_mode =
773 &pipe_config->base.adjusted_mode;
774 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
775 unsigned int bpp, fmt;
776 enum port port;
777 u16 vfp, vsync, vbp;
778
779 /*
780 * Atleast one port is active as encoder->get_config called only if
781 * encoder->get_hw_state() returns true.
782 */
783 for_each_dsi_port(port, intel_dsi->ports) {
784 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
785 break;
786 }
787
788 fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
789 pipe_config->pipe_bpp =
790 mipi_dsi_pixel_format_to_bpp(
791 pixel_format_from_register_bits(fmt));
792 bpp = pipe_config->pipe_bpp;
793
794 /* In terms of pixels */
795 adjusted_mode->crtc_hdisplay =
796 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
797 adjusted_mode->crtc_vdisplay =
798 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
799 adjusted_mode->crtc_vtotal =
800 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
801
802 /*
803 * TODO: Retrieve hfp, hsync and hbp. Adjust them for dual link and
804 * calculate hsync_start, hsync_end, htotal and hblank_end
805 */
806
807 /* vertical values are in terms of lines */
808 vfp = I915_READ(MIPI_VFP_COUNT(port));
809 vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
810 vbp = I915_READ(MIPI_VBP_COUNT(port));
811
812 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
813
814 adjusted_mode->crtc_vsync_start =
815 vfp + adjusted_mode->crtc_vdisplay;
816 adjusted_mode->crtc_vsync_end =
817 vsync + adjusted_mode->crtc_vsync_start;
818 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
819 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
820 }
821
822
823 static void intel_dsi_get_config(struct intel_encoder *encoder,
824 struct intel_crtc_state *pipe_config)
825 {
826 struct drm_device *dev = encoder->base.dev;
827 u32 pclk;
828 DRM_DEBUG_KMS("\n");
829
830 pipe_config->has_dsi_encoder = true;
831
832 if (IS_BROXTON(dev))
833 bxt_dsi_get_pipe_config(encoder, pipe_config);
834
835 /*
836 * DPLL_MD is not used in case of DSI, reading will get some default value
837 * set dpll_md = 0
838 */
839 pipe_config->dpll_hw_state.dpll_md = 0;
840
841 pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp);
842 if (!pclk)
843 return;
844
845 pipe_config->base.adjusted_mode.crtc_clock = pclk;
846 pipe_config->port_clock = pclk;
847 }
848
849 static enum drm_mode_status
850 intel_dsi_mode_valid(struct drm_connector *connector,
851 struct drm_display_mode *mode)
852 {
853 struct intel_connector *intel_connector = to_intel_connector(connector);
854 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
855 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
856
857 DRM_DEBUG_KMS("\n");
858
859 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
860 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
861 return MODE_NO_DBLESCAN;
862 }
863
864 if (fixed_mode) {
865 if (mode->hdisplay > fixed_mode->hdisplay)
866 return MODE_PANEL;
867 if (mode->vdisplay > fixed_mode->vdisplay)
868 return MODE_PANEL;
869 if (fixed_mode->clock > max_dotclk)
870 return MODE_CLOCK_HIGH;
871 }
872
873 return MODE_OK;
874 }
875
876 /* return txclkesc cycles in terms of divider and duration in us */
877 static u16 txclkesc(u32 divider, unsigned int us)
878 {
879 switch (divider) {
880 case ESCAPE_CLOCK_DIVIDER_1:
881 default:
882 return 20 * us;
883 case ESCAPE_CLOCK_DIVIDER_2:
884 return 10 * us;
885 case ESCAPE_CLOCK_DIVIDER_4:
886 return 5 * us;
887 }
888 }
889
890 /* return pixels in terms of txbyteclkhs */
891 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
892 u16 burst_mode_ratio)
893 {
894 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
895 8 * 100), lane_count);
896 }
897
898 static void set_dsi_timings(struct drm_encoder *encoder,
899 const struct drm_display_mode *adjusted_mode)
900 {
901 struct drm_device *dev = encoder->dev;
902 struct drm_i915_private *dev_priv = dev->dev_private;
903 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
904 enum port port;
905 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
906 unsigned int lane_count = intel_dsi->lane_count;
907
908 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
909
910 hactive = adjusted_mode->crtc_hdisplay;
911 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
912 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
913 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
914
915 if (intel_dsi->dual_link) {
916 hactive /= 2;
917 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
918 hactive += intel_dsi->pixel_overlap;
919 hfp /= 2;
920 hsync /= 2;
921 hbp /= 2;
922 }
923
924 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
925 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
926 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
927
928 /* horizontal values are in terms of high speed byte clock */
929 hactive = txbyteclkhs(hactive, bpp, lane_count,
930 intel_dsi->burst_mode_ratio);
931 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
932 hsync = txbyteclkhs(hsync, bpp, lane_count,
933 intel_dsi->burst_mode_ratio);
934 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
935
936 for_each_dsi_port(port, intel_dsi->ports) {
937 if (IS_BROXTON(dev)) {
938 /*
939 * Program hdisplay and vdisplay on MIPI transcoder.
940 * This is different from calculated hactive and
941 * vactive, as they are calculated per channel basis,
942 * whereas these values should be based on resolution.
943 */
944 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
945 adjusted_mode->crtc_hdisplay);
946 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
947 adjusted_mode->crtc_vdisplay);
948 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
949 adjusted_mode->crtc_vtotal);
950 }
951
952 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
953 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
954
955 /* meaningful for video mode non-burst sync pulse mode only,
956 * can be zero for non-burst sync events and burst modes */
957 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
958 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
959
960 /* vertical values are in terms of lines */
961 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
962 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
963 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
964 }
965 }
966
967 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
968 {
969 switch (fmt) {
970 case MIPI_DSI_FMT_RGB888:
971 return VID_MODE_FORMAT_RGB888;
972 case MIPI_DSI_FMT_RGB666:
973 return VID_MODE_FORMAT_RGB666;
974 case MIPI_DSI_FMT_RGB666_PACKED:
975 return VID_MODE_FORMAT_RGB666_PACKED;
976 case MIPI_DSI_FMT_RGB565:
977 return VID_MODE_FORMAT_RGB565;
978 default:
979 MISSING_CASE(fmt);
980 return VID_MODE_FORMAT_RGB666;
981 }
982 }
983
984 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
985 {
986 struct drm_encoder *encoder = &intel_encoder->base;
987 struct drm_device *dev = encoder->dev;
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
990 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
991 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
992 enum port port;
993 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
994 u32 val, tmp;
995 u16 mode_hdisplay;
996
997 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
998
999 mode_hdisplay = adjusted_mode->crtc_hdisplay;
1000
1001 if (intel_dsi->dual_link) {
1002 mode_hdisplay /= 2;
1003 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1004 mode_hdisplay += intel_dsi->pixel_overlap;
1005 }
1006
1007 for_each_dsi_port(port, intel_dsi->ports) {
1008 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1009 /*
1010 * escape clock divider, 20MHz, shared for A and C.
1011 * device ready must be off when doing this! txclkesc?
1012 */
1013 tmp = I915_READ(MIPI_CTRL(PORT_A));
1014 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1015 I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1016 ESCAPE_CLOCK_DIVIDER_1);
1017
1018 /* read request priority is per pipe */
1019 tmp = I915_READ(MIPI_CTRL(port));
1020 tmp &= ~READ_REQUEST_PRIORITY_MASK;
1021 I915_WRITE(MIPI_CTRL(port), tmp |
1022 READ_REQUEST_PRIORITY_HIGH);
1023 } else if (IS_BROXTON(dev)) {
1024 enum pipe pipe = intel_crtc->pipe;
1025
1026 tmp = I915_READ(MIPI_CTRL(port));
1027 tmp &= ~BXT_PIPE_SELECT_MASK;
1028
1029 tmp |= BXT_PIPE_SELECT(pipe);
1030 I915_WRITE(MIPI_CTRL(port), tmp);
1031 }
1032
1033 /* XXX: why here, why like this? handling in irq handler?! */
1034 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1035 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1036
1037 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1038
1039 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1040 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1041 mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1042 }
1043
1044 set_dsi_timings(encoder, adjusted_mode);
1045
1046 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1047 if (is_cmd_mode(intel_dsi)) {
1048 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1049 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1050 } else {
1051 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1052 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1053 }
1054
1055 tmp = 0;
1056 if (intel_dsi->eotp_pkt == 0)
1057 tmp |= EOT_DISABLE;
1058 if (intel_dsi->clock_stop)
1059 tmp |= CLOCKSTOP;
1060
1061 for_each_dsi_port(port, intel_dsi->ports) {
1062 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1063
1064 /* timeouts for recovery. one frame IIUC. if counter expires,
1065 * EOT and stop state. */
1066
1067 /*
1068 * In burst mode, value greater than one DPI line Time in byte
1069 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1070 * said value is recommended.
1071 *
1072 * In non-burst mode, Value greater than one DPI frame time in
1073 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1074 * said value is recommended.
1075 *
1076 * In DBI only mode, value greater than one DBI frame time in
1077 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1078 * said value is recommended.
1079 */
1080
1081 if (is_vid_mode(intel_dsi) &&
1082 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1083 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1084 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1085 intel_dsi->lane_count,
1086 intel_dsi->burst_mode_ratio) + 1);
1087 } else {
1088 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1089 txbyteclkhs(adjusted_mode->crtc_vtotal *
1090 adjusted_mode->crtc_htotal,
1091 bpp, intel_dsi->lane_count,
1092 intel_dsi->burst_mode_ratio) + 1);
1093 }
1094 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1095 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1096 intel_dsi->turn_arnd_val);
1097 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1098 intel_dsi->rst_timer_val);
1099
1100 /* dphy stuff */
1101
1102 /* in terms of low power clock */
1103 I915_WRITE(MIPI_INIT_COUNT(port),
1104 txclkesc(intel_dsi->escape_clk_div, 100));
1105
1106 if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
1107 /*
1108 * BXT spec says write MIPI_INIT_COUNT for
1109 * both the ports, even if only one is
1110 * getting used. So write the other port
1111 * if not in dual link mode.
1112 */
1113 I915_WRITE(MIPI_INIT_COUNT(port ==
1114 PORT_A ? PORT_C : PORT_A),
1115 intel_dsi->init_count);
1116 }
1117
1118 /* recovery disables */
1119 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1120
1121 /* in terms of low power clock */
1122 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1123
1124 /* in terms of txbyteclkhs. actual high to low switch +
1125 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1126 *
1127 * XXX: write MIPI_STOP_STATE_STALL?
1128 */
1129 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1130 intel_dsi->hs_to_lp_count);
1131
1132 /* XXX: low power clock equivalence in terms of byte clock.
1133 * the number of byte clocks occupied in one low power clock.
1134 * based on txbyteclkhs and txclkesc.
1135 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1136 * ) / 105.???
1137 */
1138 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1139
1140 /* the bw essential for transmitting 16 long packets containing
1141 * 252 bytes meant for dcs write memory command is programmed in
1142 * this register in terms of byte clocks. based on dsi transfer
1143 * rate and the number of lanes configured the time taken to
1144 * transmit 16 long packets in a dsi stream varies. */
1145 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1146
1147 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1148 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1149 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1150
1151 if (is_vid_mode(intel_dsi))
1152 /* Some panels might have resolution which is not a
1153 * multiple of 64 like 1366 x 768. Enable RANDOM
1154 * resolution support for such panels by default */
1155 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1156 intel_dsi->video_frmt_cfg_bits |
1157 intel_dsi->video_mode_format |
1158 IP_TG_CONFIG |
1159 RANDOM_DPI_DISPLAY_RESOLUTION);
1160 }
1161 }
1162
1163 static enum drm_connector_status
1164 intel_dsi_detect(struct drm_connector *connector, bool force)
1165 {
1166 return connector_status_connected;
1167 }
1168
1169 static int intel_dsi_get_modes(struct drm_connector *connector)
1170 {
1171 struct intel_connector *intel_connector = to_intel_connector(connector);
1172 struct drm_display_mode *mode;
1173
1174 DRM_DEBUG_KMS("\n");
1175
1176 if (!intel_connector->panel.fixed_mode) {
1177 DRM_DEBUG_KMS("no fixed mode\n");
1178 return 0;
1179 }
1180
1181 mode = drm_mode_duplicate(connector->dev,
1182 intel_connector->panel.fixed_mode);
1183 if (!mode) {
1184 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1185 return 0;
1186 }
1187
1188 drm_mode_probed_add(connector, mode);
1189 return 1;
1190 }
1191
1192 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1193 {
1194 struct intel_connector *intel_connector = to_intel_connector(connector);
1195
1196 DRM_DEBUG_KMS("\n");
1197 intel_panel_fini(&intel_connector->panel);
1198 drm_connector_cleanup(connector);
1199 kfree(connector);
1200 }
1201
1202 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1203 {
1204 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1205
1206 if (intel_dsi->panel) {
1207 drm_panel_detach(intel_dsi->panel);
1208 /* XXX: Logically this call belongs in the panel driver. */
1209 drm_panel_remove(intel_dsi->panel);
1210 }
1211
1212 /* dispose of the gpios */
1213 if (intel_dsi->gpio_panel)
1214 gpiod_put(intel_dsi->gpio_panel);
1215
1216 intel_encoder_destroy(encoder);
1217 }
1218
1219 static const struct drm_encoder_funcs intel_dsi_funcs = {
1220 .destroy = intel_dsi_encoder_destroy,
1221 };
1222
1223 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1224 .get_modes = intel_dsi_get_modes,
1225 .mode_valid = intel_dsi_mode_valid,
1226 .best_encoder = intel_best_encoder,
1227 };
1228
1229 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1230 .dpms = drm_atomic_helper_connector_dpms,
1231 .detect = intel_dsi_detect,
1232 .destroy = intel_dsi_connector_destroy,
1233 .fill_modes = drm_helper_probe_single_connector_modes,
1234 .atomic_get_property = intel_connector_atomic_get_property,
1235 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1236 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1237 };
1238
1239 void intel_dsi_init(struct drm_device *dev)
1240 {
1241 struct intel_dsi *intel_dsi;
1242 struct intel_encoder *intel_encoder;
1243 struct drm_encoder *encoder;
1244 struct intel_connector *intel_connector;
1245 struct drm_connector *connector;
1246 struct drm_display_mode *scan, *fixed_mode = NULL;
1247 struct drm_i915_private *dev_priv = dev->dev_private;
1248 enum port port;
1249 unsigned int i;
1250
1251 DRM_DEBUG_KMS("\n");
1252
1253 /* There is no detection method for MIPI so rely on VBT */
1254 if (!intel_bios_is_dsi_present(dev_priv, &port))
1255 return;
1256
1257 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1258 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1259 } else if (IS_BROXTON(dev)) {
1260 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1261 } else {
1262 DRM_ERROR("Unsupported Mipi device to reg base");
1263 return;
1264 }
1265
1266 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1267 if (!intel_dsi)
1268 return;
1269
1270 intel_connector = intel_connector_alloc();
1271 if (!intel_connector) {
1272 kfree(intel_dsi);
1273 return;
1274 }
1275
1276 intel_encoder = &intel_dsi->base;
1277 encoder = &intel_encoder->base;
1278 intel_dsi->attached_connector = intel_connector;
1279
1280 connector = &intel_connector->base;
1281
1282 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1283 NULL);
1284
1285 intel_encoder->compute_config = intel_dsi_compute_config;
1286 intel_encoder->pre_enable = intel_dsi_pre_enable;
1287 intel_encoder->enable = intel_dsi_enable_nop;
1288 intel_encoder->disable = intel_dsi_pre_disable;
1289 intel_encoder->post_disable = intel_dsi_post_disable;
1290 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1291 intel_encoder->get_config = intel_dsi_get_config;
1292
1293 intel_connector->get_hw_state = intel_connector_get_hw_state;
1294 intel_connector->unregister = intel_connector_unregister;
1295
1296 /*
1297 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1298 * port C. BXT isn't limited like this.
1299 */
1300 if (IS_BROXTON(dev_priv))
1301 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1302 else if (port == PORT_A)
1303 intel_encoder->crtc_mask = BIT(PIPE_A);
1304 else
1305 intel_encoder->crtc_mask = BIT(PIPE_B);
1306
1307 if (dev_priv->vbt.dsi.config->dual_link)
1308 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1309 else
1310 intel_dsi->ports = BIT(port);
1311
1312 /* Create a DSI host (and a device) for each port. */
1313 for_each_dsi_port(port, intel_dsi->ports) {
1314 struct intel_dsi_host *host;
1315
1316 host = intel_dsi_host_init(intel_dsi, port);
1317 if (!host)
1318 goto err;
1319
1320 intel_dsi->dsi_hosts[port] = host;
1321 }
1322
1323 for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1324 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1325 intel_dsi_drivers[i].panel_id);
1326 if (intel_dsi->panel)
1327 break;
1328 }
1329
1330 if (!intel_dsi->panel) {
1331 DRM_DEBUG_KMS("no device found\n");
1332 goto err;
1333 }
1334
1335 /*
1336 * In case of BYT with CRC PMIC, we need to use GPIO for
1337 * Panel control.
1338 */
1339 if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
1340 intel_dsi->gpio_panel =
1341 gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1342
1343 if (IS_ERR(intel_dsi->gpio_panel)) {
1344 DRM_ERROR("Failed to own gpio for panel control\n");
1345 intel_dsi->gpio_panel = NULL;
1346 }
1347 }
1348
1349 intel_encoder->type = INTEL_OUTPUT_DSI;
1350 intel_encoder->cloneable = 0;
1351 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1352 DRM_MODE_CONNECTOR_DSI);
1353
1354 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1355
1356 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1357 connector->interlace_allowed = false;
1358 connector->doublescan_allowed = false;
1359
1360 intel_connector_attach_encoder(intel_connector, intel_encoder);
1361
1362 drm_connector_register(connector);
1363
1364 drm_panel_attach(intel_dsi->panel, connector);
1365
1366 mutex_lock(&dev->mode_config.mutex);
1367 drm_panel_get_modes(intel_dsi->panel);
1368 list_for_each_entry(scan, &connector->probed_modes, head) {
1369 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1370 fixed_mode = drm_mode_duplicate(dev, scan);
1371 break;
1372 }
1373 }
1374 mutex_unlock(&dev->mode_config.mutex);
1375
1376 if (!fixed_mode) {
1377 DRM_DEBUG_KMS("no fixed mode\n");
1378 goto err;
1379 }
1380
1381 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1382 intel_panel_setup_backlight(connector, INVALID_PIPE);
1383
1384 return;
1385
1386 err:
1387 drm_encoder_cleanup(&intel_encoder->base);
1388 kfree(intel_dsi);
1389 kfree(intel_connector);
1390 }
Linux kernel - Deliverables
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