2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Jani Nikula <jani.nikula@intel.com>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_mipi_dsi.h>
33 #include <linux/slab.h>
34 #include <linux/gpio/consumer.h>
36 #include "intel_drv.h"
37 #include "intel_dsi.h"
41 struct drm_panel
* (*init
)(struct intel_dsi
*intel_dsi
, u16 panel_id
);
42 } intel_dsi_drivers
[] = {
44 .panel_id
= MIPI_DSI_GENERIC_PANEL_ID
,
45 .init
= vbt_panel_init
,
49 static void wait_for_dsi_fifo_empty(struct intel_dsi
*intel_dsi
, enum port port
)
51 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
52 struct drm_device
*dev
= encoder
->dev
;
53 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
56 mask
= LP_CTRL_FIFO_EMPTY
| HS_CTRL_FIFO_EMPTY
|
57 LP_DATA_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
;
59 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & mask
) == mask
, 100))
60 DRM_ERROR("DPI FIFOs are not empty\n");
63 static void write_data(struct drm_i915_private
*dev_priv
,
65 const u8
*data
, u32 len
)
69 for (i
= 0; i
< len
; i
+= 4) {
72 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
73 val
|= *data
++ << 8 * j
;
79 static void read_data(struct drm_i915_private
*dev_priv
,
85 for (i
= 0; i
< len
; i
+= 4) {
86 u32 val
= I915_READ(reg
);
88 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
89 *data
++ = val
>> 8 * j
;
93 static ssize_t
intel_dsi_host_transfer(struct mipi_dsi_host
*host
,
94 const struct mipi_dsi_msg
*msg
)
96 struct intel_dsi_host
*intel_dsi_host
= to_intel_dsi_host(host
);
97 struct drm_device
*dev
= intel_dsi_host
->intel_dsi
->base
.base
.dev
;
98 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
99 enum port port
= intel_dsi_host
->port
;
100 struct mipi_dsi_packet packet
;
102 const u8
*header
, *data
;
103 i915_reg_t data_reg
, ctrl_reg
;
104 u32 data_mask
, ctrl_mask
;
106 ret
= mipi_dsi_create_packet(&packet
, msg
);
110 header
= packet
.header
;
111 data
= packet
.payload
;
113 if (msg
->flags
& MIPI_DSI_MSG_USE_LPM
) {
114 data_reg
= MIPI_LP_GEN_DATA(port
);
115 data_mask
= LP_DATA_FIFO_FULL
;
116 ctrl_reg
= MIPI_LP_GEN_CTRL(port
);
117 ctrl_mask
= LP_CTRL_FIFO_FULL
;
119 data_reg
= MIPI_HS_GEN_DATA(port
);
120 data_mask
= HS_DATA_FIFO_FULL
;
121 ctrl_reg
= MIPI_HS_GEN_CTRL(port
);
122 ctrl_mask
= HS_CTRL_FIFO_FULL
;
125 /* note: this is never true for reads */
126 if (packet
.payload_length
) {
128 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & data_mask
) == 0, 50))
129 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
131 write_data(dev_priv
, data_reg
, packet
.payload
,
132 packet
.payload_length
);
136 I915_WRITE(MIPI_INTR_STAT(port
), GEN_READ_DATA_AVAIL
);
139 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & ctrl_mask
) == 0, 50)) {
140 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
143 I915_WRITE(ctrl_reg
, header
[2] << 16 | header
[1] << 8 | header
[0]);
145 /* ->rx_len is set only for reads */
147 data_mask
= GEN_READ_DATA_AVAIL
;
148 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & data_mask
) == data_mask
, 50))
149 DRM_ERROR("Timeout waiting for read data.\n");
151 read_data(dev_priv
, data_reg
, msg
->rx_buf
, msg
->rx_len
);
154 /* XXX: fix for reads and writes */
155 return 4 + packet
.payload_length
;
158 static int intel_dsi_host_attach(struct mipi_dsi_host
*host
,
159 struct mipi_dsi_device
*dsi
)
164 static int intel_dsi_host_detach(struct mipi_dsi_host
*host
,
165 struct mipi_dsi_device
*dsi
)
170 static const struct mipi_dsi_host_ops intel_dsi_host_ops
= {
171 .attach
= intel_dsi_host_attach
,
172 .detach
= intel_dsi_host_detach
,
173 .transfer
= intel_dsi_host_transfer
,
176 static struct intel_dsi_host
*intel_dsi_host_init(struct intel_dsi
*intel_dsi
,
179 struct intel_dsi_host
*host
;
180 struct mipi_dsi_device
*device
;
182 host
= kzalloc(sizeof(*host
), GFP_KERNEL
);
186 host
->base
.ops
= &intel_dsi_host_ops
;
187 host
->intel_dsi
= intel_dsi
;
191 * We should call mipi_dsi_host_register(&host->base) here, but we don't
192 * have a host->dev, and we don't have OF stuff either. So just use the
193 * dsi framework as a library and hope for the best. Create the dsi
194 * devices by ourselves here too. Need to be careful though, because we
195 * don't initialize any of the driver model devices here.
197 device
= kzalloc(sizeof(*device
), GFP_KERNEL
);
203 device
->host
= &host
->base
;
204 host
->device
= device
;
210 * send a video mode command
212 * XXX: commands with data in MIPI_DPI_DATA?
214 static int dpi_send_cmd(struct intel_dsi
*intel_dsi
, u32 cmd
, bool hs
,
217 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
218 struct drm_device
*dev
= encoder
->dev
;
219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
229 I915_WRITE(MIPI_INTR_STAT(port
), SPL_PKT_SENT_INTERRUPT
);
231 /* XXX: old code skips write if control unchanged */
232 if (cmd
== I915_READ(MIPI_DPI_CONTROL(port
)))
233 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd
);
235 I915_WRITE(MIPI_DPI_CONTROL(port
), cmd
);
237 mask
= SPL_PKT_SENT_INTERRUPT
;
238 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & mask
) == mask
, 100))
239 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd
);
244 static void band_gap_reset(struct drm_i915_private
*dev_priv
)
246 mutex_lock(&dev_priv
->sb_lock
);
248 vlv_flisdsi_write(dev_priv
, 0x08, 0x0001);
249 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0005);
250 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0025);
252 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0000);
253 vlv_flisdsi_write(dev_priv
, 0x08, 0x0000);
255 mutex_unlock(&dev_priv
->sb_lock
);
258 static inline bool is_vid_mode(struct intel_dsi
*intel_dsi
)
260 return intel_dsi
->operation_mode
== INTEL_DSI_VIDEO_MODE
;
263 static inline bool is_cmd_mode(struct intel_dsi
*intel_dsi
)
265 return intel_dsi
->operation_mode
== INTEL_DSI_COMMAND_MODE
;
268 static bool intel_dsi_compute_config(struct intel_encoder
*encoder
,
269 struct intel_crtc_state
*config
)
271 struct intel_dsi
*intel_dsi
= container_of(encoder
, struct intel_dsi
,
273 struct intel_connector
*intel_connector
= intel_dsi
->attached_connector
;
274 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
275 struct drm_display_mode
*adjusted_mode
= &config
->base
.adjusted_mode
;
280 intel_fixed_panel_mode(fixed_mode
, adjusted_mode
);
282 /* DSI uses short packets for sync events, so clear mode flags for DSI */
283 adjusted_mode
->flags
= 0;
288 static void bxt_dsi_device_ready(struct intel_encoder
*encoder
)
290 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
291 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
297 /* Exit Low power state in 4 steps*/
298 for_each_dsi_port(port
, intel_dsi
->ports
) {
300 /* 1. Enable MIPI PHY transparent latch */
301 val
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
302 I915_WRITE(BXT_MIPI_PORT_CTRL(port
), val
| LP_OUTPUT_HOLD
);
303 usleep_range(2000, 2500);
306 val
= I915_READ(MIPI_DEVICE_READY(port
));
307 val
&= ~ULPS_STATE_MASK
;
308 val
|= (ULPS_STATE_ENTER
| DEVICE_READY
);
309 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
313 val
= I915_READ(MIPI_DEVICE_READY(port
));
314 val
&= ~ULPS_STATE_MASK
;
315 val
|= (ULPS_STATE_EXIT
| DEVICE_READY
);
316 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
317 usleep_range(1000, 1500);
319 /* Clear ULPS and set device ready */
320 val
= I915_READ(MIPI_DEVICE_READY(port
));
321 val
&= ~ULPS_STATE_MASK
;
323 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
327 static void vlv_dsi_device_ready(struct intel_encoder
*encoder
)
329 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
330 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
336 mutex_lock(&dev_priv
->sb_lock
);
337 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
338 * needed everytime after power gate */
339 vlv_flisdsi_write(dev_priv
, 0x04, 0x0004);
340 mutex_unlock(&dev_priv
->sb_lock
);
342 /* bandgap reset is needed after everytime we do power gate */
343 band_gap_reset(dev_priv
);
345 for_each_dsi_port(port
, intel_dsi
->ports
) {
347 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_ENTER
);
348 usleep_range(2500, 3000);
350 /* Enable MIPI PHY transparent latch
351 * Common bit for both MIPI Port A & MIPI Port C
352 * No similar bit in MIPI Port C reg
354 val
= I915_READ(MIPI_PORT_CTRL(PORT_A
));
355 I915_WRITE(MIPI_PORT_CTRL(PORT_A
), val
| LP_OUTPUT_HOLD
);
356 usleep_range(1000, 1500);
358 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_EXIT
);
359 usleep_range(2500, 3000);
361 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
);
362 usleep_range(2500, 3000);
366 static void intel_dsi_device_ready(struct intel_encoder
*encoder
)
368 struct drm_device
*dev
= encoder
->base
.dev
;
370 if (IS_VALLEYVIEW(dev
))
371 vlv_dsi_device_ready(encoder
);
372 else if (IS_BROXTON(dev
))
373 bxt_dsi_device_ready(encoder
);
376 static void intel_dsi_port_enable(struct intel_encoder
*encoder
)
378 struct drm_device
*dev
= encoder
->base
.dev
;
379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
380 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
381 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
384 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
387 temp
= I915_READ(VLV_CHICKEN_3
);
388 temp
&= ~PIXEL_OVERLAP_CNT_MASK
|
389 intel_dsi
->pixel_overlap
<<
390 PIXEL_OVERLAP_CNT_SHIFT
;
391 I915_WRITE(VLV_CHICKEN_3
, temp
);
394 for_each_dsi_port(port
, intel_dsi
->ports
) {
395 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
396 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
399 temp
= I915_READ(port_ctrl
);
401 temp
&= ~LANE_CONFIGURATION_MASK
;
402 temp
&= ~DUAL_LINK_MODE_MASK
;
404 if (intel_dsi
->ports
== ((1 << PORT_A
) | (1 << PORT_C
))) {
405 temp
|= (intel_dsi
->dual_link
- 1)
406 << DUAL_LINK_MODE_SHIFT
;
407 temp
|= intel_crtc
->pipe
?
408 LANE_CONFIGURATION_DUAL_LINK_B
:
409 LANE_CONFIGURATION_DUAL_LINK_A
;
411 /* assert ip_tg_enable signal */
412 I915_WRITE(port_ctrl
, temp
| DPI_ENABLE
);
413 POSTING_READ(port_ctrl
);
417 static void intel_dsi_port_disable(struct intel_encoder
*encoder
)
419 struct drm_device
*dev
= encoder
->base
.dev
;
420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
421 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
424 for_each_dsi_port(port
, intel_dsi
->ports
) {
425 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
426 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
429 /* de-assert ip_tg_enable signal */
430 temp
= I915_READ(port_ctrl
);
431 I915_WRITE(port_ctrl
, temp
& ~DPI_ENABLE
);
432 POSTING_READ(port_ctrl
);
436 static void intel_dsi_enable(struct intel_encoder
*encoder
)
438 struct drm_device
*dev
= encoder
->base
.dev
;
439 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
440 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
445 if (is_cmd_mode(intel_dsi
)) {
446 for_each_dsi_port(port
, intel_dsi
->ports
)
447 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port
), 8 * 4);
449 msleep(20); /* XXX */
450 for_each_dsi_port(port
, intel_dsi
->ports
)
451 dpi_send_cmd(intel_dsi
, TURN_ON
, false, port
);
454 drm_panel_enable(intel_dsi
->panel
);
456 for_each_dsi_port(port
, intel_dsi
->ports
)
457 wait_for_dsi_fifo_empty(intel_dsi
, port
);
459 intel_dsi_port_enable(encoder
);
462 intel_panel_enable_backlight(intel_dsi
->attached_connector
);
465 static void intel_dsi_pre_enable(struct intel_encoder
*encoder
)
467 struct drm_device
*dev
= encoder
->base
.dev
;
468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
469 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
470 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
471 enum pipe pipe
= intel_crtc
->pipe
;
477 /* Panel Enable over CRC PMIC */
478 if (intel_dsi
->gpio_panel
)
479 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 1);
481 msleep(intel_dsi
->panel_on_delay
);
483 if (IS_VALLEYVIEW(dev
)) {
485 * Disable DPOunit clock gating, can stall pipe
486 * and we need DPLL REFA always enabled
488 tmp
= I915_READ(DPLL(pipe
));
489 tmp
|= DPLL_REF_CLK_ENABLE_VLV
;
490 I915_WRITE(DPLL(pipe
), tmp
);
492 /* update the hw state for DPLL */
493 intel_crtc
->config
->dpll_hw_state
.dpll
=
494 DPLL_INTEGRATED_REF_CLK_VLV
|
495 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
497 tmp
= I915_READ(DSPCLK_GATE_D
);
498 tmp
|= DPOUNIT_CLOCK_GATE_DISABLE
;
499 I915_WRITE(DSPCLK_GATE_D
, tmp
);
502 /* put device in ready state */
503 intel_dsi_device_ready(encoder
);
505 drm_panel_prepare(intel_dsi
->panel
);
507 for_each_dsi_port(port
, intel_dsi
->ports
)
508 wait_for_dsi_fifo_empty(intel_dsi
, port
);
510 /* Enable port in pre-enable phase itself because as per hw team
511 * recommendation, port should be enabled befor plane & pipe */
512 intel_dsi_enable(encoder
);
515 static void intel_dsi_enable_nop(struct intel_encoder
*encoder
)
519 /* for DSI port enable has to be done before pipe
520 * and plane enable, so port enable is done in
521 * pre_enable phase itself unlike other encoders
525 static void intel_dsi_pre_disable(struct intel_encoder
*encoder
)
527 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
532 intel_panel_disable_backlight(intel_dsi
->attached_connector
);
534 if (is_vid_mode(intel_dsi
)) {
535 /* Send Shutdown command to the panel in LP mode */
536 for_each_dsi_port(port
, intel_dsi
->ports
)
537 dpi_send_cmd(intel_dsi
, SHUTDOWN
, false, port
);
542 static void intel_dsi_disable(struct intel_encoder
*encoder
)
544 struct drm_device
*dev
= encoder
->base
.dev
;
545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
546 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
552 if (is_vid_mode(intel_dsi
)) {
553 for_each_dsi_port(port
, intel_dsi
->ports
)
554 wait_for_dsi_fifo_empty(intel_dsi
, port
);
556 intel_dsi_port_disable(encoder
);
560 for_each_dsi_port(port
, intel_dsi
->ports
) {
561 /* Panel commands can be sent when clock is in LP11 */
562 I915_WRITE(MIPI_DEVICE_READY(port
), 0x0);
564 intel_dsi_reset_clocks(encoder
, port
);
565 I915_WRITE(MIPI_EOT_DISABLE(port
), CLOCKSTOP
);
567 temp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
568 temp
&= ~VID_MODE_FORMAT_MASK
;
569 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), temp
);
571 I915_WRITE(MIPI_DEVICE_READY(port
), 0x1);
573 /* if disable packets are sent before sending shutdown packet then in
574 * some next enable sequence send turn on packet error is observed */
575 drm_panel_disable(intel_dsi
->panel
);
577 for_each_dsi_port(port
, intel_dsi
->ports
)
578 wait_for_dsi_fifo_empty(intel_dsi
, port
);
581 static void intel_dsi_clear_device_ready(struct intel_encoder
*encoder
)
583 struct drm_device
*dev
= encoder
->base
.dev
;
584 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
585 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
589 for_each_dsi_port(port
, intel_dsi
->ports
) {
590 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
591 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
592 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(PORT_A
);
595 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
597 usleep_range(2000, 2500);
599 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
601 usleep_range(2000, 2500);
603 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
605 usleep_range(2000, 2500);
607 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
608 * only. MIPI Port C has no similar bit for checking
610 if (wait_for(((I915_READ(port_ctrl
) & AFE_LATCHOUT
)
612 DRM_ERROR("DSI LP not going Low\n");
614 /* Disable MIPI PHY transparent latch */
615 val
= I915_READ(port_ctrl
);
616 I915_WRITE(port_ctrl
, val
& ~LP_OUTPUT_HOLD
);
617 usleep_range(1000, 1500);
619 I915_WRITE(MIPI_DEVICE_READY(port
), 0x00);
620 usleep_range(2000, 2500);
623 intel_disable_dsi_pll(encoder
);
626 static void intel_dsi_post_disable(struct intel_encoder
*encoder
)
628 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
629 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
634 intel_dsi_disable(encoder
);
636 intel_dsi_clear_device_ready(encoder
);
638 val
= I915_READ(DSPCLK_GATE_D
);
639 val
&= ~DPOUNIT_CLOCK_GATE_DISABLE
;
640 I915_WRITE(DSPCLK_GATE_D
, val
);
642 drm_panel_unprepare(intel_dsi
->panel
);
644 msleep(intel_dsi
->panel_off_delay
);
645 msleep(intel_dsi
->panel_pwr_cycle_delay
);
647 /* Panel Disable over CRC PMIC */
648 if (intel_dsi
->gpio_panel
)
649 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 0);
652 static bool intel_dsi_get_hw_state(struct intel_encoder
*encoder
,
655 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
656 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
657 struct drm_device
*dev
= encoder
->base
.dev
;
658 enum intel_display_power_domain power_domain
;
663 power_domain
= intel_display_port_power_domain(encoder
);
664 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
667 /* XXX: this only works for one DSI output */
668 for_each_dsi_port(port
, intel_dsi
->ports
) {
669 i915_reg_t ctrl_reg
= IS_BROXTON(dev
) ?
670 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
671 u32 dpi_enabled
, func
;
673 func
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
674 dpi_enabled
= I915_READ(ctrl_reg
) & DPI_ENABLE
;
676 /* Due to some hardware limitations on BYT, MIPI Port C DPI
677 * Enable bit does not get set. To check whether DSI Port C
678 * was enabled in BIOS, check the Pipe B enable bit
680 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
682 dpi_enabled
= I915_READ(PIPECONF(PIPE_B
)) &
685 if (dpi_enabled
|| (func
& CMD_MODE_DATA_WIDTH_MASK
)) {
686 if (I915_READ(MIPI_DEVICE_READY(port
)) & DEVICE_READY
) {
687 *pipe
= port
== PORT_A
? PIPE_A
: PIPE_B
;
696 static void intel_dsi_get_config(struct intel_encoder
*encoder
,
697 struct intel_crtc_state
*pipe_config
)
703 * DPLL_MD is not used in case of DSI, reading will get some default value
706 pipe_config
->dpll_hw_state
.dpll_md
= 0;
708 if (IS_BROXTON(encoder
->base
.dev
))
709 pclk
= bxt_get_dsi_pclk(encoder
, pipe_config
->pipe_bpp
);
710 else if (IS_VALLEYVIEW(encoder
->base
.dev
))
711 pclk
= vlv_get_dsi_pclk(encoder
, pipe_config
->pipe_bpp
);
716 pipe_config
->base
.adjusted_mode
.crtc_clock
= pclk
;
717 pipe_config
->port_clock
= pclk
;
720 static enum drm_mode_status
721 intel_dsi_mode_valid(struct drm_connector
*connector
,
722 struct drm_display_mode
*mode
)
724 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
725 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
726 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
730 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
731 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
732 return MODE_NO_DBLESCAN
;
736 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
738 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
740 if (fixed_mode
->clock
> max_dotclk
)
741 return MODE_CLOCK_HIGH
;
747 /* return txclkesc cycles in terms of divider and duration in us */
748 static u16
txclkesc(u32 divider
, unsigned int us
)
751 case ESCAPE_CLOCK_DIVIDER_1
:
754 case ESCAPE_CLOCK_DIVIDER_2
:
756 case ESCAPE_CLOCK_DIVIDER_4
:
761 /* return pixels in terms of txbyteclkhs */
762 static u16
txbyteclkhs(u16 pixels
, int bpp
, int lane_count
,
763 u16 burst_mode_ratio
)
765 return DIV_ROUND_UP(DIV_ROUND_UP(pixels
* bpp
* burst_mode_ratio
,
766 8 * 100), lane_count
);
769 static void set_dsi_timings(struct drm_encoder
*encoder
,
770 const struct drm_display_mode
*adjusted_mode
)
772 struct drm_device
*dev
= encoder
->dev
;
773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
774 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
775 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
777 unsigned int bpp
= intel_crtc
->config
->pipe_bpp
;
778 unsigned int lane_count
= intel_dsi
->lane_count
;
780 u16 hactive
, hfp
, hsync
, hbp
, vfp
, vsync
, vbp
;
782 hactive
= adjusted_mode
->crtc_hdisplay
;
783 hfp
= adjusted_mode
->crtc_hsync_start
- adjusted_mode
->crtc_hdisplay
;
784 hsync
= adjusted_mode
->crtc_hsync_end
- adjusted_mode
->crtc_hsync_start
;
785 hbp
= adjusted_mode
->crtc_htotal
- adjusted_mode
->crtc_hsync_end
;
787 if (intel_dsi
->dual_link
) {
789 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
790 hactive
+= intel_dsi
->pixel_overlap
;
796 vfp
= adjusted_mode
->crtc_vsync_start
- adjusted_mode
->crtc_vdisplay
;
797 vsync
= adjusted_mode
->crtc_vsync_end
- adjusted_mode
->crtc_vsync_start
;
798 vbp
= adjusted_mode
->crtc_vtotal
- adjusted_mode
->crtc_vsync_end
;
800 /* horizontal values are in terms of high speed byte clock */
801 hactive
= txbyteclkhs(hactive
, bpp
, lane_count
,
802 intel_dsi
->burst_mode_ratio
);
803 hfp
= txbyteclkhs(hfp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
804 hsync
= txbyteclkhs(hsync
, bpp
, lane_count
,
805 intel_dsi
->burst_mode_ratio
);
806 hbp
= txbyteclkhs(hbp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
808 for_each_dsi_port(port
, intel_dsi
->ports
) {
809 if (IS_BROXTON(dev
)) {
811 * Program hdisplay and vdisplay on MIPI transcoder.
812 * This is different from calculated hactive and
813 * vactive, as they are calculated per channel basis,
814 * whereas these values should be based on resolution.
816 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port
),
817 adjusted_mode
->crtc_hdisplay
);
818 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port
),
819 adjusted_mode
->crtc_vdisplay
);
820 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port
),
821 adjusted_mode
->crtc_vtotal
);
824 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port
), hactive
);
825 I915_WRITE(MIPI_HFP_COUNT(port
), hfp
);
827 /* meaningful for video mode non-burst sync pulse mode only,
828 * can be zero for non-burst sync events and burst modes */
829 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port
), hsync
);
830 I915_WRITE(MIPI_HBP_COUNT(port
), hbp
);
832 /* vertical values are in terms of lines */
833 I915_WRITE(MIPI_VFP_COUNT(port
), vfp
);
834 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port
), vsync
);
835 I915_WRITE(MIPI_VBP_COUNT(port
), vbp
);
839 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
)
841 struct drm_encoder
*encoder
= &intel_encoder
->base
;
842 struct drm_device
*dev
= encoder
->dev
;
843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
844 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
845 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
846 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
848 unsigned int bpp
= intel_crtc
->config
->pipe_bpp
;
852 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc
->pipe
));
854 mode_hdisplay
= adjusted_mode
->crtc_hdisplay
;
856 if (intel_dsi
->dual_link
) {
858 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
859 mode_hdisplay
+= intel_dsi
->pixel_overlap
;
862 for_each_dsi_port(port
, intel_dsi
->ports
) {
863 if (IS_VALLEYVIEW(dev
)) {
865 * escape clock divider, 20MHz, shared for A and C.
866 * device ready must be off when doing this! txclkesc?
868 tmp
= I915_READ(MIPI_CTRL(PORT_A
));
869 tmp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
870 I915_WRITE(MIPI_CTRL(PORT_A
), tmp
|
871 ESCAPE_CLOCK_DIVIDER_1
);
873 /* read request priority is per pipe */
874 tmp
= I915_READ(MIPI_CTRL(port
));
875 tmp
&= ~READ_REQUEST_PRIORITY_MASK
;
876 I915_WRITE(MIPI_CTRL(port
), tmp
|
877 READ_REQUEST_PRIORITY_HIGH
);
878 } else if (IS_BROXTON(dev
)) {
881 * BXT can connect any PIPE to any MIPI port.
882 * Select the pipe based on the MIPI port read from
883 * VBT for now. Pick PIPE A for MIPI port A and C
886 tmp
= I915_READ(MIPI_CTRL(port
));
887 tmp
&= ~BXT_PIPE_SELECT_MASK
;
890 tmp
|= BXT_PIPE_SELECT_A
;
891 else if (port
== PORT_C
)
892 tmp
|= BXT_PIPE_SELECT_C
;
894 I915_WRITE(MIPI_CTRL(port
), tmp
);
897 /* XXX: why here, why like this? handling in irq handler?! */
898 I915_WRITE(MIPI_INTR_STAT(port
), 0xffffffff);
899 I915_WRITE(MIPI_INTR_EN(port
), 0xffffffff);
901 I915_WRITE(MIPI_DPHY_PARAM(port
), intel_dsi
->dphy_reg
);
903 I915_WRITE(MIPI_DPI_RESOLUTION(port
),
904 adjusted_mode
->crtc_vdisplay
<< VERTICAL_ADDRESS_SHIFT
|
905 mode_hdisplay
<< HORIZONTAL_ADDRESS_SHIFT
);
908 set_dsi_timings(encoder
, adjusted_mode
);
910 val
= intel_dsi
->lane_count
<< DATA_LANES_PRG_REG_SHIFT
;
911 if (is_cmd_mode(intel_dsi
)) {
912 val
|= intel_dsi
->channel
<< CMD_MODE_CHANNEL_NUMBER_SHIFT
;
913 val
|= CMD_MODE_DATA_WIDTH_8_BIT
; /* XXX */
915 val
|= intel_dsi
->channel
<< VID_MODE_CHANNEL_NUMBER_SHIFT
;
917 /* XXX: cross-check bpp vs. pixel format? */
918 val
|= intel_dsi
->pixel_format
;
922 if (intel_dsi
->eotp_pkt
== 0)
924 if (intel_dsi
->clock_stop
)
927 for_each_dsi_port(port
, intel_dsi
->ports
) {
928 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), val
);
930 /* timeouts for recovery. one frame IIUC. if counter expires,
931 * EOT and stop state. */
934 * In burst mode, value greater than one DPI line Time in byte
935 * clock (txbyteclkhs) To timeout this timer 1+ of the above
936 * said value is recommended.
938 * In non-burst mode, Value greater than one DPI frame time in
939 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
940 * said value is recommended.
942 * In DBI only mode, value greater than one DBI frame time in
943 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
944 * said value is recommended.
947 if (is_vid_mode(intel_dsi
) &&
948 intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
949 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
950 txbyteclkhs(adjusted_mode
->crtc_htotal
, bpp
,
951 intel_dsi
->lane_count
,
952 intel_dsi
->burst_mode_ratio
) + 1);
954 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
955 txbyteclkhs(adjusted_mode
->crtc_vtotal
*
956 adjusted_mode
->crtc_htotal
,
957 bpp
, intel_dsi
->lane_count
,
958 intel_dsi
->burst_mode_ratio
) + 1);
960 I915_WRITE(MIPI_LP_RX_TIMEOUT(port
), intel_dsi
->lp_rx_timeout
);
961 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port
),
962 intel_dsi
->turn_arnd_val
);
963 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port
),
964 intel_dsi
->rst_timer_val
);
968 /* in terms of low power clock */
969 I915_WRITE(MIPI_INIT_COUNT(port
),
970 txclkesc(intel_dsi
->escape_clk_div
, 100));
972 if (IS_BROXTON(dev
) && (!intel_dsi
->dual_link
)) {
974 * BXT spec says write MIPI_INIT_COUNT for
975 * both the ports, even if only one is
976 * getting used. So write the other port
977 * if not in dual link mode.
979 I915_WRITE(MIPI_INIT_COUNT(port
==
980 PORT_A
? PORT_C
: PORT_A
),
981 intel_dsi
->init_count
);
984 /* recovery disables */
985 I915_WRITE(MIPI_EOT_DISABLE(port
), tmp
);
987 /* in terms of low power clock */
988 I915_WRITE(MIPI_INIT_COUNT(port
), intel_dsi
->init_count
);
990 /* in terms of txbyteclkhs. actual high to low switch +
991 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
993 * XXX: write MIPI_STOP_STATE_STALL?
995 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port
),
996 intel_dsi
->hs_to_lp_count
);
998 /* XXX: low power clock equivalence in terms of byte clock.
999 * the number of byte clocks occupied in one low power clock.
1000 * based on txbyteclkhs and txclkesc.
1001 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1004 I915_WRITE(MIPI_LP_BYTECLK(port
), intel_dsi
->lp_byte_clk
);
1006 /* the bw essential for transmitting 16 long packets containing
1007 * 252 bytes meant for dcs write memory command is programmed in
1008 * this register in terms of byte clocks. based on dsi transfer
1009 * rate and the number of lanes configured the time taken to
1010 * transmit 16 long packets in a dsi stream varies. */
1011 I915_WRITE(MIPI_DBI_BW_CTRL(port
), intel_dsi
->bw_timer
);
1013 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port
),
1014 intel_dsi
->clk_lp_to_hs_count
<< LP_HS_SSW_CNT_SHIFT
|
1015 intel_dsi
->clk_hs_to_lp_count
<< HS_LP_PWR_SW_CNT_SHIFT
);
1017 if (is_vid_mode(intel_dsi
))
1018 /* Some panels might have resolution which is not a
1019 * multiple of 64 like 1366 x 768. Enable RANDOM
1020 * resolution support for such panels by default */
1021 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port
),
1022 intel_dsi
->video_frmt_cfg_bits
|
1023 intel_dsi
->video_mode_format
|
1025 RANDOM_DPI_DISPLAY_RESOLUTION
);
1029 static void intel_dsi_pre_pll_enable(struct intel_encoder
*encoder
)
1031 DRM_DEBUG_KMS("\n");
1033 intel_dsi_prepare(encoder
);
1034 intel_enable_dsi_pll(encoder
);
1038 static enum drm_connector_status
1039 intel_dsi_detect(struct drm_connector
*connector
, bool force
)
1041 return connector_status_connected
;
1044 static int intel_dsi_get_modes(struct drm_connector
*connector
)
1046 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1047 struct drm_display_mode
*mode
;
1049 DRM_DEBUG_KMS("\n");
1051 if (!intel_connector
->panel
.fixed_mode
) {
1052 DRM_DEBUG_KMS("no fixed mode\n");
1056 mode
= drm_mode_duplicate(connector
->dev
,
1057 intel_connector
->panel
.fixed_mode
);
1059 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1063 drm_mode_probed_add(connector
, mode
);
1067 static void intel_dsi_connector_destroy(struct drm_connector
*connector
)
1069 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1071 DRM_DEBUG_KMS("\n");
1072 intel_panel_fini(&intel_connector
->panel
);
1073 drm_connector_cleanup(connector
);
1077 static void intel_dsi_encoder_destroy(struct drm_encoder
*encoder
)
1079 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1081 if (intel_dsi
->panel
) {
1082 drm_panel_detach(intel_dsi
->panel
);
1083 /* XXX: Logically this call belongs in the panel driver. */
1084 drm_panel_remove(intel_dsi
->panel
);
1087 /* dispose of the gpios */
1088 if (intel_dsi
->gpio_panel
)
1089 gpiod_put(intel_dsi
->gpio_panel
);
1091 intel_encoder_destroy(encoder
);
1094 static const struct drm_encoder_funcs intel_dsi_funcs
= {
1095 .destroy
= intel_dsi_encoder_destroy
,
1098 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs
= {
1099 .get_modes
= intel_dsi_get_modes
,
1100 .mode_valid
= intel_dsi_mode_valid
,
1101 .best_encoder
= intel_best_encoder
,
1104 static const struct drm_connector_funcs intel_dsi_connector_funcs
= {
1105 .dpms
= drm_atomic_helper_connector_dpms
,
1106 .detect
= intel_dsi_detect
,
1107 .destroy
= intel_dsi_connector_destroy
,
1108 .fill_modes
= drm_helper_probe_single_connector_modes
,
1109 .atomic_get_property
= intel_connector_atomic_get_property
,
1110 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
1111 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
1114 void intel_dsi_init(struct drm_device
*dev
)
1116 struct intel_dsi
*intel_dsi
;
1117 struct intel_encoder
*intel_encoder
;
1118 struct drm_encoder
*encoder
;
1119 struct intel_connector
*intel_connector
;
1120 struct drm_connector
*connector
;
1121 struct drm_display_mode
*scan
, *fixed_mode
= NULL
;
1122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1126 DRM_DEBUG_KMS("\n");
1128 /* There is no detection method for MIPI so rely on VBT */
1129 if (!dev_priv
->vbt
.has_mipi
)
1132 if (IS_VALLEYVIEW(dev
)) {
1133 dev_priv
->mipi_mmio_base
= VLV_MIPI_BASE
;
1135 DRM_ERROR("Unsupported Mipi device to reg base");
1139 intel_dsi
= kzalloc(sizeof(*intel_dsi
), GFP_KERNEL
);
1143 intel_connector
= intel_connector_alloc();
1144 if (!intel_connector
) {
1149 intel_encoder
= &intel_dsi
->base
;
1150 encoder
= &intel_encoder
->base
;
1151 intel_dsi
->attached_connector
= intel_connector
;
1153 connector
= &intel_connector
->base
;
1155 drm_encoder_init(dev
, encoder
, &intel_dsi_funcs
, DRM_MODE_ENCODER_DSI
,
1158 /* XXX: very likely not all of these are needed */
1159 intel_encoder
->compute_config
= intel_dsi_compute_config
;
1160 intel_encoder
->pre_pll_enable
= intel_dsi_pre_pll_enable
;
1161 intel_encoder
->pre_enable
= intel_dsi_pre_enable
;
1162 intel_encoder
->enable
= intel_dsi_enable_nop
;
1163 intel_encoder
->disable
= intel_dsi_pre_disable
;
1164 intel_encoder
->post_disable
= intel_dsi_post_disable
;
1165 intel_encoder
->get_hw_state
= intel_dsi_get_hw_state
;
1166 intel_encoder
->get_config
= intel_dsi_get_config
;
1168 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1169 intel_connector
->unregister
= intel_connector_unregister
;
1171 /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
1172 if (dev_priv
->vbt
.dsi
.port
== DVO_PORT_MIPIA
) {
1173 intel_encoder
->crtc_mask
= (1 << PIPE_A
);
1174 intel_dsi
->ports
= (1 << PORT_A
);
1175 } else if (dev_priv
->vbt
.dsi
.port
== DVO_PORT_MIPIC
) {
1176 intel_encoder
->crtc_mask
= (1 << PIPE_B
);
1177 intel_dsi
->ports
= (1 << PORT_C
);
1180 if (dev_priv
->vbt
.dsi
.config
->dual_link
)
1181 intel_dsi
->ports
= ((1 << PORT_A
) | (1 << PORT_C
));
1183 /* Create a DSI host (and a device) for each port. */
1184 for_each_dsi_port(port
, intel_dsi
->ports
) {
1185 struct intel_dsi_host
*host
;
1187 host
= intel_dsi_host_init(intel_dsi
, port
);
1191 intel_dsi
->dsi_hosts
[port
] = host
;
1194 for (i
= 0; i
< ARRAY_SIZE(intel_dsi_drivers
); i
++) {
1195 intel_dsi
->panel
= intel_dsi_drivers
[i
].init(intel_dsi
,
1196 intel_dsi_drivers
[i
].panel_id
);
1197 if (intel_dsi
->panel
)
1201 if (!intel_dsi
->panel
) {
1202 DRM_DEBUG_KMS("no device found\n");
1207 * In case of BYT with CRC PMIC, we need to use GPIO for
1210 if (dev_priv
->vbt
.dsi
.config
->pwm_blc
== PPS_BLC_PMIC
) {
1211 intel_dsi
->gpio_panel
=
1212 gpiod_get(dev
->dev
, "panel", GPIOD_OUT_HIGH
);
1214 if (IS_ERR(intel_dsi
->gpio_panel
)) {
1215 DRM_ERROR("Failed to own gpio for panel control\n");
1216 intel_dsi
->gpio_panel
= NULL
;
1220 intel_encoder
->type
= INTEL_OUTPUT_DSI
;
1221 intel_encoder
->cloneable
= 0;
1222 drm_connector_init(dev
, connector
, &intel_dsi_connector_funcs
,
1223 DRM_MODE_CONNECTOR_DSI
);
1225 drm_connector_helper_add(connector
, &intel_dsi_connector_helper_funcs
);
1227 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
; /*XXX*/
1228 connector
->interlace_allowed
= false;
1229 connector
->doublescan_allowed
= false;
1231 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1233 drm_connector_register(connector
);
1235 drm_panel_attach(intel_dsi
->panel
, connector
);
1237 mutex_lock(&dev
->mode_config
.mutex
);
1238 drm_panel_get_modes(intel_dsi
->panel
);
1239 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
1240 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
1241 fixed_mode
= drm_mode_duplicate(dev
, scan
);
1245 mutex_unlock(&dev
->mode_config
.mutex
);
1248 DRM_DEBUG_KMS("no fixed mode\n");
1252 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
1253 intel_panel_setup_backlight(connector
, INVALID_PIPE
);
1258 drm_encoder_cleanup(&intel_encoder
->base
);
1260 kfree(intel_connector
);