2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Jani Nikula <jani.nikula@intel.com>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_mipi_dsi.h>
33 #include <linux/slab.h>
34 #include <linux/gpio/consumer.h>
36 #include "intel_drv.h"
37 #include "intel_dsi.h"
41 struct drm_panel
* (*init
)(struct intel_dsi
*intel_dsi
, u16 panel_id
);
42 } intel_dsi_drivers
[] = {
44 .panel_id
= MIPI_DSI_GENERIC_PANEL_ID
,
45 .init
= vbt_panel_init
,
49 static void wait_for_dsi_fifo_empty(struct intel_dsi
*intel_dsi
, enum port port
)
51 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
52 struct drm_device
*dev
= encoder
->dev
;
53 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
56 mask
= LP_CTRL_FIFO_EMPTY
| HS_CTRL_FIFO_EMPTY
|
57 LP_DATA_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
;
59 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & mask
) == mask
, 100))
60 DRM_ERROR("DPI FIFOs are not empty\n");
63 static void write_data(struct drm_i915_private
*dev_priv
,
65 const u8
*data
, u32 len
)
69 for (i
= 0; i
< len
; i
+= 4) {
72 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
73 val
|= *data
++ << 8 * j
;
79 static void read_data(struct drm_i915_private
*dev_priv
,
85 for (i
= 0; i
< len
; i
+= 4) {
86 u32 val
= I915_READ(reg
);
88 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
89 *data
++ = val
>> 8 * j
;
93 static ssize_t
intel_dsi_host_transfer(struct mipi_dsi_host
*host
,
94 const struct mipi_dsi_msg
*msg
)
96 struct intel_dsi_host
*intel_dsi_host
= to_intel_dsi_host(host
);
97 struct drm_device
*dev
= intel_dsi_host
->intel_dsi
->base
.base
.dev
;
98 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
99 enum port port
= intel_dsi_host
->port
;
100 struct mipi_dsi_packet packet
;
102 const u8
*header
, *data
;
103 i915_reg_t data_reg
, ctrl_reg
;
104 u32 data_mask
, ctrl_mask
;
106 ret
= mipi_dsi_create_packet(&packet
, msg
);
110 header
= packet
.header
;
111 data
= packet
.payload
;
113 if (msg
->flags
& MIPI_DSI_MSG_USE_LPM
) {
114 data_reg
= MIPI_LP_GEN_DATA(port
);
115 data_mask
= LP_DATA_FIFO_FULL
;
116 ctrl_reg
= MIPI_LP_GEN_CTRL(port
);
117 ctrl_mask
= LP_CTRL_FIFO_FULL
;
119 data_reg
= MIPI_HS_GEN_DATA(port
);
120 data_mask
= HS_DATA_FIFO_FULL
;
121 ctrl_reg
= MIPI_HS_GEN_CTRL(port
);
122 ctrl_mask
= HS_CTRL_FIFO_FULL
;
125 /* note: this is never true for reads */
126 if (packet
.payload_length
) {
128 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & data_mask
) == 0, 50))
129 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
131 write_data(dev_priv
, data_reg
, packet
.payload
,
132 packet
.payload_length
);
136 I915_WRITE(MIPI_INTR_STAT(port
), GEN_READ_DATA_AVAIL
);
139 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & ctrl_mask
) == 0, 50)) {
140 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
143 I915_WRITE(ctrl_reg
, header
[2] << 16 | header
[1] << 8 | header
[0]);
145 /* ->rx_len is set only for reads */
147 data_mask
= GEN_READ_DATA_AVAIL
;
148 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & data_mask
) == data_mask
, 50))
149 DRM_ERROR("Timeout waiting for read data.\n");
151 read_data(dev_priv
, data_reg
, msg
->rx_buf
, msg
->rx_len
);
154 /* XXX: fix for reads and writes */
155 return 4 + packet
.payload_length
;
158 static int intel_dsi_host_attach(struct mipi_dsi_host
*host
,
159 struct mipi_dsi_device
*dsi
)
164 static int intel_dsi_host_detach(struct mipi_dsi_host
*host
,
165 struct mipi_dsi_device
*dsi
)
170 static const struct mipi_dsi_host_ops intel_dsi_host_ops
= {
171 .attach
= intel_dsi_host_attach
,
172 .detach
= intel_dsi_host_detach
,
173 .transfer
= intel_dsi_host_transfer
,
176 static struct intel_dsi_host
*intel_dsi_host_init(struct intel_dsi
*intel_dsi
,
179 struct intel_dsi_host
*host
;
180 struct mipi_dsi_device
*device
;
182 host
= kzalloc(sizeof(*host
), GFP_KERNEL
);
186 host
->base
.ops
= &intel_dsi_host_ops
;
187 host
->intel_dsi
= intel_dsi
;
191 * We should call mipi_dsi_host_register(&host->base) here, but we don't
192 * have a host->dev, and we don't have OF stuff either. So just use the
193 * dsi framework as a library and hope for the best. Create the dsi
194 * devices by ourselves here too. Need to be careful though, because we
195 * don't initialize any of the driver model devices here.
197 device
= kzalloc(sizeof(*device
), GFP_KERNEL
);
203 device
->host
= &host
->base
;
204 host
->device
= device
;
210 * send a video mode command
212 * XXX: commands with data in MIPI_DPI_DATA?
214 static int dpi_send_cmd(struct intel_dsi
*intel_dsi
, u32 cmd
, bool hs
,
217 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
218 struct drm_device
*dev
= encoder
->dev
;
219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
229 I915_WRITE(MIPI_INTR_STAT(port
), SPL_PKT_SENT_INTERRUPT
);
231 /* XXX: old code skips write if control unchanged */
232 if (cmd
== I915_READ(MIPI_DPI_CONTROL(port
)))
233 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd
);
235 I915_WRITE(MIPI_DPI_CONTROL(port
), cmd
);
237 mask
= SPL_PKT_SENT_INTERRUPT
;
238 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & mask
) == mask
, 100))
239 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd
);
244 static void band_gap_reset(struct drm_i915_private
*dev_priv
)
246 mutex_lock(&dev_priv
->sb_lock
);
248 vlv_flisdsi_write(dev_priv
, 0x08, 0x0001);
249 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0005);
250 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0025);
252 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0000);
253 vlv_flisdsi_write(dev_priv
, 0x08, 0x0000);
255 mutex_unlock(&dev_priv
->sb_lock
);
258 static inline bool is_vid_mode(struct intel_dsi
*intel_dsi
)
260 return intel_dsi
->operation_mode
== INTEL_DSI_VIDEO_MODE
;
263 static inline bool is_cmd_mode(struct intel_dsi
*intel_dsi
)
265 return intel_dsi
->operation_mode
== INTEL_DSI_COMMAND_MODE
;
268 static bool intel_dsi_compute_config(struct intel_encoder
*encoder
,
269 struct intel_crtc_state
*pipe_config
)
271 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
272 struct intel_dsi
*intel_dsi
= container_of(encoder
, struct intel_dsi
,
274 struct intel_connector
*intel_connector
= intel_dsi
->attached_connector
;
275 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
276 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
280 pipe_config
->has_dsi_encoder
= true;
283 intel_fixed_panel_mode(fixed_mode
, adjusted_mode
);
285 /* DSI uses short packets for sync events, so clear mode flags for DSI */
286 adjusted_mode
->flags
= 0;
288 if (IS_BROXTON(dev_priv
)) {
289 /* Dual link goes to DSI transcoder A. */
290 if (intel_dsi
->ports
== BIT(PORT_C
))
291 pipe_config
->cpu_transcoder
= TRANSCODER_DSI_C
;
293 pipe_config
->cpu_transcoder
= TRANSCODER_DSI_A
;
299 static void bxt_dsi_device_ready(struct intel_encoder
*encoder
)
301 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
302 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
308 /* Exit Low power state in 4 steps*/
309 for_each_dsi_port(port
, intel_dsi
->ports
) {
311 /* 1. Enable MIPI PHY transparent latch */
312 val
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
313 I915_WRITE(BXT_MIPI_PORT_CTRL(port
), val
| LP_OUTPUT_HOLD
);
314 usleep_range(2000, 2500);
317 val
= I915_READ(MIPI_DEVICE_READY(port
));
318 val
&= ~ULPS_STATE_MASK
;
319 val
|= (ULPS_STATE_ENTER
| DEVICE_READY
);
320 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
324 val
= I915_READ(MIPI_DEVICE_READY(port
));
325 val
&= ~ULPS_STATE_MASK
;
326 val
|= (ULPS_STATE_EXIT
| DEVICE_READY
);
327 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
328 usleep_range(1000, 1500);
330 /* Clear ULPS and set device ready */
331 val
= I915_READ(MIPI_DEVICE_READY(port
));
332 val
&= ~ULPS_STATE_MASK
;
334 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
338 static void vlv_dsi_device_ready(struct intel_encoder
*encoder
)
340 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
341 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
347 mutex_lock(&dev_priv
->sb_lock
);
348 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
349 * needed everytime after power gate */
350 vlv_flisdsi_write(dev_priv
, 0x04, 0x0004);
351 mutex_unlock(&dev_priv
->sb_lock
);
353 /* bandgap reset is needed after everytime we do power gate */
354 band_gap_reset(dev_priv
);
356 for_each_dsi_port(port
, intel_dsi
->ports
) {
358 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_ENTER
);
359 usleep_range(2500, 3000);
361 /* Enable MIPI PHY transparent latch
362 * Common bit for both MIPI Port A & MIPI Port C
363 * No similar bit in MIPI Port C reg
365 val
= I915_READ(MIPI_PORT_CTRL(PORT_A
));
366 I915_WRITE(MIPI_PORT_CTRL(PORT_A
), val
| LP_OUTPUT_HOLD
);
367 usleep_range(1000, 1500);
369 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_EXIT
);
370 usleep_range(2500, 3000);
372 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
);
373 usleep_range(2500, 3000);
377 static void intel_dsi_device_ready(struct intel_encoder
*encoder
)
379 struct drm_device
*dev
= encoder
->base
.dev
;
381 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
382 vlv_dsi_device_ready(encoder
);
383 else if (IS_BROXTON(dev
))
384 bxt_dsi_device_ready(encoder
);
387 static void intel_dsi_port_enable(struct intel_encoder
*encoder
)
389 struct drm_device
*dev
= encoder
->base
.dev
;
390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
391 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
392 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
395 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
398 temp
= I915_READ(VLV_CHICKEN_3
);
399 temp
&= ~PIXEL_OVERLAP_CNT_MASK
|
400 intel_dsi
->pixel_overlap
<<
401 PIXEL_OVERLAP_CNT_SHIFT
;
402 I915_WRITE(VLV_CHICKEN_3
, temp
);
405 for_each_dsi_port(port
, intel_dsi
->ports
) {
406 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
407 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
410 temp
= I915_READ(port_ctrl
);
412 temp
&= ~LANE_CONFIGURATION_MASK
;
413 temp
&= ~DUAL_LINK_MODE_MASK
;
415 if (intel_dsi
->ports
== (BIT(PORT_A
) | BIT(PORT_C
))) {
416 temp
|= (intel_dsi
->dual_link
- 1)
417 << DUAL_LINK_MODE_SHIFT
;
418 temp
|= intel_crtc
->pipe
?
419 LANE_CONFIGURATION_DUAL_LINK_B
:
420 LANE_CONFIGURATION_DUAL_LINK_A
;
422 /* assert ip_tg_enable signal */
423 I915_WRITE(port_ctrl
, temp
| DPI_ENABLE
);
424 POSTING_READ(port_ctrl
);
428 static void intel_dsi_port_disable(struct intel_encoder
*encoder
)
430 struct drm_device
*dev
= encoder
->base
.dev
;
431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
432 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
435 for_each_dsi_port(port
, intel_dsi
->ports
) {
436 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
437 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
440 /* de-assert ip_tg_enable signal */
441 temp
= I915_READ(port_ctrl
);
442 I915_WRITE(port_ctrl
, temp
& ~DPI_ENABLE
);
443 POSTING_READ(port_ctrl
);
447 static void intel_dsi_enable(struct intel_encoder
*encoder
)
449 struct drm_device
*dev
= encoder
->base
.dev
;
450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
451 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
456 if (is_cmd_mode(intel_dsi
)) {
457 for_each_dsi_port(port
, intel_dsi
->ports
)
458 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port
), 8 * 4);
460 msleep(20); /* XXX */
461 for_each_dsi_port(port
, intel_dsi
->ports
)
462 dpi_send_cmd(intel_dsi
, TURN_ON
, false, port
);
465 drm_panel_enable(intel_dsi
->panel
);
467 for_each_dsi_port(port
, intel_dsi
->ports
)
468 wait_for_dsi_fifo_empty(intel_dsi
, port
);
470 intel_dsi_port_enable(encoder
);
473 intel_panel_enable_backlight(intel_dsi
->attached_connector
);
476 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
);
478 static void intel_dsi_pre_enable(struct intel_encoder
*encoder
)
480 struct drm_device
*dev
= encoder
->base
.dev
;
481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
482 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
483 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
484 enum pipe pipe
= intel_crtc
->pipe
;
490 intel_enable_dsi_pll(encoder
);
491 intel_dsi_prepare(encoder
);
493 /* Panel Enable over CRC PMIC */
494 if (intel_dsi
->gpio_panel
)
495 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 1);
497 msleep(intel_dsi
->panel_on_delay
);
499 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
501 * Disable DPOunit clock gating, can stall pipe
502 * and we need DPLL REFA always enabled
504 tmp
= I915_READ(DPLL(pipe
));
505 tmp
|= DPLL_REF_CLK_ENABLE_VLV
;
506 I915_WRITE(DPLL(pipe
), tmp
);
508 /* update the hw state for DPLL */
509 intel_crtc
->config
->dpll_hw_state
.dpll
=
510 DPLL_INTEGRATED_REF_CLK_VLV
|
511 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
513 tmp
= I915_READ(DSPCLK_GATE_D
);
514 tmp
|= DPOUNIT_CLOCK_GATE_DISABLE
;
515 I915_WRITE(DSPCLK_GATE_D
, tmp
);
518 /* put device in ready state */
519 intel_dsi_device_ready(encoder
);
521 drm_panel_prepare(intel_dsi
->panel
);
523 for_each_dsi_port(port
, intel_dsi
->ports
)
524 wait_for_dsi_fifo_empty(intel_dsi
, port
);
526 /* Enable port in pre-enable phase itself because as per hw team
527 * recommendation, port should be enabled befor plane & pipe */
528 intel_dsi_enable(encoder
);
531 static void intel_dsi_enable_nop(struct intel_encoder
*encoder
)
535 /* for DSI port enable has to be done before pipe
536 * and plane enable, so port enable is done in
537 * pre_enable phase itself unlike other encoders
541 static void intel_dsi_pre_disable(struct intel_encoder
*encoder
)
543 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
548 intel_panel_disable_backlight(intel_dsi
->attached_connector
);
550 if (is_vid_mode(intel_dsi
)) {
551 /* Send Shutdown command to the panel in LP mode */
552 for_each_dsi_port(port
, intel_dsi
->ports
)
553 dpi_send_cmd(intel_dsi
, SHUTDOWN
, false, port
);
558 static void intel_dsi_disable(struct intel_encoder
*encoder
)
560 struct drm_device
*dev
= encoder
->base
.dev
;
561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
562 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
568 if (is_vid_mode(intel_dsi
)) {
569 for_each_dsi_port(port
, intel_dsi
->ports
)
570 wait_for_dsi_fifo_empty(intel_dsi
, port
);
572 intel_dsi_port_disable(encoder
);
576 for_each_dsi_port(port
, intel_dsi
->ports
) {
577 /* Panel commands can be sent when clock is in LP11 */
578 I915_WRITE(MIPI_DEVICE_READY(port
), 0x0);
580 intel_dsi_reset_clocks(encoder
, port
);
581 I915_WRITE(MIPI_EOT_DISABLE(port
), CLOCKSTOP
);
583 temp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
584 temp
&= ~VID_MODE_FORMAT_MASK
;
585 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), temp
);
587 I915_WRITE(MIPI_DEVICE_READY(port
), 0x1);
589 /* if disable packets are sent before sending shutdown packet then in
590 * some next enable sequence send turn on packet error is observed */
591 drm_panel_disable(intel_dsi
->panel
);
593 for_each_dsi_port(port
, intel_dsi
->ports
)
594 wait_for_dsi_fifo_empty(intel_dsi
, port
);
597 static void intel_dsi_clear_device_ready(struct intel_encoder
*encoder
)
599 struct drm_device
*dev
= encoder
->base
.dev
;
600 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
601 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
605 for_each_dsi_port(port
, intel_dsi
->ports
) {
606 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
607 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
608 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(PORT_A
);
611 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
613 usleep_range(2000, 2500);
615 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
617 usleep_range(2000, 2500);
619 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
621 usleep_range(2000, 2500);
623 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
624 * only. MIPI Port C has no similar bit for checking
626 if (wait_for(((I915_READ(port_ctrl
) & AFE_LATCHOUT
)
628 DRM_ERROR("DSI LP not going Low\n");
630 /* Disable MIPI PHY transparent latch */
631 val
= I915_READ(port_ctrl
);
632 I915_WRITE(port_ctrl
, val
& ~LP_OUTPUT_HOLD
);
633 usleep_range(1000, 1500);
635 I915_WRITE(MIPI_DEVICE_READY(port
), 0x00);
636 usleep_range(2000, 2500);
639 intel_disable_dsi_pll(encoder
);
642 static void intel_dsi_post_disable(struct intel_encoder
*encoder
)
644 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
645 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
649 intel_dsi_disable(encoder
);
651 intel_dsi_clear_device_ready(encoder
);
653 if (!IS_BROXTON(dev_priv
)) {
656 val
= I915_READ(DSPCLK_GATE_D
);
657 val
&= ~DPOUNIT_CLOCK_GATE_DISABLE
;
658 I915_WRITE(DSPCLK_GATE_D
, val
);
661 drm_panel_unprepare(intel_dsi
->panel
);
663 msleep(intel_dsi
->panel_off_delay
);
664 msleep(intel_dsi
->panel_pwr_cycle_delay
);
666 /* Panel Disable over CRC PMIC */
667 if (intel_dsi
->gpio_panel
)
668 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 0);
671 static bool intel_dsi_get_hw_state(struct intel_encoder
*encoder
,
674 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
675 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
676 struct drm_device
*dev
= encoder
->base
.dev
;
677 enum intel_display_power_domain power_domain
;
683 power_domain
= intel_display_port_power_domain(encoder
);
684 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
687 /* XXX: this only works for one DSI output */
688 for_each_dsi_port(port
, intel_dsi
->ports
) {
689 i915_reg_t ctrl_reg
= IS_BROXTON(dev
) ?
690 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
691 bool enabled
= I915_READ(ctrl_reg
) & DPI_ENABLE
;
693 /* Due to some hardware limitations on BYT, MIPI Port C DPI
694 * Enable bit does not get set. To check whether DSI Port C
695 * was enabled in BIOS, check the Pipe B enable bit
697 if (IS_VALLEYVIEW(dev
) && port
== PORT_C
)
698 enabled
= I915_READ(PIPECONF(PIPE_B
)) & PIPECONF_ENABLE
;
700 /* Try command mode if video mode not enabled */
702 u32 tmp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
703 enabled
= tmp
& CMD_MODE_DATA_WIDTH_MASK
;
709 if (!(I915_READ(MIPI_DEVICE_READY(port
)) & DEVICE_READY
))
712 if (IS_BROXTON(dev_priv
)) {
713 u32 tmp
= I915_READ(MIPI_CTRL(port
));
714 tmp
&= BXT_PIPE_SELECT_MASK
;
715 tmp
>>= BXT_PIPE_SELECT_SHIFT
;
717 if (WARN_ON(tmp
> PIPE_C
))
722 *pipe
= port
== PORT_A
? PIPE_A
: PIPE_B
;
729 intel_display_power_put(dev_priv
, power_domain
);
734 static void intel_dsi_get_config(struct intel_encoder
*encoder
,
735 struct intel_crtc_state
*pipe_config
)
740 pipe_config
->has_dsi_encoder
= true;
743 * DPLL_MD is not used in case of DSI, reading will get some default value
746 pipe_config
->dpll_hw_state
.dpll_md
= 0;
748 pclk
= intel_dsi_get_pclk(encoder
, pipe_config
->pipe_bpp
);
752 pipe_config
->base
.adjusted_mode
.crtc_clock
= pclk
;
753 pipe_config
->port_clock
= pclk
;
756 static enum drm_mode_status
757 intel_dsi_mode_valid(struct drm_connector
*connector
,
758 struct drm_display_mode
*mode
)
760 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
761 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
762 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
766 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
767 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
768 return MODE_NO_DBLESCAN
;
772 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
774 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
776 if (fixed_mode
->clock
> max_dotclk
)
777 return MODE_CLOCK_HIGH
;
783 /* return txclkesc cycles in terms of divider and duration in us */
784 static u16
txclkesc(u32 divider
, unsigned int us
)
787 case ESCAPE_CLOCK_DIVIDER_1
:
790 case ESCAPE_CLOCK_DIVIDER_2
:
792 case ESCAPE_CLOCK_DIVIDER_4
:
797 /* return pixels in terms of txbyteclkhs */
798 static u16
txbyteclkhs(u16 pixels
, int bpp
, int lane_count
,
799 u16 burst_mode_ratio
)
801 return DIV_ROUND_UP(DIV_ROUND_UP(pixels
* bpp
* burst_mode_ratio
,
802 8 * 100), lane_count
);
805 static void set_dsi_timings(struct drm_encoder
*encoder
,
806 const struct drm_display_mode
*adjusted_mode
)
808 struct drm_device
*dev
= encoder
->dev
;
809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
810 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
812 unsigned int bpp
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
813 unsigned int lane_count
= intel_dsi
->lane_count
;
815 u16 hactive
, hfp
, hsync
, hbp
, vfp
, vsync
, vbp
;
817 hactive
= adjusted_mode
->crtc_hdisplay
;
818 hfp
= adjusted_mode
->crtc_hsync_start
- adjusted_mode
->crtc_hdisplay
;
819 hsync
= adjusted_mode
->crtc_hsync_end
- adjusted_mode
->crtc_hsync_start
;
820 hbp
= adjusted_mode
->crtc_htotal
- adjusted_mode
->crtc_hsync_end
;
822 if (intel_dsi
->dual_link
) {
824 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
825 hactive
+= intel_dsi
->pixel_overlap
;
831 vfp
= adjusted_mode
->crtc_vsync_start
- adjusted_mode
->crtc_vdisplay
;
832 vsync
= adjusted_mode
->crtc_vsync_end
- adjusted_mode
->crtc_vsync_start
;
833 vbp
= adjusted_mode
->crtc_vtotal
- adjusted_mode
->crtc_vsync_end
;
835 /* horizontal values are in terms of high speed byte clock */
836 hactive
= txbyteclkhs(hactive
, bpp
, lane_count
,
837 intel_dsi
->burst_mode_ratio
);
838 hfp
= txbyteclkhs(hfp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
839 hsync
= txbyteclkhs(hsync
, bpp
, lane_count
,
840 intel_dsi
->burst_mode_ratio
);
841 hbp
= txbyteclkhs(hbp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
843 for_each_dsi_port(port
, intel_dsi
->ports
) {
844 if (IS_BROXTON(dev
)) {
846 * Program hdisplay and vdisplay on MIPI transcoder.
847 * This is different from calculated hactive and
848 * vactive, as they are calculated per channel basis,
849 * whereas these values should be based on resolution.
851 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port
),
852 adjusted_mode
->crtc_hdisplay
);
853 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port
),
854 adjusted_mode
->crtc_vdisplay
);
855 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port
),
856 adjusted_mode
->crtc_vtotal
);
859 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port
), hactive
);
860 I915_WRITE(MIPI_HFP_COUNT(port
), hfp
);
862 /* meaningful for video mode non-burst sync pulse mode only,
863 * can be zero for non-burst sync events and burst modes */
864 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port
), hsync
);
865 I915_WRITE(MIPI_HBP_COUNT(port
), hbp
);
867 /* vertical values are in terms of lines */
868 I915_WRITE(MIPI_VFP_COUNT(port
), vfp
);
869 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port
), vsync
);
870 I915_WRITE(MIPI_VBP_COUNT(port
), vbp
);
874 static u32
pixel_format_to_reg(enum mipi_dsi_pixel_format fmt
)
877 case MIPI_DSI_FMT_RGB888
:
878 return VID_MODE_FORMAT_RGB888
;
879 case MIPI_DSI_FMT_RGB666
:
880 return VID_MODE_FORMAT_RGB666
;
881 case MIPI_DSI_FMT_RGB666_PACKED
:
882 return VID_MODE_FORMAT_RGB666_PACKED
;
883 case MIPI_DSI_FMT_RGB565
:
884 return VID_MODE_FORMAT_RGB565
;
887 return VID_MODE_FORMAT_RGB666
;
891 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
)
893 struct drm_encoder
*encoder
= &intel_encoder
->base
;
894 struct drm_device
*dev
= encoder
->dev
;
895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
896 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
897 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
898 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
900 unsigned int bpp
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
904 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc
->pipe
));
906 mode_hdisplay
= adjusted_mode
->crtc_hdisplay
;
908 if (intel_dsi
->dual_link
) {
910 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
911 mode_hdisplay
+= intel_dsi
->pixel_overlap
;
914 for_each_dsi_port(port
, intel_dsi
->ports
) {
915 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
917 * escape clock divider, 20MHz, shared for A and C.
918 * device ready must be off when doing this! txclkesc?
920 tmp
= I915_READ(MIPI_CTRL(PORT_A
));
921 tmp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
922 I915_WRITE(MIPI_CTRL(PORT_A
), tmp
|
923 ESCAPE_CLOCK_DIVIDER_1
);
925 /* read request priority is per pipe */
926 tmp
= I915_READ(MIPI_CTRL(port
));
927 tmp
&= ~READ_REQUEST_PRIORITY_MASK
;
928 I915_WRITE(MIPI_CTRL(port
), tmp
|
929 READ_REQUEST_PRIORITY_HIGH
);
930 } else if (IS_BROXTON(dev
)) {
931 enum pipe pipe
= intel_crtc
->pipe
;
933 tmp
= I915_READ(MIPI_CTRL(port
));
934 tmp
&= ~BXT_PIPE_SELECT_MASK
;
936 tmp
|= BXT_PIPE_SELECT(pipe
);
937 I915_WRITE(MIPI_CTRL(port
), tmp
);
940 /* XXX: why here, why like this? handling in irq handler?! */
941 I915_WRITE(MIPI_INTR_STAT(port
), 0xffffffff);
942 I915_WRITE(MIPI_INTR_EN(port
), 0xffffffff);
944 I915_WRITE(MIPI_DPHY_PARAM(port
), intel_dsi
->dphy_reg
);
946 I915_WRITE(MIPI_DPI_RESOLUTION(port
),
947 adjusted_mode
->crtc_vdisplay
<< VERTICAL_ADDRESS_SHIFT
|
948 mode_hdisplay
<< HORIZONTAL_ADDRESS_SHIFT
);
951 set_dsi_timings(encoder
, adjusted_mode
);
953 val
= intel_dsi
->lane_count
<< DATA_LANES_PRG_REG_SHIFT
;
954 if (is_cmd_mode(intel_dsi
)) {
955 val
|= intel_dsi
->channel
<< CMD_MODE_CHANNEL_NUMBER_SHIFT
;
956 val
|= CMD_MODE_DATA_WIDTH_8_BIT
; /* XXX */
958 val
|= intel_dsi
->channel
<< VID_MODE_CHANNEL_NUMBER_SHIFT
;
959 val
|= pixel_format_to_reg(intel_dsi
->pixel_format
);
963 if (intel_dsi
->eotp_pkt
== 0)
965 if (intel_dsi
->clock_stop
)
968 for_each_dsi_port(port
, intel_dsi
->ports
) {
969 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), val
);
971 /* timeouts for recovery. one frame IIUC. if counter expires,
972 * EOT and stop state. */
975 * In burst mode, value greater than one DPI line Time in byte
976 * clock (txbyteclkhs) To timeout this timer 1+ of the above
977 * said value is recommended.
979 * In non-burst mode, Value greater than one DPI frame time in
980 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
981 * said value is recommended.
983 * In DBI only mode, value greater than one DBI frame time in
984 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
985 * said value is recommended.
988 if (is_vid_mode(intel_dsi
) &&
989 intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
990 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
991 txbyteclkhs(adjusted_mode
->crtc_htotal
, bpp
,
992 intel_dsi
->lane_count
,
993 intel_dsi
->burst_mode_ratio
) + 1);
995 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
996 txbyteclkhs(adjusted_mode
->crtc_vtotal
*
997 adjusted_mode
->crtc_htotal
,
998 bpp
, intel_dsi
->lane_count
,
999 intel_dsi
->burst_mode_ratio
) + 1);
1001 I915_WRITE(MIPI_LP_RX_TIMEOUT(port
), intel_dsi
->lp_rx_timeout
);
1002 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port
),
1003 intel_dsi
->turn_arnd_val
);
1004 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port
),
1005 intel_dsi
->rst_timer_val
);
1009 /* in terms of low power clock */
1010 I915_WRITE(MIPI_INIT_COUNT(port
),
1011 txclkesc(intel_dsi
->escape_clk_div
, 100));
1013 if (IS_BROXTON(dev
) && (!intel_dsi
->dual_link
)) {
1015 * BXT spec says write MIPI_INIT_COUNT for
1016 * both the ports, even if only one is
1017 * getting used. So write the other port
1018 * if not in dual link mode.
1020 I915_WRITE(MIPI_INIT_COUNT(port
==
1021 PORT_A
? PORT_C
: PORT_A
),
1022 intel_dsi
->init_count
);
1025 /* recovery disables */
1026 I915_WRITE(MIPI_EOT_DISABLE(port
), tmp
);
1028 /* in terms of low power clock */
1029 I915_WRITE(MIPI_INIT_COUNT(port
), intel_dsi
->init_count
);
1031 /* in terms of txbyteclkhs. actual high to low switch +
1032 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1034 * XXX: write MIPI_STOP_STATE_STALL?
1036 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port
),
1037 intel_dsi
->hs_to_lp_count
);
1039 /* XXX: low power clock equivalence in terms of byte clock.
1040 * the number of byte clocks occupied in one low power clock.
1041 * based on txbyteclkhs and txclkesc.
1042 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1045 I915_WRITE(MIPI_LP_BYTECLK(port
), intel_dsi
->lp_byte_clk
);
1047 /* the bw essential for transmitting 16 long packets containing
1048 * 252 bytes meant for dcs write memory command is programmed in
1049 * this register in terms of byte clocks. based on dsi transfer
1050 * rate and the number of lanes configured the time taken to
1051 * transmit 16 long packets in a dsi stream varies. */
1052 I915_WRITE(MIPI_DBI_BW_CTRL(port
), intel_dsi
->bw_timer
);
1054 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port
),
1055 intel_dsi
->clk_lp_to_hs_count
<< LP_HS_SSW_CNT_SHIFT
|
1056 intel_dsi
->clk_hs_to_lp_count
<< HS_LP_PWR_SW_CNT_SHIFT
);
1058 if (is_vid_mode(intel_dsi
))
1059 /* Some panels might have resolution which is not a
1060 * multiple of 64 like 1366 x 768. Enable RANDOM
1061 * resolution support for such panels by default */
1062 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port
),
1063 intel_dsi
->video_frmt_cfg_bits
|
1064 intel_dsi
->video_mode_format
|
1066 RANDOM_DPI_DISPLAY_RESOLUTION
);
1070 static enum drm_connector_status
1071 intel_dsi_detect(struct drm_connector
*connector
, bool force
)
1073 return connector_status_connected
;
1076 static int intel_dsi_get_modes(struct drm_connector
*connector
)
1078 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1079 struct drm_display_mode
*mode
;
1081 DRM_DEBUG_KMS("\n");
1083 if (!intel_connector
->panel
.fixed_mode
) {
1084 DRM_DEBUG_KMS("no fixed mode\n");
1088 mode
= drm_mode_duplicate(connector
->dev
,
1089 intel_connector
->panel
.fixed_mode
);
1091 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1095 drm_mode_probed_add(connector
, mode
);
1099 static void intel_dsi_connector_destroy(struct drm_connector
*connector
)
1101 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1103 DRM_DEBUG_KMS("\n");
1104 intel_panel_fini(&intel_connector
->panel
);
1105 drm_connector_cleanup(connector
);
1109 static void intel_dsi_encoder_destroy(struct drm_encoder
*encoder
)
1111 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1113 if (intel_dsi
->panel
) {
1114 drm_panel_detach(intel_dsi
->panel
);
1115 /* XXX: Logically this call belongs in the panel driver. */
1116 drm_panel_remove(intel_dsi
->panel
);
1119 /* dispose of the gpios */
1120 if (intel_dsi
->gpio_panel
)
1121 gpiod_put(intel_dsi
->gpio_panel
);
1123 intel_encoder_destroy(encoder
);
1126 static const struct drm_encoder_funcs intel_dsi_funcs
= {
1127 .destroy
= intel_dsi_encoder_destroy
,
1130 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs
= {
1131 .get_modes
= intel_dsi_get_modes
,
1132 .mode_valid
= intel_dsi_mode_valid
,
1133 .best_encoder
= intel_best_encoder
,
1136 static const struct drm_connector_funcs intel_dsi_connector_funcs
= {
1137 .dpms
= drm_atomic_helper_connector_dpms
,
1138 .detect
= intel_dsi_detect
,
1139 .destroy
= intel_dsi_connector_destroy
,
1140 .fill_modes
= drm_helper_probe_single_connector_modes
,
1141 .atomic_get_property
= intel_connector_atomic_get_property
,
1142 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
1143 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
1146 void intel_dsi_init(struct drm_device
*dev
)
1148 struct intel_dsi
*intel_dsi
;
1149 struct intel_encoder
*intel_encoder
;
1150 struct drm_encoder
*encoder
;
1151 struct intel_connector
*intel_connector
;
1152 struct drm_connector
*connector
;
1153 struct drm_display_mode
*scan
, *fixed_mode
= NULL
;
1154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1158 DRM_DEBUG_KMS("\n");
1160 /* There is no detection method for MIPI so rely on VBT */
1161 if (!intel_bios_is_dsi_present(dev_priv
, &port
))
1164 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1165 dev_priv
->mipi_mmio_base
= VLV_MIPI_BASE
;
1167 DRM_ERROR("Unsupported Mipi device to reg base");
1171 intel_dsi
= kzalloc(sizeof(*intel_dsi
), GFP_KERNEL
);
1175 intel_connector
= intel_connector_alloc();
1176 if (!intel_connector
) {
1181 intel_encoder
= &intel_dsi
->base
;
1182 encoder
= &intel_encoder
->base
;
1183 intel_dsi
->attached_connector
= intel_connector
;
1185 connector
= &intel_connector
->base
;
1187 drm_encoder_init(dev
, encoder
, &intel_dsi_funcs
, DRM_MODE_ENCODER_DSI
,
1190 intel_encoder
->compute_config
= intel_dsi_compute_config
;
1191 intel_encoder
->pre_enable
= intel_dsi_pre_enable
;
1192 intel_encoder
->enable
= intel_dsi_enable_nop
;
1193 intel_encoder
->disable
= intel_dsi_pre_disable
;
1194 intel_encoder
->post_disable
= intel_dsi_post_disable
;
1195 intel_encoder
->get_hw_state
= intel_dsi_get_hw_state
;
1196 intel_encoder
->get_config
= intel_dsi_get_config
;
1198 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1199 intel_connector
->unregister
= intel_connector_unregister
;
1201 /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
1203 intel_encoder
->crtc_mask
= BIT(PIPE_A
);
1205 intel_encoder
->crtc_mask
= BIT(PIPE_B
);
1207 if (dev_priv
->vbt
.dsi
.config
->dual_link
)
1208 intel_dsi
->ports
= BIT(PORT_A
) | BIT(PORT_C
);
1210 intel_dsi
->ports
= BIT(port
);
1212 /* Create a DSI host (and a device) for each port. */
1213 for_each_dsi_port(port
, intel_dsi
->ports
) {
1214 struct intel_dsi_host
*host
;
1216 host
= intel_dsi_host_init(intel_dsi
, port
);
1220 intel_dsi
->dsi_hosts
[port
] = host
;
1223 for (i
= 0; i
< ARRAY_SIZE(intel_dsi_drivers
); i
++) {
1224 intel_dsi
->panel
= intel_dsi_drivers
[i
].init(intel_dsi
,
1225 intel_dsi_drivers
[i
].panel_id
);
1226 if (intel_dsi
->panel
)
1230 if (!intel_dsi
->panel
) {
1231 DRM_DEBUG_KMS("no device found\n");
1236 * In case of BYT with CRC PMIC, we need to use GPIO for
1239 if (dev_priv
->vbt
.dsi
.config
->pwm_blc
== PPS_BLC_PMIC
) {
1240 intel_dsi
->gpio_panel
=
1241 gpiod_get(dev
->dev
, "panel", GPIOD_OUT_HIGH
);
1243 if (IS_ERR(intel_dsi
->gpio_panel
)) {
1244 DRM_ERROR("Failed to own gpio for panel control\n");
1245 intel_dsi
->gpio_panel
= NULL
;
1249 intel_encoder
->type
= INTEL_OUTPUT_DSI
;
1250 intel_encoder
->cloneable
= 0;
1251 drm_connector_init(dev
, connector
, &intel_dsi_connector_funcs
,
1252 DRM_MODE_CONNECTOR_DSI
);
1254 drm_connector_helper_add(connector
, &intel_dsi_connector_helper_funcs
);
1256 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
; /*XXX*/
1257 connector
->interlace_allowed
= false;
1258 connector
->doublescan_allowed
= false;
1260 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1262 drm_connector_register(connector
);
1264 drm_panel_attach(intel_dsi
->panel
, connector
);
1266 mutex_lock(&dev
->mode_config
.mutex
);
1267 drm_panel_get_modes(intel_dsi
->panel
);
1268 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
1269 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
1270 fixed_mode
= drm_mode_duplicate(dev
, scan
);
1274 mutex_unlock(&dev
->mode_config
.mutex
);
1277 DRM_DEBUG_KMS("no fixed mode\n");
1281 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
1282 intel_panel_setup_backlight(connector
, INVALID_PIPE
);
1287 drm_encoder_cleanup(&intel_encoder
->base
);
1289 kfree(intel_connector
);