2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Jani Nikula <jani.nikula@intel.com>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_mipi_dsi.h>
33 #include <linux/slab.h>
35 #include "intel_drv.h"
36 #include "intel_dsi.h"
40 struct drm_panel
* (*init
)(struct intel_dsi
*intel_dsi
, u16 panel_id
);
41 } intel_dsi_drivers
[] = {
43 .panel_id
= MIPI_DSI_GENERIC_PANEL_ID
,
44 .init
= vbt_panel_init
,
48 static void wait_for_dsi_fifo_empty(struct intel_dsi
*intel_dsi
, enum port port
)
50 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
51 struct drm_device
*dev
= encoder
->dev
;
52 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
55 mask
= LP_CTRL_FIFO_EMPTY
| HS_CTRL_FIFO_EMPTY
|
56 LP_DATA_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
;
58 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & mask
) == mask
, 100))
59 DRM_ERROR("DPI FIFOs are not empty\n");
62 static void write_data(struct drm_i915_private
*dev_priv
, u32 reg
,
63 const u8
*data
, u32 len
)
67 for (i
= 0; i
< len
; i
+= 4) {
70 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
71 val
|= *data
++ << 8 * j
;
77 static void read_data(struct drm_i915_private
*dev_priv
, u32 reg
,
82 for (i
= 0; i
< len
; i
+= 4) {
83 u32 val
= I915_READ(reg
);
85 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
86 *data
++ = val
>> 8 * j
;
90 static ssize_t
intel_dsi_host_transfer(struct mipi_dsi_host
*host
,
91 const struct mipi_dsi_msg
*msg
)
93 struct intel_dsi_host
*intel_dsi_host
= to_intel_dsi_host(host
);
94 struct drm_device
*dev
= intel_dsi_host
->intel_dsi
->base
.base
.dev
;
95 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
96 enum port port
= intel_dsi_host
->port
;
97 struct mipi_dsi_packet packet
;
99 const u8
*header
, *data
;
100 u32 data_reg
, data_mask
, ctrl_reg
, ctrl_mask
;
102 ret
= mipi_dsi_create_packet(&packet
, msg
);
106 header
= packet
.header
;
107 data
= packet
.payload
;
109 if (msg
->flags
& MIPI_DSI_MSG_USE_LPM
) {
110 data_reg
= MIPI_LP_GEN_DATA(port
);
111 data_mask
= LP_DATA_FIFO_FULL
;
112 ctrl_reg
= MIPI_LP_GEN_CTRL(port
);
113 ctrl_mask
= LP_CTRL_FIFO_FULL
;
115 data_reg
= MIPI_HS_GEN_DATA(port
);
116 data_mask
= HS_DATA_FIFO_FULL
;
117 ctrl_reg
= MIPI_HS_GEN_CTRL(port
);
118 ctrl_mask
= HS_CTRL_FIFO_FULL
;
121 /* note: this is never true for reads */
122 if (packet
.payload_length
) {
124 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & data_mask
) == 0, 50))
125 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
127 write_data(dev_priv
, data_reg
, packet
.payload
,
128 packet
.payload_length
);
132 I915_WRITE(MIPI_INTR_STAT(port
), GEN_READ_DATA_AVAIL
);
135 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & ctrl_mask
) == 0, 50)) {
136 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
139 I915_WRITE(ctrl_reg
, header
[2] << 16 | header
[1] << 8 | header
[0]);
141 /* ->rx_len is set only for reads */
143 data_mask
= GEN_READ_DATA_AVAIL
;
144 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & data_mask
) == data_mask
, 50))
145 DRM_ERROR("Timeout waiting for read data.\n");
147 read_data(dev_priv
, data_reg
, msg
->rx_buf
, msg
->rx_len
);
150 /* XXX: fix for reads and writes */
151 return 4 + packet
.payload_length
;
154 static int intel_dsi_host_attach(struct mipi_dsi_host
*host
,
155 struct mipi_dsi_device
*dsi
)
160 static int intel_dsi_host_detach(struct mipi_dsi_host
*host
,
161 struct mipi_dsi_device
*dsi
)
166 static const struct mipi_dsi_host_ops intel_dsi_host_ops
= {
167 .attach
= intel_dsi_host_attach
,
168 .detach
= intel_dsi_host_detach
,
169 .transfer
= intel_dsi_host_transfer
,
172 static struct intel_dsi_host
*intel_dsi_host_init(struct intel_dsi
*intel_dsi
,
175 struct intel_dsi_host
*host
;
176 struct mipi_dsi_device
*device
;
178 host
= kzalloc(sizeof(*host
), GFP_KERNEL
);
182 host
->base
.ops
= &intel_dsi_host_ops
;
183 host
->intel_dsi
= intel_dsi
;
187 * We should call mipi_dsi_host_register(&host->base) here, but we don't
188 * have a host->dev, and we don't have OF stuff either. So just use the
189 * dsi framework as a library and hope for the best. Create the dsi
190 * devices by ourselves here too. Need to be careful though, because we
191 * don't initialize any of the driver model devices here.
193 device
= kzalloc(sizeof(*device
), GFP_KERNEL
);
199 device
->host
= &host
->base
;
200 host
->device
= device
;
206 * send a video mode command
208 * XXX: commands with data in MIPI_DPI_DATA?
210 static int dpi_send_cmd(struct intel_dsi
*intel_dsi
, u32 cmd
, bool hs
,
213 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
214 struct drm_device
*dev
= encoder
->dev
;
215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
225 I915_WRITE(MIPI_INTR_STAT(port
), SPL_PKT_SENT_INTERRUPT
);
227 /* XXX: old code skips write if control unchanged */
228 if (cmd
== I915_READ(MIPI_DPI_CONTROL(port
)))
229 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd
);
231 I915_WRITE(MIPI_DPI_CONTROL(port
), cmd
);
233 mask
= SPL_PKT_SENT_INTERRUPT
;
234 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & mask
) == mask
, 100))
235 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd
);
240 static void band_gap_reset(struct drm_i915_private
*dev_priv
)
242 mutex_lock(&dev_priv
->sb_lock
);
244 vlv_flisdsi_write(dev_priv
, 0x08, 0x0001);
245 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0005);
246 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0025);
248 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0000);
249 vlv_flisdsi_write(dev_priv
, 0x08, 0x0000);
251 mutex_unlock(&dev_priv
->sb_lock
);
254 static inline bool is_vid_mode(struct intel_dsi
*intel_dsi
)
256 return intel_dsi
->operation_mode
== INTEL_DSI_VIDEO_MODE
;
259 static inline bool is_cmd_mode(struct intel_dsi
*intel_dsi
)
261 return intel_dsi
->operation_mode
== INTEL_DSI_COMMAND_MODE
;
264 static bool intel_dsi_compute_config(struct intel_encoder
*encoder
,
265 struct intel_crtc_state
*config
)
267 struct intel_dsi
*intel_dsi
= container_of(encoder
, struct intel_dsi
,
269 struct intel_connector
*intel_connector
= intel_dsi
->attached_connector
;
270 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
271 struct drm_display_mode
*adjusted_mode
= &config
->base
.adjusted_mode
;
276 intel_fixed_panel_mode(fixed_mode
, adjusted_mode
);
278 /* DSI uses short packets for sync events, so clear mode flags for DSI */
279 adjusted_mode
->flags
= 0;
284 static void intel_dsi_port_enable(struct intel_encoder
*encoder
)
286 struct drm_device
*dev
= encoder
->base
.dev
;
287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
288 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
289 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
293 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
294 temp
= I915_READ(VLV_CHICKEN_3
);
295 temp
&= ~PIXEL_OVERLAP_CNT_MASK
|
296 intel_dsi
->pixel_overlap
<<
297 PIXEL_OVERLAP_CNT_SHIFT
;
298 I915_WRITE(VLV_CHICKEN_3
, temp
);
301 for_each_dsi_port(port
, intel_dsi
->ports
) {
302 temp
= I915_READ(MIPI_PORT_CTRL(port
));
303 temp
&= ~LANE_CONFIGURATION_MASK
;
304 temp
&= ~DUAL_LINK_MODE_MASK
;
306 if (intel_dsi
->ports
== ((1 << PORT_A
) | (1 << PORT_C
))) {
307 temp
|= (intel_dsi
->dual_link
- 1)
308 << DUAL_LINK_MODE_SHIFT
;
309 temp
|= intel_crtc
->pipe
?
310 LANE_CONFIGURATION_DUAL_LINK_B
:
311 LANE_CONFIGURATION_DUAL_LINK_A
;
313 /* assert ip_tg_enable signal */
314 I915_WRITE(MIPI_PORT_CTRL(port
), temp
| DPI_ENABLE
);
315 POSTING_READ(MIPI_PORT_CTRL(port
));
319 static void intel_dsi_port_disable(struct intel_encoder
*encoder
)
321 struct drm_device
*dev
= encoder
->base
.dev
;
322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
323 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
327 for_each_dsi_port(port
, intel_dsi
->ports
) {
328 /* de-assert ip_tg_enable signal */
329 temp
= I915_READ(MIPI_PORT_CTRL(port
));
330 I915_WRITE(MIPI_PORT_CTRL(port
), temp
& ~DPI_ENABLE
);
331 POSTING_READ(MIPI_PORT_CTRL(port
));
335 static void intel_dsi_device_ready(struct intel_encoder
*encoder
)
337 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
338 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
344 mutex_lock(&dev_priv
->sb_lock
);
345 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
346 * needed everytime after power gate */
347 vlv_flisdsi_write(dev_priv
, 0x04, 0x0004);
348 mutex_unlock(&dev_priv
->sb_lock
);
350 /* bandgap reset is needed after everytime we do power gate */
351 band_gap_reset(dev_priv
);
353 for_each_dsi_port(port
, intel_dsi
->ports
) {
355 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_ENTER
);
356 usleep_range(2500, 3000);
358 /* Enable MIPI PHY transparent latch
359 * Common bit for both MIPI Port A & MIPI Port C
360 * No similar bit in MIPI Port C reg
362 val
= I915_READ(MIPI_PORT_CTRL(PORT_A
));
363 I915_WRITE(MIPI_PORT_CTRL(PORT_A
), val
| LP_OUTPUT_HOLD
);
364 usleep_range(1000, 1500);
366 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_EXIT
);
367 usleep_range(2500, 3000);
369 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
);
370 usleep_range(2500, 3000);
374 static void intel_dsi_enable(struct intel_encoder
*encoder
)
376 struct drm_device
*dev
= encoder
->base
.dev
;
377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
378 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
383 if (is_cmd_mode(intel_dsi
)) {
384 for_each_dsi_port(port
, intel_dsi
->ports
)
385 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port
), 8 * 4);
387 msleep(20); /* XXX */
388 for_each_dsi_port(port
, intel_dsi
->ports
)
389 dpi_send_cmd(intel_dsi
, TURN_ON
, false, port
);
392 drm_panel_enable(intel_dsi
->panel
);
394 for_each_dsi_port(port
, intel_dsi
->ports
)
395 wait_for_dsi_fifo_empty(intel_dsi
, port
);
397 intel_dsi_port_enable(encoder
);
401 static void intel_dsi_pre_enable(struct intel_encoder
*encoder
)
403 struct drm_device
*dev
= encoder
->base
.dev
;
404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
405 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
406 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
407 enum pipe pipe
= intel_crtc
->pipe
;
413 /* Disable DPOunit clock gating, can stall pipe
414 * and we need DPLL REFA always enabled */
415 tmp
= I915_READ(DPLL(pipe
));
416 tmp
|= DPLL_REF_CLK_ENABLE_VLV
;
417 I915_WRITE(DPLL(pipe
), tmp
);
419 /* update the hw state for DPLL */
420 intel_crtc
->config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
421 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
423 tmp
= I915_READ(DSPCLK_GATE_D
);
424 tmp
|= DPOUNIT_CLOCK_GATE_DISABLE
;
425 I915_WRITE(DSPCLK_GATE_D
, tmp
);
427 /* put device in ready state */
428 intel_dsi_device_ready(encoder
);
430 msleep(intel_dsi
->panel_on_delay
);
432 drm_panel_prepare(intel_dsi
->panel
);
434 for_each_dsi_port(port
, intel_dsi
->ports
)
435 wait_for_dsi_fifo_empty(intel_dsi
, port
);
437 /* Enable port in pre-enable phase itself because as per hw team
438 * recommendation, port should be enabled befor plane & pipe */
439 intel_dsi_enable(encoder
);
442 static void intel_dsi_enable_nop(struct intel_encoder
*encoder
)
446 /* for DSI port enable has to be done before pipe
447 * and plane enable, so port enable is done in
448 * pre_enable phase itself unlike other encoders
452 static void intel_dsi_pre_disable(struct intel_encoder
*encoder
)
454 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
459 if (is_vid_mode(intel_dsi
)) {
460 /* Send Shutdown command to the panel in LP mode */
461 for_each_dsi_port(port
, intel_dsi
->ports
)
462 dpi_send_cmd(intel_dsi
, SHUTDOWN
, false, port
);
467 static void intel_dsi_disable(struct intel_encoder
*encoder
)
469 struct drm_device
*dev
= encoder
->base
.dev
;
470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
471 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
477 if (is_vid_mode(intel_dsi
)) {
478 for_each_dsi_port(port
, intel_dsi
->ports
)
479 wait_for_dsi_fifo_empty(intel_dsi
, port
);
481 intel_dsi_port_disable(encoder
);
485 for_each_dsi_port(port
, intel_dsi
->ports
) {
486 /* Panel commands can be sent when clock is in LP11 */
487 I915_WRITE(MIPI_DEVICE_READY(port
), 0x0);
489 temp
= I915_READ(MIPI_CTRL(port
));
490 temp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
491 I915_WRITE(MIPI_CTRL(port
), temp
|
492 intel_dsi
->escape_clk_div
<<
493 ESCAPE_CLOCK_DIVIDER_SHIFT
);
495 I915_WRITE(MIPI_EOT_DISABLE(port
), CLOCKSTOP
);
497 temp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
498 temp
&= ~VID_MODE_FORMAT_MASK
;
499 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), temp
);
501 I915_WRITE(MIPI_DEVICE_READY(port
), 0x1);
503 /* if disable packets are sent before sending shutdown packet then in
504 * some next enable sequence send turn on packet error is observed */
505 drm_panel_disable(intel_dsi
->panel
);
507 for_each_dsi_port(port
, intel_dsi
->ports
)
508 wait_for_dsi_fifo_empty(intel_dsi
, port
);
511 static void intel_dsi_clear_device_ready(struct intel_encoder
*encoder
)
513 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
514 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
519 for_each_dsi_port(port
, intel_dsi
->ports
) {
521 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
523 usleep_range(2000, 2500);
525 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
527 usleep_range(2000, 2500);
529 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
531 usleep_range(2000, 2500);
533 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
534 * only. MIPI Port C has no similar bit for checking
536 if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A
)) & AFE_LATCHOUT
)
538 DRM_ERROR("DSI LP not going Low\n");
540 /* Disable MIPI PHY transparent latch
541 * Common bit for both MIPI Port A & MIPI Port C
543 val
= I915_READ(MIPI_PORT_CTRL(PORT_A
));
544 I915_WRITE(MIPI_PORT_CTRL(PORT_A
), val
& ~LP_OUTPUT_HOLD
);
545 usleep_range(1000, 1500);
547 I915_WRITE(MIPI_DEVICE_READY(port
), 0x00);
548 usleep_range(2000, 2500);
551 vlv_disable_dsi_pll(encoder
);
554 static void intel_dsi_post_disable(struct intel_encoder
*encoder
)
556 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
557 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
562 intel_dsi_disable(encoder
);
564 intel_dsi_clear_device_ready(encoder
);
566 val
= I915_READ(DSPCLK_GATE_D
);
567 val
&= ~DPOUNIT_CLOCK_GATE_DISABLE
;
568 I915_WRITE(DSPCLK_GATE_D
, val
);
570 drm_panel_unprepare(intel_dsi
->panel
);
572 msleep(intel_dsi
->panel_off_delay
);
573 msleep(intel_dsi
->panel_pwr_cycle_delay
);
576 static bool intel_dsi_get_hw_state(struct intel_encoder
*encoder
,
579 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
580 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
581 struct drm_device
*dev
= encoder
->base
.dev
;
582 enum intel_display_power_domain power_domain
;
583 u32 dpi_enabled
, func
;
588 power_domain
= intel_display_port_power_domain(encoder
);
589 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
592 /* XXX: this only works for one DSI output */
593 for_each_dsi_port(port
, intel_dsi
->ports
) {
594 func
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
595 dpi_enabled
= I915_READ(MIPI_PORT_CTRL(port
)) &
598 /* Due to some hardware limitations on BYT, MIPI Port C DPI
599 * Enable bit does not get set. To check whether DSI Port C
600 * was enabled in BIOS, check the Pipe B enable bit
602 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
604 dpi_enabled
= I915_READ(PIPECONF(PIPE_B
)) &
607 if (dpi_enabled
|| (func
& CMD_MODE_DATA_WIDTH_MASK
)) {
608 if (I915_READ(MIPI_DEVICE_READY(port
)) & DEVICE_READY
) {
609 *pipe
= port
== PORT_A
? PIPE_A
: PIPE_B
;
618 static void intel_dsi_get_config(struct intel_encoder
*encoder
,
619 struct intel_crtc_state
*pipe_config
)
625 * DPLL_MD is not used in case of DSI, reading will get some default value
628 pipe_config
->dpll_hw_state
.dpll_md
= 0;
630 pclk
= vlv_get_dsi_pclk(encoder
, pipe_config
->pipe_bpp
);
634 pipe_config
->base
.adjusted_mode
.crtc_clock
= pclk
;
635 pipe_config
->port_clock
= pclk
;
638 static enum drm_mode_status
639 intel_dsi_mode_valid(struct drm_connector
*connector
,
640 struct drm_display_mode
*mode
)
642 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
643 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
647 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
648 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
649 return MODE_NO_DBLESCAN
;
653 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
655 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
662 /* return txclkesc cycles in terms of divider and duration in us */
663 static u16
txclkesc(u32 divider
, unsigned int us
)
666 case ESCAPE_CLOCK_DIVIDER_1
:
669 case ESCAPE_CLOCK_DIVIDER_2
:
671 case ESCAPE_CLOCK_DIVIDER_4
:
676 /* return pixels in terms of txbyteclkhs */
677 static u16
txbyteclkhs(u16 pixels
, int bpp
, int lane_count
,
678 u16 burst_mode_ratio
)
680 return DIV_ROUND_UP(DIV_ROUND_UP(pixels
* bpp
* burst_mode_ratio
,
681 8 * 100), lane_count
);
684 static void set_dsi_timings(struct drm_encoder
*encoder
,
685 const struct drm_display_mode
*mode
)
687 struct drm_device
*dev
= encoder
->dev
;
688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
689 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
690 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
692 unsigned int bpp
= intel_crtc
->config
->pipe_bpp
;
693 unsigned int lane_count
= intel_dsi
->lane_count
;
695 u16 hactive
, hfp
, hsync
, hbp
, vfp
, vsync
, vbp
;
697 hactive
= mode
->hdisplay
;
698 hfp
= mode
->hsync_start
- mode
->hdisplay
;
699 hsync
= mode
->hsync_end
- mode
->hsync_start
;
700 hbp
= mode
->htotal
- mode
->hsync_end
;
702 if (intel_dsi
->dual_link
) {
704 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
705 hactive
+= intel_dsi
->pixel_overlap
;
711 vfp
= mode
->vsync_start
- mode
->vdisplay
;
712 vsync
= mode
->vsync_end
- mode
->vsync_start
;
713 vbp
= mode
->vtotal
- mode
->vsync_end
;
715 /* horizontal values are in terms of high speed byte clock */
716 hactive
= txbyteclkhs(hactive
, bpp
, lane_count
,
717 intel_dsi
->burst_mode_ratio
);
718 hfp
= txbyteclkhs(hfp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
719 hsync
= txbyteclkhs(hsync
, bpp
, lane_count
,
720 intel_dsi
->burst_mode_ratio
);
721 hbp
= txbyteclkhs(hbp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
723 for_each_dsi_port(port
, intel_dsi
->ports
) {
724 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port
), hactive
);
725 I915_WRITE(MIPI_HFP_COUNT(port
), hfp
);
727 /* meaningful for video mode non-burst sync pulse mode only,
728 * can be zero for non-burst sync events and burst modes */
729 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port
), hsync
);
730 I915_WRITE(MIPI_HBP_COUNT(port
), hbp
);
732 /* vertical values are in terms of lines */
733 I915_WRITE(MIPI_VFP_COUNT(port
), vfp
);
734 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port
), vsync
);
735 I915_WRITE(MIPI_VBP_COUNT(port
), vbp
);
739 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
)
741 struct drm_encoder
*encoder
= &intel_encoder
->base
;
742 struct drm_device
*dev
= encoder
->dev
;
743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
744 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
745 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
746 struct drm_display_mode
*adjusted_mode
=
747 &intel_crtc
->config
->base
.adjusted_mode
;
749 unsigned int bpp
= intel_crtc
->config
->pipe_bpp
;
753 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc
->pipe
));
755 mode_hdisplay
= adjusted_mode
->hdisplay
;
757 if (intel_dsi
->dual_link
) {
759 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
760 mode_hdisplay
+= intel_dsi
->pixel_overlap
;
763 for_each_dsi_port(port
, intel_dsi
->ports
) {
764 /* escape clock divider, 20MHz, shared for A and C.
765 * device ready must be off when doing this! txclkesc? */
766 tmp
= I915_READ(MIPI_CTRL(PORT_A
));
767 tmp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
768 I915_WRITE(MIPI_CTRL(PORT_A
), tmp
| ESCAPE_CLOCK_DIVIDER_1
);
770 /* read request priority is per pipe */
771 tmp
= I915_READ(MIPI_CTRL(port
));
772 tmp
&= ~READ_REQUEST_PRIORITY_MASK
;
773 I915_WRITE(MIPI_CTRL(port
), tmp
| READ_REQUEST_PRIORITY_HIGH
);
775 /* XXX: why here, why like this? handling in irq handler?! */
776 I915_WRITE(MIPI_INTR_STAT(port
), 0xffffffff);
777 I915_WRITE(MIPI_INTR_EN(port
), 0xffffffff);
779 I915_WRITE(MIPI_DPHY_PARAM(port
), intel_dsi
->dphy_reg
);
781 I915_WRITE(MIPI_DPI_RESOLUTION(port
),
782 adjusted_mode
->vdisplay
<< VERTICAL_ADDRESS_SHIFT
|
783 mode_hdisplay
<< HORIZONTAL_ADDRESS_SHIFT
);
786 set_dsi_timings(encoder
, adjusted_mode
);
788 val
= intel_dsi
->lane_count
<< DATA_LANES_PRG_REG_SHIFT
;
789 if (is_cmd_mode(intel_dsi
)) {
790 val
|= intel_dsi
->channel
<< CMD_MODE_CHANNEL_NUMBER_SHIFT
;
791 val
|= CMD_MODE_DATA_WIDTH_8_BIT
; /* XXX */
793 val
|= intel_dsi
->channel
<< VID_MODE_CHANNEL_NUMBER_SHIFT
;
795 /* XXX: cross-check bpp vs. pixel format? */
796 val
|= intel_dsi
->pixel_format
;
800 if (intel_dsi
->eotp_pkt
== 0)
802 if (intel_dsi
->clock_stop
)
805 for_each_dsi_port(port
, intel_dsi
->ports
) {
806 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), val
);
808 /* timeouts for recovery. one frame IIUC. if counter expires,
809 * EOT and stop state. */
812 * In burst mode, value greater than one DPI line Time in byte
813 * clock (txbyteclkhs) To timeout this timer 1+ of the above
814 * said value is recommended.
816 * In non-burst mode, Value greater than one DPI frame time in
817 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
818 * said value is recommended.
820 * In DBI only mode, value greater than one DBI frame time in
821 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
822 * said value is recommended.
825 if (is_vid_mode(intel_dsi
) &&
826 intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
827 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
828 txbyteclkhs(adjusted_mode
->htotal
, bpp
,
829 intel_dsi
->lane_count
,
830 intel_dsi
->burst_mode_ratio
) + 1);
832 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
833 txbyteclkhs(adjusted_mode
->vtotal
*
834 adjusted_mode
->htotal
,
835 bpp
, intel_dsi
->lane_count
,
836 intel_dsi
->burst_mode_ratio
) + 1);
838 I915_WRITE(MIPI_LP_RX_TIMEOUT(port
), intel_dsi
->lp_rx_timeout
);
839 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port
),
840 intel_dsi
->turn_arnd_val
);
841 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port
),
842 intel_dsi
->rst_timer_val
);
846 /* in terms of low power clock */
847 I915_WRITE(MIPI_INIT_COUNT(port
),
848 txclkesc(intel_dsi
->escape_clk_div
, 100));
851 /* recovery disables */
852 I915_WRITE(MIPI_EOT_DISABLE(port
), tmp
);
854 /* in terms of low power clock */
855 I915_WRITE(MIPI_INIT_COUNT(port
), intel_dsi
->init_count
);
857 /* in terms of txbyteclkhs. actual high to low switch +
858 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
860 * XXX: write MIPI_STOP_STATE_STALL?
862 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port
),
863 intel_dsi
->hs_to_lp_count
);
865 /* XXX: low power clock equivalence in terms of byte clock.
866 * the number of byte clocks occupied in one low power clock.
867 * based on txbyteclkhs and txclkesc.
868 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
871 I915_WRITE(MIPI_LP_BYTECLK(port
), intel_dsi
->lp_byte_clk
);
873 /* the bw essential for transmitting 16 long packets containing
874 * 252 bytes meant for dcs write memory command is programmed in
875 * this register in terms of byte clocks. based on dsi transfer
876 * rate and the number of lanes configured the time taken to
877 * transmit 16 long packets in a dsi stream varies. */
878 I915_WRITE(MIPI_DBI_BW_CTRL(port
), intel_dsi
->bw_timer
);
880 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port
),
881 intel_dsi
->clk_lp_to_hs_count
<< LP_HS_SSW_CNT_SHIFT
|
882 intel_dsi
->clk_hs_to_lp_count
<< HS_LP_PWR_SW_CNT_SHIFT
);
884 if (is_vid_mode(intel_dsi
))
885 /* Some panels might have resolution which is not a
886 * multiple of 64 like 1366 x 768. Enable RANDOM
887 * resolution support for such panels by default */
888 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port
),
889 intel_dsi
->video_frmt_cfg_bits
|
890 intel_dsi
->video_mode_format
|
892 RANDOM_DPI_DISPLAY_RESOLUTION
);
896 static void intel_dsi_pre_pll_enable(struct intel_encoder
*encoder
)
900 intel_dsi_prepare(encoder
);
902 vlv_enable_dsi_pll(encoder
);
905 static enum drm_connector_status
906 intel_dsi_detect(struct drm_connector
*connector
, bool force
)
908 return connector_status_connected
;
911 static int intel_dsi_get_modes(struct drm_connector
*connector
)
913 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
914 struct drm_display_mode
*mode
;
918 if (!intel_connector
->panel
.fixed_mode
) {
919 DRM_DEBUG_KMS("no fixed mode\n");
923 mode
= drm_mode_duplicate(connector
->dev
,
924 intel_connector
->panel
.fixed_mode
);
926 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
930 drm_mode_probed_add(connector
, mode
);
934 static void intel_dsi_connector_destroy(struct drm_connector
*connector
)
936 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
939 intel_panel_fini(&intel_connector
->panel
);
940 drm_connector_cleanup(connector
);
944 static void intel_dsi_encoder_destroy(struct drm_encoder
*encoder
)
946 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
948 if (intel_dsi
->panel
) {
949 drm_panel_detach(intel_dsi
->panel
);
950 /* XXX: Logically this call belongs in the panel driver. */
951 drm_panel_remove(intel_dsi
->panel
);
953 intel_encoder_destroy(encoder
);
956 static const struct drm_encoder_funcs intel_dsi_funcs
= {
957 .destroy
= intel_dsi_encoder_destroy
,
960 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs
= {
961 .get_modes
= intel_dsi_get_modes
,
962 .mode_valid
= intel_dsi_mode_valid
,
963 .best_encoder
= intel_best_encoder
,
966 static const struct drm_connector_funcs intel_dsi_connector_funcs
= {
967 .dpms
= intel_connector_dpms
,
968 .detect
= intel_dsi_detect
,
969 .destroy
= intel_dsi_connector_destroy
,
970 .fill_modes
= drm_helper_probe_single_connector_modes
,
971 .atomic_get_property
= intel_connector_atomic_get_property
,
972 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
973 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
976 void intel_dsi_init(struct drm_device
*dev
)
978 struct intel_dsi
*intel_dsi
;
979 struct intel_encoder
*intel_encoder
;
980 struct drm_encoder
*encoder
;
981 struct intel_connector
*intel_connector
;
982 struct drm_connector
*connector
;
983 struct drm_display_mode
*scan
, *fixed_mode
= NULL
;
984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
990 /* There is no detection method for MIPI so rely on VBT */
991 if (!dev_priv
->vbt
.has_mipi
)
994 if (IS_VALLEYVIEW(dev
)) {
995 dev_priv
->mipi_mmio_base
= VLV_MIPI_BASE
;
997 DRM_ERROR("Unsupported Mipi device to reg base");
1001 intel_dsi
= kzalloc(sizeof(*intel_dsi
), GFP_KERNEL
);
1005 intel_connector
= intel_connector_alloc();
1006 if (!intel_connector
) {
1011 intel_encoder
= &intel_dsi
->base
;
1012 encoder
= &intel_encoder
->base
;
1013 intel_dsi
->attached_connector
= intel_connector
;
1015 connector
= &intel_connector
->base
;
1017 drm_encoder_init(dev
, encoder
, &intel_dsi_funcs
, DRM_MODE_ENCODER_DSI
);
1019 /* XXX: very likely not all of these are needed */
1020 intel_encoder
->compute_config
= intel_dsi_compute_config
;
1021 intel_encoder
->pre_pll_enable
= intel_dsi_pre_pll_enable
;
1022 intel_encoder
->pre_enable
= intel_dsi_pre_enable
;
1023 intel_encoder
->enable
= intel_dsi_enable_nop
;
1024 intel_encoder
->disable
= intel_dsi_pre_disable
;
1025 intel_encoder
->post_disable
= intel_dsi_post_disable
;
1026 intel_encoder
->get_hw_state
= intel_dsi_get_hw_state
;
1027 intel_encoder
->get_config
= intel_dsi_get_config
;
1029 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1030 intel_connector
->unregister
= intel_connector_unregister
;
1032 /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
1033 if (dev_priv
->vbt
.dsi
.config
->dual_link
) {
1034 /* XXX: does dual link work on either pipe? */
1035 intel_encoder
->crtc_mask
= (1 << PIPE_A
);
1036 intel_dsi
->ports
= ((1 << PORT_A
) | (1 << PORT_C
));
1037 } else if (dev_priv
->vbt
.dsi
.port
== DVO_PORT_MIPIA
) {
1038 intel_encoder
->crtc_mask
= (1 << PIPE_A
);
1039 intel_dsi
->ports
= (1 << PORT_A
);
1040 } else if (dev_priv
->vbt
.dsi
.port
== DVO_PORT_MIPIC
) {
1041 intel_encoder
->crtc_mask
= (1 << PIPE_B
);
1042 intel_dsi
->ports
= (1 << PORT_C
);
1045 /* Create a DSI host (and a device) for each port. */
1046 for_each_dsi_port(port
, intel_dsi
->ports
) {
1047 struct intel_dsi_host
*host
;
1049 host
= intel_dsi_host_init(intel_dsi
, port
);
1053 intel_dsi
->dsi_hosts
[port
] = host
;
1056 for (i
= 0; i
< ARRAY_SIZE(intel_dsi_drivers
); i
++) {
1057 intel_dsi
->panel
= intel_dsi_drivers
[i
].init(intel_dsi
,
1058 intel_dsi_drivers
[i
].panel_id
);
1059 if (intel_dsi
->panel
)
1063 if (!intel_dsi
->panel
) {
1064 DRM_DEBUG_KMS("no device found\n");
1068 intel_encoder
->type
= INTEL_OUTPUT_DSI
;
1069 intel_encoder
->cloneable
= 0;
1070 drm_connector_init(dev
, connector
, &intel_dsi_connector_funcs
,
1071 DRM_MODE_CONNECTOR_DSI
);
1073 drm_connector_helper_add(connector
, &intel_dsi_connector_helper_funcs
);
1075 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
; /*XXX*/
1076 connector
->interlace_allowed
= false;
1077 connector
->doublescan_allowed
= false;
1079 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1081 drm_connector_register(connector
);
1083 drm_panel_attach(intel_dsi
->panel
, connector
);
1085 mutex_lock(&dev
->mode_config
.mutex
);
1086 drm_panel_get_modes(intel_dsi
->panel
);
1087 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
1088 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
1089 fixed_mode
= drm_mode_duplicate(dev
, scan
);
1093 mutex_unlock(&dev
->mode_config
.mutex
);
1096 DRM_DEBUG_KMS("no fixed mode\n");
1100 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
1105 drm_encoder_cleanup(&intel_encoder
->base
);
1107 kfree(intel_connector
);